RDOQ circuit assembly, rate distortion optimization quantization method, chip and equipment

Abstract

The invention discloses an RDOQ circuit assembly, a rate distortion optimization quantization method, a chip and equipment, and relates to the technical field of video coding and decoding. The RDOQ circuit assembly comprises a coefficient adjustment circuit, a non-zero coefficient position calculation circuit, an SBH adjustment circuit and an output circuit. And the coefficient adjusting circuit, the non-zero coefficient position calculation circuit, the SBH adjusting circuit and the output circuit are connected in sequence. Through the RDOQ circuit assembly, parallel processing of multiple coefficients in the CG and pipeline processing between the CGs can be achieved, hardware resources are saved, and meanwhile the hardware throughput efficiency and algorithm benefit maximization are guaranteed.

Description

Technical Field

[0001] The present application relates to the field of video coding and decoding technology, and in particular to an RDOQ circuit component, a rate-distortion optimization quantization method, a chip, and a device. Background Art

[0002] Rate-Distortion Optimization Quantization (RDOQ) technology can be applied to video coding standards such as H.264, H.265, and H.266 to improve video coding performance.

[0003] In related technologies, since the RDOQ algorithm itself is computationally dependent and requires an accurate entropy coding probability model to achieve good bit rate estimation accuracy, the RDOQ technology is usually implemented through a software module in a video codec device. Summary of the Invention

[0004] The present invention provides an RDOQ circuit component, a rate-distortion optimization quantization method, a chip, and a device that can improve data transfer efficiency. The technical solution is as follows.

[0005] In one aspect, an RDOQ circuit component is provided, the RDOQ circuit component comprising: a coefficient adjustment circuit, a non-zero coefficient position calculation circuit, an SBH adjustment circuit, and an output circuit;

[0006] The coefficient adjustment circuit, the non-zero coefficient position calculation circuit, the SBH adjustment circuit and the output circuit are connected in sequence;

[0007] The coefficient adjustment circuit is configured to calculate and output a first coefficient adjustment mode for the CG in a TU; the first coefficient adjustment mode is an optimal solution between a mode in which coefficients at each coefficient position of the CG are adjusted one by one and a mode in which all coefficients at each coefficient position of the CG are set to zero;

[0008] The non-zero coefficient position calculation circuit is configured to calculate, based on an output result of the coefficient adjustment circuit, a coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and a rate-distortion cost variation before and after each non-zero coefficient position in the CG is the last non-zero coefficient position; determine an optimal last non-zero coefficient position in the CG based on the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and the rate-distortion cost variation before and after each non-zero coefficient position in the CG is the last non-zero coefficient position;

[0009] The SBH adjustment circuit is used to determine the SBH adjustment method of the CG based on the calculation result of the non-zero coefficient position calculation circuit;

[0010] The output circuit is used to output the coefficients of each coefficient position of the CG based on the output result of the SBH adjustment circuit.

[0011] In another aspect, a rate-distortion optimized quantization method is provided. The method is executed by the RDOQ circuit component described above in a pipeline manner, and the method comprises:

[0012] The coefficient adjustment circuit calculates and outputs a first coefficient adjustment method for the CG in the TU; the first coefficient adjustment method is an optimal solution between a method of adjusting coefficients at each coefficient position of the CG one by one and an adjustment method of setting all coefficients at each coefficient position of the CG to 0;

[0013] By means of the non-zero coefficient position calculation circuit, based on the output result of the coefficient adjustment circuit, a coding rate when each non-zero coefficient position in the CG is used as the last non-zero coefficient position, and a rate-distortion cost variation before and after each non-zero coefficient position in the CG is used as the last non-zero coefficient position are calculated; based on the coding rate when each non-zero coefficient position in the CG is used as the last non-zero coefficient position, and a rate-distortion cost variation before and after each non-zero coefficient position in the CG is used as the last non-zero coefficient position, an optimal last non-zero coefficient position in the CG is determined;

[0014] Determining, by the SBH adjustment circuit, an SBH adjustment method of the CG based on a calculation result of the non-zero coefficient position calculation circuit;

[0015] Through the output circuit, the coefficients of each coefficient position of the CG are output based on the output result of the SBH adjustment circuit.

[0016] In some embodiments, the method further includes: reading, by the startup subcircuit, unquantized coefficients corresponding to respective coefficient positions in the TU, pre-fetching a probability model table corresponding to the TU from the RDO; and determining configuration parameters required for RDOQ calculation of the TU;

[0017] By means of the quantization subcircuit, each coefficient position of the CG is quantized in parallel with the CG as a unit to obtain an initial coefficient of each coefficient position of the CG;

[0018] The rate estimation preprocessing sub-circuit calculates, in parallel, the context index offsets of the rate estimation of each coefficient position of the CG based on the coefficients of the neighborhood of each coefficient position of the CG; and, based on the probability model table, calculates in parallel the number of remaining available coding bits corresponding to each coefficient position of the CG;

[0019] The first comparison sub-circuit calculates, based on the calculation result of the rate estimation preprocessing sub-circuit, the distortion, rate, and rate-distortion cost of each coefficient position of the CG in parallel when the coefficient is not adjusted, the coefficient is reduced by 1, and the coefficient is 0; based on the rate-distortion cost of each coefficient position of the CG when the coefficient is not adjusted and the coefficient is reduced by 1, a second coefficient adjustment method is determined; the second coefficient adjustment method is an adjustment method corresponding to a smaller rate-distortion cost among the adjustment method of each coefficient position of the CG when the coefficient is not adjusted and the adjustment method of each coefficient position of the CG when the coefficient is reduced by 1;

[0020] Through the second comparison sub-circuit, the rate-distortion cost of the coefficients at each coefficient position of the CG after adjustment according to the second coefficient adjustment method, and the rate-distortion cost after all the coefficients at each coefficient position of the CG are set to 0 are calculated; and the adjustment method with the smaller rate-distortion cost among the second coefficient adjustment method and the adjustment method of setting all the coefficients at each coefficient position of the CG to 0 is determined as the first coefficient adjustment method.

[0021] In some embodiments, the method further comprises: calculating and outputting, by the coefficient adjustment circuit, a quantization error of each coefficient position in the CG, a bit rate after the coefficient at the coefficient position is increased, and a bit rate after the coefficient at the coefficient position is reduced by -1;

[0022] The non-zero coefficient position calculation circuit is used to calculate the coding rate of the CG at the optimal last non-zero coefficient position and the coding rate of the CG when all coefficients at each coefficient position are set to 0; the rate-distortion cost of the CG at the optimal last non-zero coefficient position and the distortion when all coefficients at each coefficient position of the CG are set to 0 are cumulatively calculated;

[0023] Through the SBH adjustment circuit, based on the calculation results of the non-zero coefficient position calculation circuit, it is determined whether the current TU is all 0. If the current TU is not all 0, based on the rate-distortion cost when each coefficient position in the CG is increased and decreased, the optimal SBH adjustment method for each coefficient position in the CG is determined, and the SBH adjustment methods of each coefficient position of the CG are compared to determine the SBH adjustment method of the CG.

[0024] In some embodiments, the method further includes: calculating, by the first comparison subcircuit, for each coefficient position in the CG, in parallel, the distortion when the coefficient is set to 0; and calculating, for each coefficient position in the CG, in parallel, the bit rate after the coefficient is +1; and calculating, for each coefficient position in the CG, in parallel, the bit rate after the coefficient is -1;

[0025] Through the second comparison sub-circuit, based on the distortion calculated by the first comparison sub-circuit when the coefficient at each coefficient position in the CG is set to 0, the bit rate after the coefficient at each coefficient position in the CG is +1, and the bit rate after the coefficient at each coefficient position in the CG is -1, the quantization error is calculated in parallel for each coefficient position in the CG, the bit rate after the coefficient is increased is calculated in parallel for each coefficient position in the CG; and the bit rate after the coefficient is reduced is calculated in parallel for each coefficient position in the CG.

[0026] In some embodiments, the method further includes: through the quantization subcircuit, when it is detected that the initial coefficients of each coefficient position in the CG are not all 0, sending the initial coefficients of each coefficient position of the CG to the bit rate estimation preprocessing subcircuit.

[0027] In some embodiments, the method further comprises: storing, by the quantization subcircuit, the initial coefficients of each coefficient position of the CG into a bypass queue in the output circuit when detecting that the initial coefficients of each coefficient position in the CG are all 0;

[0028] Through the output circuit, when the initial coefficients of each coefficient position in the CG are all 0, the initial coefficients of each coefficient position of the CG in the bypass queue are output as the coefficients of each coefficient position of the CG.

[0029] In some embodiments, the method further comprises: outputting, by the multiplexer, the coefficients of each coefficient position of the CG in the bypass queue upon receiving a control signal indicating that the initial coefficients of each coefficient position in the CG are all 0;

[0030] Through the multiplexer, when a control signal indicating that the initial coefficients of each coefficient position in the CG are all 0 is not received, or when a control signal indicating that the initial coefficients of each coefficient position in the CG are not all 0 is received, the coefficients of each coefficient position of the CG in the normal queue are output.

[0031] In some embodiments, the start subcircuit, the quantization subcircuit, the rate estimation preprocessing subcircuit, the first comparison subcircuit, the second comparison subcircuit, the non-zero coefficient position calculation circuit, the SBH adjustment circuit and the output circuit process the same CG in different pipeline stages respectively.

[0032] In another aspect, a chip is provided, comprising: at least one RDOQ circuit component as described above.

[0033] In another aspect, a computer device is provided, comprising: at least one chip, wherein the chip includes at least one RDOQ circuit component as described above.

[0034] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0035] The RDOQ circuit component is a pipeline structure composed of a coefficient adjustment circuit, a non-zero coefficient position calculation circuit, an SBH adjustment circuit and an output circuit connected in sequence; specifically, the coefficient adjustment circuit calculates and outputs the first coefficient adjustment method of the CG in the TU as a unit, and the non-zero coefficient position calculation circuit calculates the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position based on the output result of the coefficient adjustment circuit, and the rate-distortion cost change amount before and after each non-zero coefficient position in the CG is the last non-zero coefficient position; based on the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and the rate-distortion cost change amount before and after each non-zero coefficient position in the CG is the last non-zero coefficient position, the optimal last non-zero coefficient position in the CG is determined. Then, the SBH adjustment method of the CG is determined based on the calculation result of the non-zero coefficient position calculation circuit through the SBH adjustment circuit; finally, the coefficients of each coefficient position of the CG are output through the output circuit based on the output result of the SBH adjustment circuit. In the above scheme, the rate-distortion cost change of each non-zero coefficient position in the CG is replaced by the rate-distortion cost when each non-zero coefficient position in the CG is used as the last non-zero coefficient position to determine the optimal last non-zero coefficient position in the CG. The rate-distortion cost change can be obtained using the calculation result of the previous pipeline stage. Therefore, the determination process of the optimal last non-zero coefficient position can be calculated through the pipeline, so that the pipeline processing of the RDOQ process can be realized through hardware, greatly improving the processing efficiency of the RDOQ process. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 is a flowchart of RDOQ software processing provided by an exemplary embodiment of the present application;

[0038] Figure 2 is a schematic diagram of a scanning sequence provided by an exemplary embodiment of the present application;

[0039] Figure 3 is a structural diagram of an RDOQ circuit component provided by an exemplary embodiment of the present application;

[0040] Figure 4 is a structural diagram of an RDOQ circuit component provided by an exemplary embodiment of the present application;

[0041] Figure 5 This is a schematic diagram of the positions of coefficients and their corresponding domain coefficients provided by an exemplary embodiment of the present application;

[0042] Figure 6 is a structural diagram of an RDOQ circuit component provided by an exemplary embodiment of the present application;

[0043] Figure 7 This is a schematic diagram of an H.265 / H.266 universal RDOQ hardware processing architecture provided by an exemplary embodiment of the present application;

[0044] Figure 8 This is a flowchart of RDOQ calculation suitable for hardware processing provided by an exemplary embodiment of the present application;

[0045] Figure 9 This is a flowchart of a rate-distortion optimization quantization method provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0047] It should be understood that although the terms first, second, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter without departing from the scope of this disclosure. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0048] The following are some definitions of terms involved in this application:

[0049] Quantization: This typically involves two processes: quantization and inverse quantization. The quantization process converts transform coefficients into quantized coefficients. The encoder needs to determine the optimal quantized coefficients and perform entropy coding on them. The inverse quantization process converts the quantized coefficients obtained after entropy decoding into transform coefficients. The transform coefficients then undergo an inverse transform process to obtain a residual, which is used in the reconstruction of the coding block.

[0050] BD-rate: One of the main parameters for evaluating the performance of video coding algorithms, used to evaluate the rate distortion (RD) performance of different video encoders.

[0051] RDOQ: Rate Distortion Optimization Quantization (RDOQ) is a crucial performance enhancement technology in video coding standards such as H.264, H.265, H.266, VP9, and AV1. RDOQ can significantly reduce bitrate at the expense of minimal distortion. However, due to the computational dependencies of the RDOQ algorithm and its reliance on an accurate entropy coding probability model for accurate bitrate estimation, RDOQ is challenging to implement in hardware.

[0052] Please refer to Figure 1 , which shows a flowchart of RDOQ software processing provided by an exemplary embodiment of the present application. Please refer to Figure 2 , which shows a schematic diagram of a scanning sequence provided by an exemplary embodiment of the present application.

[0053] like Figure 1 As shown, the RDOQ software processing flow includes the following steps:

[0054] Step A1, quantization (Quant): Divide the TU into 4×4 coefficient groups (Coefficient Group, CG), perform scalar quantization according to the agreed scanning order, and obtain the initial transform coefficient (init_coefficient) corresponding to each position; Figure 2As shown, the scanning order includes at least one of diagonal, horizontal, and vertical.

[0055] Step A2, update CG Ctx: determine the context (Context, Ctx) index of the syntax element corresponding to the current CG based on the information of the value of the current CG and its neighboring CG (such as the neighboring CG on the left of the current CG or the neighboring CG below the current CG).

[0056] Step A3, update the Ctx offset: for the 16 transform coefficients (coefficient, coeff) in the current CG, determine the Ctx offset (offset) of the syntax element corresponding to each encoding position in turn according to the agreed scanning order; wherein, the Ctx offset calculation of the current position depends on the coefficient value of the position before the scanning order.

[0057] Step A4, calculate RD_Cost & adjust Coeff: There are multiple candidate coefficients in each position (where the typical candidate value is 0 / init_coefficient / init_cofficient-1). According to the Context probability model obtained from RDO, the Ctx offset obtained in step A3 is used as the index to look up the table to obtain the bit rate (Rate) required for encoding. At the same time, the inverse quantization (De-Quant) process can be used to obtain the recovered coefficient, which is subtracted from the value before quantization and squared to obtain the corresponding distortion (Distortion, Dist). Then, the Lagrange formula is used to obtain the corresponding rate-distortion cost (RateDistortion cost, RD_cost). Multiple candidate coefficients select the optimal coefficient after adjustment for the current position based on the size of RD_cost. The calculation formula for RD_cost can be shown as follows.

[0058] RD_cost = Distortion + λ × Rate

[0059] Where λ is the Lagrange constant.

[0060] Step A5: Loop through steps A3 to A4, traverse the 16 positions in the CG, and obtain the optimal coefficient after the entire CG is adjusted.

[0061] Step A6, CG is set to 0 (all zero): For the adjusted CG, force all 16 positions to be 0, and calculate the corresponding RD_cost, and then compare it with the RD_cost corresponding to the CG not all 0 obtained in step A5 to determine whether the current CG is all set to 0.

[0062] Step A7: Based on the final adjustment result of the current CG, update the corresponding CG status flag to provide data for the next CG to obtain the correct Ctx.

[0063] Step A8, adjust the last position: A TU contains multiple CGs. After all CGs of the current TU are adjusted, determine the last non-zero coefficient position (lastNonPos) of the current TU. Then, taking CG as the unit, in the reverse order of the agreed scanning order, take each non-zero coefficient position as lastNonPos, calculate the corresponding RD_cost, and compare the coefficient position corresponding to the minimum RD_cost, which is the final determined lastNonPos.

[0064] Step A9: Sign Bit Hide (SBH): The H.265 / H.266 coding protocol stipulates that the sign bit of the first non-zero coefficient in each CG (in the reverse order of the agreed scanning order) does not need to be encoded, but is derived by the encoder from other symbols of the CG. The inference method is: the lost sign is equal to the least significant bit (LSB) of the sum of the absolute values of all coefficients in the CG. Therefore, when the least significant bit of the sum of the absolute values of all coefficients in the CG is inconsistent with the hidden sign bit, one of the coefficients in the CG needs to be adjusted (to +1 or -1) to meet the sign bit hiding requirements.

[0065] from Figure 1 As can be seen, the software flow involves three loops: Loop 1 and Loop 2 are nested within each other, and Loop 3 must wait for Loop 2 to complete before executing. Loop 1 requires that the adjustment of the 16 coefficients within a CG be performed serially, as each coefficient adjustment depends on the result of the previous adjustment. Loop 3 must wait until Loop 2 completes, meaning all CGs in the entire TU have been adjusted. This requires the hardware implementation to cache a large number of intermediate results. The existence of these three loops makes directly copying the software flow extremely expensive for hardware implementation, consuming significant resources and causing significant processing delays.

[0066] Please refer to Figure 3 , which shows a structural diagram of an RDOQ circuit component provided by an exemplary embodiment of the present application. The system may include: a coefficient adjustment circuit 310, a non-zero coefficient position calculation circuit 320, an SBH adjustment circuit 330 and an output circuit 340.

[0067] The coefficient adjustment circuit 310 , the non-zero coefficient position calculation circuit 320 , the SBH adjustment circuit 330 and the output circuit 340 are connected in sequence.

[0068] Among them, the coefficient adjustment circuit 310, the non-zero coefficient position calculation circuit 320, the SBH adjustment circuit 330 and the output circuit 340 are connected in sequence, which means that the coefficient adjustment circuit 310, the non-zero coefficient position calculation circuit 320, the SBH adjustment circuit 330 and the output circuit 340 are electrically connected in sequence; the non-zero coefficient position calculation circuit 320 can receive instructions / signals / data sent by the coefficient adjustment circuit 310, the SBH adjustment circuit 330 can receive instructions / signals / data sent by the non-zero coefficient position calculation circuit 320, and the output circuit 340 can receive instructions / signals / data sent by the SBH adjustment circuit 330.

[0069] In the embodiment of the present application, the RDOQ circuit component is a pipeline structure consisting of a coefficient adjustment circuit 310, a non-zero coefficient position calculation circuit 320, an SBH adjustment circuit 330 and an output circuit 340. The RDOQ circuit component can continuously pipeline multiple TUs.

[0070] The coefficient adjustment circuit 310 is used to calculate and output the first coefficient adjustment method of CG based on the CG in TU; the first coefficient adjustment method is the optimal solution between the method of adjusting the coefficients of each coefficient position of CG one by one and the adjustment method of setting all the coefficients of each coefficient position of CG to 0.

[0071] In an embodiment of the present application, when it is necessary to obtain the first coefficient adjustment method of each CG in a TU, the coefficient adjustment of each CG does not need to consider the dependency between the corresponding transform coefficients. The computer device can realize parallel processing of each transform coefficient in each CG through the coefficient adjustment circuit 310. That is, the coefficient adjustment circuit 310 performs parallel calculations on the transform coefficients of each coefficient position in the CG in units of CG, so as to quickly obtain the optimal solution between the method of adjusting the coefficients of each coefficient position of each CG in the TU one by one and the adjustment method of setting all the coefficients of each coefficient position of the CG to 0, and sends the first coefficient adjustment method of each CG and related data to the non-zero coefficient position calculation circuit 320.

[0072] The supported TU sizes include 32×32, 16×16, 8×8, and 4×4. When the TU size is larger than 4×4, all coefficients within the TU are divided into non-overlapping 4×4 coefficient groups (CGs). Therefore, when the TU size is 8×8, 16×16, or 32×32, the CG arrays are 2×2, 4×4, and 8×8, respectively.

[0073] For example, if the TU size is 4×4, the computer device obtains a CG corresponding to the TU; if the TU size is greater than 4×4, the computer device obtains multiple CGs corresponding to the TU, and calculates each CG in sequence according to the scanning order (such as diagonal / horizontal / vertical).

[0074] Among them, the coefficient adjustment circuit 310 performs parallel calculations on each coefficient within the CG, obtains the RD_cost corresponding to the adjustment method of each coefficient position within the CG one by one, and the RD_cost corresponding to the adjustment method of setting all coefficients to 0 at each coefficient position within the CG, compares the RD_cost corresponding to the two adjustment methods, and determines the adjustment method corresponding to the smaller RD_cost as the first coefficient adjustment method of the CG.

[0075] For example, the coefficient adjustment circuit 310 can calculate the RD_cost corresponding to the coefficient -1, coefficient +1, and coefficient 0 for non-zero coefficients respectively; compare the RD_cost corresponding to the coefficient -1 and coefficient +1, and determine the coefficient adjustment method corresponding to the smaller RD_cost as the one-by-one adjustment method; then compare the one-by-one adjustment method and the RD_cost corresponding to the coefficient 0, and determine the adjustment method corresponding to the smaller RD_cost as the first coefficient adjustment method of CG.

[0076] Optionally, the coefficient adjustment circuit 310 can adjust each non-zero coefficient in the CG to the RD_cost corresponding to 0, and send it to the non-zero coefficient position calculation circuit 320.

[0077] In some embodiments, the coefficient adjustment circuit 310 can be a pipeline structure composed of different sub-circuits electrically connected in sequence. The sub-circuit with an earlier timing sequence can send instructions / signals / data to the next sub-circuit, and the sub-circuit with a later timing sequence can receive instructions / signals / data sent by the previous sub-circuit.

[0078] The non-zero coefficient position calculation circuit 320 is used to calculate the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and the rate-distortion cost change before and after each non-zero coefficient position in the CG is the last non-zero coefficient position based on the output result of the coefficient adjustment circuit 310; based on the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and the rate-distortion cost change before and after each non-zero coefficient position in the CG is the last non-zero coefficient position, determine the optimal last non-zero coefficient position in the CG.

[0079] In an embodiment of the present application, when it is necessary to obtain the optimal last non-zero coefficient position of each CG in a TU, the computer device can obtain the coding rate of each non-zero coefficient position in the CG when it is the last non-zero coefficient position, and the rate-distortion cost change before and after each non-zero coefficient position in the CG is used as the last non-zero coefficient position through the non-zero coefficient position calculation circuit 320 to determine the optimal last non-zero coefficient position in the CG; and send the optimal last non-zero coefficient position in the CG to the SBH adjustment circuit 330.

[0080] Among them, the non-zero coefficient position calculation circuit 320 can perform parallel calculations on the coefficients of each coefficient position of CG according to the output result of the coefficient adjustment circuit 310, so as to obtain the coding rate corresponding to each non-zero coefficient position as the last non-zero coefficient position, and the rate-distortion cost change before and after each non-zero coefficient position as the last non-zero coefficient position.

[0081] Since the non-zero coefficient position calculation circuit 320 can obtain each non-zero coefficient position in the CG as the rate-distortion cost change before and after the last non-zero coefficient position, the computer device does not need to wait for the coefficient adjustment of each CG in the TU to be completed before determining the last non-zero coefficient position; this solution enables the non-zero coefficient position calculation circuit 320 to form a pipeline with the coefficient adjustment circuit 310, reducing computational complexity and improving the timing performance of the hardware design.

[0082] In the embodiment of the present application, the optimal last non-zero coefficient position in the CG is determined by taking each non-zero coefficient position in the CG as the rate-distortion cost change before and after the last non-zero coefficient position, instead of taking each non-zero coefficient position in the CG as the last non-zero coefficient position. The rate-distortion cost change can be obtained using the calculation results of the previous pipeline stage. Therefore, the present application can achieve the determination of the optimal last non-zero coefficient position through pipeline.

[0083] Exemplarily, the non-zero coefficient position calculation circuit 320 may include a calculation unit and a comparison unit. The calculation unit is used to calculate the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and the RD_cost corresponding to each non-zero coefficient in the CG adjusted to 0 sent by the receiving coefficient adjustment circuit 310; the comparison unit is used to determine the optimal last non-zero coefficient position in the CG based on the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position and the cumulative sum of the RD_cost corresponding to each non-zero coefficient in the CG adjusted to 0.

[0084] The SBH adjustment circuit 330 is used to determine the SBH adjustment method of the CG based on the calculation result of the non-zero coefficient position calculation circuit 320.

[0085] In an embodiment of the present application, when it is necessary to obtain the SBH adjustment method of each CG in a TU, the computer device can determine the SBH adjustment method through the SBH adjustment circuit 330.

[0086] For example, the computer device can calculate the RD_cost corresponding to different adjustment methods for each coefficient position in the CG through the SBH adjustment circuit 330, and obtain the SBH adjustment method corresponding to the smaller RD_cost of each coefficient position; and then determine the SBH adjustment method of the CG by comparing the various coefficient positions in the same CG.

[0087] Exemplarily, the SBH adjustment circuit 330 may include two comparison units. One comparison unit is configured to calculate the RD_cost corresponding to the coefficients +1 and -1 at each coefficient position within the CG, and obtain the SBH adjustment method corresponding to the smaller RD_cost at each coefficient position; the other comparison unit is configured to determine the SBH adjustment method for the CG based on the SBH adjustment methods for each coefficient position of the CG calculated by the first comparison unit.

[0088] The output circuit 340 is used to output the coefficients of each coefficient position of CG based on the output result of the SBH adjustment circuit 330.

[0089] In an embodiment of the present application, the output circuit 340 can output the coefficients of each coefficient position of the CG according to the output result of the SBH adjustment circuit 330 and the scanning order in the coefficient adjustment circuit 310.

[0090] To summarize, the solution shown in the embodiment of the present application is a pipeline structure consisting of a coefficient adjustment circuit, a non-zero coefficient position calculation circuit, an SBH adjustment circuit and an output circuit; specifically, the coefficient adjustment circuit calculates and outputs the first coefficient adjustment method of the CG in the TU as a unit, and the non-zero coefficient position calculation circuit calculates the coding rate of each non-zero coefficient position in the CG as the last non-zero coefficient position based on the output result of the coefficient adjustment circuit, as well as the rate-distortion cost change of each non-zero coefficient position in the CG before and after the last non-zero coefficient position. Based on the coding rate of each non-zero coefficient position in the CG as the last non-zero coefficient position, as well as the rate-distortion cost change of each non-zero coefficient position in the CG before and after the last non-zero coefficient position, the optimal last non-zero coefficient position in the CG is determined, and then the SBH adjustment circuit determines the SBH adjustment method of the CG based on the calculation result of the non-zero coefficient position calculation circuit; finally, the output circuit outputs the coefficients of each coefficient position of the CG based on the output result of the SBH adjustment circuit. In the above scheme, the optimal last non-zero coefficient position in the CG is determined by taking each non-zero coefficient position in the CG as the rate-distortion cost change before and after the last non-zero coefficient position, instead of taking each non-zero coefficient position in the CG as the last non-zero coefficient position. The rate-distortion cost change can be obtained using the calculation results of the previous pipeline stage. Therefore, the process of determining the optimal last non-zero coefficient position can be calculated through the pipeline, so that the pipeline processing of the RDOQ process can be realized through hardware, greatly improving the processing efficiency of the RDOQ process.

[0091] based on Figure 3 For the example shown, please refer to Figure 4 , which shows a schematic structural diagram of an RDOQ circuit component provided by an exemplary embodiment of the present application, such as Figure 4 As shown above Figure 3 The coefficient adjustment circuit 310 shown includes: a start subcircuit 310a, a quantization subcircuit 310b, a rate estimation preprocessing subcircuit 310c, a first comparison subcircuit 310d, and a second comparison subcircuit 310e.

[0092] The starting subcircuit 310a, the quantization subcircuit 310b, the rate estimation preprocessing subcircuit 310c, the first comparison subcircuit 310d and the second comparison subcircuit 310e are connected in sequence.

[0093] Among them, the starting subcircuit 310a, the quantization subcircuit 310b, the rate estimation preprocessing subcircuit 310c, the first comparison subcircuit 310d and the second comparison subcircuit 310e are connected in sequence, which means that the starting subcircuit 310a, the quantization subcircuit 310b, the rate estimation preprocessing subcircuit 310c, the first comparison subcircuit 310d and the second comparison subcircuit 310e are electrically connected in sequence; the starting subcircuit 310a can receive instructions / signals / data sent by the quantization subcircuit 310b, the quantization subcircuit 310b can receive instructions / signals / data sent by the rate estimation preprocessing subcircuit 310c, the rate estimation preprocessing subcircuit 310c can receive instructions / signals / data sent by the first comparison subcircuit 310d, and the first comparison subcircuit 310d can receive instructions / signals / data sent by the second comparison subcircuit 310e.

[0094] In an embodiment of the present application, the coefficient adjustment circuit 310 is a pipeline structure composed of a start subcircuit 310a, a quantization subcircuit 310b, a rate estimation preprocessing subcircuit 310c, a first comparison subcircuit 310d and a second comparison subcircuit 310e. The coefficient adjustment circuit 310 can perform continuous pipeline processing on multiple TUs.

[0095] The startup subcircuit 310a is configured to read the unquantized coefficients corresponding to each coefficient position in the TU, pre-fetch the probability model table corresponding to the TU from the RDO, and determine the configuration parameters required for RDOQ calculation of the TU.

[0096] In an embodiment of the present application, the computer device can read the unquantized coefficients corresponding to each coefficient position of each CG in the TU through the startup sub-circuit 310a, and send the unquantized coefficients to the quantization sub-circuit 310b.

[0097] The computer device may also pre-fetch a probability model table corresponding to a TU from the RDO based on the information of the TU through the startup sub-circuit 310 a ; and send the probability model table to the quantization sub-circuit 310 b .

[0098] For example, the probability model table includes the number of bits that different syntax elements may occupy in the bitstream. The probability model table generated by RDO has a high accuracy, that is, the estimated number of bits is approximately close to the number of bits in the actual bitstream.

[0099] After RDO calculates the optimal partition, the generated probability model table is stored in the probability model memory inside RDOQ. RDOQ only needs to read the memory during calculation.

[0100] The computer device may also determine configuration parameters such as quantization parameters required for RDOQ calculation of the TU through the startup sub-circuit 310 a , and send the configuration parameters to the quantization sub-circuit 310 b .

[0101] The quantization sub-circuit 310b is used to quantize each coefficient position of CG in parallel based on CG, so as to obtain the initial coefficient of each coefficient position of CG.

[0102] In the embodiment of the present application, the quantization sub-circuit 310b receives the unquantized coefficients, the probability model table, and the configuration parameters sent by the start sub-circuit 310a, and sends the probability model table to the bit rate estimation pre-processing sub-circuit 310c.

[0103] When it is necessary to obtain the initial coefficients of each coefficient position of each CG in the TU, the computer device can receive the unquantized coefficients sent by the start subcircuit 310a through the quantization subcircuit 310b, calculate each CG in turn according to the scanning order (such as diagonal / horizontal / vertical) in units of CG, quantize the various coefficient positions of the same CG in parallel, obtain the initial coefficients of each coefficient position of the CG, and send the initial coefficients to the bit rate estimation preprocessing subcircuit 310c.

[0104] Exemplarily, the quantization subcircuit 310b performs scalar quantization or vector quantization on each coefficient position of CG in parallel, taking CG as a unit.

[0105] The rate estimation preprocessing sub-circuit 310c is used to parallelly calculate the context index offset of the rate estimation of each coefficient position of CG based on the coefficients of the neighborhood of each coefficient position of CG; and, based on the probability model table, parallelly calculate the remaining available coding bits corresponding to each coefficient position of CG.

[0106] In an embodiment of the present application, the computer device can receive the initial coefficients sent by the quantization subcircuit 310b through the rate estimation preprocessing subcircuit 310c, and obtain the initial coefficients of the neighborhood of each coefficient position of CG; based on the initial coefficients of the neighborhood of each coefficient position of CG, calculate the context index offset (Ctx_offset) of each coefficient position of CG in parallel.

[0107] For example, each CG has a flag cg_flag indicating whether it is all 0. The flag corresponding to the CG on the right side of the current CG is counted as cg_flag 0, and the flag corresponding to the CG on the bottom side of the current CG is counted as cg_flag 1. When encoding the syntax element cg_flag of the current CG, the required context index value = cg_flag 0 + cg_flag 1.

[0108] Among them, the coefficient at each coefficient position is surrounded by 5 neighboring coefficients. When encoding the value of a coefficient, the Ctx offset of the corresponding syntax element is calculated based on the corresponding values of the 5 neighbors.

[0109] Please refer to Figure 5 , which shows a schematic diagram of the positions of coefficients and their corresponding domain coefficients provided by an exemplary embodiment of the present application. Figure 5 As shown, the coefficient 501 at each coefficient position corresponds to 5 neighboring coefficients, namely 502, 503, 504, 505, and 506.

[0110] In an embodiment of the present application, the rate estimation preprocessing sub-circuit 310c receives the probability model table sent by the quantization sub-circuit 310b; according to the probability model table, the remaining available coding bits corresponding to each coefficient position of CG are calculated in parallel, and the remaining available coding bits and related data are sent to the first comparison sub-circuit 310d.

[0111] Exemplarily, the rate estimation preprocessing sub-circuit 310c uses the Ctx offset of each coefficient position of CG as an index, searches the probability model table, obtains the estimated number of bits of the corresponding syntax element, calculates the remaining available coding bits corresponding to the coefficient of each coefficient position in parallel, and sends the estimated number of bits and the remaining available coding bits to the first comparison sub-circuit 310d.

[0112] The first comparison sub-circuit 310d is used to calculate the distortion, code rate and rate-distortion cost of each coefficient position of CG in parallel when the coefficient is not adjusted, the coefficient is reduced by 1, and the coefficient is 0 based on the calculation result of the code rate estimation preprocessing sub-circuit 310c; based on the rate-distortion cost of each coefficient position of CG when the coefficient is not adjusted and the coefficient is reduced by 1, determine the second coefficient adjustment method; the second coefficient adjustment method is the adjustment method of each coefficient position of CG in the method of not adjusting the coefficient and the adjustment method of reducing the coefficient by 1, whichever has the smaller rate-distortion cost.

[0113] In an embodiment of the present application, when it is necessary to obtain the adjustment method of each CG in the TU, the computer device can obtain the various coefficient positions of the CG through the first comparison sub-circuit 310d and parallelly calculate the distortion (Dist), code rate (Rate) and rate-distortion cost (RD_cost) when the initial coefficient is not adjusted, the initial coefficient is -1, and the initial coefficient is set to 0; by comparing the RD_cost of each coefficient position when the initial coefficient is not adjusted and the initial coefficient is -1, the adjustment method corresponding to the smaller RD_cost is determined as the second coefficient adjustment method of the CG, and the RD_cost corresponding to the second coefficient adjustment method and the initial coefficient being set to 0 are sent to the second comparison sub-circuit 310e.

[0114] Exemplarily, the first comparison subcircuit 310d receives the estimated number of bits and the remaining available coding bits sent by the rate estimation preprocessing subcircuit 310c; and obtains input values corresponding to the calculated rate (Rate) in parallel based on the estimated number of bits and the remaining available coding bits.

[0115] The second comparison sub-circuit 310e is used to calculate the rate-distortion cost of the coefficients at each coefficient position of CG after adjustment according to the second coefficient adjustment method, and the rate-distortion cost after all the coefficients at each coefficient position of CG are set to 0; and the adjustment method with the smaller rate-distortion cost among the second coefficient adjustment method and the adjustment method of setting all the coefficients at each coefficient position of CG to 0 is determined as the first coefficient adjustment method.

[0116] In an embodiment of the present application, the second comparison sub-circuit 310e receives the second coefficient adjustment method of each coefficient position of the CG and the RD_cost corresponding to the initial coefficient set to 0 sent by the first comparison sub-circuit 310d; determines the adjustment method corresponding to the smaller RD_cost as the first coefficient adjustment method of each coefficient position of the CG, and sends the first coefficient adjustment method of each CG and related data to the non-zero coefficient position calculation circuit 320.

[0117] The present application provides a feasible solution for a coefficient adjustment circuit, implementing the coefficient adjustment circuit as a pipelined structure consisting of a starter subcircuit, a quantization subcircuit, a rate estimation preprocessing subcircuit, a first comparison subcircuit, and a second comparison subcircuit. Specifically, the starter subcircuit reads the unquantized coefficients and pre-fetches the probability model table from the RDO; the quantization subcircuit parallel-quantizes the unquantized coefficients in the CG to obtain the initial coefficients for each coefficient position; the rate estimation preprocessing subcircuit parallel-calculates the context index offset for the rate estimation of each coefficient position based on the coefficients of the neighborhood of each coefficient position; the rate estimation preprocessing subcircuit can also parallel-calculate the number of remaining available coding bits corresponding to each coefficient position based on the probability model table; the first comparison subcircuit determines the second coefficient adjustment method based on the rate-distortion cost corresponding to not adjusting the initial coefficient and reducing the initial coefficient by 1; the second comparison subcircuit determines the first coefficient adjustment method based on the rate-distortion cost corresponding to the second coefficient adjustment method and setting the initial coefficient to 0. This solution implements pipeline calculation to determine the first coefficient adjustment method, thereby enabling pipeline processing of the RDOQ process through hardware.

[0118] In some embodiments, the coefficient adjustment circuit 310 is also used to calculate and output the quantization error of each coefficient position in the CG, the bit rate after the coefficient at the coefficient position is increased, and the bit rate after the coefficient at the coefficient position is reduced.

[0119] In an embodiment of the present application, the computer device can also calculate the quantization error of each coefficient position in the CG, the bit rate after the initial coefficient of the coefficient position is increased, and the bit rate after the initial coefficient of the coefficient position is reduced through the coefficient adjustment circuit 310; and send the quantization error of each coefficient position, the bit rate after the initial coefficient of the coefficient position is increased, and the bit rate after the initial coefficient of the coefficient position is reduced to the non-zero coefficient position calculation circuit 320.

[0120] Exemplarily, the non-zero coefficient position calculation circuit 320 sends the quantization error of each coefficient position, the code rate after the initial coefficient of the coefficient position is +1, and the code rate after the initial coefficient of the coefficient position is -1 to the SBH adjustment circuit 330.

[0121] Exemplarily, the computer device calculates and outputs data such as the quantization error of each coefficient position in CG, the bit rate after the initial coefficient of the coefficient position is +1, and the bit rate after the initial coefficient of the coefficient position is -1 through the first comparison sub-circuit 310d and the second comparison sub-circuit 310e.

[0122] For example, the first comparison sub-circuit 310d obtains the corresponding distortion of each coefficient position in the CG through the inverse quantization process, and then the second comparison sub-circuit 310e can obtain the corresponding quantization error based on the distortion; the second comparison sub-circuit 310e calculates and outputs the bit rate corresponding to the initial coefficient +1 and the initial coefficient -1 of each coefficient position in the CG.

[0123] The non-zero coefficient position calculation circuit 320 is also used to calculate the coding rate of CG at the optimal last non-zero coefficient position, and the coding rate of CG when the coefficients of each coefficient position are all set to 0; and cumulatively calculate the rate-distortion cost of CG at the optimal last non-zero coefficient position, and the distortion when the coefficients of each coefficient position of CG are all set to 0.

[0124] In an embodiment of the present application, the non-zero coefficient position calculation circuit 320 can also calculate the Rate of CG at the optimal LastNonPos position and the Rate of CG when all coefficients at each coefficient position are set to 0 based on the optimal LastNonPos position; at the same time, the non-zero coefficient position calculation circuit 320 can also accumulate the rate-distortion cost (normal cost) of CG at the optimal last non-zero coefficient position and the distortion (Dist 0) when all coefficients at each coefficient position of CG are set to 0, and send the normal cost and Dist 0 corresponding to CG to the SBH adjustment circuit 330.

[0125] The SBH adjustment circuit 330 is used to determine whether the current TU is all 0 based on the calculation result of the non-zero coefficient position calculation circuit 320. If the current TU is not all 0, it determines the optimal SBH adjustment method for each coefficient position in the CG based on the rate-distortion cost when each coefficient position in the CG is increased or decreased, compares the SBH adjustment methods of each coefficient position of the CG, and determines the SBH adjustment method of the CG.

[0126] In the embodiment of the present application, the SBH adjustment circuit 330 may receive the calculation result sent by the non-zero coefficient position calculation circuit 320 and determine whether the current TU is all zero based on the normal cost and the RD_cost corresponding to Dist 0.

[0127] Among them, when the RD_cost corresponding to the normal cost is small, that is, the current TU is not all 0, the SBH adjustment circuit 330 can determine the optimal SBH adjustment method for each coefficient position in the CG according to the RD_cost corresponding to each coefficient position in the CG, increasing (such as coefficient +1) or decreasing (such as coefficient -1); and then determine the SBH adjustment method of the CG according to the SBH adjustment method of each coefficient position of the CG.

[0128] The embodiment of the present application determines a feasible solution for the SBH adjustment method of CG. By reusing some calculation results (such as bit rate, distortion, etc.) in the coefficient adjustment circuit and the non-zero coefficient position calculation circuit, it can save hardware resource consumption and reduce the calculation complexity of the SBH adjustment method.

[0129] In some embodiments, the first comparison sub-circuit 310d is configured to parallelly calculate the distortion when the coefficient is set to 0 for each coefficient position in the CG; and parallelly calculate the bit rate when the coefficient is +1 for each coefficient position in the CG; and parallelly calculate the bit rate when the coefficient is -1 for each coefficient position in the CG;

[0130] The second comparison sub-circuit 310e is used to calculate the quantization error for each coefficient position in the CG in parallel, and calculate the code rate after the coefficient is increased for each coefficient position in the CG in parallel; and calculate the code rate after the coefficient is reduced for each coefficient position in the CG in parallel based on the distortion when the coefficient is set to 0 at each coefficient position in the CG, the code rate after the coefficient is +1 at each coefficient position in the CG, and the code rate after the coefficient is -1 at each coefficient position in the CG calculated by the first comparison sub-circuit 310d.

[0131] In an embodiment of the present application, the first comparison sub-circuit 310d can calculate in parallel the Dist corresponding to the initial coefficients of each coefficient position in the CG set to 0; and send the above Dist data to the second comparison sub-circuit 310e.

[0132] The first comparison sub-circuit 310d can also calculate in parallel the rates corresponding to the initial coefficients +1 and -1 of each coefficient position in the CG; and send the above rate data to the second comparison sub-circuit 310e.

[0133] The second comparison sub-circuit 310e can receive the Dist data and Rate data sent by the first comparison sub-circuit 310d; calculate the quantization error (deltaU) in parallel based on the Dist data and Rate data; and send the quantization error (deltaU) data to the SBH adjustment circuit 330 through the non-zero coefficient position calculation circuit 320.

[0134] The second comparison sub-circuit 310e can also concurrently calculate the rates for each coefficient position in the CG after the coefficient is increased or decreased. The rates corresponding to the increased coefficients include the rates corresponding to the initial coefficient +1, and the rates corresponding to the decreased coefficients include the rates corresponding to the initial coefficient -1 and the rates corresponding to the initial coefficient being set to 0.

[0135] The present application implements a pipelined structure of the first comparison sub-circuit 310d and the second comparison sub-circuit 310e to achieve parallel calculation of the bit rate corresponding to the quantization error and the coefficient adjustment, thereby improving the timing performance of the RDOQ circuit component.

[0136] In some embodiments, the quantization sub-circuit 310b is used to send the initial coefficients of each coefficient position in the CG to the rate estimation preprocessing sub-circuit 310c when it is detected that the initial coefficients of each coefficient position in the CG are not all 0.

[0137] Among them, the initial coefficients of each coefficient position in the CG obtained by the quantization sub-circuit 310b may be all 0 or may not be all 0.

[0138] When the initial coefficients of each coefficient position in the CG obtained by the quantization sub-circuit 310b are not all 0, that is, when the initial coefficients of at least one coefficient position in the CG are not 0, the quantization sub-circuit 310b sends the initial coefficients of each coefficient position of the CG to the bit rate estimation preprocessing sub-circuit 310c to perform subsequent steps.

[0139] When the initial coefficients of each coefficient position in the CG obtained by the quantization sub-circuit 310b are all 0, the initial coefficients 0 of each coefficient position of the CG can be directly sent to the output circuit 340, skipping the subsequent intermediate steps.

[0140] The embodiment of the present application provides a feasible solution for the case where the initial coefficients are not all zero. After the quantization subcircuit 310b quantizes the positions of each coefficient in the CG, if the initial coefficients are not all zero, the subsequent steps are continued. This solution can improve the timing performance of the hardware circuit, thereby improving the parallel processing efficiency of the RDOQ circuit components.

[0141] based on Figure 4 For the example shown, please refer to Figure 6 , which shows a schematic structural diagram of an RDOQ circuit component provided by an exemplary embodiment of the present application, such as Figure 6 As shown above Figure 4 Output circuitry 340 is shown including a bypass queue 340a.

[0142] In some embodiments, the quantization subcircuit 310b is further configured to store the initial coefficients of each coefficient position of the CG into the bypass queue 340a in the output circuit 340 when detecting that the initial coefficients of each coefficient position in the CG are all 0;

[0143] The output circuit 340 is used to output the initial coefficients of each coefficient position of the CG in the bypass queue 340a as coefficients of each coefficient position of the CG when the initial coefficients of each coefficient position in the CG are all 0.

[0144] In an embodiment of the present application, when the initial coefficients of each coefficient position in the CG obtained by the quantization sub-circuit 310b are all 0, the quantization sub-circuit 310b stores the initial coefficient 0 of each coefficient position of the CG into the output circuit 340 through the bypass queue 340a without the need for calculation by other circuits.

[0145] Among them, the output circuit 340 can determine the initial coefficient 0 of each coefficient position of CG in the bypass queue 340a as the coefficient of each coefficient position of CG and output it in order.

[0146] Exemplarily, the output circuit 340 may store the initial coefficients of each coefficient position of the CG into a buffer.

[0147] The embodiment of the present application provides a feasible solution for the case where all initial coefficients are zero. After the quantization subcircuit 310b quantizes each coefficient position in the CG, if the initial coefficients are all zero, unnecessary hardware processes are skipped and the corresponding data is directly stored in the output circuit 340 through the bypass queue 340a. This solution can improve the timing performance of the hardware circuit, thereby improving the parallel processing efficiency of the RDOQ circuit components.

[0148] In some embodiments, as Figure 6 As shown above Figure 4 The output circuit 340 is shown to also include a normal queue 340b and a multiplexer 340c.

[0149] The output end of the bypass queue 340a is connected to one input end of the multiplexer 340c, and the output end of the normal queue 340b is connected to the other input end of the multiplexer 340c.

[0150] That is, the multiplexer 340c includes two input ends, one input end is connected to the output end of the bypass queue 340a, and the other input end is connected to the output end of the normal queue 340b; the multiplexer 340c can receive instructions / signals / data sent by the bypass queue 340a and the normal queue 340b.

[0151] a multiplexer 340c for outputting the coefficients of each coefficient position of the CG in the bypass queue 340a upon receiving a control signal indicating that the initial coefficients of each coefficient position in the CG are all zero;

[0152] The multiplexer 340c is also used to output the coefficients of each coefficient position of the CG in the normal queue 340b when a control signal indicating that the initial coefficients of each coefficient position in the CG are all 0 is not received, or when a control signal indicating that the initial coefficients of each coefficient position in the CG are not all 0 is received.

[0153] In an embodiment of the present application, the multiplexer 340c can not only output the coefficients of each coefficient position of the CG in the bypass queue 340a in order, but also output the coefficients of each coefficient position of the CG in the normal queue 340b in order.

[0154] Among them, the multiplexer 340c outputs the coefficients of each coefficient position of the CG in the bypass queue 340a, or in the normal queue 340b, or in the bypass queue 340a and the normal queue 340b according to the received control signal.

[0155] When the received control signal indicates that the initial coefficients of each coefficient position in the CG are all 0, the multiplexer 340c outputs the coefficients of each coefficient position of the CG in the bypass queue 340a in order; when the non-received control signal indicates that the initial coefficients of each coefficient position in the CG are all 0, the multiplexer 340c outputs the coefficients of each coefficient position of the CG in the normal queue 340b in order; when the received control signal indicates that the initial coefficients of each coefficient position in the CG are not all 0, the multiplexer 340c outputs the coefficients of each coefficient position of the CG in the normal queue 340b in order.

[0156] For example, when the processing flow of a CG is completed, the multiplexer 340c can output the coefficients of each coefficient position of the CG according to the scanning order in the coefficient adjustment circuit 310.

[0157] The embodiments of the present application provide a feasible solution for an output circuit, which realizes the input and output of data in a normal path and a bypass path through a multiplexer, reduces the complexity of RDOQ circuit component design, realizes efficient hardware arrangement, and saves hardware design resource consumption.

[0158] In some embodiments, the starting subcircuit 310a, the quantization subcircuit 310b, the rate estimation preprocessing subcircuit 310c, the first comparison subcircuit 310d, the second comparison subcircuit 310e, the non-zero coefficient position calculation circuit 320, the SBH adjustment circuit 330 and the output circuit 340 process the same CG in different pipeline stages respectively.

[0159] In an embodiment of the present application, the processing of the same CG by a computer device can be achieved through different pipeline stages.

[0160] Among them, the above-mentioned pipeline stages correspond to the processing flow of the starting subcircuit 310a, the quantization subcircuit 310b, the code rate estimation preprocessing subcircuit 310c, the first comparison subcircuit 310d, the second comparison subcircuit 310e, the non-zero coefficient position calculation circuit 320, the SBH adjustment circuit 330 and the output circuit 340 in sequence.

[0161] For example, the scanning order is CG1, CG2, CG3, ... CGn. For example, after the starter sub-circuit 310a completes the processing flow for CG1, CG1 can enter the processing flow corresponding to the quantization sub-circuit 310b. At this time, the starter sub-circuit 310a can proceed to the processing flow of the next CG2. After the quantization sub-circuit 310b completes the processing flow for CG1, CG1 can enter the processing flow of the bit rate estimation pre-processing sub-circuit 310c. At this time, CG2 can enter the processing flow of the quantization sub-circuit 310b. The starter sub-circuit 310a can proceed to the processing flow of the next CG3. This process continues in this way until the output circuit 340 completes the processing flow for CGn.

[0162] The embodiment of the present application realizes parallel processing of each transform coefficient in CG through reasonable hardware design, thereby realizing pipeline processing of the RDOQ process, greatly improving the processing efficiency of the RDOQ process.

[0163] In summary, this application proposes a hardware implementation of RDOQ suitable for the H.265 / H.266 encoding protocol. By using a probability model updated in real time by RDO, an accurate and fast bit rate estimation is achieved using a table lookup method. And the computational dependency within / between CGs is broken, and parallel processing of 16 transform coefficients within CGs and pipeline processing between CGs are achieved. Finally, through efficient hardware pipeline arrangement, pipeline processing of coefficient adjustment within CGs, judgment of all 0 CGs, and judgment of the last non-zero coefficient position (lastNonPos) of TUs is achieved. At the same time, the intermediate calculation results of RDOQ are reused, and the sign bit can be conveniently hidden and embedded in RDOQ. While saving hardware resources, it also ensures the maximization of hardware throughput efficiency and algorithm benefits.

[0164] Please refer to Figure 7 , which shows a schematic diagram of the H.265 / H.266 universal RDOQ hardware processing architecture provided by an exemplary embodiment of the present application. The entire hardware architecture is divided into 8 pipeline stages, and the processing unit is CG. The specific hardware design can flexibly determine the RDOQ throughput and processing delay based on resource consumption, the computational complexity of each pipeline stage, and the supported encoding protocols.

[0165] Please refer to Figure 8 , which shows an RDOQ calculation flow chart suitable for hardware processing provided by an exemplary embodiment of the present application. It is not difficult to find that the hardware processing flow no longer has the problem of nested loops. Since there are no cyclic dependencies, the hardware can use pipeline processing to process different steps.

[0166] like Figure 7 As shown, the specific processing content of each pipeline level is as follows:

[0167] S0: At the front end of the pipeline, it controls the activation of RDOQ, reads unquantized coefficients from the previous stage, and pre-fetches the corresponding probability model table from RDO based on the current TU information (size, partition type, brightness and chroma). It also determines the configuration parameters required for the current TU calculation (such as quantizer parameter (QP) and luminance (lambda)).

[0168] S1: Perform scalar quantization on the 16 coefficients in CG.

[0169] Among them, such as Figure 8 As shown in step B1, the TU is divided into 4×4 coefficient groups (CGs), and then scalar quantization is performed in the agreed scanning order (at least one of diagonal, horizontal, and vertical) to obtain the initial transform coefficient (init_coefficient) corresponding to each position; the hardware design is performed in units of CG, and 16 positions within the CG are calculated in parallel.

[0170] After CG quantization, a judgment is made. If all 16 coefficients are 0, the subsequent S2 to S6 are skipped and the result is directly stored in the bypass queue (bypass fifo) of S7 through the bypass path.

[0171] S2: Read / update the neighborhood information of CG / coefficient (the neighborhood information is only related to the calculation result of S1). Calculate the Ctx_offset required for the coefficient bit rate estimation based on the neighborhood information of each position, and look up the probability model table to get the estimated number of bits of the corresponding syntax element (the syntax elements of H.265 are sig / gt1 / gt2, and the syntax elements of H.266 are sig / gt1 / par / gt3). Calculate the remaining available coding bits corresponding to each coefficient (H.265 sets a maximum of the first 8 coefficients for each CG, and H.266 sets a maximum of 1.74×N-4 syntax elements for all CGs, where N is the TU size) for subsequent bit rate estimation.

[0172] Among them, such as Figure 8 As shown in step B2, for the Ctx dependencies of the 16 coefficients within and between CGs, the hardware implementation no longer relies on the adjusted results of each CG, but instead directly utilizes the results calculated in step B1. Therefore, the corresponding Ctx offsets of the 16 coefficients within a CG can be obtained in parallel based on these results.

[0173] S3: Adjust the coefficients for each position within the CG (CG normal), calculate the distortion and rate for the unadjusted coefficients, the coefficients minus 1, and the coefficients equal to 0, and calculate the RD_cost. Compare the optimal adjustment method for the current position between the unadjusted coefficients and the coefficients minus 1.

[0174] Among them, such as Figure 8 As shown in step B3, within each position, multiple candidate coefficients are used in parallel to calculate the bit rate based on the S2 result (estimated number of bits and the remaining available coding bits). At the same time, the recovered coefficients are obtained by the dequantization process, and the corresponding distortion is obtained by subtracting the recovered coefficients from the pre-quantization values and squaring them. The Lagrange formula is then used to obtain the corresponding RD_cost. Multiple candidate coefficients are used to select the optimal coefficient after adjustment for the current position based on the size of the RD_cost. In terms of hardware design, the candidate coefficient values for each position are constructed according to the following rules:

[0175] If the initial init_coefficient = 0, the position is not adjusted and the optimal coefficient = 0;

[0176] Otherwise, the candidate coefficient for this position contains three values: init_coefficient / init_coefficient-1 / 0. Among them, only init_coefficient / init_coefficient-1 participate in the RD_cost PK, and the RD_cost of 0 will be used in subsequent processes.

[0177] S4: Calculate the RD_cost after adjusting the CG coefficient and the RD_cost of CG all zero, and select the best between CG normal and CG all zero. At the same time, calculate the rate and quantization error (deltaU) of coefficient+1 / coefficient-1 at each CG position (prepared for SBH in S6).

[0178] The rate calculation method varies depending on the protocol. In the H.265 / H.266 protocols, entropy coding specifies a corresponding binarization method for each syntax element to be encoded (converting the input value into a binary string according to specific rules). The rate calculation process in S4 is to implement the binarization method of the coefficient syntax element. Then, based on the binarization result, combined with the estimated number of bits and the number of remaining available coding bits, the corresponding algorithm is performed to obtain the final rate.

[0179] Among them, such as Figure 8 As shown in step B4, for the adjusted CG, force all 16 positions to be set to 0, and calculate the corresponding RDcost (since step B3 has calculated the RD_cost with coefficient = 0, step B4 only needs to accumulate the results of 16 positions), and then compare it with the RD_cost corresponding to the non-all-0 CG obtained above to determine whether the current CG is all set to 0.

[0180] S5: Calculate the rate and rate-distortion cost delta (delta_cost) for each non-zero coefficient position in the CG as the LastNonPos, and then perform a PK to determine the optimal LastNonPos position. Calculate the rate of the syntax element (root_cbf / cbf) and accumulate the normal cost and Dist 0 for each CG (to prepare for the PK of TU normal and TU all zero in S6).

[0181] The calculation process of Rate is referred to S4 and will not be repeated here. The calculation process of delta_cost is equivalent to the calculation of the LastNonPos position (by Figure 2 The cumulative sum of the RD_costs of all positions with the coefficient set to 0 (in the scan order).

[0182] Among them, such as Figure 8 As shown in step B5, the LastNonPos judgment of the hardware design of this application does not need to wait until all CGs of the entire TU are adjusted before proceeding, because this application performs PK through the relative change of RD_cost (instead of the actual RD_cost), so it can form a pipeline with the previous steps, avoiding the caching of a large number of intermediate results, and also reducing hardware processing delays.

[0183] The adjustment of the last position (Last Position) is to sequentially use each non-zero position as the last non-zero coefficient (LastNonPos) and calculate the corresponding RD_cost at this time.

[0184] Assume that the RD_cost corresponding to all CGs in the entire TU after adjustment is base_cost. If a non-zero position A is used as LastNonPos, it means that the values of all positions before A (that is, before the agreed scan order) are set to 0, and the values of all positions after A (that is, after the agreed scan order) remain unchanged. Therefore, the corresponding RD_cost when A is used as LastNonPos can be derived from base_cost:

[0185] RD_cost A =base_cost+RD_cost A_add -RD_cost A_unuse -delta_RD_cost post_A

[0186] Among them, RD_cost A_add Indicates the RD_cost corresponding to the newly added syntax element that needs to be represented in the code stream when A is used as LastNonPos, RD_cost A_unuse Indicates that when A is used as LastNonPos, the RD_cost and delta_RD_cost corresponding to the syntax element no longer need to be represented in the code stream post_A Indicates the RD_cost change required for all positions before A to change from normal to 0.

[0187] Correspondingly, if another position B is used as LastNonPos, its corresponding RD_cost is:

[0188] RD_cost B =base_cost+RD_cost B_add -RD_cost B_unuse -delta_RD_cost post_B

[0189] Among them, RD_cost B_add Indicates the RD_cost corresponding to the newly added syntax element that needs to be represented in the code stream when B is used as LastNonPos, RD_cost B_unuse Indicates that when B is used as LastNonPos, the RD_cost and delta_RD_cost corresponding to the syntax element no longer need to be represented in the code stream post_B Indicates the RD_cost change required for all positions before B to change from normal to 0.

[0190] Among them, RD_cost A_add and RD_cost B_add correspond Figure 5The calculation result of LastNonPos bit rate in S5, delta_RD_cost post_A and delta_RD_cost post_B correspond Figure 5 The calculation results of delta_cost in S5, RD_cost A_unuse and RD_cost B_unuse correspond Figure 5 The coefficient calculated in S3 does not adjust an intermediate variable corresponding to RD_cost, and the corresponding data can be passed to S5.

[0191] Comparing A and B as the better LastNonPos is to compare RD_cost A and RD_cost B The size of A and B has nothing to do with the value of base_cost. The value of base_cost depends on all CGs being adjusted before it can be calculated. A_add 、RD_cost A_unuse 、delta_RD_cost post_A 、RD_cost B_add 、RD_cost B_unuse 、delta_RD_cost post_B The values are all the corresponding results of the positions before the LastNonPos scan order, and the processing order of RDOQ is in accordance with the scan order, so the above values are naturally prepared when processing a certain position.

[0192] Therefore, the Last Position adjustment process in the hardware design directly ignores the value of base_cost. Therefore, the calculated RD_cost is not the exact RD_cost, but the change relative to base_cost. Therefore, the hardware Last Position adjustment process can be CG-pipelined with the previous step.

[0193] S6: Determine whether the current TU is all zero by comparing the normal adjustment RD_cost (TUnormal cost) and the RD_cost with a coefficient of 0 (TUall zerocost). Calculate the cost of each coefficient +1 / -1 in the CG, compare the optimal SBH adjustment method for each coefficient, and then compare all 16 coeffs to obtain the optimal SBH adjustment method for the current CG.

[0194] Among them, such as Figure 8As shown in step B6, SBH needs to adjust one of the coefficients in CG (for example, value +1 or value -1). Since SBH is also calculated in units of CG, it is necessary to calculate the cost change delta_RD_cost after the adjustment of the corresponding position during the coefficient adjustment process, which includes two parts: delta_D (relative change in distortion) and delta_R (relative change in bit rate), where: delta_D = D_(coeff+1)-D_coeff, delta_R = R_(coeff+1-R_coeff, and D_coeff and R_coeff have been calculated in the aforementioned step B3, and the information (quantization parameter QP, Context, etc.) on which the calculation of D_(coeff+1) and R_(coeff+1) depends is also prepared in the aforementioned steps B2 and B3. Therefore, the calculation of SBH can be pre-calculated in advance using the existing results in the RDOQ stage. On the one hand, some calculation results can be reused to reduce hardware resource consumption, and on the other hand, the calculation time of the entire SBH can be shortened.

[0195] At the same time, since the RDOQ stage calculates both the optimal adjusted RD_cost and the RD_cost of adjusting the coefficient to 0 when making each coefficient adjustment, the two RD_costs of each position can be accumulated in parallel in the SBH stage, and finally the RD_cost of the entire TU is obtained. It is then decided whether to set the entire TU to 0 at the end of the TU.

[0196] S7: Cache the CG coefficients processed by the normal path and the CG coefficients of the bypass path. When the last CG in the TU is processed, it is output in order through the multiplexer (MUX) in the scan order.

[0197] Among them, such as Figure 8 As shown in step B7, if the last CG is not processed, the results of the CG will be cached and output uniformly when the last CG is processed.

[0198] The technical solution of this application takes hardware implementation as the starting point. By considering the entire process of RDOQ and SBH, an RDOQ hardware structure with high throughput and high compression rate suitable for hardware implementation is designed.

[0199] This application can be embedded in the implementation of various video coding protocols, such as H.265 / H.266, and can improve video encoding quality by 4% to 6%. It can then be widely used in various video application products such as live broadcast, on-demand, and cloud gaming, while reducing video transmission bandwidth while ensuring unchanged video quality.

[0200] The hardware RDOQ architecture proposed in this application can achieve similar benefits to software RDOQ on both H.265 and H.266 encoding protocols, while still having higher processing performance on the hardware encoder and significantly improving the hardware encoding quality.

[0201] For the results on the H.265 encoding protocol, please refer to Table 1 and Table 2 (the baseline is with RDOQ disabled, and the comparison is with RDOQ enabled):

[0202] As shown in Table 1, the BD-rate gains of software RDOQ under Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity (SSIM) are 7.8% for PSNR and 4.2% for SSIM.

[0203] As shown in Table 2, the BD-rate benefits of hardware RDOQ under PSNR and SSIM are 7.37% for PSNR and 3.5% for SSIM.

[0204] As can be seen from the table, on the H.265 encoding protocol, the benefits of the hardware RDOQ implementation are similar to those of the software RDOQ.

[0205] Table 1

[0206]

[0207] Table 2

[0208]

[0209]

[0210] Please refer to Table 3 and Table 4 for the results on the H.266 encoding protocol. Table 3 shows a performance comparison table of hardware RDOQ and software RDOQ on the H.266 encoding protocol provided by an exemplary embodiment of the present application. Table 3 shows the hardware RDOQ benefit on the H.266 encoding protocol provided by an exemplary embodiment of the present application.

[0211] Table 3 shows a performance comparison between hardware RDOQ and software RDOQ. Hardware RDOQ suffers a 0.15% PSNR difference and a 0.24% SSIM difference compared to software RDOQ. Table 4 shows the BD-rate gains of hardware RDOQ in terms of PSNR and SSIM (the baseline is with RDOQ enabled, while the comparison is with RDOQ disabled). The PSNR gain is 4.66% and the SSIM gain is 2.28%. As can be seen from the table, for the H.266 encoding protocol, the gains achieved by the hardware RDOQ implementation are similar to those achieved by software RDOQ.

[0212] Table 3

[0213]

[0214] Table 4

[0215]

[0216]

[0217] Please refer to Figure 9 , which shows a flow chart of a rate-distortion optimized quantization method provided by an exemplary embodiment of the present application. The method is executed by the above-mentioned RDOQ circuit component in a pipeline manner, and the method includes the following steps:

[0218] In step 910, a coefficient adjustment circuit calculates and outputs a first coefficient adjustment method for the CG in a transform unit (TU). The first coefficient adjustment method is the optimal solution between a method of adjusting the coefficients of each coefficient position of the CG one by one and a method of setting all coefficients of each coefficient position of the CG to zero.

[0219] Step 920: Calculate, by the non-zero coefficient position calculation circuit and based on the output result of the coefficient adjustment circuit, the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and the rate-distortion cost variation before and after each non-zero coefficient position in the CG is the last non-zero coefficient position; determine the optimal last non-zero coefficient position in the CG based on the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and the rate-distortion cost variation before and after each non-zero coefficient position in the CG is the last non-zero coefficient position;

[0220] Step 930: Determine the SBH adjustment method of the CG based on the calculation result of the non-zero coefficient position calculation circuit through the SBH adjustment circuit;

[0221] Step 940: Output the coefficients of each coefficient position of CG based on the output result of the SBH adjustment circuit through the output circuit.

[0222] In some embodiments, the above Figure 9 The illustrated method further includes:

[0223] By starting the subcircuit, the unquantized coefficients corresponding to each coefficient position in the TU are read, and the probability model table corresponding to the TU is pre-fetched from the RDO; and the configuration parameters required for the RDOQ calculation of the TU are determined;

[0224] Through the quantization subcircuit, each coefficient position of CG is quantized in parallel with CG as a unit to obtain the initial coefficient of each coefficient position of CG;

[0225] The rate estimation preprocessing subcircuit calculates the context index offset of the rate estimation of each coefficient position of the CG in parallel based on the coefficients of the neighborhood of each coefficient position of the CG; and the number of remaining available coding bits corresponding to each coefficient position of the CG is calculated in parallel based on the probability model table;

[0226] The first comparison subcircuit calculates, based on the calculation result of the rate estimation preprocessing subcircuit, the distortion, rate, and rate-distortion cost of each coefficient position of the CG in parallel when the coefficient is not adjusted, the coefficient is reduced by 1, and the coefficient is 0; based on the rate-distortion cost of each coefficient position of the CG when the coefficient is not adjusted and the coefficient is reduced by 1, a second coefficient adjustment method is determined; the second coefficient adjustment method is an adjustment method corresponding to a smaller rate-distortion cost among the adjustment methods of the coefficient not adjusted and the coefficient reduced by 1 for each coefficient position of the CG;

[0227] Through the second comparison sub-circuit, the rate-distortion cost of the coefficients at each coefficient position of CG after adjustment according to the second coefficient adjustment method, as well as the rate-distortion cost after all the coefficients at each coefficient position of CG are set to 0, are calculated; the adjustment method with the smaller rate-distortion cost among the second coefficient adjustment method and the adjustment method of setting all the coefficients at each coefficient position of CG to 0 is determined as the first coefficient adjustment method.

[0228] In some embodiments, the above Figure 9 The illustrated method further includes:

[0229] Through the coefficient adjustment circuit, the quantization error of each coefficient position in the CG, the code rate after the coefficient at the coefficient position is increased, and the code rate after the coefficient at the coefficient position is reduced by -1 are calculated and output;

[0230] The coding rate of CG at the optimal last non-zero coefficient position and the coding rate of CG when all coefficients at each coefficient position are set to 0 are calculated through the non-zero coefficient position calculation circuit; the rate-distortion cost of CG at the optimal last non-zero coefficient position and the distortion when all coefficients at each coefficient position of CG are set to 0 are cumulatively calculated;

[0231] Through the SBH adjustment circuit, based on the calculation results of the non-zero coefficient position calculation circuit, determine whether the current TU is all 0. If the current TU is not all 0, based on the rate-distortion cost of increasing and decreasing each coefficient position in the CG, determine the optimal SBH adjustment method for each coefficient position in the CG, compare the SBH adjustment methods of each coefficient position of the CG, and determine the SBH adjustment method of the CG.

[0232] In some embodiments, the above Figure 9 The illustrated method further includes:

[0233] The first comparison sub-circuit calculates the distortion of each coefficient position in the CG in parallel when the coefficient is set to 0; and calculates the bit rate of each coefficient position in the CG after the coefficient is +1; and calculates the bit rate of each coefficient position in the CG after the coefficient is -1;

[0234] Through the second comparison sub-circuit, based on the distortion calculated by the first comparison sub-circuit when the coefficient at each coefficient position in the CG is set to 0, the bit rate after the coefficient at each coefficient position in the CG is +1, and the bit rate after the coefficient at each coefficient position in the CG is -1, the quantization error is calculated in parallel for each coefficient position in the CG, the bit rate after the coefficient is increased is calculated in parallel for each coefficient position in the CG; and the bit rate after the coefficient is reduced is calculated in parallel for each coefficient position in the CG.

[0235] In some embodiments, the above Figure 9 The illustrated method further includes:

[0236] Through the quantization sub-circuit, when it is detected that the initial coefficients of each coefficient position in the CG are not all 0, the initial coefficients of each coefficient position of the CG are sent to the bit rate estimation preprocessing sub-circuit.

[0237] In some embodiments, the above Figure 9 The illustrated method further includes:

[0238] When the initial coefficients of the coefficient positions in the CG are all detected to be 0 by the quantization subcircuit, the initial coefficients of the coefficient positions in the CG are stored in the bypass queue in the output circuit;

[0239] Through the output circuit, when the initial coefficients of each coefficient position in the CG are all 0, the initial coefficients of each coefficient position of the CG in the bypass queue are output as the coefficients of each coefficient position of the CG.

[0240] In some embodiments, the above Figure 9 The illustrated method further includes:

[0241] Outputting the coefficients of each coefficient position of the CG in the bypass queue through the multiplexer upon receiving a control signal indicating that the initial coefficients of each coefficient position in the CG are all 0;

[0242] Through the multiplexer, when a control signal indicating that the initial coefficients of each coefficient position in the CG are all 0 is not received, or when a control signal indicating that the initial coefficients of each coefficient position in the CG are not all 0 is received, the coefficients of each coefficient position of the CG in the normal queue are output.

[0243] In some embodiments, the above Figure 9 The illustrated method further includes:

[0244] The same CG is processed in different pipeline stages through the starting subcircuit, quantization subcircuit, code rate estimation preprocessing subcircuit, first comparison subcircuit, second comparison subcircuit, non-zero coefficient position calculation circuit, SBH adjustment circuit and output circuit.

[0245] The embodiment of the present application further provides a chip, the chip comprising: at least one of the above Figure 3 、 Figure 4 as well as Figure 6 Any of the RDOQ circuit components shown.

[0246] The embodiment of the present application further provides a computer device, the computer device comprising: at least one chip, the chip including at least one of the above Figure 3 、 Figure 4 as well as Figure 6 Any of the RDOQ circuit components shown.

[0247] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A rate-distortion optimized quantization (RDOQ) circuit component, characterized in that: The RDOQ circuit assembly includes: a coefficient adjustment circuit, a non-zero coefficient position calculation circuit, an SBH adjustment circuit and an output circuit; The coefficient adjustment circuit, the non-zero coefficient position calculation circuit, the SBH adjustment circuit and the output circuit are connected in sequence; The coefficient adjustment circuit is configured to calculate and output a first coefficient adjustment mode for the CG in a TU; the first coefficient adjustment mode is an optimal solution between a mode in which coefficients at each coefficient position of the CG are adjusted one by one and a mode in which all coefficients at each coefficient position of the CG are set to zero; The non-zero coefficient position calculation circuit is configured to calculate, based on an output result of the coefficient adjustment circuit, a coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and a rate-distortion cost variation before and after each non-zero coefficient position in the CG is the last non-zero coefficient position; determine an optimal last non-zero coefficient position in the CG based on the coding rate when each non-zero coefficient position in the CG is the last non-zero coefficient position, and the rate-distortion cost variation before and after each non-zero coefficient position in the CG is the last non-zero coefficient position; The SBH adjustment circuit is used to determine the SBH adjustment method of the CG based on the calculation result of the non-zero coefficient position calculation circuit; The output circuit is used to output the coefficients of each coefficient position of the CG based on the output result of the SBH adjustment circuit.

2. The RDOQ circuit assembly according to claim 1, wherein: The coefficient adjustment circuit includes: a start subcircuit, a quantization subcircuit, a code rate estimation preprocessing subcircuit, a first comparison subcircuit and a second comparison subcircuit; The start subcircuit, the quantization subcircuit, the rate estimation preprocessing subcircuit, the first comparison subcircuit and the second comparison subcircuit are connected in sequence; The startup subcircuit is configured to read the unquantized coefficients corresponding to the coefficient positions in the TU, pre-fetch the probability model table corresponding to the TU from the RDO, and determine the configuration parameters required for RDOQ calculation of the TU; The quantization subcircuit is used to quantize each coefficient position of the CG in parallel with the CG as a unit to obtain the initial coefficient of each coefficient position of the CG; The rate estimation preprocessing subcircuit is configured to calculate, in parallel, context index offsets for rate estimation of each coefficient position of the CG based on coefficients of neighborhoods of each coefficient position of the CG; and, based on the probability model table, calculate, in parallel, the number of remaining available coding bits corresponding to each coefficient position of the CG; The first comparison subcircuit is configured to, based on the calculation result of the rate estimation preprocessing subcircuit, concurrently calculate the distortion, rate, and rate-distortion cost for each coefficient position of the CG when the coefficient is not adjusted, the coefficient is reduced by 1, and the coefficient is 0; determine a second coefficient adjustment method based on the rate-distortion cost for each coefficient position of the CG when the coefficient is not adjusted and when the coefficient is reduced by 1; the second coefficient adjustment method is an adjustment method corresponding to a smaller rate-distortion cost among the adjustment methods of the coefficients of each coefficient position of the CG when the coefficients are not adjusted and when the coefficients are reduced by 1; The second comparison sub-circuit is used to calculate the rate-distortion cost of the coefficients at each coefficient position of the CG after being adjusted according to the second coefficient adjustment method, and the rate-distortion cost after all the coefficients at each coefficient position of the CG are set to 0; and determine the adjustment method with the smaller rate-distortion cost among the second coefficient adjustment method and the adjustment method of setting all the coefficients at each coefficient position of the CG to 0 as the first coefficient adjustment method.

3. The RDOQ circuit assembly according to claim 2, wherein: The coefficient adjustment circuit is further configured to calculate and output the quantization error of each coefficient position in the CG, the bit rate after the coefficient at the coefficient position is increased, and the bit rate after the coefficient at the coefficient position is reduced; The non-zero coefficient position calculation circuit is further used to calculate the coding rate of the CG at the optimal last non-zero coefficient position, and the coding rate of the CG when the coefficients of each coefficient position are all set to 0; cumulatively calculate the rate-distortion cost of the CG at the optimal last non-zero coefficient position, and the distortion when the coefficients of each coefficient position of the CG are all set to 0; The SBH adjustment circuit is used to determine whether the current TU is all 0 based on the calculation result of the non-zero coefficient position calculation circuit. If the current TU is not all 0, the optimal SBH adjustment method for each coefficient position in the CG is determined based on the rate-distortion cost when each coefficient position in the CG is increased or decreased, and the SBH adjustment methods of each coefficient position of the CG are compared to determine the SBH adjustment method of the CG.

4. The RDOQ circuit assembly according to claim 3, wherein: The first comparison sub-circuit is used to parallelly calculate the distortion of each coefficient position in the CG when the coefficient is set to 0; and parallelly calculate the bit rate of each coefficient position in the CG after the coefficient is increased by 1; Parallel calculation of the bit rate after coefficient -1 for each coefficient position in the CG; The second comparison sub-circuit is used to calculate the quantization error for each coefficient position in the CG in parallel, calculate the code rate after the coefficient is increased for each coefficient position in the CG in parallel, and calculate the code rate after the coefficient is reduced for each coefficient position in the CG in parallel based on the distortion when the coefficient is set to 0 at each coefficient position in the CG, the code rate after the coefficient is increased at each coefficient position in the CG, and the code rate after the coefficient is reduced for each coefficient position in the CG.

5. The RDOQ circuit assembly according to claim 3, wherein: The quantization sub-circuit is used to send the initial coefficients of each coefficient position of the CG to the bit rate estimation preprocessing sub-circuit when it is detected that the initial coefficients of each coefficient position in the CG are not all 0.

6. The RDOQ circuit assembly according to claim 5, wherein: The quantization subcircuit is further configured to store the initial coefficients of each coefficient position of the CG into a bypass queue in the output circuit when detecting that the initial coefficients of each coefficient position in the CG are all 0; The output circuit is used to output the initial coefficients of each coefficient position of the CG in the bypass queue as coefficients of each coefficient position of the CG when the initial coefficients of each coefficient position in the CG are all 0.

7. The RDOQ circuit assembly according to claim 6, wherein: The output circuit also includes a normal queue and a multiplexer; The output end of the bypass queue is connected to one input end of the multiplexer, and the output end of the normal queue is connected to the other input end of the multiplexer; The multiplexer is configured to output the coefficients of each coefficient position of the CG in the bypass queue upon receiving a control signal indicating that the initial coefficients of each coefficient position in the CG are all 0; The multiplexer is also used to output the coefficients of each coefficient position of the CG in the normal queue when it does not receive a control signal indicating that the initial coefficients of each coefficient position in the CG are all 0, or when it receives a control signal indicating that the initial coefficients of each coefficient position in the CG are not all 0.

8. The RDOQ circuit assembly according to claim 2, wherein: The starting subcircuit, the quantization subcircuit, the bit rate estimation preprocessing subcircuit, the first comparison subcircuit, the second comparison subcircuit, the non-zero coefficient position calculation circuit, the SBH adjustment circuit and the output circuit process the same CG in different pipeline stages respectively.

9. A rate-distortion optimization quantization method, characterized in that: The method is performed by the RDOQ circuit component according to any one of claims 1 to 8 in a pipeline manner, and the method includes: The coefficient adjustment circuit calculates and outputs a first coefficient adjustment method for the CG in the TU; the first coefficient adjustment method is an optimal solution between a method of adjusting coefficients at each coefficient position of the CG one by one and an adjustment method of setting all coefficients at each coefficient position of the CG to 0; By means of the non-zero coefficient position calculation circuit, based on the output result of the coefficient adjustment circuit, a coding rate when each non-zero coefficient position in the CG is used as the last non-zero coefficient position, and a rate-distortion cost variation before and after each non-zero coefficient position in the CG is used as the last non-zero coefficient position are calculated; based on the coding rate when each non-zero coefficient position in the CG is used as the last non-zero coefficient position, and a rate-distortion cost variation before and after each non-zero coefficient position in the CG is used as the last non-zero coefficient position, an optimal last non-zero coefficient position in the CG is determined; Determining, by the SBH adjustment circuit, an SBH adjustment method of the CG based on a calculation result of the non-zero coefficient position calculation circuit; Through the output circuit, the coefficients of each coefficient position of the CG are output based on the output result of the SBH adjustment circuit.

10. The method according to claim 9, characterized in that The method further comprises: Reading, through the startup subcircuit, unquantized coefficients corresponding to respective coefficient positions in the TU, pre-fetching a probability model table corresponding to the TU from the RDO; and determining configuration parameters required for RDOQ calculation of the TU; By means of the quantization subcircuit, each coefficient position of the CG is quantized in parallel with the CG as a unit to obtain an initial coefficient of each coefficient position of the CG; The rate estimation preprocessing sub-circuit calculates, in parallel, the context index offsets of the rate estimation of each coefficient position of the CG based on the coefficients of the neighborhood of each coefficient position of the CG; and, based on the probability model table, calculates in parallel the number of remaining available coding bits corresponding to each coefficient position of the CG; The first comparison sub-circuit calculates, based on the calculation result of the rate estimation preprocessing sub-circuit, the distortion, rate, and rate-distortion cost of each coefficient position of the CG in parallel when the coefficient is not adjusted, the coefficient is reduced by 1, and the coefficient is 0; based on the rate-distortion cost of each coefficient position of the CG when the coefficient is not adjusted and the coefficient is reduced by 1, a second coefficient adjustment method is determined; the second coefficient adjustment method is an adjustment method corresponding to a smaller rate-distortion cost among the adjustment method of each coefficient position of the CG when the coefficient is not adjusted and the adjustment method of each coefficient position of the CG when the coefficient is reduced by 1; Through the second comparison sub-circuit, the rate-distortion cost of the coefficients at each coefficient position of the CG after adjustment according to the second coefficient adjustment method, and the rate-distortion cost after all the coefficients at each coefficient position of the CG are set to 0 are calculated; and the adjustment method with the smaller rate-distortion cost among the second coefficient adjustment method and the adjustment method of setting all the coefficients at each coefficient position of the CG to 0 is determined as the first coefficient adjustment method.

11. The method according to claim 9, characterized in that The method further comprises: Calculate and output the quantization error of each coefficient position in the CG, the bit rate after the coefficient at the coefficient position is increased, and the bit rate after the coefficient at the coefficient position is reduced by -1 through the coefficient adjustment circuit; The non-zero coefficient position calculation circuit is used to calculate the coding rate of the CG at the optimal last non-zero coefficient position and the coding rate of the CG when all coefficients at each coefficient position are set to 0; the rate-distortion cost of the CG at the optimal last non-zero coefficient position and the distortion when all coefficients at each coefficient position of the CG are set to 0 are cumulatively calculated; Through the SBH adjustment circuit, based on the calculation results of the non-zero coefficient position calculation circuit, it is determined whether the current TU is all 0. If the current TU is not all 0, based on the rate-distortion cost when each coefficient position in the CG is increased and decreased, the optimal SBH adjustment method for each coefficient position in the CG is determined, and the SBH adjustment methods of each coefficient position of the CG are compared to determine the SBH adjustment method of the CG.

12. The method according to claim 9, characterized in that The method further comprises: When it is detected by the quantization subcircuit that the initial coefficients of the coefficient positions in the CG are all 0, the initial coefficients of the coefficient positions in the CG are stored in the bypass queue in the output circuit; Through the output circuit, when the initial coefficients of each coefficient position in the CG are all 0, the initial coefficients of each coefficient position of the CG in the bypass queue are output as the coefficients of each coefficient position of the CG.

13. The method according to claim 9, characterized in that The method further comprises: Outputting, through the multiplexer, the coefficients of the respective coefficient positions of the CG in the bypass queue upon receiving a control signal indicating that the initial coefficients of the respective coefficient positions in the CG are all 0; Through the multiplexer, when a control signal indicating that the initial coefficients of each coefficient position in the CG are all 0 is not received, or when a control signal indicating that the initial coefficients of each coefficient position in the CG are not all 0 is received, the coefficients of each coefficient position of the CG in the normal queue are output.

14. A chip, characterized in that: The chip comprises: at least one RDOQ circuit component according to any one of claims 1 to 8.

15. A computer device, characterized in that: The computer device comprises: at least one chip, wherein the chip comprises at least one RDOQ circuit component according to any one of claims 1 to 8.

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