TV board card circuit with CA interface and CA working method

Abstract

The invention discloses a TV board card circuit with a CA interface and a CA working method, and belongs to the technical field of TV board card circuits, the TV board card circuit comprises a chip CPU and a CA interface coupled with the chip CPU, the CA interface comprises a CHIP chip circuit, a CA card interface circuit and a UART TO IO circuit, the CHIP chip circuit is coupled with the CA card interface circuit and the UART TO IO circuit, a chip performs data interaction with external equipment through the UART TO IO circuit, the CA card interface circuit is connected with the chip CPU, and the CA interface circuit is connected with the chip CPU. And the CHIP chip circuit is used for interacting with various cards, providing control signals and power supplies for the various cards through the CA card interface circuit, and carrying out read-write operation and state detection on the cards.

Description

Technical Field

[0001] The present invention relates to a TV board circuit, in particular to a TV board circuit with a CA interface and a CA working method, belonging to the technical field of TV board circuits. Background Art

[0002] In the TV motherboard market, CI interface dominates.

[0003] However, the CI interface has obvious cost issues. The corresponding CI module is expensive, ranging from tens to hundreds of US dollars depending on the type of supported cards.

[0004] This high cost increases the overall price of television equipment and increases the purchasing burden for consumers.

[0005] At the same time, the application scenarios of CI interfaces are relatively few, and their functional and compatibility limitations restrict users' access to diversified content and services, and cannot fully meet the market demand for cost-effective, multi-functional interfaces.

[0006] Most TV sets lack CA (Conditional Access) functionality.

[0007] The CA function is crucial for users to obtain advanced service content. It encrypts and decrypts digital TV signals to enable authorized access to specific programs or services.

[0008] The lack of CA functionality means that users cannot access high-quality content that requires authorization, such as paid high-definition film and television resources and live broadcasts of professional sports events. This greatly limits users' viewing options and reduces user experience.

[0009] To access premium content, users have to purchase a separate set-top box for the corresponding service. This not only increases hardware costs but also brings inconvenience, requires additional connections and setup, takes up more space in the home, and increases energy consumption.

[0010] Moreover, the use of multiple devices may also lead to cumbersome operations, and the usage threshold is high for users who are not familiar with technology.

[0011] Judging from the situation of TV board suppliers, it is extremely rare to find TV boards with CA interfaces, whether they are Android or non-Android systems.

[0012] Against the backdrop of growing user demand for low-cost, multi-functional TV devices, this gap in the market has created a sharp contradiction between supply and demand. An innovative solution is urgently needed that can both reduce costs and meet user demands for CA functions and diversified services. To this end, a TV board circuit with a CA interface and a CA operation method are designed to address the above issues. Summary of the Invention

[0013] The main purpose of the present invention is to provide a TV board circuit with a CA interface and a CA working method.

[0014] The purpose of the present invention can be achieved by adopting the following technical solutions: A TV board circuit with a CA interface includes a chip CPU and a CA interface coupled to the chip CPU; The CA interface includes a CHIP chip circuit, a CA card interface circuit and a UART TO IO circuit; The CHIP chip circuit couples the CA card interface circuit and the UART TO IO circuit; The chip exchanges data with external devices through the UART TO IO circuit; The CA card interface circuit is used to interact with various cards. The CHIP chip circuit provides control signals and power to various cards through the CA card interface circuit, and performs card read and write operations and status detection.

[0015] Preferably, the CA card interface circuit includes a CA card socket J11, a K1 connection terminal of the CA card socket J11 is grounded, and a K2 connection terminal of the CA card socket J11 is electrically connected to one end of a resistor R114 and one end of a resistor R113; The C3 terminal of the CA card holder J11 is electrically connected to one end of the capacitor C126, and the other end of the capacitor C126 is grounded. The C2 terminal of the CA card holder J11 is electrically connected to one end of the capacitor C127, and the other end of the capacitor C127 is grounded. The C1 terminal of the CA card holder J11 is electrically connected to one end of the capacitor C128, and the other end of the capacitor C128 is electrically connected to the C5 terminal of the CA card holder J11; The C7 terminal of the CA card socket J11 is electrically connected to one end of the resistor R106 and one end of the resistor R105 and is also electrically connected to one end of the capacitor C218. The other end of the capacitor C218 is grounded.

[0016] Preferably, the UART TO IO circuit includes a field effect transistor Q6 and a field effect transistor Q5; Terminal 1 of the field effect transistor Q6 is connected to a 3.3V power supply, terminal 3 of the field effect transistor Q6 is electrically connected to one end of a resistor R182, the other end of the resistor R182 is electrically connected to one end of a resistor R95, and the other end of the resistor R95 is grounded; Terminal 3 of the field effect transistor Q6 is also electrically connected to one end of a resistor R97, and the other end of the resistor R97 is electrically connected to terminal 2 of the field effect transistor Q6; Terminal 1 of field effect transistor Q5 is electrically connected to a 3.3V power supply and one end of resistor R88. The other end of resistor R88 is electrically connected to one end of resistor R82, one end of resistor R91, one end of resistor R89, and terminal 2 of field effect transistor Q5. The other end of the resistor R89 is grounded, and the terminal 3 of the field effect transistor Q5 is electrically connected to the other end of the resistor R82.

[0017] Preferably, the CHIP chip circuit includes a chip U14, a terminal 17 of the chip U14 is electrically connected to a terminal C1 of the CA card holder J11 and is also electrically connected to one end of a capacitor C151, and the other end of the capacitor C151 is grounded; The 16th terminal of the chip U14 is electrically connected to the C2th terminal of the chip J11, and the 15th terminal of the chip U14 is electrically connected to the C3th terminal of the chip J11; The terminal 12 of the chip U14 is electrically connected to the other end of the resistor R105 , and the terminal 11 of the chip U14 is electrically connected to the other end of the resistor R106 ; The terminal 10 of the chip U14 is electrically connected to the other end of the resistor R113, one end of the resistor R175, and one end of the resistor R118. The other end of the resistor R175 is grounded. Terminal 9 of chip U14 is electrically connected to one end of resistor R176, one end of resistor R119 and the other end of resistor R114. The other end of resistor R176 is grounded. The other end of resistor R119 and the other end of resistor R118 are electrically connected to SMC_3.3V.

[0018] Preferably, terminal 28 of chip U14 is electrically connected to one end of resistor R96, the other end of resistor R96 is electrically connected to terminal 2 of field effect transistor Q6, terminal 28 of chip U14 is also electrically connected to one end of capacitor C222, the other end of capacitor C222 is grounded; The other end of the resistor R96 is electrically connected to one end of the resistor R221 , and the other end of the resistor R221 is grounded; Terminal 26 of chip U14 is electrically connected to one end of resistor R122 and one end of capacitor C152, and the other end of resistor R122 is electrically connected to terminal 3 of effect transistor Q5; The other end of capacitor C153 is grounded.

[0019] Preferably, the terminal 18 of the chip U14 is electrically connected to one end of the resistor R125 and one end of the resistor R126, the other end of the resistor R125 is electrically connected to SMC_3.3V, and the other end of the resistor R125 is grounded; Terminal 24 of chip U14 is electrically connected to one end of capacitor C158 and terminal 1 of crystal oscillator X3. The other end of capacitor C158 is grounded and electrically connected to terminals 2 and 4 of the crystal oscillator and the other end of capacitor C159. Terminal 25 of chip U14 is electrically connected to one end of capacitor C159 and terminal 3 of the crystal oscillator; Terminal 22 of chip U14 is electrically connected to one end of capacitor C157, terminal 21 of chip U14 is electrically connected to the other end of capacitor C157 and XMC_3.3V, terminal 7 of chip U14 is electrically connected to one end of capacitor C212, and terminal 5 of chip U14 is electrically connected to the other end of capacitor C212; Terminal 6 of chip U14 is electrically connected to SMC_5V, one end of capacitor C196, and one end of capacitor C197; Terminal 8 of chip U14 is electrically connected to one end of capacitor C213, and the other ends of capacitor C196, C197, and C213 are electrically connected to terminal 4 of chip U14 and grounded. Terminal 1 of chip U14 is electrically connected to one end of resistor R173 , one end of resistor R174 , and one end of resistor R161 ; Terminal 2 of chip U14 is electrically connected to one end of resistor R171 , one end of resistor R172 , and one end of resistor R153 ; Terminal 3 of chip U14 is electrically connected to one end of resistor R169, one end of resistor R171, one end of resistor R174, and one end of resistor R170. The other end of resistor R170, the other end of resistor R173, and the other end of resistor R172 are electrically connected to XMC_3.3V. The other end of the resistor R174 , the other end of the resistor R171 , and the other end of the resistor R169 are grounded.

[0020] Preferably, SMC_5V is electrically connected to one end of capacitor C220, the other end of capacitor C220 is grounded, SMC_5V is electrically connected to one end of fuse FB6, SMC_3.3V is electrically connected to one end of capacitor C139, the other end of capacitor C139 is grounded, and one end of capacitor C139 is also electrically connected to one end of fuse FB5.

[0021] Beneficial technical effects of the present invention: The present invention provides a TV board circuit with a CA interface and a CA working method. CI interfaces supporting Smartcards on the market require an external expensive CI module, and the price ranges from tens to hundreds of US dollars depending on the card type.

[0022] The TV board of the present invention directly reads the Smartcard without the need for an external CI module, thus saving the user the expense of purchasing the CI module and alleviating the user's burden from the source of hardware cost.

[0023] At the same time, it avoids the additional expense of purchasing a separate set-top box to obtain advanced service content, reducing the overall hardware procurement cost.

[0024] The integrated design of the TV motherboard and CA circuit, along with the stacked CA card and other component circuits, minimizes PCB area. This compact layout reduces PCB board usage and manufacturing costs. Furthermore, it reduces the length and complexity of circuit wiring, lowering wiring costs and the risk of failures caused by wiring problems.

[0025] Most traditional TVs lack CA functionality and are unable to access premium content. The TV board of the present invention is equipped with a CA card socket and supports CA functionality. By inserting a CA card, users can access previously restricted premium content, such as premium HD movies and live professional sports events. This significantly enriches the TV program resources, expands the functional boundaries of the TV, and enhances the user's viewing options and experience.

[0026] Both Android and non-Android TV boards can support the CA circuit and interface of the present invention. This makes the technology widely applicable to various types of TV sets, breaking system limitations and expanding the product's application scenarios and market coverage.

[0027] The controllable base clock frequency selection function allows you to set the appropriate clock frequency specifications for different CA card types, ensuring stable operation. The card reader circuit efficiently reads CA card data, and the signal transmission level matching circuit converts the signal levels of different CA cards to levels recognizable by the CPU, ensuring accurate data transmission. The data signal channel splitting circuit splits the CA card's single-line bidirectional data signal into independent receive and transmit channels, communicating independently with the CPU's UART RX and UART TX channels. This avoids data transmission conflicts and improves data processing efficiency and transmission stability.

[0028] The stacked layout of the CA card and other component circuits, combined with the overall compact design, shortens the signal transmission path and reduces the possibility of signal interference and being interfered with. This helps improve the stability and accuracy of TV signal processing, reduces problems such as image freezes and sound distortion, and enhances the user viewing experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A system diagram of a preferred embodiment of a TV card circuit with a CA interface and a CA operation method according to the present invention; Figure 2 A circuit diagram of a preferred embodiment of a TV card circuit with a CA interface and a CA operation method according to the present invention; Figure 3 A circuit diagram of a preferred embodiment of a TV card circuit with a CA interface and a CA operation method according to the present invention; Figure 4 The present invention is a circuit diagram of a preferred embodiment of a TV card circuit with a CA interface and a CA operation method according to the present invention. DETAILED DESCRIPTION

[0030] In order to make the technical solution of the present invention more clear and specific to those skilled in the art, the present invention is further described in detail below with reference to embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0031] like Figure 1-Figure 4 As shown, this embodiment provides a TV card circuit with a CA interface, including a chip CPU and a CA interface coupled to the chip CPU; The CA interface includes a CHIP chip circuit, a CA card interface circuit and a UART TO IO circuit; The CHIP chip circuit couples the CA card interface circuit and the UART TO IO circuit; The chip exchanges data with external devices through the UART TO IO circuit; The CA card interface circuit is used to interact with various cards. The CHIP chip circuit provides control signals and power to various cards through the CA card interface circuit, performing card read and write operations and status detection. When a CA card is properly inserted into the CA card holder (J11), the insertion detection pin of the CA card holder is triggered, providing a detection level to chip U14. Upon detecting the insertion signal, U14 begins configuring the clock model and performs preliminary handshake communication with the CA card in the CA card holder through the data port. U14 divides the frequency of the external crystal oscillator to match the clock of the various CA cards. When the configured CA card clock matches the actual CA card, the CA card returns a handshake signal, initiating data communication. U14 inputs and outputs data through the RX and TX pins connected to the CHIP IC. After receiving the CA data information through the UART port, the CHIPIC performs normal decoding operations.

[0032] In this embodiment, the CA card interface circuit includes a CA card socket J11, a K1 connection terminal of the CA card socket J11 is grounded, and a K2 connection terminal of the CA card socket J11 is electrically connected to one end of a resistor R114 and one end of a resistor R113; The C3 terminal of the CA card holder is electrically connected to one end of the capacitor C126, and the other end of the capacitor C126 is grounded. The C2 terminal of the CA card holder J11 is electrically connected to one end of the capacitor C127, and the other end of the capacitor C127 is grounded. The C1 terminal of the CA card holder J11 is electrically connected to one end of the capacitor C128, and the other end of the capacitor C128 is electrically connected to the C5 terminal of the CA card holder J11; The C7 terminal of the CA card socket J11 is electrically connected to one end of the resistor R106 and one end of the resistor R105 and is also electrically connected to one end of the capacitor C218. The other end of the capacitor C218 is grounded.

[0033] K2 of J11 is the CA card insertion detection pin. When a card is inserted, it will generate a high or low level to IC U14 through R114 or R114; C3 on J11 is the CLK clock signal pin, and the connected C126 is a decoupling capacitor. C2 on J11 is the RST reset pin. When U14 detects a card insertion, it simultaneously provides a reset signal to reset the CA card. Capacitor C127 connected to it is a decoupling capacitor. C1 on J11 is VCC, the external power supply voltage for the CA card. VCC is 5V or 3V depending on the card type. Capacitor C128 is a decoupling capacitor. C7 on J11 is the DATA port, which communicates with U14 through R105 and R106.

[0034] In this embodiment, the UART TO IO circuit includes a field effect transistor Q6 and a field effect transistor Q5; Terminal 1 of the field effect transistor Q6 is connected to a 3.3V power supply, terminal 3 of the field effect transistor Q6 is electrically connected to one end of a resistor R182, the other end of the resistor R182 is electrically connected to one end of a resistor R95, and the other end of the resistor R95 is grounded; Terminal 3 of the field effect transistor Q6 is also electrically connected to one end of a resistor R97, and the other end of the resistor R97 is electrically connected to terminal 2 of the field effect transistor Q6; Terminal 1 of field effect transistor Q5 is electrically connected to a 3.3V power supply and one end of resistor R88. The other end of resistor R88 is electrically connected to one end of resistor R82, one end of resistor R91, one end of resistor R89, and terminal 2 of field effect transistor Q5. The other end of resistor R89 is grounded, and terminal 3 of field-effect transistor Q5 is electrically connected to the other end of resistor R82. The CA signal passes through IO port IO-TX of IC U14, where field-effect transistor Q6 converts the 3.3V IO level into a 5V signal recognizable by the chip IC. The chip IC's 5V signal, SMC_IO_RX, is converted by field-effect transistor Q5 into a level signal recognizable by U14.

[0035] This enables normal communication between U14 and CHIP IC.

[0036] In this embodiment, the CHIP chip circuit includes a chip U14, a terminal 17 of the chip U14 is electrically connected to a terminal C1 of the chip J11 and is also electrically connected to one end of a capacitor C151, and the other end of the capacitor C151 is grounded; The 16th terminal of the chip U14 is electrically connected to the C2th terminal of the chip J11, and the 15th terminal of the chip U14 is electrically connected to the C3th terminal of the chip J11; The terminal 12 of the chip U14 is electrically connected to the other end of the resistor R105 , and the terminal 11 of the chip U14 is electrically connected to the other end of the resistor R106 ; The terminal 10 of the chip U14 is electrically connected to the other end of the resistor R113, one end of the resistor R175, and one end of the resistor R118. The other end of the resistor R175 is grounded. Terminal 9 of chip U14 is electrically connected to one end of resistor R176, one end of resistor R119 and the other end of resistor R114. The other end of resistor R176 is grounded. The other end of resistor R119 and the other end of resistor R118 are electrically connected to SMC_3.3V.

[0037] Pin 9 of U14 is the CA card insertion status detection pin, which is valid when low level input; Pin 10 of U14 is the CA card insertion status detection pin, which is valid when high level input; Pin 12 of U14 is connected to the data pin of CA card socket J11 through resistor R105; Pin 11 of U14 is connected to the data pin of CA card socket J11 through resistor R106; Pin 16 of U14 is connected to the RST reset pin of J11 of the CA card holder to provide a reset signal for the CA card. Pin 17 of U14 is the VCC pin, which is connected to the VCC of the CA card socket J11 to provide power for the CA card.

[0038] In this embodiment, terminal 28 of chip U14 is electrically connected to one end of resistor R96, the other end of resistor R96 is electrically connected to terminal 2 of field effect transistor Q6, and terminal 28 of chip U14 is also electrically connected to one end of capacitor C222, the other end of capacitor C222 is grounded. The other end of the resistor R96 is electrically connected to one end of the resistor R221 , and the other end of the resistor R221 is grounded; Terminal 26 of chip U14 is electrically connected to one end of resistor R122 and one end of capacitor C152, and the other end of resistor R122 is electrically connected to terminal 3 of effect transistor Q5; The other end of capacitor C153 is grounded. Pin 28 of U14 is an I / O port, which communicates normally with the UART port of the CHIP IC after level matching through the series resistor R96 and the field effect transistor Q6. Pin 26 of U14 is an I / O port, which communicates with the UART port of the CHIP IC after level matching through the series resistor R122 and the field effect transistor Q5.

[0039] In this embodiment, terminal 18 of chip U14 is electrically connected to one end of resistor R125 and one end of resistor R126, the other end of resistor R125 is electrically connected to SMC_3.3V, and the other end of resistor R125 is grounded; Terminal 24 of chip U14 is electrically connected to one end of capacitor C158 and terminal 1 of crystal oscillator X3. The other end of capacitor C158 is grounded and electrically connected to terminals 2 and 4 of the crystal oscillator and the other end of capacitor C159. Terminal 25 of chip U14 is electrically connected to one end of capacitor C159 and terminal 3 of the crystal oscillator; Terminal 22 of chip U14 is electrically connected to one end of capacitor C157, terminal 21 of chip U14 is electrically connected to the other end of capacitor C157 and XMC_3.3V, terminal 7 of chip U14 is electrically connected to one end of capacitor C212, and terminal 5 of chip U14 is electrically connected to the other end of capacitor C212; Terminal 6 of chip U14 is electrically connected to SMC_5V, one end of capacitor C196, and one end of capacitor C197; Terminal 8 of chip U14 is electrically connected to one end of capacitor C213, and the other ends of capacitor C196, C197, and C213 are electrically connected to terminal 4 of chip U14 and grounded. Terminal 1 of chip U14 is electrically connected to one end of resistor R173 , one end of resistor R174 , and one end of resistor R161 ; Terminal 2 of chip U14 is electrically connected to one end of resistor R171 , one end of resistor R172 , and one end of resistor R153 ; Terminal 3 of chip U14 is electrically connected to one end of resistor R169, one end of resistor R171, one end of resistor R174, and one end of resistor R170. The other end of resistor R170, the other end of resistor R173, and the other end of resistor R172 are electrically connected to XMC_3.3V. The other end of the resistor R174 , the other end of the resistor R171 , and the other end of the resistor R169 are grounded.

[0040] Pins 1 and 2 of U14 are frequency selection pins, connected to the I / O port of the CHIP IC through resistors R161 and R153. Different frequency divisions are configured by controlling the high and low levels of the I / O port. Pin 3 of U14 is configured to a high level through the connected resistor R170 and to a low level through the connected resistor R169. The high level is when VCC is powered by 5V, and the low level is when it is powered by 3V, which provides power to CA. Pin 6 of U14 is the positive power supply for the DC / DC circuit. Pin 18 of U14 is the power-on reset level adjustment terminal. The reset level can be adjusted by adjusting the values of resistors R125 and R126. Pin 22 of U14 is the ground pin of the chip; pins 24 and 25 of U14 are the connection pins of the crystal oscillator, which provide a suitable clock for the CA card to work.

[0041] In this embodiment, SMC_5V is electrically connected to one end of capacitor C220, the other end of capacitor C220 is grounded, SMC_5V is electrically connected to one end of fuse FB6, SMC_3.3V is electrically connected to one end of capacitor C139, the other end of capacitor C139 is grounded, and one end of capacitor C139 is also electrically connected to one end of fuse FB5.

[0042] The capacitor C220 connected to SMC_5V is a filter capacitor that provides power supply voltage to the CA card through the DC / DC principle; SMC_3.3V provides voltage for U14 operation, and capacitor C139 is a filter capacitor.

[0043] Further explanation in Figure 2Pins 26, 27, and 28 of U14 are all IO ports, and you can select any two of them as RX and TX connections respectively.

[0044] Or pins 26, 27, and 28 of U14 are all IO ports. You can select any one of the pins and connect RX and TX together to achieve UART data communication.

[0045] Or normal communication is performed when the CPU has the CLK and DATA required by the SMARTCARD.

[0046] When a CA card is inserted into the CA card holder J11, the voltage level at terminal K2 changes (high or low) and is transmitted to pins 9 and 10 of chip U14 through resistors R113 and R114. U14 uses dual-terminal detection (PRES_N and PRES_P) to determine whether a CA card is inserted, avoiding false positives that could occur with single-terminal detection. For example, when a CA card is inserted, terminal K2 forms a path with the grounded terminal K1, causing the voltage divider at R114 to change. Pin 9 of U14 detects a low level, triggering an insertion event.

[0047] VCC Power Supply Adaptation: The C1 pin of the CA card connector J11 provides power for CA cards, automatically adapting to the card type (5V or 3V). Pin 3 of chip U14 is configured for power supply via resistors R170 and R169: High voltage output (R170 connected) 5V, low voltage output (R169 connected), adapting to different CA card standards (such as ISO7816 and EMV).

[0048] Decoupling capacitor network: C126 (CLK clock line), C127 (RST reset line), and C128 (VCC power line) are all connected in parallel to ground capacitors to suppress high-frequency noise. Taking C128 as an example, a 220N / 16V capacitor can filter out power ripple, ensuring stable power supply for the CA card and avoiding read and write errors caused by voltage fluctuations.

[0049] Signal transmission from the CPU to the CA chip: Pin 28 (IO_TX) of chip U14 outputs a 3.3V signal. After current limiting by resistor R96, it drives field-effect transistor Q6 (N-channel MOSFET) into conduction. Pin 2 of Q6 converts the signal to a 5V level (powered by SMC_5V) and transmits it to the CHIP chip circuit, resolving voltage mismatches between the CPU and CA chip (e.g., the CPU's 3.3VIO is compatible with the CA chip's 5V interface).

[0050] Signal reception from the CA chip to the CPU: The 5V signal (SMC_IO_RX) from the CHIP chip is converted to 3.3V via field-effect transistor Q5 (P-channel MOSFET). When the input is high, Q5 is cut off, and the output is pulled up to 3.3V via R88. When the input is low, Q5 is turned on, and the output is grounded, ensuring that U14's pin 26 (IO_RX) can correctly recognize the signal.

[0051] Resistor R221 and C222 form an RC filter circuit to smooth the IO_TX signal and suppress high-frequency interference; Resistors R82 and R89 form a voltage divider network to adjust the conduction threshold of Q5 and avoid bit errors caused by signal jitter.

[0052] Pins 24 and 25 of chip U14 are connected to an external crystal oscillator X3 (e.g., 27MHz), and different clock frequencies (e.g., 1MHz, 4MHz, 8MHz) are generated through the internal divider. Pins 1 and 2 of U14 serve as frequency selectors, and the frequency division coefficient is configured through resistors R173, R174, R161, and R171. For example: When pin 1 is high and pin 2 is low, the frequency division ratio is 27:1, and a 1MHz clock is output, which is suitable for low-speed CA cards. When both pins are high, the division ratio is 27:3, and the output is 9MHz (close to the standard 8MHz), which is suitable for high-speed cards.

[0053] Pin 16 of U14 outputs the RST reset signal to the C2 terminal of the CA card connector J11. The reset timing follows the ISO7816 standard: After the power supply (VCC) is stable, the reset signal is sent after a delay of 100ms; Reset pulse width ≥ 100μs, low level is valid; After reset, wait for the CA card to return the ATR (AnswerToReset) signal before starting the clock.

[0054] Connect the SMC_5V line in series with fuse FB6 (such as a 2A resettable fuse). When the CA card is short-circuited, FB6 will fuse and cut off the power supply to prevent damage to the motherboard. The SMC_3.3V line fuse FB5 (1A) protects the U14 chip to prevent current backflow.

[0055] SMC_5V uses C220 (10μF / 10V) and C196, C197 (100nF) to form a π-type filter to remove high-frequency and low-frequency noise in the power supply; SMC_3.3V is filtered by C139 (10μF) and C212 (100nF) to ensure that the power supply ripple of chip U14 is ≤50mV.

[0056] Android system adaptation: In the Android TV board, the UARTTOIO circuit communicates with the CPU serial port to achieve API docking between CA card data and the Android system, supporting DRM decryption of paid content such as Netflix and Disney+; Non-Android system adaptation: In Linux or RTOS systems, the U14 chip is controlled through the underlying driver to achieve plug-and-play of the CA card, which is suitable for scenarios such as hotel TVs and industrial control terminals.

[0057] Anti-interference measured data; In an electromagnetic interference environment (such as when a microwave oven is working), the performance of this circuit is: Clock jitter: ≤500ps (standard requirement ≤1ns); Data transmission bit error rate: ≤10^-7 (better than the industry standard 10^-6); Reset stability: 1000 times of continuous plugging and unplugging without failure.

[0058] Signal layer hierarchical design; The CA card interface circuit and CHIP chip circuit are located on the top layer of the PCB, and the UARTTOIO circuit is located on the bottom layer, connected by vias to reduce crosstalk between layers; The length of the clock line (CLK) is controlled within 10 mm, and grounded copper foil is laid around it to reduce EMI radiation.

[0059] SMC_5V and SMC_3.3V power planes are separated to avoid interference between different voltage domains; The ground plane uses a complete copper foil, and the K1 end of the CA card connector J11 is connected to the main ground through multiple vias (≥4) to reduce the ground impedance.

[0060] Insertion detection troubleshooting; If there is no response after inserting the CA card, you can check it by following the steps below: Measure the resistance between K2 and K1 of J11 (should be <10Ω when inserted and >100kΩ when unplugged); Check the voltage of pin 9 of U14 (it should be below 0.3V when plugged in and 3.3V when unplugged); Check whether R113 and R114 are poorly soldered (the resistance should be 10kΩ).

[0061] Data communication exception handling; If data transmission errors occur, you can observe them through an oscilloscope: CLK clock waveform (duty cycle 50%, rising edge ≤ 50ns); DATA line signal (high level ≥ 4.5V, low level ≤ 0.5V); There is a level conversion delay between pin 28 of U14 and pin 2 of Q6 (should be <100ns).

[0062] The above is only a further embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes based on the technical solutions and concepts of the present invention within the scope disclosed by the present invention, which fall within the scope of protection of the present invention.

Claims

1. A TV board circuit with a CA interface, comprising a chip CPU and a CA interface coupled to the chip CPU; Its characteristics are: The CA interface includes a CHIP chip circuit, a CA card interface circuit and a UART TO IO circuit; The CHIP chip circuit couples the CA card interface circuit and the UART TO IO circuit; The chip exchanges data with external devices through the UART TO IO circuit; The CA card interface circuit is used to interact with various cards. The CHIP chip circuit provides control signals and power to various cards through the CA card interface circuit, and performs card read and write operations and status detection.

2. The TV card circuit with a CA interface according to claim 1, characterized in that: The CA card interface circuit includes a chip J11, a K1 terminal of the chip J11 is grounded, and a K2 terminal of the chip J11 is electrically connected to one end of a resistor R114 and one end of a resistor R113; The C3 terminal of the chip J11 is electrically connected to one end of the capacitor C126, and the other end of the capacitor C126 is grounded. The C2 terminal of the chip J11 is electrically connected to one end of the capacitor C127, and the other end of the capacitor C127 is grounded. The C1 terminal of the chip J11 is electrically connected to one end of the capacitor C128, and the other end of the capacitor C128 is electrically connected to the C5 terminal of the chip J11; The C7 terminal of the chip J11 is electrically connected to one end of the resistor R106 and one end of the resistor R105 and is also electrically connected to one end of the capacitor C218 . The other end of the capacitor C218 is grounded.

3. The TV board circuit with CA interface according to claim 2, characterized in that: The UART TO IO circuit includes a field effect transistor Q6 and a field effect transistor Q5; Terminal 1 of the field effect transistor Q6 is connected to a 3.3V power supply, terminal 3 of the field effect transistor Q6 is electrically connected to one end of a resistor R182, the other end of the resistor R182 is electrically connected to one end of a resistor R95, and the other end of the resistor R95 is grounded; Terminal 3 of the field effect transistor Q6 is also electrically connected to one end of a resistor R97, and the other end of the resistor R97 is electrically connected to terminal 2 of the field effect transistor Q6; Terminal 1 of field effect transistor Q5 is electrically connected to a 3.3V power supply and one end of resistor R88. The other end of resistor R88 is electrically connected to one end of resistor R82, one end of resistor R91, one end of resistor R89, and terminal 2 of field effect transistor Q5. The other end of the resistor R89 is grounded, and the terminal 3 of the field effect transistor Q5 is electrically connected to the other end of the resistor R82.

4. The TV board circuit with CA interface according to claim 3, characterized in that: The CHIP chip circuit includes a chip U14, wherein a terminal 17 of the chip U14 is electrically connected to a terminal C1 of the chip J11 and is also electrically connected to one end of a capacitor C151, and the other end of the capacitor C151 is grounded; The 16th terminal of the chip U14 is electrically connected to the C2th terminal of the chip J11, and the 15th terminal of the chip U14 is electrically connected to the C3th terminal of the chip J11; The terminal 12 of the chip U14 is electrically connected to the other end of the resistor R105 , and the terminal 11 of the chip U14 is electrically connected to the other end of the resistor R106 ; The terminal 10 of the chip U14 is electrically connected to the other end of the resistor R113, one end of the resistor R175, and one end of the resistor R118. The other end of the resistor R175 is grounded. Terminal 9 of chip U14 is electrically connected to one end of resistor R176, one end of resistor R119 and the other end of resistor R114. The other end of resistor R176 is grounded. The other end of resistor R119 and the other end of resistor R118 are electrically connected to SMC_3.3V.

5. The TV board circuit with CA interface according to claim 4, characterized in that: Terminal 28 of chip U14 is electrically connected to one end of resistor R96, the other end of resistor R96 is electrically connected to terminal 2 of field effect transistor Q6, and terminal 28 of chip U14 is also electrically connected to one end of capacitor C222, the other end of capacitor C222 is grounded. The other end of the resistor R96 is electrically connected to one end of the resistor R221 , and the other end of the resistor R221 is grounded; Terminal 26 of chip U14 is electrically connected to one end of resistor R122 and one end of capacitor C152, and the other end of resistor R122 is electrically connected to terminal 3 of effect transistor Q5; The other end of capacitor C153 is grounded.

6. The TV card circuit with CA interface according to claim 5, characterized in that: Terminal 18 of chip U14 is electrically connected to one end of resistor R125 and one end of resistor R126. The other end of resistor R125 is electrically connected to SMC_3.3V. The other end of resistor R125 is grounded. Terminal 24 of chip U14 is electrically connected to one end of capacitor C158 and terminal 1 of crystal oscillator X3. The other end of capacitor C158 is grounded and electrically connected to terminals 2 and 4 of the crystal oscillator and the other end of capacitor C159. Terminal 25 of chip U14 is electrically connected to one end of capacitor C159 and terminal 3 of the crystal oscillator; Terminal 22 of chip U14 is electrically connected to one end of capacitor C157, terminal 21 of chip U14 is electrically connected to the other end of capacitor C157 and XMC_3.3V, terminal 7 of chip U14 is electrically connected to one end of capacitor C212, and terminal 5 of chip U14 is electrically connected to the other end of capacitor C212; Terminal 6 of chip U14 is electrically connected to SMC_5V, one end of capacitor C196, and one end of capacitor C197; Terminal 8 of chip U14 is electrically connected to one end of capacitor C213, and the other ends of capacitor C196, C197, and C213 are electrically connected to terminal 4 of chip U14 and grounded. Terminal 1 of chip U14 is electrically connected to one end of resistor R173 , one end of resistor R174 , and one end of resistor R161 ; Terminal 2 of chip U14 is electrically connected to one end of resistor R171 , one end of resistor R172 , and one end of resistor R153 ; Terminal 3 of chip U14 is electrically connected to one end of resistor R169, one end of resistor R171, one end of resistor R174, and one end of resistor R170. The other end of resistor R170, the other end of resistor R173, and the other end of resistor R172 are electrically connected to XMC_3.3V. The other end of the resistor R174 , the other end of the resistor R171 , and the other end of the resistor R169 are grounded.

7. The TV board circuit with CA interface according to claim 6, characterized in that: SMC_5V is electrically connected to one end of capacitor C220, the other end of capacitor C220 is grounded, SMC_5V is electrically connected to one end of fuse FB6, SMC_3.3V is electrically connected to one end of capacitor C139, the other end of capacitor C139 is grounded, and one end of capacitor C139 is also electrically connected to one end of fuse FB5.

Images