Image sensing apparatus and method of operation

Abstract

The invention relates to an image sensing apparatus and an operation method. An image sensing apparatus includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal, and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supply circuit coupled between the output terminal and the high voltage terminal, and configured to provide a pre-charge current configured to adaptively adjust according to the voltage level of the pixel signal to the output terminal based on the control voltage.

Description

[0001] This application is a divisional application of the original invention patent application number 202210188490.7 (application date: February 28, 2022, invention name: image sensing device). Technical Field

[0002] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to image sensing devices and operating methods. Background Art

[0003] Image sensing devices are devices for capturing images using the properties of semiconductors that react to light. Image sensing devices are generally classified as charge-coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices. CMOS image sensing devices have recently become widely used because they can allow both analog and digital control circuits to be directly implemented on a single integrated circuit (IC).

[0004] The paper "A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps" describes a reference-shared in-pixel differential common-source amplifier (RSDA). This in-pixel amplifier achieves high conversion gain when reading out pixel signals, but there are concerns that this design may reduce readout speed. Summary of the Invention

[0005] Various embodiments of the present disclosure are directed to an image sensing device capable of reducing a load on a readout line of a pixel signal in a structure in which an in-pixel amplifier is coupled to the readout line.

[0006] Furthermore, various embodiments of the present disclosure relate to an image sensing device and an operating method of the image sensing device capable of minimizing a settling time of a pixel signal output through a readout line of the pixel signal in a structure in which an in-pixel amplifier is coupled to the readout line.

[0007] According to an embodiment, an image sensing device may include: a control circuit, which is connected between an output terminal of a pixel signal and a high voltage terminal and is configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supply circuit, which is connected between the output terminal and the high voltage terminal and is configured to provide a pre-charge current to the output terminal based on the control voltage, which is configured to be adaptively adjusted according to the voltage level of the pixel signal.

[0008] According to an embodiment, an image sensing device may include: a reference circuit, which is connected between a high voltage terminal and a control node and is configured to provide a reference voltage to the control node based on a reference control signal; a sensing circuit, which is connected between the control node and an output terminal of a pixel signal and is configured to sense a slope of the pixel signal based on the reference control signal and a boost control signal, wherein the sensing circuit is configured to provide a control voltage to the control node according to the sensed slope; a subtraction circuit, which is connected between the high voltage terminal and the low voltage terminal and is configured to generate a subtraction current corresponding to the reference voltage; and a current supply circuit, which is connected between the output terminal and the high voltage terminal and is configured to provide a pre-charge current to which the subtraction current is applied to the output terminal based on the control voltage and the subtraction current.

[0009] According to an embodiment, an image sensing device may include: a reference pixel; a target pixel; an amplifier, which is commonly connected to the reference pixel and the target pixel and is configured to output a pixel signal of the target pixel through an output terminal during a readout period of a target row time; and a precharger, which is configured to provide a precharge current to the output terminal during an initial time of the readout period, which is configured to be adaptively adjusted according to a voltage level of the pixel signal.

[0010] According to an embodiment, an image sensing device may include: a reference pixel; a target pixel including a floating diffusion node; and a reset transistor element configured to reset the potential of the floating diffusion node during a reset period of a target row time; an amplifier commonly connected to the reference pixel and the target pixel and configured to output a target pixel signal of the target pixel through an output terminal during a readout period of the target row time; and a switching circuit configured to decouple the reset transistor element from the output terminal during at least the readout period.

[0011] The switch circuit may be configured to couple the reset transistor element to the output terminal during at least the reset period.

[0012] The switching circuit may include a first switch and a second switch connected in series between the output terminal and the reset transistor element, the first switch may be configured to be disconnected based on the line decoupling signal during at least a readout period of a target row time, and the second switch may be configured to be short-circuited based on the row change signal during the target row time.

[0013] The reference pixels may include pixels disposed in a row adjacent to a row in which the target pixels are disposed.

[0014] According to an embodiment, an image sensing device may include: a plurality of pixels, each including a floating diffusion node and a reset transistor element, the reset transistor element being configured to reset the potential of the floating diffusion node; an amplifier being configured to sequentially output a plurality of pixel signals of the plurality of pixels through an output terminal; and a switching circuit being configured to connect a first pixel of the plurality of pixels to the amplifier as a reference pixel and a second pixel of the plurality of pixels to the amplifier as a target pixel for each target row time, wherein the switching circuit includes a first switch configured to decouple the output terminal from the reset transistor element included in the target pixel during row times other than an initial row time of the target row time.

[0015] The first switch may be configured to couple the reset transistor element to the output terminal during an initial row time.

[0016] The reset transistor element may be configured to reset the potential of the floating diffusion node during a reset period of the target row time, and the initial row time includes the reset period.

[0017] The target pixel may be configured to generate a target pixel signal during a readout period of a target row time, and the other row times include the readout period.

[0018] The switching circuit may further include a second switch connected in series to the first switch between the output terminal and the reset transistor element, the first switch may be configured to be disconnected during other row times of the target row time based on the line decoupling signal, and the second switch may be configured to be shorted during the target row time based on the row change signal.

[0019] The first pixels may be disposed in a first row adjacent to a second row in which the second pixels are disposed.

[0020] According to an embodiment, an image sensing device may include: a reference pixel; a target pixel, which is electrically decoupled from an output terminal of a target pixel signal during a transfer time, charge accumulated in a photodiode during the transfer time is transferred to a floating diffusion node, and the target pixel is configured to output the target pixel signal through the output terminal during a readout period after the transfer time; an amplifier, which is coupled to the reference pixel and the target pixel and is configured to amplify the target pixel signal during the readout period; and a disable circuit, which is configured to disable the amplifier during the transfer time.

[0021] The disabling circuit may be coupled between the high voltage terminal and the amplifier and may be configured to electrically decouple the high voltage terminal from the amplifier during the transfer time.

[0022] The image sensing device may further include a compensation circuit configured to provide a compensation current to a common node to which a current source included in the amplifier is coupled during a transfer time.

[0023] The compensation circuit may include: a first switch coupled between the high voltage terminal and a coupling node and configured to operate based on a first control signal having a fixed voltage level; and a second switch coupled between the coupling node and a common node and configured to operate based on a second control signal activated during a transfer time.

[0024] The image sensing device may further include an interrupt circuit configured to electrically decouple the common node from a current source included in the amplifier during a transfer time.

[0025] The reference pixels may include pixels disposed in a row adjacent to a row in which the target pixels are disposed.

[0026] According to an embodiment, an image sensing device may include: a plurality of pixels; an amplifier configured to sequentially amplify a plurality of pixel signals output from the plurality of pixels; a switching circuit configured to connect a first pixel among the plurality of pixels to the amplifier as a reference pixel during a corresponding row time, and to connect a second pixel among the plurality of pixels to the amplifier as a target pixel; and a disabling circuit configured to disable the amplifier during a portion of the corresponding row time.

[0027] The portion of the corresponding row time may include a transfer time to transfer charges accumulated in a photodiode of a target pixel to a floating diffusion node of the target pixel.

[0028] The disabling circuit may be coupled between the high voltage terminal and the amplifier and configured to electrically decouple the high voltage terminal from the amplifier during the portion of the corresponding row time.

[0029] The image sensing device may further include a compensation circuit configured to provide a compensation current to a common node to which a current source included in the amplifier is coupled during the portion of the corresponding row time.

[0030] The compensation circuit may include: a first switch connected between the high voltage terminal and a connection node and configured to operate based on a first control signal having a fixed voltage level; and a second switch connected between the connection node and a common node and configured to operate based on a second control signal activated during a portion of a corresponding row time.

[0031] The image sensing device may further include an interrupt circuit configured to electrically decouple the common node from a current source included in the amplifier during the portion of the corresponding row time.

[0032] The first pixels may be disposed in a first row adjacent to a second row in which the second pixels are disposed.

[0033] According to an embodiment, an operating method of an image sensing device may include the following steps: maintaining a voltage level of an output terminal of a target pixel at a reset level of the target pixel during a transfer time, during which charge accumulated in a photodiode is transferred to a floating diffusion node; and amplifying a voltage level of the output terminal from the reset level to a target level corresponding to the target pixel during a readout period after the transfer time.

[0034] During the readout period, the amplifier coupled to the output terminal may be configured to be disabled, and the target pixel may be configured to be electrically decoupled from the output terminal.

[0035] During the readout period, a current generated from a current source included in the amplifier may be configured to be compensated.

[0036] During the readout period, a current source included in the amplifier may be configured to be electrically decoupled from a common node to which the target pixel and the reference pixel are coupled. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a block diagram illustrating an image sensing device according to a first embodiment.

[0038] Figure 2 This is an example Figure 1 Circuit diagram of an example of a pixel array and magnified area shown.

[0039] Figure 3 This is an example Figure 2 The equivalent circuit diagram of the (n-1)th pixel, the nth pixel, the intra-pixel amplifier, and the third and fifth switches is shown.

[0040] Figure 4 This is an example Figure 1 A timing diagram illustrating the operation of the image sensing device is shown.

[0041] Figure 5 is a block diagram illustrating an image sensing device according to a second embodiment.

[0042] Figure 6 This is an example Figure 5 Circuit diagram of an example of a pixel array and magnified area shown.

[0043] Figure 7 This is an example Figure 6 The equivalent circuit diagram of the (n-1)th pixel, nth pixel, in-pixel amplifier, disable circuit and compensation circuit is shown.

[0044] Figure 8This is an example Figure 5 A circuit diagram of another example of a pixel array and an amplified area is shown.

[0045] Figure 9 This is an example Figure 8 The equivalent circuit diagram of the (n-1)th pixel, the nth pixel, the intra-pixel amplifier, the disable circuit, and the interrupt circuit is shown.

[0046] Figure 10 This is an example Figure 5 A timing diagram illustrating an example of the operation of an image sensing device is shown.

[0047] Figure 11 This is an example Figure 5 A timing diagram illustrating yet another example of the operation of the image sensing device is shown.

[0048] Figure 12 is a block diagram illustrating an image sensing device according to a third embodiment.

[0049] Figure 13 This is an example Figure 12 Circuit diagram of an example of a pixel array and magnified area shown.

[0050] Figure 14 This is an example Figure 13 The equivalent circuit diagram of the (n-1)th pixel, nth pixel, in-pixel amplifier and pre-charger is shown.

[0051] Figure 15 This is an example Figure 13 and Figure 14 An example circuit diagram of a pre-charger is shown.

[0052] Figure 16 This is an example Figure 13 and Figure 14 A circuit diagram of another example of a pre-charger is shown.

[0053] Figure 17 This is an example Figure 12 A timing diagram illustrating the operation of the image sensing device is shown.

[0054] Figure 18 Another example Figure 17 A timing diagram illustrating the operation of the image sensing device is shown. DETAILED DESCRIPTION

[0055] Various embodiments are described below with reference to the accompanying drawings in order to describe the present disclosure in detail so that those skilled in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure.

[0056] It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the other element, or electrically connected to or coupled to the other element with one or more elements interposed therebetween. In addition, it will be understood that, unless otherwise stated, when used in this specification, the terms “include,” “comprise,” “have,” and “contain” do not exclude the presence of one or more other elements, but may further include or have one or more other elements. Throughout the description of the specification, some components are described in the singular, but the present disclosure is not limited thereto, and it will be understood that these components may be formed in the plural.

[0057] Figure 1 is a block diagram illustrating the image sensing device 100 according to the first embodiment.

[0058] Reference Figure 1 , the image sensing device 100 may include a timing controller 110 , a row decoder 120 , a pixel array 130 , an amplification region 140 , a signal conversion region 150 , and a column decoder 160 .

[0059] The timing controller 110 may control the overall operation of the image sensing apparatus 100. The timing controller 110 is also referred to as a timing generator.

[0060] The row decoder 120 may control the pixel array 130 for each row. For example, the row decoder 120 may generate a first row control signal for controlling pixels arranged in the first row of the pixel array 130, and generate a y-th row control signal for controlling pixels arranged in the y-th row of the pixel array 130. Herein, "y" is a natural number greater than 2.

[0061] The pixel array 130 may include pixels arranged at intersections of a plurality of rows and a plurality of columns. The pixels may generate pixel signals for each row under the control of the row decoder 120.

[0062] The amplification region 140 may amplify the gain of the pixel signal. For example, the amplification region 140 may connect a random first pixel among the pixels as a target pixel, connect a random second pixel among the pixels as a reference pixel, and amplify the gain of the pixel signal read out from the target pixel. The amplification region 140 may include a plurality of in-pixel amplifiers and a plurality of switching circuits corresponding to a plurality of columns of the pixel array 130 (see FIG. Figure 2 and Figure 3 ).

[0063] The signal conversion area 150 may convert analog pixel signals into digital signals. For example, the signal conversion area 150 may include a plurality of analog-to-digital converters (ADCs) corresponding to a plurality of columns of the pixel array 130 .

[0064] The column decoder 160 may control the signal conversion region 150 for each column. For example, the column decoder 160 may control the plurality of ADCs in sequence.

[0065] Figure 2 This is an example Figure 1 FIG. 1 is a circuit diagram of an example of a pixel array 130 and an amplification region 140 shown in FIG. Figure 2 , a circuit diagram corresponding to a portion of the pixel array 130 and a portion of the amplification region 140 is illustrated in FIG. The portion of the pixel array 130 may include pixels corresponding to any one of a plurality of columns, and the portion of the amplification region 140 may include an intra-pixel amplifier 141 and a switch circuit 143 corresponding to the any one column.

[0066] The pixel array 130 may include pixels arranged in a column direction. Hereinafter, a pixel PXn arranged in the nth row among the pixels is referred to as the nth pixel, and a pixel PXn-1 arranged in the (n-1)th row among the pixels is referred to as the (n-1)th pixel. In this document, "n" is a natural number greater than 2. When the nth pixel PXn is a target pixel, the (n-1)th pixel PXn-1 may be a reference pixel. In other words, the target pixel and the reference pixel may be normal pixels arranged adjacent to each other in the column direction.

[0067] The nth pixel PXn may include an nth photodiode PDn, an nth transfer element TTn, an nth floating diffusion node FDn, an nth reset gate-controlled transistor element RTn (hereinafter referred to as a reset transistor element), an nth driving element DTn, and an nth selecting element STn.

[0068] The nth photodiode PDn may be coupled between a low voltage terminal (eg, a ground voltage terminal) and the nth transfer element TTn. For example, the nth photodiode PDn may generate charges corresponding to incident light during an nth integration time.

[0069] An nth transfer element TTn may be coupled between an nth photodiode PDn and an nth floating diffusion node FDn. The nth transfer element TTn may selectively couple the nth photodiode PDn to the nth floating diffusion node FDn based on an nth transfer control signal TXn. For example, the nth transfer element TTn may transfer charge of the nth photodiode PDn to the nth floating diffusion node FDn during an nth transfer time Cn of an nth row time nth_RT.

[0070] The nth floating diffusion node FDn may be coupled to the nth capacitor CCn. The nth capacitor CCn may store charges generated by the nth photodiode PDn. For example, the nth capacitor CCn may be a parasitic capacitor.

[0071] An nth reset transistor element RTn may be coupled between the fifth line L4 and the nth floating diffusion node FDn. The nth reset transistor element RTn may selectively couple the fifth line L4 to the nth floating diffusion node FDn based on an nth reset control signal Rxn. For example, the nth reset transistor element RTn may electrically couple the fifth line L4 to the nth floating diffusion node FDn during an nth reset time (i.e., reset period) An of the nth row time nth_RT. During the reset time An, the voltage level at the floating diffusion node FDn is returned (reset) to a reference level so that subsequent charge transfer from the nth photodiode PDn to the nth floating diffusion node FDn during a subsequent nth transfer time Cn may be measured relative to the reference level.

[0072] The nth driving element DTn may be coupled between the first line L0 and the nth selecting element STn. The nth driving element DTn may generate an nth pixel signal corresponding to a voltage loaded on the nth floating diffusion node FDn.

[0073] The nth selection element STn may be coupled between the nth driving element DTn and the third line L2. The nth selection element STn may output the nth pixel signal to the third line L2 based on the nth selection control signal SXn. For example, the nth selection element STn may output the nth reset signal as the nth pixel signal during the nth reset readout time (i.e., reset readout period) Bn of the nth row time nth_RT, and output the nth data signal as the nth pixel signal during the nth data readout time (i.e., data readout period) Dn of the nth row time nth_RT.

[0074] The nth transfer control signal TXn, the nth reset control signal RXn, and the nth selection control signal SXn may be nth row control signals generated by the row decoder 120 .

[0075] The (n-1)th pixel PXn-1 may include an (n-1)th photodiode PDn-1, an (n-1)th transfer element TTn-1, an (n-1)th floating diffusion node FDn-1, an (n-1)th reset transistor element RTn-1, an (n-1)th driving element DTn-1 and an (n-1)th selection element STn-1.

[0076] The (n-1)th photodiode PDn-1 may be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the (n-1)th transfer element TTn-1. For example, the (n-1)th photodiode PDn-1 may generate charges corresponding to incident light during the (n-1)th integration time.

[0077] The (n-1)th transfer element TTn-1 may be coupled between the (n-1)th photodiode PDn-1 and the (n-1)th floating diffusion node FDn-1. The (n-1)th transfer element TTn-1 may selectively couple the (n-1)th photodiode PDn-1 to the (n-1)th floating diffusion node FDn-1 based on the (n-1)th transfer control signal TXn-1. For example, the (n-1)th transfer element TTn-1 may transfer charge of the (n-1)th photodiode PDn-1 to the (n-1)th floating diffusion node FDn-1 during the (n-1)th transfer time of the (n-1)th row time (n-1)th_RT.

[0078] The (n-1)th floating diffusion node FDn-1 may be coupled to the (n-1)th capacitor CCn-1. The (n-1)th capacitor CCn-1 may store charge generated by the (n-1)th photodiode PDn-1. For example, the (n-1)th capacitor CCn-1 may be a parasitic capacitor.

[0079] The (n-1)th reset transistor element RTn-1 may be coupled between the fourth line L3 and the (n-1)th floating diffusion node FDn-1. The (n-1)th reset transistor element RTn-1 may selectively couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 based on the (n-1)th reset control signal RXn-1. For example, the (n-1)th reset transistor element RTn-1 may electrically couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 during the (n-1)th reset time of the (n-1)th row time (n-1)th_RT. Additionally, the (n-1)th reset transistor element RTn-1 may electrically couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 during the nth reset time An of the nth row time nth_RT.

[0080] The (n-1)th driving element DTn-1 may be coupled between the first line L0 and the (n-1)th selecting element STn-1. The (n-1)th driving element DTn-1 may generate the (n-1)th pixel signal corresponding to the voltage applied to the (n-1)th floating diffusion node FDn-1.

[0081] The (n-1)th selection element STn-1 may be coupled between the (n-1)th drive element DTn-1 and the second line L1. The (n-1)th selection element STn-1 may output the (n-1)th pixel signal to the second line L1 based on the (n-1)th selection control signal SXn-1. For example, the (n-1)th selection element STn-1 may output the (n-1)th reset signal as the (n-1)th pixel signal during the (n-1)th reset readout time of the (n-1)th row time (n-1)th_RT, and output the (n-1)th data signal as the (n-1)th pixel signal during the (n-1)th data readout time of the (n-1)th row time (n-1)th_RT. In addition, the (n-1)th selection element STn-1 may electrically couple the (n-1)th drive element DTn-1 to the second line L1 during the nth row time nth_RT.

[0082] The (n−1)th transfer control signal TXn−1, the (n−1)th reset control signal RXn−1, and the (n−1)th selection control signal SXn−1 may be the (n−1)th row control signals generated by the row decoder 120 .

[0083] The amplification region 140 may include an in-pixel amplifier 141 and a switching circuit 143 .

[0084] The in-pixel amplifier 141 can sequentially output the (n-1)th pixel signal and the nth pixel signal. For example, the in-pixel amplifier 141 can amplify the gain of the (n-1)th pixel signal during the (n-1)th row time (n-1)th_RT, and amplify the gain of the nth pixel signal during the nth row time nth_RT. Since the in-pixel amplifier 141 corresponds to the reference-shared in-pixel differential common-source amplifier (RSDA) disclosed in the paper "A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps", its detailed description is omitted.

[0085] The switch circuit 143 may include a first switch S0 to a tenth switch S9. The first switch S0 to the fourth switch S3 and the seventh switch S6 to the tenth switch S9 may be controlled (closed or opened) based on a row change signal RC during a target row time (such as an nth row time nth_RT), for example, and the fifth switch S4 and the sixth switch S5 may be controlled based on a line decoupling signal LC. The row change signal RC and the line decoupling signal LC may be controlled by Figure 1The timing controller 110 shown generates the following. Since the first switch S0 to the fourth switch S3 and the seventh switch S6 to the tenth switch S9 are respectively connected to the paper “A0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-PixelDifferential Amplifier at 8.3Mpixel 35fps” Figure 5 8.2 corresponds to the switches shown in FIG. 8.2, and thus a detailed description thereof is omitted. However, the first switch S0 to the fourth switch S3 and the seventh switch S6 to the tenth switch S9 are exemplified according to the RSDA mode disclosed in the paper.

[0086] The fifth switch S4 may be coupled between the third switch S2 and the third line L2. For example, the fifth switch S4 may electrically couple the third switch S2 to the third line L2 during the nth reset time An of the nth row time nth_RT, and electrically decouple the third switch S2 from the third line L2 during the other row times Bn, Cn, and Dn of the nth row time nth_RT.

[0087] The sixth switch S5 may be coupled between the fourth switch S3 and the second line L1. For example, the sixth switch S5 may electrically couple the fourth switch S3 to the second line L1 during the (n-1)th reset time of the (n-1)th row time (n-1)th_RT, and electrically decouple the fourth switch S3 from the second line L1 during the remaining row times of the (n-1)th row time (n-1)th_RT.

[0088] Figure 3 This is an example Figure 2 1 and 2 are equivalent circuit diagrams of the (n-1)th pixel PXn-1, the nth pixel PXn, the intra-pixel amplifier 141, the third switch S2, and the fifth switch S4. Figure 3 A case where the n-th pixel PXn is coupled to the output terminal VOUT of the intra-pixel amplifier 141 is illustrated.

[0089] Reference Figure 3Although the third switch S2 may be shorted during the nth row time nth_RT, the fifth switch S4 may be shorted during the initial row time of the nth row time nth_RT, which includes the nth reset time An, and may be open during other row times of the nth row time nth_RT, including some or all of the nth reset readout time Bn, the nth transfer time Cn, and the nth data readout time Dn. During these other row times, only the third line L2 may be coupled to the output terminal VOUT of the intra-pixel amplifier 141. Therefore, during these other row times, of the load caused by the first parasitic capacitor PC1 of the third line L2 and the load caused by the second parasitic capacitor PC2 of the fifth line L4, because the fifth switch S4 is open, only the load caused by the first parasitic capacitor PC1 of the third line L2 may be reflected to the output terminal VOUT of the intra-pixel amplifier 141. In other words, during these other row times, the output terminal VOUT of the intra-pixel amplifier 141 is not affected by the load caused by the second parasitic capacitor PC2 of the fifth line L4. Therefore, the stabilization time of the pixel signal of the n-th pixel PXn read out through the output terminal VOUT can be reduced, and thus the readout speed of the pixel signal can be increased.

[0090] In the following, reference is made to Figure 4 The operation of the image sensing device 100 according to the first embodiment having the above-described configuration is described.

[0091] Figure 4 This is an example Figure 1 1 is a timing chart showing the operation of the image sensing device 100. The following representatively describes a case where the n-th pixel PXn is a target pixel.

[0092] Reference Figure 4 During the nth row time nth_RT, the (n-1)th pixel PXn-1 may be coupled to the intra-pixel amplifier 141 as a reference pixel via the switch circuit 143, and the nth pixel PXn may be coupled to the intra-pixel amplifier 141 as a target pixel via the switch circuit 143. During the nth row time nth_RT, the (n-1)th selection element STn-1 may be turned on based on the (n-1)th selection control signal SXn-1, and the nth selection element STn may be turned on based on the nth selection control signal SXn.

[0093] During the nth initial row time (i.e., the nth reset time An) of the nth row time nth_RT, the (n-1)th reset transistor element RTn-1 can be turned on based on the (n-1)th reset control signal RXn-1, and the nth reset transistor element RTn can be turned on based on the nth reset control signal RXn. In addition, during the nth initial row time (i.e., the nth reset time An), the fifth switch S4 included in the switch circuit 143 can be shorted based on the line decoupling signal LC. Therefore, a negative feedback loop can be formed between the nth floating diffusion node FDn and the output terminal VOUT, and an offset can be stored in the nth floating diffusion node FDn. The offset can refer to the mismatch between the (n-1)th pixel PXn-1 and the nth pixel PXn. For reference, the offset can be offset by a correlated double sampling (CDS) operation.

[0094] During the other row times of the nth row time nth_RT (i.e., the nth reset readout time Bn, the nth transfer time Cn, and the nth data readout time Dn), the fifth switch S4 may be disconnected based on the line decoupling signal LC. In this case, the line decoupling signal LC may transition from a high logic level to a low logic level during the initial period of the nth reset readout time Bn. The disconnected fifth switch S4 minimizes non-ideal effects, such as charge unintentionally injected into the nth floating diffusion node FDn due to the switching operation.

[0095] During other row times, because the fifth switch S4 is turned off during other times, the output terminal VOUT of the intra-pixel amplifier 141 is not affected by the load caused by the second parasitic capacitor PC2 of the fifth line L4, out of the load caused by the first parasitic capacitor PC1 of the third line L2 and the load caused by the second parasitic capacitor PC2 of the fifth line L4. In particular, during the n-th data readout time Dn, because the reset transistor element RTn is decoupled from the output terminal VOUT when the fifth switch S4 of the switch circuit 143 is turned off, the output terminal VOUT of the intra-pixel amplifier 141 is not affected by the load caused by the second parasitic capacitor PC2 of the fifth line L4.

[0096] Therefore, the stabilization time of the pixel signal of the n-th pixel PXn read out through the output terminal VOUT can be reduced, and thus the readout speed of the pixel signal can be increased.

[0097] According to the first embodiment, there is an advantage of minimizing the load reflected to the output terminal during the period of reading out the pixel signal (the period including at least the data readout time).

[0098] Figure 5 is a block diagram illustrating an image sensing device 200 according to the second embodiment.

[0099] Reference Figure 5 , the image sensing device 200 may include a timing controller 210 , a row decoder 220 , a pixel array 230 , an amplification region 240 , a signal conversion region 250 , and a column decoder 260 .

[0100] The timing controller 210 may control the overall operation of the image sensing apparatus 200. The timing controller 210 is also referred to as a timing generator.

[0101] The row decoder 220 may control the pixel array 230 for each row. For example, the row decoder 220 may generate a first row control signal for controlling pixels arranged in the first row of the pixel array 230, and generate a y-th row control signal for controlling pixels arranged in the y-th row of the pixel array 230. Herein, "y" is a natural number greater than 2.

[0102] The pixel array 230 may include pixels arranged at intersections of a plurality of rows and a plurality of columns. The pixels may generate pixel signals for each row under the control of the row decoder 220.

[0103] The amplification region 240 can amplify the gain of the pixel signal. For example, the amplification region 240 can connect a random first pixel among the pixels as a target pixel, connect a random second pixel among the pixels as a reference pixel, and amplify the gain of the pixel signal read out from the target pixel. The amplification region 240 may include a plurality of in-pixel amplifiers and a plurality of switching circuits corresponding to a plurality of columns of the pixel array 230 (refer to FIG. Figure 7 or Figure 9 ).

[0104] The signal conversion area 250 may convert analog pixel signals into digital signals. For example, the signal conversion area 250 may include a plurality of analog-to-digital converters (ADCs) corresponding to a plurality of columns of the pixel array 230 .

[0105] The column decoder 260 may control the signal conversion region 250 for each column. For example, the column decoder 260 may control the plurality of ADCs in sequence.

[0106] Figure 6 This is an example Figure 5 The circuit diagram of the example of the pixel array 230 and the amplification area 240 is shown in FIG. Figure 6 2 shows a circuit diagram corresponding to a portion of pixel array 230 and a portion of amplification region 240. The portion of pixel array 230 may include pixels corresponding to any one of a plurality of columns, and the portion of amplification region 240 may include an intra-pixel amplifier 241, a disabling circuit 245, a compensation circuit 247, and a switching circuit 243 corresponding to the any one column.

[0107] The pixel array 230 may include pixels arranged in a column direction. Hereinafter, a pixel PXn arranged in the nth row among the pixels is referred to as the nth pixel, and a pixel PXn-1 arranged in the (n-1)th row among the pixels is referred to as the (n-1)th pixel. In this document, "n" is a natural number greater than 2. When the nth pixel PXn is a target pixel, the (n-1)th pixel PXn-1 may be a reference pixel. In other words, the target pixel and the reference pixel may be normal pixels arranged adjacent to each other in the column direction.

[0108] The nth pixel PXn may include an nth photodiode PDn, an nth transfer element TTn, an nth floating diffusion node FDn, an nth reset transistor element RTn, an nth driving element DTn, and an nth selection element STn.

[0109] The nth photodiode PDn may be coupled between a low voltage terminal (eg, a ground voltage terminal) and the nth transfer element TTn. For example, the nth photodiode PDn may generate charges corresponding to incident light during an nth integration time.

[0110] An nth transfer element TTn may be coupled between an nth photodiode PDn and an nth floating diffusion node FDn. The nth transfer element TTn may selectively couple the nth photodiode PDn to the nth floating diffusion node FDn based on an nth transfer control signal TXn. For example, the nth transfer element TTn may transfer charge of the nth photodiode PDn to the nth floating diffusion node FDn during an nth transfer time Cn of an nth row time nth_RT.

[0111] The nth floating diffusion node FDn may be coupled to the nth capacitor CCn. The nth capacitor CCn may store charges generated by the nth photodiode PDn. For example, the nth capacitor CCn may be a parasitic capacitor.

[0112] The nth reset transistor element RTn may be coupled between the fifth line L4 and the nth floating diffusion node FDn. The nth reset transistor element RTn may selectively couple the fifth line L4 to the nth floating diffusion node FDn based on an nth reset control signal RXn. For example, the nth reset transistor element RTn may electrically couple the fifth line L4 to the nth floating diffusion node FDn during an nth reset time An of an nth row time nth_RT.

[0113] The nth driving element DTn may be coupled between the first line L0 and the nth selecting element STn. The nth driving element DTn may generate an nth pixel signal corresponding to a voltage loaded on the nth floating diffusion node FDn.

[0114] The nth selection element STn may be coupled between the nth driving element DTn and the third line L2. The nth selection element STn may output the nth pixel signal to the third line L2 based on the nth selection control signal SXn. For example, the nth selection element STn may output the nth reset signal as the nth pixel signal during the nth reset readout time Bn of the nth row time nth_RT, and output the nth data signal as the nth pixel signal during the nth data readout time Dn of the nth row time nth_RT.

[0115] The nth transfer control signal TXn, the nth reset control signal RXn, and the nth selection control signal SXn may be nth row control signals generated by the row decoder 220 .

[0116] The (n-1)th pixel PXn-1 may include an (n-1)th photodiode PDn-1, an (n-1)th transfer element TTn-1, an (n-1)th floating diffusion node FDn-1, an (n-1)th reset transistor element RTn-1, an (n-1)th driving element DTn-1 and an (n-1)th selection element STn-1.

[0117] The (n-1)th photodiode PDn-1 may be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the (n-1)th transfer element TTn-1. For example, the (n-1)th photodiode PDn-1 may generate charges corresponding to incident light during the (n-1)th integration time.

[0118] The (n-1)th transfer element TTn-1 may be coupled between the (n-1)th photodiode PDn-1 and the (n-1)th floating diffusion node FDn-1. The (n-1)th transfer element TTn-1 may selectively couple the (n-1)th photodiode PDn-1 to the (n-1)th floating diffusion node FDn-1 based on the (n-1)th transfer control signal TXn-1. For example, the (n-1)th transfer element TTn-1 may transfer charge of the (n-1)th photodiode PDn-1 to the (n-1)th floating diffusion node FDn-1 during the (n-1)th transfer time of the (n-1)th row time.

[0119] The (n-1)th floating diffusion node FDn-1 may be coupled to the (n-1)th capacitor CCn-1. The (n-1)th capacitor CCn-1 may store charge generated by the (n-1)th photodiode PDn-1. For example, the (n-1)th capacitor CCn-1 may be a parasitic capacitor.

[0120] The (n-1)th reset transistor element RTn-1 can be coupled between the fourth line L3 and the (n-1)th floating diffusion node FDn-1. The (n-1)th reset transistor element RTn-1 can selectively couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 based on the (n-1)th reset control signal RXn-1. For example, the (n-1)th reset transistor element RTn-1 can electrically couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 during the (n-1)th reset time of the (n-1)th row time. In addition, the (n-1)th reset transistor element RTn-1 can electrically couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 during the nth reset time An of the nth row time nth_RT.

[0121] The (n-1)th driving element DTn-1 may be coupled between the first line L0 and the (n-1)th selecting element STn-1. The (n-1)th driving element DTn-1 may generate the (n-1)th pixel signal corresponding to the voltage applied to the (n-1)th floating diffusion node FDn-1.

[0122] The (n-1)th selection element STn-1 can be coupled between the (n-1)th drive element DTn-1 and the second line L1. The (n-1)th selection element STn-1 can output the (n-1)th pixel signal to the second line L1 based on the (n-1)th selection control signal SXn-1. For example, the (n-1)th selection element STn-1 can output the (n-1)th reset signal as the (n-1)th pixel signal during the (n-1)th reset readout time of the (n-1)th row time, and output the (n-1)th data signal as the (n-1)th pixel signal during the (n-1)th data readout time of the (n-1)th row time. In addition, the (n-1)th selection element STn-1 can electrically couple the (n-1)th drive element DTn-1 to the second line L1 during the nth row time nth_RT.

[0123] The (n−1)th transfer control signal TXn−1, the (n−1)th reset control signal RXn−1, and the (n−1)th selection control signal SXn−1 may be the (n−1)th row control signals generated by the row decoder 220 .

[0124] The amplification region 240 may include an in-pixel amplifier 241 , a disabling circuit 245 , a compensation circuit 247 , and a switching circuit 243 .

[0125] The in-pixel amplifier 241 can sequentially output the (n-1)th pixel signal and the nth pixel signal. For example, the in-pixel amplifier 241 can amplify the gain of the (n-1)th pixel signal during the (n-1)th row time, and amplify the gain of the nth pixel signal during the nth row time nth_RT. Because the in-pixel amplifier 241 corresponds to the reference-shared in-pixel differential common source amplifier (RSDA) disclosed in the paper "A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps", its detailed description is omitted.

[0126] The disabling circuit 245 may disable the intra-pixel amplifier 241 for each transfer time. For example, the disabling circuit 245 may disable the intra-pixel amplifier 241 during the (n-1)th transfer time and disable the intra-pixel amplifier 241 during the nth transfer time Cn. The disabling circuit 245 is described in more detail below.

[0127] The compensation circuit 247 may provide a compensation current to the common node CN for each transfer time. The compensation circuit 247 is described in more detail below.

[0128] The switch circuit 243 may include first to eighth switches S0 to S7. The first to eighth switches S0 to S7 may be controlled based on a row change signal RC. The row change signal RC may be generated by the timing controller 210. Since the first to eighth switches S0 to S7 are similar to the switch described in the paper “A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps”, Figure 5 .8.2 corresponds to the switch shown in FIG. 8.2, so a detailed description thereof is omitted. However, the switch circuit 243 is exemplified according to the RSDA mode disclosed in the paper.

[0129] Figure 7 This is an example Figure 6 1 and 2. An equivalent circuit diagram of the (n-1)th pixel PXn-1, the nth pixel PXn, the intra-pixel amplifier 241, the disabling circuit 245, and the compensation circuit 247 is shown. Figure 7 A case where the n-th pixel PXn is coupled to the output terminal VOUT of the intra-pixel amplifier 241 is illustrated.

[0130] Reference Figure 7, the (n-1)th pixel PXn-1 may be coupled between any one of the two output terminals of the intra-pixel amplifier 241 and the common node CN of the intra-pixel amplifier 241. When the (n-1)th pixel PXn-1 serves as a reference pixel, the (n-1)th reset transistor element RTn-1 included in the (n-1)th pixel PXn-1 may be coupled to the high voltage terminal VRX for resetting.

[0131] The nth pixel PXn may be coupled between the other output terminal VOUT of the two output terminals and the common node CN. When the nth pixel PXn serves as a target pixel, the nth reset transistor element RTn included in the nth pixel PXn may be coupled to the output terminal VOUT.

[0132] The disabling circuit 245 may be coupled between the high voltage terminal and the intra-pixel amplifier 241. The disabling circuit 245 may electrically decouple the high voltage terminal from the intra-pixel amplifier 241 during the nth transfer time Cn. For example, the disabling circuit 245 may include a PMOS transistor. The PMOS transistor may have a gate terminal for receiving a disabling signal SXB activated for each transfer time, and a source terminal and a drain terminal coupled between the high voltage terminal and the intra-pixel amplifier 241. The disabling signal SXB may be generated by the timing controller 210.

[0133] The compensation circuit 247 may be coupled between the high voltage terminal and the common node CN. The compensation circuit 247 may prevent power fluctuations caused by the disabling circuit 245 for each transfer time. For example, the compensation circuit 247 may include a first switch S11 and a second switch S12.

[0134] The first switch S11 may be coupled between the high voltage terminal and a connection node CPN. The first switch S11 may operate based on a first control signal FS having a fixed voltage level. For example, the first control signal FS may include a high voltage provided from the high voltage terminal VRX for resetting. For example, the first switch S11 may include an NMOS transistor. The NMOS transistor may have a gate terminal for receiving the first control signal FS, and source and drain terminals coupled between the high voltage terminal and the connection node CPN.

[0135] The second switch S12 may be coupled between the connection node CPN and the common node CN. The second switch S12 may operate based on a disable signal SXB. For example, the second switch S12 may include an NMOS transistor. The NMOS transistor may have a gate terminal for receiving the disable signal SXB and a source terminal and a drain terminal coupled between the connection node CPN and the common node CN.

[0136] Figure 8 This is an example Figure 5 FIG. 2 is a circuit diagram of another example of the pixel array 230 and the amplification area 240 shown in FIG. Figure 8 2 illustrates a circuit diagram corresponding to a portion of the pixel array 230 and a portion of the amplification region 240. The portion of the pixel array 230 may include pixels corresponding to any one of a plurality of columns, and the portion of the amplification region 240 may include an intra-pixel amplifier 241, a disable circuit 245, an interrupt circuit 249, and a switch circuit 243 corresponding to the arbitrary column. In the following, only the circuit diagram corresponding to the pixel array 230 and the amplification region 240 will be described. Figure 6 The configuration of the interrupt circuit 249 is different from the configuration of the interrupt circuit 249.

[0137] The interruption circuit 249 can electrically disconnect the common node CN from the current source for each transfer time. Figure 9 The interrupt circuit 249 is described in more detail.

[0138] Figure 9 This is an example Figure 8 1 and 2. The equivalent circuit diagram of the (n-1)th pixel PXn-1, the nth pixel PXn, the intra-pixel amplifier 241, the disable circuit 245, and the interrupt circuit 249 is shown. Figure 9 The case where the n-th pixel PXn is connected to the output terminal VOUT of the intra-pixel amplifier 241 is illustrated. Figure 7 The configuration of the interrupt circuit 249 is different from the configuration of the interrupt circuit 249.

[0139] Reference Figure 9 The interrupt circuit 249 may be coupled between the common node CN and the current source 249a included in the in-pixel amplifier 241. The interrupt circuit 249 may prevent fluctuations in the common node CN caused by the disable circuit 245 for each transfer time. For example, the interrupt circuit 249 may include an NMOS transistor. The NMOS transistor may have a gate terminal for receiving the interrupt control signal SXX, and a source terminal and a drain terminal coupled between the common node CN and the current source 249a. The interrupt control signal SXX may be generated by the timing controller 210.

[0140] In the following, reference is made to Figure 10 and Figure 11 The operation of the image sensing device 200 according to the second embodiment having the above-described configuration is described.

[0141] Figure 10 This is an example Figure 5 1 is a timing diagram illustrating an example of the operation of the image sensing device 200. For convenience of description, a case where the n-th pixel PXn is a target pixel is representatively described.

[0142] Reference Figure 10During the nth row time nth_RT, the (n-1)th pixel PXn-1 may be coupled to the intra-pixel amplifier 241 as a reference pixel through the switch circuit 243, and the nth pixel PXn may be coupled to the intra-pixel amplifier 241 as a target pixel through the switch circuit 243. During the nth row time nth_RT, the (n-1)th selection element STn-1 may be turned on based on the (n-1)th selection control signal SXn-1, and during one or more times of respective row processing signals including the reset time An, the reset readout time Bn, the transfer time Cn, and the data readout time Dn, the nth selection element STn may be turned on based on the nth selection control signal SXn.

[0143] The nth row time nth_RT may include an nth reset time An, an nth reset readout time Bn, an nth transfer time Cn, and an nth data readout time Dn.

[0144] During the nth reset time An, the nth pixel PXn may store an offset in the nth floating diffusion node FDn based on the nth reset control signal RXn.

[0145] During the nth reset readout time Bn, the nth pixel PXn may generate a pixel signal corresponding to a reset level according to a voltage loaded on the nth floating diffusion node FDn.

[0146] During the nth transfer time Cn, the nth pixel PXn can transfer the charge accumulated in the nth photodiode PDn to the nth floating diffusion node FDn based on the nth transfer control signal TXn. At this time, the disabling circuit 245 can disable the intra-pixel amplifier 241 based on the disabling signal SXB. For example, the disabling circuit 245 can electrically decouple the high voltage terminal from the intra-pixel amplifier 241 during the nth transfer time Cn. The compensation circuit 247 can provide a compensation current to the common node CN during the nth transfer time Cn, thereby preventing power fluctuations that affect the current source when the power (i.e., high voltage) provided to the intra-pixel amplifier 241 is cut off. The nth pixel PXn can be electrically decoupled from the output terminal VOUT based on the nth selection control signal SXn. Therefore, during the nth transfer time Cn, the voltage level of the output terminal VOUT can be maintained at a reset level. For example, the voltage level of the output terminal VOUT can be maintained at the reset level by a parasitic capacitor coupled to the output terminal VOUT.

[0147] During the nth data readout time Dn, the nth pixel PXn can generate a pixel signal corresponding to the target level (i.e., the data level of the pixel signal) according to the voltage loaded on the nth floating diffusion node FDn. At this time, the voltage level of the output terminal VOUT from which the pixel signal is output can be increased (or amplified) from the reset level to the target level, thereby minimizing the stabilization time for the pixel signal to reach the target level. In other words, during the nth data readout time Dn, due to the operating range or swing range of the voltage level of the output terminal VOUT (refer to Figure 10 The dotted line for VOUT in the figure can be reduced to the effective output range (refer to Figure 10 solid line for VOUT in ), thus minimizing the settling time.

[0148] Figure 11 This is an example Figure 5 1 is a timing chart showing another example of the operation of the image sensing device 200. A case where the n-th pixel PXn is a target pixel is representatively described.

[0149] Reference Figure 11 During the nth row time nth_RT, the (n-1)th pixel PXn-1 may be coupled to the intra-pixel amplifier 241 as a reference pixel via the switch circuit 243, and the nth pixel PXn may be coupled to the intra-pixel amplifier 241 as a target pixel via the switch circuit 243. During the nth row time nth_RT, the (n-1)th selection element STn-1 may be turned on based on the (n-1)th selection control signal SXn-1, and the nth selection element STn may be turned on based on the nth selection control signal SXn.

[0150] The nth row time nth_RT may include an nth reset time An, an nth reset readout time Bn, an nth transfer time Cn, and an nth data readout time Dn.

[0151] During the nth reset time An, the nth pixel PXn may store an offset in the nth floating diffusion node FDn based on the nth reset control signal RXn.

[0152] During the nth reset readout time Bn, the nth pixel PXn may generate a pixel signal corresponding to a reset level according to a voltage loaded on the nth floating diffusion node FDn.

[0153] During the nth transfer time Cn, the nth pixel PXn can transfer the charge accumulated in the nth photodiode PDn to the nth floating diffusion node FDn based on the nth transfer control signal TXn. At this time, the disabling circuit 245 can disable the intra-pixel amplifier 241 based on the disabling signal SXB. For example, the disabling circuit 245 can electrically decouple the high voltage terminal from the intra-pixel amplifier 241 during the nth transfer time Cn. During the nth transfer time Cn, the interrupt circuit 249 can electrically decouple the common node CN from the current source 249a based on the interrupt control signal SXX, thereby protecting the current source 249a from fluctuations in the common node CN that occur when the power (i.e., high voltage) supplied to the intra-pixel amplifier 241 is cut off. The nth pixel PXn can be electrically decoupled from the output terminal VOUT based on the nth selection control signal SXn. Therefore, during the nth transfer time Cn, the voltage level of the output terminal VOUT can be maintained at a reset level. For example, the voltage level of the output terminal VOUT can be maintained at the reset level by a parasitic capacitor coupled to the output terminal VOUT.

[0154] During the nth data readout time Dn, the nth pixel PXn can generate a pixel signal corresponding to the target level (i.e., the data level of the pixel signal) according to the voltage loaded on the nth floating diffusion node FDn. At this time, the voltage level of the output terminal VOUT from which the pixel signal is output can be increased (or amplified) from the reset level to the target level, thereby minimizing the stabilization time for the pixel signal to reach the target level. In other words, during the nth data readout time Dn, due to the operating range or swing range of the voltage level of the output terminal VOUT (refer to Figure 11 The dotted line for VOUT in the figure can be reduced to the effective output range (refer to Figure 11 solid line for VOUT in ), thus minimizing the settling time.

[0155] According to the second embodiment, when a pixel signal is read out, it is possible to minimize the stabilization time for the pixel signal to reach a target level.

[0156] Figure 12 is a block diagram illustrating an image sensing device 300 according to the third embodiment.

[0157] Reference Figure 12 , the image sensing device 300 may include a timing controller 310 , a row decoder 320 , a pixel array 330 , an amplification region 340 , a signal conversion region 350 , and a column decoder 360 .

[0158] The timing controller 310 may control the overall operation of the image sensing apparatus 300. The timing controller 310 is also referred to as a timing generator.

[0159] The row decoder 320 may control the pixel array 330 for each row. For example, the row decoder 320 may generate a first row control signal for controlling pixels arranged in the first row of the pixel array 330, and generate a y-th row control signal for controlling pixels arranged in the y-th row of the pixel array 330. Herein, "y" is a natural number greater than 2.

[0160] The pixel array 330 may include pixels arranged at intersections of a plurality of rows and a plurality of columns. The pixels may generate pixel signals for each row under the control of the row decoder 320.

[0161] The amplification region 340 can amplify the gain of the pixel signal. For example, the amplification region 340 can access a random first pixel among the pixels as a target pixel, access a random second pixel among the pixels as a reference pixel, and amplify the gain of the pixel signal read out from the target pixel. The amplification region 340 may include a plurality of in-pixel amplifiers corresponding to a plurality of columns of the pixel array 330, a plurality of switching circuits, and a plurality of prechargers (refer to FIG. Figure 13 ).

[0162] The signal conversion area 350 may convert analog pixel signals into digital signals. For example, the signal conversion area 350 may include a plurality of analog-to-digital converters (ADCs) corresponding to a plurality of columns of the pixel array 330 .

[0163] The column decoder 360 may control the signal conversion region 350 for each column. For example, the column decoder 360 may control the plurality of ADCs in sequence.

[0164] Figure 13 This is an example Figure 12 3. For ease of description, the circuit diagram of the example of the pixel array 330 and the amplification area 340 is shown. Figure 13 3 shows a circuit diagram corresponding to a portion of the pixel array 330 and a portion of the amplification region 340. The portion of the pixel array 330 may include pixels corresponding to any one of a plurality of columns, and the portion of the amplification region 340 may include an intra-pixel amplifier 341 and a switch circuit 343 corresponding to the any one column.

[0165] The pixel array 330 may include pixels arranged in a column direction. Hereinafter, a pixel PXn arranged in the nth row among the pixels is referred to as the nth pixel, and a pixel PXn-1 arranged in the (n-1)th row among the pixels is referred to as the (n-1)th pixel. In this article, "n" is a natural number greater than 2. When the nth pixel PXn is a target pixel, the (n-1)th pixel PXn-1 may be a reference pixel. In other words, the target pixel and the reference pixel may be normal pixels arranged adjacent to each other in the column direction.

[0166] The nth pixel Pxn may include an nth photodiode PDn, an nth transfer element TTn, an nth floating diffusion node FDn, an nth reset transistor element RTn, an nth driving element DTn, and an nth selection element STn.

[0167] The nth photodiode PDn may be coupled between a low voltage terminal (eg, a ground voltage terminal) and the nth transfer element TTn. For example, the nth photodiode PDn may generate charges corresponding to incident light during an nth integration time.

[0168] An nth transfer element TTn may be coupled between an nth photodiode PDn and an nth floating diffusion node FDn. The nth transfer element TTn may selectively couple the nth photodiode PDn to the nth floating diffusion node FDn based on an nth transfer control signal TXn. For example, the nth transfer element TTn may transfer charge of the nth photodiode PDn to the nth floating diffusion node FDn during an nth transfer time Cn of an nth row time nth_RT.

[0169] The nth floating diffusion node FDn may be coupled to the nth capacitor CCn. The nth capacitor CCn may store charges generated by the nth photodiode PDn. For example, the nth capacitor CCn may be a parasitic capacitor.

[0170] The nth reset transistor element RTn may be coupled between the fifth line L4 and the nth floating diffusion node FDn. The nth reset transistor element RTn may selectively couple the fifth line L4 to the nth floating diffusion node FDn based on an nth reset control signal Rxn. For example, the nth reset transistor element RTn may electrically couple the fifth line L4 to the nth floating diffusion node FDn during an nth reset time An of an nth row time nth_RT.

[0171] The nth driving element DTn may be coupled between the first line L0 and the nth selecting element STn. The nth driving element DTn may generate an nth pixel signal corresponding to a voltage loaded on the nth floating diffusion node FDn.

[0172] The nth selection element STn may be coupled between the nth driving element DTn and the third line L2. The nth selection element STn may output the nth pixel signal to the third line L2 based on the nth selection control signal SXn. For example, the nth selection element STn may output the nth reset signal as the nth pixel signal during the nth reset readout time Bn of the nth row time nth_RT, and output the nth data signal as the nth pixel signal during the nth data readout time Dn of the nth row time nth_RT.

[0173] The nth transfer control signal TXn, the nth reset control signal RXn, and the nth selection control signal SXn may be nth row control signals generated by the row decoder 320 .

[0174] The (n-1)th pixel PXn-1 may include an (n-1)th photodiode PDn-1, an (n-1)th transfer element TTn-1, an (n-1)th floating diffusion node FDn-1, an (n-1)th reset transistor element RTn-1, an (n-1)th driving element DTn-1 and an (n-1)th selection element STn-1.

[0175] The (n-1)th photodiode PDn-1 may be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the (n-1)th transfer element TTn-1. For example, the (n-1)th photodiode PDn-1 may generate charges corresponding to incident light during the (n-1)th integration time.

[0176] The (n-1)th transfer element TTn-1 may be coupled between the (n-1)th photodiode PDn-1 and the (n-1)th floating diffusion node FDn-1. The (n-1)th transfer element TTn-1 may selectively couple the (n-1)th photodiode PDn-1 to the (n-1)th floating diffusion node FDn-1 based on the (n-1)th transfer control signal TXn-1. For example, the (n-1)th transfer element TTn-1 may transfer charge of the (n-1)th photodiode PD-1 to the (n-1)th floating diffusion node FDn-1 during the (n-1)th transfer time of the (n-1)th row time (n-1)th_RT.

[0177] The (n-1)th floating diffusion node FDn-1 may be coupled to the (n-1)th capacitor CCn-1. The (n-1)th capacitor CCn-1 may store charge generated by the (n-1)th photodiode PD-1. For example, the (n-1)th capacitor CCn-1 may be a parasitic capacitor.

[0178] The (n-1)th reset transistor element RTn-1 may be coupled between the fourth line L3 and the (n-1)th floating diffusion node FDn-1. The (n-1)th reset transistor element RTn-1 may selectively couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 based on the (n-1)th reset control signal RXn-1. For example, the (n-1)th reset transistor element RTn-1 may electrically couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 during the (n-1)th reset time of the (n-1)th row time (n-1)th_RT. Additionally, the (n-1)th reset transistor element RTn-1 may electrically couple the fourth line L3 to the (n-1)th floating diffusion node FDn-1 during the nth reset time An of the nth row time nth_RT.

[0179] The (n-1)th driving element DTn-1 may be coupled between the first line L0 and the (n-1)th selecting element STn-1. The (n-1)th driving element DTn-1 may generate the (n-1)th pixel signal corresponding to the voltage applied to the (n-1)th floating diffusion node FDn-1.

[0180] The (n-1)th selection element STn-1 may be coupled between the (n-1)th drive element DTn-1 and the second line L1. The (n-1)th selection element STn-1 may output the (n-1)th pixel signal to the second line L1 based on the (n-1)th selection control signal SXn-1. For example, the (n-1)th selection element STn-1 may output the (n-1)th reset signal as the (n-1)th pixel signal during the (n-1)th reset readout time of the (n-1)th row time (n-1)th_RT, and output the (n-1)th data signal as the (n-1)th pixel signal during the (n-1)th data readout time of the (n-1)th row time (n-1)th_RT. In addition, the (n-1)th selection element STn-1 may electrically couple the (n-1)th drive element DTn-1 to the second line L1 during the nth row time nth_RT.

[0181] The (n−1)th transfer control signal TXn−1, the (n−1)th reset control signal RXn−1, and the (n−1)th selection control signal SXn−1 may be the (n−1)th row control signals generated by the row decoder 320 .

[0182] The amplification region 340 may include an in-pixel amplifier 341 , a switching circuit 343 , and a precharger 345 .

[0183] The in-pixel amplifier 341 can sequentially output the (n-1)th pixel signal and the nth pixel signal through the output terminal VOUT. For example, the in-pixel amplifier 341 can amplify the gain of the (n-1)th pixel signal during the (n-1)th row time (n-1)th_RT, and amplify the gain of the nth pixel signal during the nth row time nth_RT. Because the in-pixel amplifier 341 corresponds to the reference-shared in-pixel differential common source amplifier (RSDA) disclosed in the paper "A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps", its detailed description is omitted.

[0184] The switch circuit 343 may include first to eighth switches S0 to S7. The first to eighth switches S0 to S7 may be controlled based on a row change signal RC. The row change signal RC may be generated by the timing controller 310. Since the first to eighth switches S0 to S7 are similar to the switch described in the paper “A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps” Figure 5 8.2, and therefore a detailed description thereof is omitted. However, the switch circuit 343 is shown according to the RSDA mode disclosed in the paper.

[0185] The precharger 345 may be coupled to the output terminal VOUT of the in-pixel amplifier 341. The precharger 345 is described in more detail below.

[0186] Figure 14 This is an example Figure 13 The equivalent circuit diagram of the (n-1)th pixel PXn-1, the nth pixel PXn, the in-pixel amplifier 341 and the pre-charger 345 is shown. Figure 14 A case where the n-th pixel PXn is coupled to the output terminal VOUT of the intra-pixel amplifier 341 is illustrated.

[0187] Reference Figure 14 , the intra-pixel amplifier 341 may output the pixel signal of the n-th pixel PXn through the output terminal VOUT by using the (n-1)-th pixel PXn-1.

[0188] The precharger 345 may provide a precharge current IP to the output terminal VOUT according to the voltage level of the pixel signal of the n-th pixel PXn read out through the output terminal VOUT. For example, the precharger 345 may provide a precharge current IP adaptively adjusted according to the slope of the pixel signal (i.e., the amount of change in the voltage level of the pixel signal) to the output terminal VOUT during the initial time of the n-th data readout time Dn, wherein a steeper slope is compensated for with a larger precharge current.

[0189] Figure 15 This is an example Figure 13 and Figure 14 An example circuit diagram of a pre-charger 345 is shown.

[0190] Reference Figure 15 , the precharger 345 may include a control circuit 345A and a current supply circuit 345B.

[0191] The control circuit 345A may be coupled between the output terminal VOUT and the high voltage terminal. The control circuit 345A may generate a control voltage corresponding to the voltage level of the pixel signal of the nth pixel PXn. For example, the control circuit 345A may include a sensing circuit 3451 and a reference circuit 3453.

[0192] The sensing circuit 3451 may be coupled between the output terminal VOUT and the control node AA. The sensing circuit 3451 may sense the slope of the pixel signal of the nth pixel PXn based on the control signal ROB and provide a control voltage to the control node AA based on the sensing result. For example, the sensing circuit 3451 may include a first switch SS0 and an AC coupler ACC. The first switch SS0 may be coupled to the output terminal VOUT and the first node. The first switch SS0 may operate based on the control signal ROB. For example, the first switch SS0 may be short-circuited during the nth reset time An and the initial time. The control signal ROB may be a signal obtained by performing an OR operation on a reference control signal RXX and a boost control signal BST. The reference control signal RXX and the boost control signal BST may be generated by the timing controller 310. The AC coupler ACC may be coupled between the first node and the control node AA. The AC coupler ACC may generate a control voltage, via the control node AA, whose voltage level varies in accordance with the slope of the pixel signal of the nth pixel PXn.

[0193] The reference circuit 3453 can provide a reference voltage to the control node AA based on a reference control signal RXX. That is, the reference circuit 3453 can initialize the control node AA to the reference voltage during the nth reset time An. For example, the reference circuit 3453 may include a second switch SS1, a current-voltage converter NM0, a third switch SS2, and a current source CS. The second switch SS1 may be coupled between the control node AA and a second node. The second switch SS1 may operate based on the reference control signal RXX. For example, the second switch SS1 may be short-circuited during the nth reset time An. The current-voltage converter NM0 may be coupled between the second node and the third node. The current-voltage converter NM0 may convert a reference current generated by the current source CS into a reference voltage. The third switch SS2 may be coupled between the third node and the fourth node. The third switch SS2 may operate based on the reference control signal RXX. For example, the third switch SS2 may be short-circuited during the nth reset time An. The current source CS may be coupled between the fourth node and the high voltage terminal. The current source CS may generate a reference current.

[0194] The current supply circuit 345B can be coupled between the output terminal VOUT and the high voltage terminal. The current supply circuit 345B can provide a pre-charge current IP adaptively adjusted according to the voltage level of the pixel signal of the nth pixel PXn (e.g., a higher voltage level results in a greater pre-charge current) to the output terminal VOUT based on a control voltage applied via the control node AA. For example, the current supply circuit 345B may include a first voltage-to-current converter NM1, a fourth switch SS3, first current mirrors PM0 and PM1, and a driver PM2. The first voltage-to-current converter NM1 can be coupled between the low voltage terminal and the fifth node. The first voltage-to-current converter NM1 can convert the control voltage into a control current IS. The fourth switch SS3 can be coupled between the fifth node and the sixth node. The fourth switch SS3 can operate based on a boost control signal BST. For example, the fourth switch SS3 can be short-circuited during the initial period of the nth data readout time Dn. The first current mirrors PM0 and PM1 can be coupled between the sixth node, the output terminal VOUT, and the high voltage terminal. The first current mirrors PM0 and PM1 can generate a precharge current IP corresponding to the control current IS. A driver PM2 can be coupled between a high voltage terminal and a common gate node of the first current mirrors PM0 and PM1. The driver PM2 can be controlled based on a boost control signal BST. For example, the driver PM2 can disable the first current mirrors PM0 and PM1 during the nth row time nth_RT, except for the initialization time of the nth data readout time Dn.

[0195] Figure 16 This is an example Figure 13 and Figure 14 A circuit diagram of another example of a pre-charger 345 is shown.

[0196] Reference Figure 16 , the precharger 345 may include a control circuit 345A, a current supply circuit 345B and a subtraction circuit 345C.

[0197] Since the control circuit 345A and the current supply circuit 345B are Figure 15 The same as described in , so the detailed description is omitted. Figure 16 In the embodiment, the subtraction current IR may be applied to the precharge current IP generated by the current supply circuit 345B. That is, the precharge current IP may be equal to the current obtained by subtracting the subtraction current IR from the control current IS (IP=IS-IR).

[0198] The subtraction circuit 345C can be coupled between the high voltage terminal and the low voltage terminal. The subtraction circuit 345C can be coupled between the second node of the reference circuit 3453 and the sixth node of the current supply circuit 345B. The subtraction circuit 345C can receive a reference voltage via the second node and generate a subtraction current IR corresponding to the reference voltage or reference current via the sixth node. For example, the subtraction circuit 345C can include a fifth switch SS4, a capacitor CC, a second voltage-current converter NM2, a sixth switch SS5, and second current mirrors PM3 and PM4.

[0199] The fifth switch SS4 may be coupled between the second node and the seventh node. The fifth switch SS4 may be operated based on the reference control signal RXX. For example, the fifth switch SS4 may be short-circuited during the nth reset time An.

[0200] The capacitor CC may be coupled between the seventh node and the low voltage terminal. The capacitor CC may store a reference voltage.

[0201] The second voltage-current converter NM2 may be coupled between the seventh node, the low voltage terminal, and the eighth node. The second voltage-current converter NM2 may generate a storage current corresponding to the reference voltage stored in the capacitor CC through the eighth node.

[0202] The sixth switch SS5 may be coupled between the eighth node and the ninth node. The sixth switch SS5 may be operated based on the boost control signal BST. For example, the sixth switch SS5 may be short-circuited during the initial period of the nth data readout time Dn.

[0203] The second current mirrors PM3 and PM4 may be coupled between the ninth node, the high voltage terminal, and the sixth node of the current supply circuit 345B. The second current mirrors PM3 and PM4 may generate a subtraction current IR corresponding to the storage current through the sixth node.

[0204] In the following, reference is made to Figure 17 and Figure 18 The operation of the image sensing device 300 according to the third embodiment having the above-described configuration is described.

[0205] Figure 17 This is an example Figure 12 The timing diagram of the operation of the image sensing device shown in FIG. A case where the n-th pixel PXn is the target pixel is representatively described.

[0206] Reference Figure 17 During the nth row time nth_RT, the (n-1)th pixel PXn-1 may be coupled to the intra-pixel amplifier 341 as a reference pixel via the switch circuit 343, and the nth pixel PXn may be coupled to the intra-pixel amplifier 341 as a target pixel via the switch circuit 343. During the nth row time nth_RT, the (n-1)th selection element STn-1 may be turned on based on the (n-1)th selection control signal SXn-1, and the nth selection element STn may be turned on based on the nth selection control signal SXn.

[0207] During the nth reset time An of the nth row time nth_RT, the (n-1)th reset transistor element RTn-1 can be turned on based on the (n-1)th reset control signal RXn-1, and the nth reset transistor element RTn can be turned on based on the nth reset control signal RXn. Therefore, a negative feedback loop can be formed between the nth floating diffusion node FDn and the output terminal VOUT, and an offset can be stored in the nth floating diffusion node FDn. The offset can refer to a mismatch between the (n-1)th pixel PXn-1 and the nth pixel PXn. For reference, the offset can be offset by a correlated double sampling (CDS) operation.

[0208] Meanwhile, during the nth reset time An, the first switch SS0 included in the sensing circuit 3451 and the second and third switches SS1 and SS2 included in the reference circuit 3453 may be short-circuited by the reference control signal RXX. Therefore, the control voltage of the control node AA may be initialized to a voltage level corresponding to the reference voltage generated by the reference circuit 3453.

[0209] During the nth reset readout time Bn, the in-pixel amplifier 341 may output a reset signal corresponding to the offset as a pixel signal of the nth pixel PXn.

[0210] During the nth transfer time Cn, the nth pixel PXn may transfer charges accumulated in the nth photodiode PDn to the nth floating diffusion node FDn based on the nth transfer control signal TXn.

[0211] During the nth data readout time Dn, the in-pixel amplifier 341 can output a data signal corresponding to the charge as the pixel signal of the nth pixel PXn. At this time, during the initial time of the nth data readout time Dn, the precharger 345 can provide a precharge current IP adaptively adjusted according to the voltage level of the pixel signal of the nth pixel PXn to the output terminal VOUT (for example, a higher voltage level results in a larger precharge current). Therefore, the stabilization time of the pixel signal of the nth pixel PXn output through the output terminal VOUT can be reduced, and thus the readout time of the pixel signal can be shortened.

[0212] When the subtraction circuit 345C is included in the precharger 345, the subtraction current IR can be applied to the precharge current IP. That is, the precharger 345 can generate a current obtained by subtracting the subtraction current IR from the control current IS as the precharge current IP (IP=IS-IR). Therefore, when the pixel signal of the nth pixel PXn is output through the output terminal VOUT, the overshoot that occurs in the pixel signal can be prevented. As the pixel signal has a lower voltage level, the pixel signal is more affected by the reference voltage of the reference circuit 3453 due to the precharge current IP. Therefore, when the pixel signal has a lower voltage level, an overshoot with a larger level may occur in the pixel signal due to the precharge current IP, but the precharge current IP can be generated by subtracting the subtraction current IR corresponding to the reference voltage from the control current IS, thereby preventing the overshoot.

[0213] Figure 18 Another example Figure 17 A timing diagram of the operation of the image sensing device 300 is shown.

[0214] Reference Figure 18 As described above, the precharger 345 may generate a precharge current IP that is adaptively adjusted according to the voltage level of the pixel signal of the n-th pixel PXn. For example, as the slope of the pixel signal is smaller (i.e., as the amount of change in the voltage level of the pixel signal decreases), the precharger 345 may generate a precharge current IP having a lower level, and as the slope of the pixel signal is steeper (i.e., as the amount of change in the voltage level of the pixel signal increases), the precharger 345 may generate a precharge current IP having a higher level.

[0215] According to the third embodiment, there is an advantage in that the voltage of the readout line (ie, the output terminal) of the pixel signal is adaptively boosted according to the voltage level of the pixel signal.

[0216] According to an embodiment of the present disclosure, the load of a readout line of a pixel signal can be reduced in a structure in which an in-pixel amplifier is coupled to the readout line, and thus the readout speed of the pixel signal can be increased.

[0217] In addition, according to an embodiment of the present disclosure, the stabilization time of a pixel signal output through a readout line of the pixel signal can be minimized in a structure in which an intra-pixel amplifier is coupled to the readout line, and thus the readout speed of the pixel signal can be improved.

[0218] Although the present disclosure has been shown and described with respect to specific embodiments, the disclosed embodiments are provided for illustration and are not intended to be limiting. Furthermore, it should be noted that, as will be appreciated by those skilled in the art from this disclosure, the present disclosure may be implemented in various ways by substitutions, changes, and modifications that fall within the scope of the appended claims.

[0219] In addition, the methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device (e.g., control circuit 345A (described above)). The computer, processor, controller, or other signal processing device can be those described herein or elements in addition to those described herein. Because the algorithms (or operations of the computer, processor, controller, or other signal processing device) that form the basis of these methods are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0220] When implemented at least partially in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers and other signal generation and signal processing functions (such as control circuit 345A (described above)) may include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing device.

[0221] CROSS-REFERENCE TO RELATED APPLICATIONS

[0222] This application claims priority to Korean Patent Application No. 10-2021-0028903, filed on March 4, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensing device, comprising: Reference pixels; a target pixel including a floating diffusion node and a reset transistor element that resets a potential of the floating diffusion node during a reset period of a target row time; an amplifier that is commonly coupled to the reference pixel and the target pixel and outputs a target pixel signal of the target pixel through an output terminal during a readout period of the target row time; as well as A switch circuit decouples the reset transistor element from the output terminal during at least the readout period.

2. The image sensing device according to claim 1, wherein The switch circuit couples the reset transistor element to the output terminal during at least the reset period.

3. The image sensing device according to claim 1, wherein The switching circuit includes a first switch and a second switch connected in series between the output terminal and the reset transistor element, the first switch being disconnected based on a line decoupling signal during at least the readout period of the target row time, and the second switch being shorted based on a row change signal during the target row time.

4. The image sensing device according to claim 1, wherein The reference pixels include pixels disposed in a row adjacent to a row in which the target pixels are disposed.

5. An image sensing device, comprising: a plurality of pixels, each of the plurality of pixels including a floating diffusion node and a reset transistor element, the reset transistor element resetting a potential of the floating diffusion node; an amplifier, wherein the amplifier sequentially outputs a plurality of pixel signals of the plurality of pixels through an output terminal; as well as a switching circuit that couples a first pixel of the plurality of pixels to the amplifier as a reference pixel and a second pixel of the plurality of pixels to the amplifier as a target pixel for each target row time, The switch circuit includes a first switch that decouples the output terminal from the reset transistor element included in the target pixel during other row times of the target row time except for an initial row time.

6. The image sensing device according to claim 5, wherein: The first switch couples the reset transistor element to the output terminal during the initial row time.

7. The image sensing device according to claim 5, wherein: The reset transistor element resets the potential of the floating diffusion node during a reset period of the target row time, and the initial row time includes the reset period.

8. The image sensing device according to claim 5, wherein: The target pixel generates a target pixel signal during a readout period of the target row time, and the other row time includes the readout period.

9. The image sensing device according to claim 5, wherein: The switch circuit further includes a second switch serially coupled to the first switch between the output terminal and the reset transistor element, the first switch being opened during the other row time of the target row time based on a line decoupling signal, and the second switch being shorted during the target row time based on a row change signal.

10. The image sensing device according to claim 5, wherein: The first pixels are arranged in a first row adjacent to a second row in which the second pixels are arranged.

11. An image sensing device, comprising: a target pixel that is electrically decoupled from an output terminal of a target pixel signal during a transfer time during which charge accumulated in the photodiode is transferred to a floating diffusion node, and outputs the target pixel signal through the output terminal during a readout time after the transfer time; an amplifier coupled to a reference pixel and the target pixel and amplifying the target pixel signal during the readout time; a disabling circuit that disables the amplifier during the transfer time; as well as A compensation circuit provides a compensation current to a common node to which a current source included in the amplifier is coupled during the transfer time.

12. The image sensing device according to claim 11, wherein The disabling circuit is coupled between a high voltage terminal and the amplifier and electrically decouples the high voltage terminal from the amplifier during the transfer time.

13. The image sensing device according to claim 11, wherein The compensation circuit comprises: a first switch coupled between the high voltage terminal and a connection node and operated based on a first control signal having a fixed voltage level; and A second switch is coupled between the coupling node and the common node and operates based on a second control signal activated during the transfer time.

14. The image sensing device according to claim 11, further comprising: A switching circuit couples the reference pixel to the amplifier and couples the target pixel to the amplifier during the transfer time and the readout time.

15. The image sensing device according to claim 11, wherein The reference pixels include pixels disposed in a row adjacent to a row in which the target pixels are disposed.

16. An image sensing device, comprising: Reference pixels; a target pixel that is electrically decoupled from an output terminal of a target pixel signal during a transfer time during which charge accumulated in the photodiode is transferred to a floating diffusion node, and outputs the target pixel signal through the output terminal during a readout time after the transfer time; an amplifier coupled to the reference pixel and the target pixel and amplifying the target pixel signal during the readout time; a disabling circuit that disables the amplifier during the transfer time; as well as An interrupt circuit electrically decouples a common node from a current source included in the amplifier during the transfer time.

17. The image sensing device according to claim 16, wherein: The disabling circuit is coupled between a high voltage terminal and the amplifier and electrically decouples the high voltage terminal from the amplifier during the transfer time.

18. The image sensing device according to claim 16, wherein: The reference pixels include pixels disposed in a row adjacent to a row in which the target pixels are disposed. 19 . The image sensing device according to claim 16 , the image sensing pixel further comprising a switching circuit that couples the reference pixel to the amplifier and couples the target pixel to the amplifier during the transfer time and the readout time.

20. An image sensing device, comprising: Reference pixels; a target pixel that is electrically decoupled from an output terminal of a target pixel signal during a transfer time during which charge accumulated in the photodiode is transferred to a floating diffusion node, and outputs the target pixel signal through the output terminal during a readout time after the transfer time; an amplifier coupled to the reference pixel, the target pixel, a high voltage terminal, and a low voltage terminal, and amplifying the target pixel signal during the readout time; A disabling circuit is coupled between the high voltage terminal and the amplifier and disables the amplifier during the transfer time.

21. An image sensing device, comprising: Multiple pixels; an amplifier that sequentially amplifies a plurality of pixel signals output from the plurality of pixels; a switching circuit that couples a first pixel of the plurality of pixels to the amplifier as a reference pixel and couples a second pixel of the plurality of pixels to the amplifier as a target pixel during a corresponding row time; as well as A disabling circuit disables the amplifier during a portion of the corresponding row time.

22. The image sensing device according to claim 21, wherein The portion of the corresponding row time includes a transfer time for transferring charges accumulated in a photodiode of the target pixel to a floating diffusion node of the target pixel.

23. The image sensing device according to claim 21, wherein The disabling circuit is coupled between a high voltage terminal and the amplifier and electrically decouples the high voltage terminal from the amplifier during the portion of the corresponding row time. 24 . The image sensing device of claim 21 , further comprising a compensation circuit that provides a compensation current to a common node to which a current source included in the amplifier is coupled during the portion of the corresponding row time.

25. The image sensing device according to claim 24, wherein: The compensation circuit comprises: a first switch coupled between the high voltage terminal and a connection node and operated based on a first control signal having a fixed voltage level; and A second switch is coupled between the coupling node and the common node and operates based on a second control signal activated during the portion of the corresponding row time. 26 . The image sensing device of claim 21 , further comprising an interrupt circuit that electrically decouples a common node from a current source included in the amplifier during the portion of the corresponding row time.

27. The image sensing device according to claim 21, wherein The first pixels are arranged in a first row adjacent to a second row in which the second pixels are arranged.

28. A method for operating an image sensing device, the method comprising the following steps: maintaining a voltage level of an output terminal of a target pixel at a reset level of the target pixel during a transfer time during which charges accumulated in the photodiode are transferred to a floating diffusion node; as well as During a readout period after the transfer time, a voltage level of the output terminal is amplified from the reset level to a target level corresponding to the target pixel.

29. The operating method according to claim 28, wherein: During the readout period, the amplifier coupled to the output terminal is disabled, and the target pixel is electrically decoupled from the output terminal.

30. The operating method according to claim 29, wherein: During the readout period, a current generated from a current source included in the amplifier is compensated.

31. The operating method according to claim 29, wherein: During the readout period, a current source included in the amplifier is electrically decoupled from a common node to which the target pixel and the reference pixel are coupled.

Images