Semiconductor device and method for manufacturing the same
By setting grooves between dummy gate structures and converting the hard mask layer during the preparation process of semiconductor devices, the problem of dummy gate height difference is solved, and the uniformity and yield of the device are improved.
Patent Information
- Application Number
- CN202510933785.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-08
- Publication Date
- 2025-09-16
- Estimated Expiration
- 2045-07-08
AI Technical Summary
In the HKMG process, after the dummy gate etching and sidewall etching, the dummy gate heights in the storage area and the peripheral area are different, resulting in instability in the subsequent process, affecting the uniformity of the WAT test and the device yield.
A groove is set between the pseudo gate structure of the storage area and the peripheral area, and a part of the thickness of the first hard mask layer is converted into a silicon oxynitride hard mask layer, so that the upper surfaces of the silicon oxynitride hard mask layers in the storage area and the peripheral area are on the same horizontal plane, and the height difference is removed by flattening treatment.
The thickness uniformity of semiconductor devices is improved, and the uniformity of WAT testing and device yield are enhanced.
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Figure CN120456556B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a preparation method thereof. Background Art
[0002] As semiconductor technology nodes shrink to 28 nanometers and below, low leakage high dielectric constant dielectric metal gate (HKMG) technology is widely used in MOSFETs to meet the requirements of metal gates with smaller line widths (for example, below 30 nm).
[0003] However, the HKMG process usually has the problem of different dummy gate heights in different areas (such as the storage area and peripheral area) after the dummy gate etching and sidewall etching processes, which brings instability to the subsequent process and affects the uniformity of WAT (Wafer Acceptable Test) testing and device yield. Summary of the Invention
[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can solve the problem that the HKMG process usually has different dummy gate heights in different regions after the dummy gate etching and sidewall etching processes.
[0005] In order to solve the above problems, the present invention provides a method for preparing a semiconductor device, comprising the following steps:
[0006] A method for preparing a semiconductor device comprises the following steps:
[0007] Providing a substrate, the substrate comprising a storage region and a peripheral region, dummy gate structures spaced apart are formed on the substrate in both the storage region and the peripheral region, grooves are provided between adjacent dummy gate structures in each of the storage region and the peripheral region, the dummy gate structure comprising, from bottom to top, a polysilicon layer, a first hard mask layer, and a second hard mask layer, wherein the thickness of the second hard mask layer in the peripheral region is greater than the thickness of the second hard mask layer in the storage region;
[0008] removing the second hard mask layer and converting a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer;
[0009] Filling the groove with a dielectric layer, wherein the upper surface of the dielectric layer is higher than the upper surface of the dummy gate structure;
[0010] The dielectric layer is planarized, and a first hard mask layer having a partial thickness in the dummy gate structure is retained.
[0011] Optionally, the thickness of the first hard mask layer satisfies the formula:
[0012] H=a*h;
[0013] Among them, the value of a is 3~6; the value of h is 190 Å ~210Å.
[0014] Optionally, the material of the first hard mask layer includes silicon nitride, and the material of the second hard mask layer includes a silicon oxide layer.
[0015] Furthermore, the specific method of converting a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer is:
[0016] filling the groove with an organic material layer, wherein the organic material layer fills a portion of the depth of the groove;
[0017] A partial thickness of the first hard mask layer is converted into a silicon oxynitride hard mask layer.
[0018] Furthermore, the specific method of forming the silicon oxynitride hard mask layer is:
[0019] Oxygen plasma is injected into the surface of the first hard mask layer to convert a portion of the first hard mask layer into an oxygen-rich silicon oxynitride hard mask layer.
[0020] Furthermore, an upper surface of the silicon oxynitride hard mask layer in the storage region and an upper surface of the silicon oxynitride hard mask layer in the peripheral region are on the same horizontal plane.
[0021] Furthermore, the thickness of the unconverted first hard mask layer is greater than h, and the value of h is 190 Å ~ 210 Å.
[0022] Optionally, the specific method for removing the second hard mask layer is:
[0023] The second hard mask layer is removed by a wet etching process.
[0024] Optionally, the specific method of filling the dielectric layer is:
[0025] forming a contact etch stop layer, wherein the contact etch stop layer covers the substrate surface at the groove, the sidewall of the dummy gate structure, and the upper surface of the silicon oxynitride hard mask layer;
[0026] A dielectric layer is filled in the groove, and the dielectric layer also covers the contact etching stop layer on the dummy gate structure.
[0027] On the other hand, the present invention also provides a semiconductor device manufactured using the semiconductor device manufacturing method.
[0028] Compared with the prior art, the present invention has the following unexpected technical effects:
[0029] The present invention provides a semiconductor device and a method for preparing the same. The method for preparing the semiconductor device comprises the following steps: providing a substrate, the substrate comprising a storage area and a peripheral area, dummy gate structures arranged at intervals are formed on the substrate in the storage area and the peripheral area, grooves are provided between adjacent dummy gate structures in the storage area and the peripheral area, the dummy gate structures comprising, from bottom to top, a polysilicon layer, a first hard mask layer, and a second hard mask layer, wherein the thickness of the second hard mask layer located in the peripheral area is greater than the thickness of the second hard mask layer located in the storage area; removing the second hard mask layer and converting a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer; filling the groove with a dielectric layer, the upper surface of the dielectric layer being higher than the upper surface of the dummy gate structure; planarizing the dielectric layer and retaining a portion of the thickness of the first hard mask layer in the dummy gate structure. The present invention removes the second hard mask layer and converts a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer, so that the upper surface of the silicon oxynitride hard mask layer in the storage area and the upper surface of the silicon oxynitride hard mask layer in the peripheral area are on the same horizontal plane. In this way, there is no step between the storage area and the peripheral area when the dielectric layer is planarized, which is beneficial to improving the thickness uniformity of the semiconductor device, thereby improving the uniformity of the WAT test and the device yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 This is a schematic diagram of the structure of a semiconductor device after dummy gate etching.
[0031] Figure 2 This is a schematic diagram of the structure of a semiconductor device after the grinding process.
[0032] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor device provided in one embodiment of the present invention.
[0033] Figure 4 A schematic structural diagram of a substrate provided in one embodiment of the present invention.
[0034] Figure 5 This is a schematic structural diagram after forming a dummy gate structure and a groove according to an embodiment of the present invention.
[0035] Figure 6 This is a structural diagram after forming the first sidewall according to an embodiment of the present invention.
[0036] Figure 7 FIG. 1 is a schematic structural diagram after the second hard mask layer is removed according to an embodiment of the present invention.
[0037] Figure 8 FIG. 1 is a schematic structural diagram after forming an organic material layer according to an embodiment of the present invention.
[0038] Figure 9 FIG. 1 is a schematic structural diagram of a silicon oxynitride hard mask layer formed according to an embodiment of the present invention.
[0039] Figure 10 FIG. 1 is a schematic structural diagram after forming a dielectric layer according to an embodiment of the present invention.
[0040] Figure 11 FIG. 1 is a schematic diagram of a structure after a planarization process according to an embodiment of the present invention.
[0041] Description of reference numerals:
[0042] Figure 1-Figure 2 Middle: 1-polysilicon layer; 2-second hard mask layer; I-peripheral region; II-storage region;
[0043] Figure 4-11 Figure 1: 100 - substrate; 201, 202 - grooves; 203 - dummy dummy gate structure; 204 - test dummy gate structure; 205 - dummy gate structure of storage area; 210 - polysilicon layer; 220 - first hard mask layer; 230 - second hard mask layer; 241 - first sidewall spacer; 242 - contact etch stop layer; 250 - silicon oxynitride hard mask layer; 260 - dielectric layer; 300 - organic material layer; I - peripheral region; II - storage region. DETAILED DESCRIPTION
[0044] The following is a further detailed description of a semiconductor device and a method for manufacturing the same according to the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a general guide for those skilled in the art and not as a limitation of the present invention.
[0045] For the sake of clarity, not all features of actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as adapting from one embodiment to another to accommodate system or business constraints. Furthermore, it should be understood that such development work may be complex and time-consuming, but is nevertheless a routine undertaking for those skilled in the art.
[0046] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific embodiments of the present invention are further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0047] The method for preparing the metal gate includes:
[0048] First, a polysilicon layer 1, a nitride hard mask layer and an oxide hard mask layer 2 are formed on a substrate, wherein the thickness h of the nitride hard mask layer is 190 Å to 210 Å, and the substrate includes a peripheral region and a storage region.
[0049] Then, if Figure 1 As shown, the oxide hard mask layer 2, the nitride hard mask layer and the polysilicon layer 1 are sequentially etched to form a groove and a dummy gate;
[0050] Next, please continue to read Figure 1 , forming a first spacer film layer on the outer wall of the dummy gate, and etching the first spacer film layer to expose the oxide hard mask layer 2 and the substrate, and forming a spacer;
[0051] Then, if Figure 2 As shown, a contact etch stop layer (CESL) is formed outside the first spacer, the CESL also covers the oxide hard mask layer 2, a dielectric layer is filled in the groove, and the dielectric layer also covers the second spacer on the dummy gate;
[0052] Next, please continue to read Figure 2 , grinding and removing the dielectric layer, the contact etch stop layer, the oxide hard mask layer 2 and part of the nitride hard mask layer above the dummy gate;
[0053] Next, the polysilicon layer 1 is removed by etching. If there is a nitride hard mask layer on the polysilicon layer 1, it can be removed together with the nitride hard mask layer.
[0054] It can be seen that after forming the dummy gate and dummy gate sidewalls, the thickness of the oxide hard mask layer in the storage area is less than the thickness of the oxide hard mask layer in the peripheral area, and the height difference between the dummy gate in the storage area and the dummy gate in the peripheral area is, for example, Δh1. According to analysis, the main reason for the height difference is that the line width of the dummy gate in the peripheral area is generally too large. For example, there are dummy gates with the same line width as the dummy gate in storage area II (for example, used to form a test MOS tube) and dummy gates with a line width greater than the line width of the dummy gate in storage area II (for example, used to form virtual dummy gates located on both sides of the test MOS tube). This consumes too much oxide hard mask layer in the storage area during the gate etching and sidewall etching processes. The above height difference causes the height of the dummy gate in the peripheral area to be greater than the height of the dummy gate in the storage area during the subsequent grinding and removal process, and the height difference is, for example, Δh2. This height difference brings instability to the subsequent manufacturing process, thereby affecting the uniformity of WAT testing and device yield.
[0055] Based on the above analysis, Figure 3 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is provided. Figure 3As shown, this embodiment provides a method for preparing a semiconductor device, comprising the following steps:
[0056] Step S10: Providing a substrate, the substrate comprising a storage region and a peripheral region, dummy gate structures spaced apart are formed on the substrate in the storage region and the peripheral region, grooves are provided between adjacent dummy gate structures in the storage region and the peripheral region, the dummy gate structures comprising, from bottom to top, a polysilicon layer, a first hard mask layer, and a second hard mask layer, wherein the thickness of the second hard mask layer in the peripheral region is greater than the thickness of the second hard mask layer in the storage region;
[0057] Step S20: removing the second hard mask layer, and converting a portion of the first hard mask layer into a silicon oxynitride hard mask layer;
[0058] Step S30: filling the groove with a dielectric layer, wherein the upper surface of the dielectric layer is higher than the upper surface of the dummy gate structure;
[0059] Step S40: planarizing the dielectric layer and retaining a portion of the thickness of the first hard mask layer in the dummy gate structure.
[0060] This embodiment provides a method for preparing a semiconductor device. By removing the second hard mask layer and converting a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer, the upper surface of the silicon oxynitride hard mask layer in the storage area and the upper surface of the silicon oxynitride hard mask layer in the peripheral area are on the same horizontal plane. In this way, there is no step between the storage area and the peripheral area during the planarization process of the dielectric layer, which is conducive to improving the thickness uniformity of the semiconductor device, thereby improving the uniformity of the WAT test and the device yield.
[0061] The following combination Figure 4-11 A method for manufacturing a semiconductor device provided in this embodiment is described in detail.
[0062] like Figure 4-Figure 6 As shown, step S10 is first performed to provide a substrate 100, wherein the substrate 100 includes a storage area II and a peripheral area I, and dummy gate structures are formed on the substrate 100 in the storage area II and the peripheral area I. In the storage area II and the peripheral area I, grooves 201 or 202 are provided between adjacent dummy gate structures, respectively. The dummy gate structure includes, from bottom to top, a polysilicon layer 210, a first hard mask layer 220, and a second hard mask layer 230, wherein the thickness of the second hard mask layer 230 located in the peripheral area I is greater than the thickness of the second hard mask layer 230 located in the storage area II.
[0063] This step specifically includes:
[0064] like Figure 4As shown, a substrate 100 is first provided, wherein the substrate 100 includes a storage region II and a peripheral region I. A polysilicon layer 210 , a first hard mask layer 220 and a second hard mask layer 230 are formed on the substrate 100 through a deposition process.
[0065] The thickness of the first hard mask layer 220 satisfies the formula:
[0066] H=a*h;
[0067] Among them, the value of a is 3~6; the value of h is 190 Å ~210Å.
[0068] The increased thickness of the first hard mask layer 220 formed in this embodiment is beneficial for ensuring that a sufficient thickness of the first hard mask layer 220 remains after the subsequent formation of the silicon oxynitride hard mask layer 250 .
[0069] The substrate 100 can provide an operating platform for subsequent processes. It can be any base material for carrying semiconductor integrated circuit components known to those skilled in the art. It can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate 100 can be, for example, a silicon-on-insulator (SOI) substrate 100, a bulk silicon substrate 100, a germanium substrate 100, a germanium silicon substrate 100, an indium phosphide (InP) substrate 100, a gallium arsenide (GaAs) substrate 100, or a germanium-on-insulator substrate 100, etc.
[0070] The material of the first hard mask layer 220 includes but is not limited to silicon nitride, and the material of the second hard mask layer 230 includes but is not limited to a silicon oxide layer.
[0071] like Figure 5 As shown, a dummy gate structure is formed by photolithography and etching processes. Specifically, a patterned first photoresist layer is formed on the second hard mask layer 230 by photolithography, and the second hard mask layer 230, the first hard mask layer 220, and the polysilicon layer 210 are sequentially etched using the patterned first photoresist layer as a mask to form the dummy gate structure and the grooves 201 and 202.
[0072] The dummy gate structure of the peripheral region I includes a dummy dummy gate structure 203 and a test dummy gate structure 204, and the line width of the dummy dummy gate structure 203 (ie Figure 5 The length of each virtual dummy gate structure 203 from left to right is greater than the line width of the test dummy gate structure 204 ; the line width of the dummy gate structure of the storage area II is equal to the line width of the test dummy gate structure 204 .
[0073] In this step, due to the line width difference of the dummy gate structure, that is, the line width difference between the virtual dummy gate structure 203 and the test dummy gate structure 204 and the dummy gate structure of the storage area II, after the etching process, in this step, due to the size of the dummy gate structure (for example Figure 5 Due to the length (from left to right) of the second hard mask layer 230 in the peripheral area I, the thickness of the second hard mask layer 230 is greater than the thickness of the second hard mask layer 230 in the storage area II. At this time, the thickness difference between the second hard mask layer 230 in the peripheral area I and the second hard mask layer 230 in the storage area II is Δh0, which is also the height difference between the dummy gate structure in the peripheral area I and the dummy gate structure in the storage area II in this step.
[0074] like Figure 6 As shown, next, a first spacer 241 film layer is deposited on the outer surface (ie, the upper surface and the sidewall) of the dummy gate structure. The first spacer 241 film layer also covers the surface of the substrate 100 at the bottom of the grooves 201 and 202 .
[0075] Next, please continue to read Figure 6 The first spacer 241 film layer on the upper surface of the dummy gate structure and the first spacer 241 film layer on the surface of the substrate 100 at the bottom of the grooves 201 and 202 are dry-etched by a maskless etching process to obtain the first spacer 241. The first spacer 241 only covers the sidewall of the dummy gate structure and exposes a portion of the sidewall of the second hard mask layer 230. The material of the first spacer 241 includes, but is not limited to, silicon nitride.
[0076] In this step, the thickness of the second hard mask layer 230 located in the peripheral area I is reduced, and the thickness of the second hard mask layer 230 located in the storage area II is also reduced. However, due to the line width difference between the virtual pseudo gate structure 203 and the test pseudo gate structure 204 and the pseudo gate structure 205 of the storage area II, the etching process further aggravates the thickness difference between the second hard mask layer 230 located in the peripheral area I and the second hard mask layer 230 located in the storage area II. At this time, the thickness difference is △h1.
[0077] like Figure 7-Figure 9 As shown, step S20 is then performed to remove the second hard mask layer 230 and convert a portion of the first hard mask layer 220 into a silicon oxynitride hard mask layer 250 , which serves as a stop layer in the subsequent CMP process.
[0078] This step specifically includes:
[0079] like Figure 7As shown, first, the second hard mask layer 230 in the dummy gate structure is removed by a wet etching process to expose the first hard mask layer 220. This step ensures that the height of the dummy gate structure 205 in the storage area II is the same as that of the dummy gate in the peripheral area I.
[0080] like Figure 8 As shown, an organic material layer 300 is filled in the grooves 201 and 202. The organic material layer 300 fills a portion of the depth of the grooves 201 and 202, and the upper surface of the organic material layer 300 is located between the upper surface of the polysilicon gate and the upper surface of the first hard mask layer 220. Specifically, the organic material layer 300 (e.g., a photoresist layer) is filled in the grooves 201 and 202 so that the organic material layer 300 covers the surface of the first hard mask layer 220. The organic material layer 300 on the surface of the first hard mask layer 220 and the portion of the organic material layer 300 in the grooves 201 and 202 are then removed. Taking the organic material layer 300 as a photoresist layer as an example, the photoresist layer is filled in the grooves 201 and 202, and the photoresist layer covers the surface of the first hard mask layer 220; the photoresist layer is etched back to expose the surface of the first hard mask layer 220 and expose the grooves 201 and 202 of a partial depth.
[0081] like Figure 9 As shown, oxygen plasma is injected into the surface of the first hard mask layer 220 to convert a portion of the first hard mask layer 220 into an oxygen-rich silicon oxynitride hard mask layer 250. This step ensures that the upper surface of the silicon oxynitride hard mask layer 250 in the storage area II is on the same level as the upper surface of the silicon oxynitride hard mask layer 250 in the peripheral area I.
[0082] In this step, the thickness of the unconverted first hard mask layer 220 is greater than h, and the value of h is 190 Å to 210 Å.
[0083] like Figure 10 As shown, step S30 is then performed to fill the grooves 201 and 202 with a dielectric layer 260 , wherein the upper surface of the dielectric layer 260 is higher than the upper surface of the dummy gate structure.
[0084] This step specifically includes:
[0085] First, a contact etch stop layer 242 (CESL) is formed outside the first spacer 241 . The CESL 242 covers the surface of the substrate 100 at the grooves 201 and 202 and also covers the upper surface of the silicon oxynitride hard mask layer 250 .
[0086] Next, a dielectric layer 260 is filled in the grooves 201 and 202 . The dielectric layer 260 also covers the contact etch stop layer 242 on the dummy gate structure, so that the upper surface of the dielectric layer 260 is higher than the upper surface of the contact etch stop layer 242 on the dummy gate structure.
[0087] like Figure 11 As shown, step S40 is then performed to planarize the dielectric layer 260 and retain a portion of the thickness of the first hard mask layer 220 in the dummy gate structure. Specifically, the dielectric layer 260 is planarized by at least one CMP (chemical mechanical polishing) process to remove the dielectric layer 260 above the dummy gate structure, the contact etch stop layer 242, the silicon oxynitride hard mask layer 250, and at least a portion of the thickness of the first hard mask layer 220.
[0088] In this step, since there is no height difference (ie, no step) between the peripheral region I and the storage region II, it is beneficial to improve the thickness uniformity of the semiconductor device.
[0089] Please continue reading Figure 11 This embodiment further provides a semiconductor device, including a substrate 100, wherein the substrate 100 includes a storage region II and a peripheral region I, and dummy gate structures are formed on the substrate 100, with grooves 201 and 202 provided between adjacent dummy gate structures. The dummy gate structure includes, from bottom to top, a polysilicon layer 210 and a first hard mask layer 220; the grooves 201 and 202 are filled with a dielectric layer 260.
[0090] In summary, the present invention provides a semiconductor device and a method for preparing the same. The method for preparing the semiconductor device includes the following steps: providing a substrate, the substrate including a storage area and a peripheral area, dummy gate structures arranged at intervals are formed on the substrate in the storage area and the peripheral area, grooves are provided between adjacent dummy gate structures in the storage area and the peripheral area, respectively, the dummy gate structure includes, from bottom to top, a polysilicon layer, a first hard mask layer, and a second hard mask layer, wherein the thickness of the second hard mask layer located in the peripheral area is greater than the thickness of the second hard mask layer located in the storage area; removing the second hard mask layer, and converting a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer; filling the groove with a dielectric layer, the upper surface of the dielectric layer being higher than the upper surface of the dummy gate structure; planarizing the dielectric layer, and retaining a portion of the thickness of the first hard mask layer in the dummy gate structure. The present invention removes the second hard mask layer and converts a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer, so that the upper surface of the silicon oxynitride hard mask layer in the storage area and the upper surface of the silicon oxynitride hard mask layer in the peripheral area are on the same horizontal plane. In this way, there is no step between the storage area and the peripheral area when the dielectric layer is planarized, which is beneficial to improving the thickness uniformity of the semiconductor device, thereby improving the uniformity of the WAT test and the device yield.
[0091] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0092] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.
Claims
1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a storage region and a peripheral region, dummy gate structures spaced apart are formed on the substrate in both the storage region and the peripheral region, grooves are provided between adjacent dummy gate structures in each of the storage region and the peripheral region, the dummy gate structure comprising, from bottom to top, a polysilicon layer, a first hard mask layer, and a second hard mask layer, wherein the thickness of the second hard mask layer in the peripheral region is greater than the thickness of the second hard mask layer in the storage region; removing the second hard mask layer and converting a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer; Filling the groove with a dielectric layer, wherein the upper surface of the dielectric layer is higher than the upper surface of the dummy gate structure; The dielectric layer is planarized, and a first hard mask layer having a partial thickness in the dummy gate structure is retained.
2. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the first hard mask layer satisfies the formula: H=a*h; Among them, the value of a is 3~6; the value of h is 190 Å ~210Å.
3. The method for preparing a semiconductor device according to claim 2, wherein: The material of the first hard mask layer includes silicon nitride, and the material of the second hard mask layer includes silicon oxide.
4. The method for preparing a semiconductor device according to claim 3, wherein: The specific method of converting a portion of the thickness of the first hard mask layer into a silicon oxynitride hard mask layer is: filling the groove with an organic material layer, wherein the organic material layer fills a portion of the depth of the groove; A partial thickness of the first hard mask layer is converted into a silicon oxynitride hard mask layer.
5. The method for preparing a semiconductor device according to claim 3, wherein: The specific method of forming the silicon oxynitride hard mask layer is as follows: Oxygen plasma is injected into the surface of the first hard mask layer to convert a portion of the first hard mask layer into an oxygen-rich silicon oxynitride hard mask layer.
6. The method for preparing a semiconductor device according to claim 4, wherein: An upper surface of the silicon oxynitride hard mask layer in the storage region and an upper surface of the silicon oxynitride hard mask layer in the peripheral region are on the same level.
7. The method for preparing a semiconductor device according to claim 4, wherein: The thickness of the unconverted first hard mask layer is greater than h, and the value of h is 190 Å ~ 210 Å.
8. The method for preparing a semiconductor device according to claim 1, wherein: The specific method for removing the second hard mask layer is: The second hard mask layer is removed by a wet etching process.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: The specific method of filling the dielectric layer is: forming a contact etch stop layer, wherein the contact etch stop layer covers the substrate surface at the groove, the sidewall of the dummy gate structure, and the upper surface of the silicon oxynitride hard mask layer; A dielectric layer is filled in the groove, and the dielectric layer also covers the contact etching stop layer on the dummy gate structure.
10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.
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