Field effect transistor

Abstract

A field effect transistor includes: an n-type semiconductor layer having a first main surface and a second main surface facing the first main surface; a drain electrode forming Schottky contact with the second main surface of the n-type semiconductor layer; a trench gate structure including a gate trench extending inward from the first main surface of the n-type semiconductor layer, and a gate electrode embedded in the gate trench after being wrapped with a gate insulating film; the source electrode contact grooves extend downwards from the first main surface of the n-type semiconductor layer, and the source electrode contact grooves are located on the two sides of the grid electrode groove; the source electrode comprises a first part and a second part of the source electrode, the first part is in contact with the n-type semiconductor layer along the side wall and the bottom of the source electrode contact groove and forms Schottky contact with the n-type semiconductor layer, and the second part is located on the first part of the source electrode and is in contact with the n-type semiconductor layer along the side wall of the source electrode contact groove to form ohmic contact. According to the invention, the normally-closed field effect transistor with high frequency, low conduction loss and bidirectional blocking capability can be formed.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor devices, and in particular relates to a field effect transistor. Background Art

[0002] For some power electronics applications, such as matrix converters, power semiconductor devices with bidirectional blocking characteristics must be used, such as IGBT devices with bidirectional blocking capabilities. Figure 3 As shown, Figure 3 The IGBT is a traditional IGBT device, which has: a collector 11, a p+ collector region 211, an n-type field stop layer 212, an n-type drift region 31a, a p-type body region 214, an n+ type source region 213, a gate trench (including a gate electrode 61 and a gate insulating film 41a), an emitter 51c, and an insulating dielectric layer 41b.

[0003] Figure 3 The working principle of IGBT is as follows: the IGBT has a pn junction J1 located on the collector C side of the device bottom and a pn junction J2 located on the emitter E side of the device top. When the voltage V between the collector and emitter is CE >0, the pn junction J2 located on the emitter E side of the device is reverse biased and subjected to the electric field. When the voltage V between the collector and the emitter CE When <0, the pn junction J1 at the bottom of the device is reverse biased and subjected to the electric field. The two pn junction structures are inversely proportional to each other, making the attached Figure 3 The IGBT shown has bidirectional blocking capability. However, since the IGBT is a bipolar device, the presence of a pn junction in its structure also leads to some electrical performance deficiencies.

[0004] First, IGBT devices all have a serious tailing effect, such as Figure 3 As shown in the figure, when the IGBT is on, electrons flow from the n-type drift region 31a to the backside p+ collector region 211. The p+ collector region 211 emits holes upward, and the electrons and holes together constitute the IGBT current. When the IGBT is off, the electrons are quickly extracted, while the excess holes can only disappear through slow recombination, thus forming a tail current. During the tail current period, the voltage is usually very high, resulting in a significant increase in losses during this period.

[0005] Secondly, IGBT devices have a latch-up effect caused by parasitic thyristors, such as the following Figure 3As shown, the pnp transistor and npn transistor in the IGBT structure form a thyristor. Under high current conditions, the npn sub-transistor located on the emitter 51c side may be activated and turned on, thereby turning on the parasitic thyristor. At this time, the gate will lose its switch control function, forming a self-locking conduction. This situation is a static latch-up effect. In addition, the attached Figure 3 When the IGBT shown in the figure switches at high speed, if the current drops too quickly (i.e., the di / dt is large), the voltage change dv / dt will also be large, causing a large displacement current. This may also activate the npn sub-transistor on the emitter side 51c, causing the thyristor to self-lock into conduction. This situation is called dynamic latch-up. Latch-up causes the collector current to increase, exceeding the safe operating area of the IGBT device, resulting in excessive power consumption and ultimately failure of the IGBT device. Summary of the Invention

[0006] In view of this, the technical problem to be solved by the present invention is to provide a field effect transistor with bidirectional blocking capability, which at least solves one of the technical problems existing in the prior art to a certain extent.

[0007] To solve the above problems, the present invention provides a field effect transistor embodiment and technical solution as follows:

[0008] A field effect transistor, comprising:

[0009] An n-type semiconductor layer having a first main surface on one side and a second main surface on the other side opposite thereto;

[0010] a drain electrode, the drain electrode being in contact with the second main surface of the n-type semiconductor layer to form a Schottky contact;

[0011] a trench gate structure comprising a gate trench extending inwardly from the first main surface of the n-type semiconductor layer, and a gate electrode embedded in the gate trench after being wrapped by a gate insulating film;

[0012] a source contact groove, wherein the source contact groove extends downward from the first main surface of the n-type semiconductor layer into the n-type semiconductor layer, and the source contact groove is located on both sides of the gate trench;

[0013] a source electrode, the source electrode comprising a first portion of the source electrode and a second portion of the source electrode, the first portion of the source electrode contacting the n-type semiconductor layer along the sidewalls and bottom of the source contact groove and forming a Schottky contact therewith, the second portion of the source electrode being located above the first portion of the source electrode and contacting the n-type semiconductor layer along the sidewalls of the source contact groove and forming an ohmic contact therewith;

[0014] The width of the n-type semiconductor layer between the gate trench and the source contact trench is in the range of 20 nm to 200 nm.

[0015] Preferably, the width of the n-type semiconductor layer between the gate trench and the source contact trench is in the range of 20 nm to 150 nm.

[0016] Preferably, the material of the n-type semiconductor layer is one of silicon, silicon carbide, gallium nitride, gallium oxide, and tin oxide.

[0017] Preferably, the first portion of the source electrode and the second portion of the source electrode correspond to different metals or alloys respectively.

[0018] Preferably, in order to reduce off-state leakage, the gate electrode is made of a conductive material having a work function higher than that of the n-type semiconductor layer.

[0019] Preferably, each trench gate structure further comprises: a shielding electrode, and an insulating dielectric layer is provided at the bottom of the trench gate structure, between the shielding electrode and the n-type semiconductor layer, and between the gate electrodes.

[0020] Preferably, a p-type semiconductor region exists on the second main surface of the n-type semiconductor layer, and the n-type semiconductor region and the p-type semiconductor region are alternately arranged and distributed, the drain electrode forms a Schottky contact with the n-type semiconductor region, and the drain electrode forms an ohmic contact with the p-type semiconductor region.

[0021] Preferably, a p-type semiconductor region further exists on the second main surface of the n-type semiconductor layer, and the drain electrode and the p-type semiconductor region are alternately arranged and distributed, and the p-type semiconductor region forms an ohmic contact with the drain electrode.

[0022] In view of the above invention contents, the present invention has the following beneficial effects:

[0023] (1) The field effect transistor of the embodiment of the present invention adjusts the pure Schottky source to a combination of an ohmic source and a Schottky source. While maintaining the normally-off design of the device, the problem of low on-state current of the Schottky source-drain field effect transistor can be solved, the current carrying capacity of the Schottky source-drain field effect transistor can be improved, and the on-resistance of the channel region can be reduced, thereby reducing the conduction loss of the device.

[0024] (2) The field effect transistor of the embodiment of the present invention divides the source electrode into two parts, the first part forms a Schottky contact with the semiconductor layer, and the second part forms an ohmic contact with the semiconductor layer, and an n-type semiconductor layer is inserted between the drain electrode and the n+ type semiconductor layer, which also forms a Schottky contact with one side of the drain electrode. The Schottky barriers on both sides of the source and drain are used to achieve a bidirectional shutoff effect. Due to the bidirectional blocking capability, compared with the IGBT device with the same bidirectional blocking capability, the device does not have the tailing effect and latch-up effect, so that the device has the advantages of high frequency and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a vertical cross-sectional view of an embodiment of a conventional Schottky source-drain MOSFET;

[0026] Figure 2 is a vertical cross-sectional view of an embodiment of a trench gate MOSFET proposed in patent application number 202310325051.0;

[0027] Figure 3 is a vertical cross-sectional view of a specific embodiment of a conventional IGBT;

[0028] Figure 4 is a vertical cross-sectional view of a first specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention;

[0029] Figure 5 is a vertical cross-sectional view of a second specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention;

[0030] Figure 6 is a vertical cross-sectional view of a third specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention;

[0031] Figure 7 is a vertical cross-sectional view of a fourth specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention;

[0032] Figure 8 It is a vertical cross-sectional view of a fifth specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention.

[0033] The technical features corresponding to the marks in the figure are:

[0034] 11 drain electrode;

[0035] 21n+ type semiconductor layer;

[0036] 31a n-type drift region;

[0037] 31b n-type semiconductor layer

[0038] 41a gate insulating film;

[0039] 41b insulating dielectric layer;

[0040] 51a first part source electrode;

[0041] 51b surface source electrode;

[0042] 51c Part II source electrode;

[0043] 61 gate electrode;

[0044] 62 shielding gate electrode;

[0045] 71 source region;

[0046] 211p+ collector region

[0047] 212n type field stop layer

[0048] 213n+ source region

[0049] 214p-type body region

[0050] 215p+ semiconductor layer DETAILED DESCRIPTION

[0051] To more clearly illustrate the technical solution of the present invention, the following will be briefly introduced through embodiments or descriptions of the prior art. Obviously, the following drawings are only illustrative of some embodiments of the present invention, and the scope of protection claimed by the present invention is not limited to the embodiments. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0052] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0053] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0055] In the present invention, unless otherwise specified, directional words such as "up, down, left, right" etc. are usually used with reference to the directions shown in the drawings, or with reference to the vertical, perpendicular or gravity directions of the components themselves; similarly, for ease of understanding and description, "inside and outside" refer to the inside and outside relative to the outline of each component itself, but the above directional words are not used to limit the present invention.

[0056] Figure 1 This is a vertical cross-sectional view of an embodiment of a conventional Schottky source-drain MOSFET. This MOSFET comprises: a drain electrode 11; an n+-type semiconductor layer 21; an n-type drift region 31a; a gate trench extending into the n-type drift region 31a; a gate electrode 61 located in the gate trench and surrounded by a gate insulating film 41a; a first portion of a source electrode 51a forming a Schottky contact with the n-type drift region 31a; and a surface source electrode 51b.

[0057] Figure 1 In the conventional Schottky source-drain MOSFET shown, due to the presence of the Schottky junction formed between the first source electrode 51a and the n-type drift region 31a, when only a forward voltage is applied between the drain electrode 11 and the surface source electrode 51b, the Schottky junction is reverse biased, causing the depletion region to widen. This prevents a complete electron conduction channel from forming between the drain electrode 11 and the surface source electrode 51b, and no current flows between the drain and source. Based on this principle, Figure 1 The Schottky junction MOSFET shown is a normally-off device; when a positive voltage is applied between the gate electrode 61 and the surface source electrode 51b, due to the presence of the Schottky barrier between the first part source electrode 51a and the n-type drift region 31a, a complete and high-concentration electron conduction channel cannot be formed between the drain electrode 11 and the surface source electrode 51b. At this time, even when a positive voltage is applied between the drain electrode 11 and the surface source electrode 51b, the reverse-biased depletion layer of the Schottky barrier formed between the first part source electrode 51a and the n-type drift region 31a is widened, which inhibits the transport of electron carriers, so that only a small number of electron carriers form current through the tunneling effect between the drain electrode 11 and the first part source electrode 51a. This results in the traditional Schottky junction MOSFET having a very poor on-state current conduction capability and cannot meet the application requirements of currents above the ampere level.

[0058] Based on the above-mentioned defects of the traditional Schottky junction MOSFET, the applicant and / or affiliated enterprises of the present invention have conducted research and filed Chinese invention patent application 202310325051.0.

[0059] The patent application document with application number 202310325051.0 proposes a new Schottky junction MOSFET structure. This MOSFET structure is a trench gate MOSFET with large on-state current capability. Compared with the traditional pn junction MOSFET, this Schottky MOSFET has four advantages: First, the metal Schottky contact has the characteristics of an ultra-shallow junction, which can effectively solve the short channel effect and source-drain punchthrough problems of MOSFET caused by a significant reduction in device size, providing the possibility for further size reduction of MOSFET; second, the high conductivity of the metal-semiconductor contact can further reduce the drain-source resistance; third, there is no p-region in the Schottky source-drain MOSFET, which has a faster response speed and can be used at a higher frequency; fourth, ion implantation is not required to form n+ or p+ source-drain regions, so high-temperature annealing is eliminated, the process is simple, and the lattice damage problem caused by ion implantation and annealing is avoided, which helps to obtain high interface quality, thereby obtaining a high-quality dielectric layer with better voltage resistance and reliability.

[0060] Figure 2 202310325051.0 is a vertical cross-sectional view of an embodiment of a trench gate MOSFET proposed in the patent application with application number 202310325051.0. Figure 2 This MOSFET has: a drain electrode 11, located at the bottom layer of the field effect transistor; an n+ type semiconductor layer 21, located above the drain electrode 11; an n-type drift region 31a, located above the n+ type semiconductor layer 21; a gate trench, extending downward from the upper surface of the n-type drift region 31a, further, the gate trench includes a gate electrode 61 and a gate insulating film 41a, and the gate insulating film 41a wraps the gate electrode 61; a first portion of the source electrode 51a, recessed in the n-type drift region 31a, and forming a Schottky contact with the n-type drift region 31a; a second portion of the source electrode 51c, located above the first portion of the source electrode 51a, adjacent to the source region 71, and forming an ohmic contact with the source region 71, and also located above the insulating dielectric layer 41b, and separated from the gate electrode by the insulating dielectric layer 41b.

[0061] Figure 2 The MOSFET shown in the figure has optimized the design of the source electrode, and the pure first part source electrode 51a in the traditional Schottky source-drain MOSFET is adjusted to a combination design of the second part source electrode 51c and the first part source electrode 51a. When the voltage V GS Greater than the threshold voltage V GS(th)When the gate insulating dielectric layer 41a of the n-type drift region 31a is adjacent to the gate drift region 31a, electron carriers gather to form a high-concentration electron channel. Since there is no potential barrier between the second partial source electrode 51c and the source region 71, when a positive voltage is applied between the drain electrode 11 and the second partial source electrode 51c, a complete and high-concentration electron channel is formed between the drain electrode 11 and the second partial source electrode 51c, and current flows between the drain electrode 11 and the second partial source electrode 51c. When the voltage V GS =0, the Schottky barrier formed by the first partial source electrode 51a and the n-type drift region 31a will produce a longitudinal and lateral depletion effect on the electron carriers. In addition, when there is a work function difference between the material of the gate electrode 61 and the material of the n-type drift region 31a (that is, the work function of the material of the gate electrode 61 is greater than the work function of the material of the n-type drift region 31a), the gate electrode 61 will also produce a lateral depletion effect on the electron carriers in the n-type drift region 31a. In this way, under the joint action of the first partial source electrode 51a and the gate electrode 61, the electron carriers in the n-type drift region 31a located between the first partial source electrode 51a and the gate electrode 61 can be completely depleted, thereby blocking the electron conduction channel between the drain electrode 11 and the second partial source electrode 51c. Figure 2 The MOSFET shown can be a normally-off device, and can be a normally-off device with a large on-state current capability.

[0062] In summary, the patent application with application number 202310325051.0 solves the problem of low on-state current of Schottky source-drain MOSFET by adjusting the pure Schottky source in the Schottky source-drain MOSFET to a combination design of ohmic source and Schottky source while maintaining the normally-off design of the device, thereby improving the current-carrying capacity of the Schottky source-drain MOSFET, reducing the on-resistance, and thus reducing the conduction loss of the device.

[0063] However, for some power electronics applications, such as applications in matrix converters, power semiconductor devices with bidirectional blocking characteristics must be used. However, the MOSFET proposed in the patent application document with application number 202310325051.0 only has unidirectional blocking characteristics and cannot meet the requirements of device applications.

[0064] IGBT in power devices has bidirectional blocking capability, which can meet some applications in power electronics. Figure 3The conventional IGBT device shown above has a reverse-biased pn junction in both the forward and reverse directions, providing bidirectional blocking capability. However, because the IGBT is a bipolar device, the presence of the pn junction in its structure also leads to some electrical performance deficiencies. IGBT devices have two drawbacks: the first is a severe tailing effect; the second is a latch-up effect caused by parasitic thyristors.

[0065] In order to solve the above problems, the inventors of this application conducted in-depth research and Figure 2 The device is improved and the present application is proposed, so that it has bidirectional blocking characteristics, and has the advantages of high frequency and high reliability.

[0066] Figure 4 1 is a vertical cross-sectional view of a first specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention. The field effect transistor comprises: a drain electrode 11 located at the bottom of the field effect transistor; an n-type semiconductor layer 31b located above the drain electrode 11 and forming a Schottky contact with the drain electrode 11; an n+ type semiconductor layer 21 located above the n-type semiconductor layer 31b; an n-type drift region 31a located above the n+ type semiconductor layer 21; a gate trench extending downward from the upper surface of the n-type drift region 31a; and further, the gate trench includes a gate electrode 61 and a gate insulator. The gate insulating film 41a and the gate insulating film 41a are wrapped around the outer surfaces of the gate electrode 61 and the shielding gate electrode 62; the first part of the source electrode 51a is recessed in the n-type drift region 31a and forms a Schottky contact with the n-type drift region 31a; the second part of the source electrode 51c is located above the first part of the source electrode 51a, adjacent to the source region 71, and forms an ohmic contact with the source region 71, and is also located above the insulating dielectric layer 41b, and is separated from the gate electrode 61 by the insulating dielectric layer 41b, and the first part of the source electrode 51a and the second part of the source electrode 51c correspond to different metals or alloys respectively.

[0067] Figure 4 The bidirectional blocking capability of the field effect transistor shown is in the attached Figure 2 On the basis of the MOSFET shown in FIG, an n-type semiconductor layer 31b is inserted between the drain electrode 11 and the n+ type semiconductor layer 21 to form a Schottky contact with the drain electrode 11. Figure 2 While having the advantages of the MOSFET shown, it also has bidirectional blocking capability.

[0068] Figure 4 When a voltage V is applied between the gate electrode 61 and the second portion source electrode 51c of the MOSFET shown in FIG. GS Greater than the threshold voltage V GS(th)When the gate insulating dielectric layer 41a is adjacent to the drain electrode 11, electron carriers gather in the n-type drift region 31a to form a high-concentration electron channel. Since there is no potential barrier between the second partial source electrode 51c and the source region 71, when a positive voltage is applied between the drain electrode 11 and the second partial source electrode 51c, a complete and high-concentration electron channel will be formed between the drain electrode 11 and the second partial source electrode 51c, and current will flow between the drain electrode 11 and the second partial source electrode 51c.

[0069] When the voltage V is applied between the gate electrode 61 and the second partial source electrode 51c GS =0, when a forward voltage is applied between the drain electrode 11 and the second part source electrode 51c, the Schottky barrier formed by the first part source electrode 51a and the n-type drift region 31a will produce a longitudinal and lateral depletion effect on the electron carriers. In addition, when there is a work function difference between the material of the gate electrode 61 and the material of the n-type drift region 31a (that is, the work function of the material of the gate electrode 61 is greater than the work function of the material of the n-type drift region 31a), the gate electrode 61 will also produce a lateral depletion effect on the electron carriers in the n-type drift region 31a. The width t of the n-type drift region 31a between the gate trench and the first partial source electrode 51a is in the range of 20nm to 200nm; more preferably, the width t of the n-type drift region 31a between the gate trench and the first partial source electrode 51a is in the range of 20nm to 150nm. In this way, under the joint action of the first partial source electrode 51a and the gate electrode 61, the electron carriers in the n-type drift region 31a between the first partial source electrode 51a and the gate electrode 61 can be completely depleted, thereby blocking the electron conduction channel between the drain electrode 11 and the second partial source electrode 51c. Figure 4 The MOSFET shown can be a normally-off device, and can be a normally-off device with a large on-state current capability.

[0070] Figure 4 As shown, when the voltage V is applied between the gate electrode 61 and the second partial source electrode 51c GS = 0, when a reverse voltage is applied between the drain electrode 11 and the second partial source electrode 51c, a Schottky contact is formed between the n-type semiconductor layer 31b and the drain electrode 11. At this time, the Schottky junction is reverse biased to form a depletion layer, and no current flows between the drain electrode 11 and the second partial source electrode 51c. Figure 4 The MOSFET shown is a normally-off field-effect transistor with bidirectional blocking capability.

[0071] Figure 4 The device shown is compared to the attached Figure 2 The MOSFET shown has bidirectional blocking capability. Figure 3The IGBT shown here has no current tailing effect and no latch-up effect caused by parasitic thyristors. This field-effect transistor is a high-frequency, highly reliable, and bidirectional blocking-capable conventional field-effect transistor.

[0072] Figure 5 is a vertical cross-sectional view of a second specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention, Figure 4 The difference is that the gate trench includes a shielding gate electrode 62 at the bottom, a gate electrode 61 at the top, and a gate insulating film 41 a , and the gate insulating film 41 a wraps around the outer surfaces of the gate electrode 61 and the shielding gate electrode 62 .

[0073] Figure 4 It is a trench-type field-effect transistor with bidirectional blocking capability. Figure 5 It is a shielded gate field effect transistor with bidirectional blocking capability. Figure 4 , under the same n-type drift region concentration, Figure 5 The withstand voltage is higher. Since the shield grid participates in the lateral depletion effect when withstanding the voltage, the electric field is closer to the rectangular distribution, thereby improving the withstand voltage of the device. Figure 4 same, Figure 5 It has bidirectional blocking capability, no tailing effect, and no latch-up effect caused by parasitic thyristors.

[0074] Figure 6 is a vertical cross-sectional view of a third specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention, Figure 5 The difference is that the shielding gate electrode 62 is located in the middle of the gate trench, the gate electrode 61 is formed around both sides of the upper portion of the shielding gate electrode 62 , and the insulating dielectric layer 41 b is located above the gate trench and the source region 71 .

[0075] Figure 6 The gate electrode 61 and the shield gate electrode 62 are located at the same position as Figure 5 The embodiments are different, but the other structures of the devices are the same. Figure 5 The embodiment has the same advantages as the field effect transistor with high frequency, high reliability and bidirectional blocking capability.

[0076] Figure 7 is a vertical cross-sectional view of a fourth specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention, Figure 4 The difference is that a p+ type semiconductor layer 215 is inserted into the n- type semiconductor layer 31b, and the p+ type semiconductor layer 215 forms an ohmic contact with the drain electrode 11. Figure 4While showing the advantages of MOSFET, it has the ability to conduct large current during forward conduction. During reverse cutoff, due to the participation of the pn junction in depletion, the reverse cutoff capability is stronger and the leakage current is smaller.

[0077] Figure 8 is a vertical cross-sectional view of a fifth specific embodiment of a field effect transistor with bidirectional blocking capability according to the present invention, Figure 4 The difference is that the n-type semiconductor layer 31b is in contact with the p+ type semiconductor layer 215 and the drain electrode 11, and the p+ type semiconductor layer 215 forms an ohmic contact with the drain electrode 11, and the n-type semiconductor layer 31b forms a Schottky contact with the drain electrode 11. Figure 4 While having the advantages of MOSFET shown in the figure, it also has the ability to conduct large currents.

[0078] The MOSFETs shown in the various embodiments of the present invention are based on the structural innovation of the Schottky junction MOSFET, forming a turn-off field-effect transistor with bidirectional blocking capability. Without the use of p-type diffusion or injection, the MOSFETs are not only applicable to silicon (Si)-based semiconductor materials, but are particularly suitable for use with other types of semiconductor materials, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and tin oxide (SnO2). In these materials, the diffusion, injection, and activation processes are difficult to complete and control. In addition, for example, in traditional pn-junction SiC-based normally-off MOSFETs, the inversion channel contributes particularly significantly to the on-resistance due to the low channel carrier mobility. However, when the solution of the present invention is adopted, the inversion channel is converted into an accumulation channel, which can significantly increase the channel carrier mobility, thereby reducing the on-resistance.

[0079] It should be understood that the above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above-described embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A field effect transistor, characterized in that: include: An n-type semiconductor layer having a first main surface on one side and a second main surface on the other side opposite thereto; a drain electrode, the drain electrode being in contact with the second main surface of the n-type semiconductor layer to form a Schottky contact; a trench gate structure comprising a gate trench extending inwardly from the first main surface of the n-type semiconductor layer, and a gate electrode embedded in the gate trench after being wrapped by a gate insulating film; a source contact groove, wherein the source contact groove extends downward from the first main surface of the n-type semiconductor layer into the n-type semiconductor layer, and the source contact groove is located on both sides of the gate trench; a source electrode, the source electrode comprising a first portion of the source electrode and a second portion of the source electrode, the first portion of the source electrode contacting the n-type semiconductor layer along the sidewalls and bottom of the source contact groove and forming a Schottky contact therewith, the second portion of the source electrode being located above the first portion of the source electrode and contacting the n-type semiconductor layer along the sidewalls of the source contact groove and forming an ohmic contact therewith; The width of the n-type semiconductor layer between the gate trench and the source contact trench is in the range of 20 nm to 200 nm.

2. The field effect transistor according to claim 1, characterized in that The width of the n-type semiconductor layer between the gate trench and the source contact trench is in the range of 20 nm to 150 nm.

3. The field effect transistor according to claim 1, wherein: The material of the n-type semiconductor layer is one of silicon, silicon carbide, gallium nitride, gallium oxide, and tin oxide.

4. The field effect transistor according to claim 1, wherein: The first portion of the source electrode and the second portion of the source electrode correspond to different metals or alloys respectively.

5. The field effect transistor according to claim 1, wherein: In order to reduce off-state leakage, the gate electrode is made of a conductive material having a work function higher than that of the n-type semiconductor layer.

6. The field effect transistor according to claim 1, wherein: Each trench gate structure further includes a shielding electrode. At the bottom of the trench gate structure, an insulating dielectric layer is provided between the shielding electrode and the n-type semiconductor layer and between the gate electrodes.

7. The field effect transistor according to claim 1, wherein: A p-type semiconductor region exists on the second main surface of the n-type semiconductor layer, and the n-type semiconductor region and the p-type semiconductor region are alternately arranged and distributed. The drain electrode forms a Schottky contact with the n-type semiconductor region, and the drain electrode forms an ohmic contact with the p-type semiconductor region.

8. The field effect transistor according to claim 1, wherein: A p-type semiconductor region further exists on the second main surface of the n-type semiconductor layer, and the drain electrode and the p-type semiconductor region are alternately arranged and distributed, and the p-type semiconductor region forms an ohmic contact with the drain electrode.

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