Solar cell and preparation method thereof, laminated cell and photovoltaic module

Abstract

The invention relates to a solar cell and a preparation method thereof, a laminated cell and a photovoltaic module. The preparation method of the solar cell comprises the following steps: providing a substrate; the substrate is provided with a first surface and a second surface, and the first surface is provided with a first area and a second area; forming a tunneling layer and a doped conductive layer on a first region of the first surface of the substrate; the doped conductive layer is located on the surface of one side, deviating from the substrate, of the tunneling layer; an accommodating groove is formed in the surface of one side, deviating from the tunneling layer, of the doped conductive layer; forming an electrode in ohmic contact with the doped conductive layer on the surface of one side, deviating from the tunneling layer, of the doped conductive layer; the orthographic projection of the electrode on the first surface is at least partially overlapped with the orthographic projection of the accommodating groove on the first surface. According to the solar cell, the doped conductive layer can be thickened, so that the grooved doped conductive layer still has a certain thickness, and meanwhile, the accommodating groove can be filled with the metal slurry, so that better ohmic contact between the electrode and the doped conductive layer is realized.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, a stacked cell and a photovoltaic module. Background Art

[0002] The Topcon (Tunnel Oxide Passivated Contact) cell is a tunnel oxide passivated contact solar cell with a silicon substrate. Because it uses a tunnel oxide with excellent charge transfer properties as the charge transfer layer on the back of the cell, and then deposits a layer of doped polysilicon to form a back passivated contact structure, it can effectively reduce surface recombination and metal contact recombination, thereby improving the opening voltage and energy conversion efficiency.

[0003] However, in the current Topcon battery manufacturing process, due to technical defects, it is difficult to form good ohmic contact between the electrodes and the battery cells, which greatly limits the efficiency of the battery. Summary of the Invention

[0004] Based on this, it is necessary to provide a solar cell and a preparation method thereof, a laminated cell and a photovoltaic module to address the problem of poor contact performance of the electrodes.

[0005] A solar cell comprising:

[0006] A substrate having a first surface and a second surface disposed opposite to each other along a thickness direction of the substrate, wherein the first surface has a first area and a second area;

[0007] a tunneling layer, disposed in the first region of the first surface of the substrate;

[0008] a doped conductive layer, disposed on a side of the tunneling layer away from the substrate, wherein a surface of the doped conductive layer facing away from the tunneling layer is provided with a receiving groove; and

[0009] An electrode is provided on a surface of the doped conductive layer facing away from the tunneling layer, and an orthographic projection of the electrode on the first surface at least partially overlaps with an orthographic projection of the receiving groove on the first surface.

[0010] In one embodiment, the thickness of the doped conductive layer in the region where the receiving groove is not provided is 160 nm to 200 nm.

[0011] In one embodiment, the depth of the receiving groove in the thickness direction of the substrate is 10 nm to 50 nm.

[0012] In one embodiment, the width of the accommodating groove is 22um to 32um.

[0013] In one embodiment, a longitudinal section of the receiving groove parallel to the thickness direction of the substrate is rectangular.

[0014] In one embodiment, the phosphorus doping concentration of the doped conductive layer is 3.5×10 20 atom / cm 3 to 6×10 20 atom / cm 3 .

[0015] A method for preparing a solar cell, comprising:

[0016] Providing a substrate; the substrate having a first surface and a second surface disposed opposite to each other along a thickness direction of the substrate, the first surface having a first area and a second area;

[0017] forming a tunneling layer and a doped conductive layer on the first region of the first surface of the substrate; the doped conductive layer is located on a surface of the tunneling layer that is away from the substrate;

[0018] A receiving groove is formed on a surface of the doped conductive layer that is away from the tunneling layer;

[0019] An electrode in ohmic contact with the doped conductive layer is formed on a surface of the doped conductive layer facing away from the tunneling layer; the orthographic projection of the electrode on the first surface at least partially overlaps with the orthographic projection of the accommodating groove on the first surface.

[0020] In one embodiment, the receiving groove is formed on a surface of the doped conductive layer that is away from the tunneling layer by using a laser etching process.

[0021] In one embodiment, the step of forming a tunneling layer and a doped conductive layer on the first region of the first surface of the substrate specifically includes:

[0022] forming an initial tunneling layer and an initial doped conductive layer on the first surface of the substrate; the initial doped conductive layer is located on a side of the initial tunneling layer away from the substrate;

[0023] Portions of the initial tunneling layer and the initial doped conductive layer located in the second region are removed to form the tunneling layer and the doped conductive layer.

[0024] In one embodiment, a laser etching process is used to remove the portions of the initial tunneling layer and the initial doped conductive layer located in the second region.

[0025] In one embodiment, the scanning speed of the laser used in the laser etching process is 50,000 mm / s to 70,000 mm / s, the power of the laser is 60W to 70W, and the frequency of the laser is 850Khz to 900Khz.

[0026] In one embodiment, after the step of forming a receiving groove on a surface of the doped conductive layer facing away from the tunneling layer, the method further includes:

[0027] A passivation layer is formed in the second region of the first surface of the substrate and on a surface of the doped conductive layer facing away from the tunneling layer.

[0028] A stacked cell comprises the solar cell described above, or a solar cell prepared by the method for preparing the solar cell described above.

[0029] A photovoltaic module comprises the above-mentioned solar cell, or a solar cell prepared by the above-mentioned method for preparing a solar cell, or the above-mentioned laminated cell.

[0030] The solar cell can be designed to have a thicker doped conductive layer so that the doped conductive layer still has a certain thickness after the grooves are cut. At the same time, metal paste can be filled into the grooves to achieve better ohmic contact between the electrode and the doped conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a solar cell according to an embodiment of the present application.

[0034] Figure 2 FIG. 1 is a schematic diagram of step S110 according to an embodiment of the present application.

[0035] Figure 3 This is a schematic diagram of step S1211 according to an embodiment of the present application.

[0036] Figure 4 This is a schematic diagram of step S1212 according to an embodiment of the present application.

[0037] Figure 5 FIG. 1 is a schematic diagram of step S122 according to an embodiment of the present application.

[0038] Figure 6 This is a schematic diagram of step S140 according to an embodiment of the present application.

[0039] Figure 7 Schematic diagram of steps S150 and S160 according to an embodiment of the present application.

[0040] Figure 8 Schematic diagram of steps S170 and S180 according to an embodiment of the present application.

[0041] Description of reference numerals:

[0042] 100, solar cell; 110, substrate; 110a, first surface; 110b, second surface; 121, initial tunneling layer; 131, initial silicon layer; 132, initial doped conductive layer; 122, tunneling layer; 133, doped conductive layer; 133a, receiving groove; 140, first passivation layer; 150, second passivation layer; 160, first electrode; 170, second electrode. DETAILED DESCRIPTION

[0043] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0044] In the description of this application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0045] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0046] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connected," "fixed," etc., should be interpreted broadly. For example, these terms may refer to fixed connections, removable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; and internal communication between two components or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0047] In this application, unless otherwise expressly specified or limited, if a first feature is described as being "above" or "below" a second feature, or similar descriptions, this may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is described as being "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is described as being "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0048] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only embodiment.

[0049] See Figure 1 , the embodiment of the present application provides a method for preparing a solar cell, for a solar cell 100 (such as Figure 8The solar cell 100 is specifically a Topcon (Tunnel Oxide Passivated Contact) cell. It is understood that the solar cell manufacturing method can also be used to manufacture other types of solar cells and is not specifically limited here.

[0050] As described in the background, in the manufacturing process of Topcon cells, to control costs, the screen printing process will control the unit consumption of metal paste to be increasingly low. However, this method easily increases the contact resistance between the metal paste and the cell, making it difficult to form a good ohmic contact, seriously affecting the fill factor and greatly limiting the efficiency improvement of the cell. At the same time, in order to grow a tunneling oxide layer with excellent uniformity and a polysilicon layer with excellent deposition uniformity on the back of the cell, the back tower base formed by back etching becomes increasingly flat, which is not conducive to forming a good ohmic contact on the back of the cell.

[0051] Based on the above technical problems, the present application provides a method for preparing a solar cell, which specifically includes the following steps:

[0052] Step S110: providing a substrate; the substrate has a first surface and a second surface disposed opposite to each other along a thickness direction of the substrate, and the first surface has a first area and a second area.

[0053] The substrate can be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which can be at least one of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type doping element, which can be at least one of Group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0054] Please combine Figure 1 、 Figure 2 As shown, the substrate 110 is a rectangular flat plate structure having a first surface 110a and a second surface 110b that are opposite and horizontally arranged along the thickness direction of the substrate 110. The first surface 110a is the surface of the substrate 110 facing the backlight side of the solar cell 100, and the second surface 110b is the surface of the substrate 110 facing the light-receiving side of the solar cell 100.

[0055] Furthermore, the first surface 110a has a first region and a second region. The first region is the region where the electrodes are provided, and the second region is the region of the first surface 110a excluding the first region. The shapes and sizes of the first and second regions can be configured as needed. The second surface 110b has a third region and a fourth region. The third region is the region where the electrodes are provided, and the fourth region is the region of the second surface 110b excluding the third region. The shapes and sizes of the third and fourth regions can be configured as needed. It is understood that the positions of the first and third regions, and the second and fourth regions, can completely correspond in the thickness direction of the substrate 110, or can be offset, and this is not limited here.

[0056] In some embodiments, step S110 includes the following steps:

[0057] Step S111: providing a silicon wafer and performing double-sided texturing on the silicon wafer.

[0058] In some embodiments, an N-type silicon wafer is provided. Oil stains on the surface of the silicon wafer are first removed by pre-cleaning. An alkaline solution is then used to remove the mechanical damage layer on the silicon wafer caused during the cutting process, and a texturing treatment is performed to form an uneven velvet structure on the surface of the silicon wafer. This velvet structure not only increases the light-receiving area but also reduces the reflection of sunlight from the surface of the solar cell 100, thereby increasing the absorption rate of sunlight from the surface of the solar cell 100 and ultimately improving the photoelectric conversion efficiency of the solar cell 100.

[0059] Step S112: performing boron diffusion treatment on the textured silicon wafer to form a boron diffusion layer on one side of the silicon wafer.

[0060] In some specific embodiments, a texturing-treated silicon wafer is placed in a diffusion furnace. Heat is applied to evaporate or sublime a boron source (e.g., boron tribromide (BBr3) or boron trichloride (BCl3)). The generated boron atoms, after being heated to a certain temperature by the diffusion source, diffuse into the silicon wafer, forming a boron diffusion layer on the front surface of the wafer. This layer forms a PN junction with the wafer. During the boron diffusion process, the boron atoms chemically react with silicon atoms on the wafer's surface to form borosilicate compounds. These compounds fuse at high temperatures on the surface of the boron diffusion layer and the back surface of the wafer, forming a borosilicate glass layer.

[0061] In some embodiments, the boron diffusion process includes a front boron diffusion process and a post boron diffusion process. The front boron diffusion process is a boron diffusion process performed on the silicon wafer after texturing, and the post boron diffusion process is a further boron diffusion process performed on the silicon wafer after the front boron diffusion is completed.

[0062] Step S113: removing the borosilicate glass layer on the back of the silicon wafer and polishing the back of the silicon wafer.

[0063] Specifically, in some embodiments, since an excess borosilicate glass layer is formed on the back of the silicon wafer when the silicon wafer is subjected to boron diffusion treatment, chain cleaning is used to remove the excess borosilicate glass layer on the back of the silicon wafer after the boron diffusion treatment, and then the back of the silicon wafer is polished with a solution such as potassium hydroxide (KOH) to form a flat tower base structure.

[0064] So, like Figure 2 As shown, the silicon wafer is processed by texturing, boron diffusion, etching, polishing, etc. to form a substrate 110. The back of the silicon wafer serves as the first surface 110a of the substrate 110, and the side surface of the silicon wafer having the boron diffusion layer and the borosilicate glass layer serves as the second surface 110b of the substrate 110.

[0065] After step S110 , the method further includes step S120 : forming a tunneling layer and a doped conductive layer on a first area of the first surface of the substrate; the doped conductive layer is located on a surface of the tunneling layer that is away from the substrate.

[0066] Specifically in some embodiments, step S120 includes the following steps:

[0067] Step S121: forming an initial tunneling layer and an initial doped conductive layer on the first surface of the substrate; the initial doped conductive layer is located on a side of the initial tunneling layer that is away from the substrate.

[0068] like Figures 1 to 4 As shown, the initial tunneling layer 121 and the initial doped conductive layer 132 together form a passivation contact structure, which can block the recombination of minority carriers and holes, thereby improving the open circuit voltage and short circuit current of the battery.

[0069] Specifically, in the present application, the initial doped conductive layer 132 is thickened compared to the prior art. The thickness of the initial doped conductive layer 132 is increased by 10 nm to 50 nm compared to the prior art. The total thickness H1 of the initial doped conductive layer 132 satisfies: 160 nm ≤ H1 ≤ 200 nm, so as to facilitate the arrangement of electrodes in subsequent processes. It can be understood that the total thickness H1 of the initial doped conductive layer 132 is not limited to this and can be set as needed to meet different requirements. On the contrary, if the initial doped conductive layer 132 is too thin, it will be detrimental to the arrangement of electrodes in subsequent processes. If the thickness of the initial doped conductive layer 132 is too thick, it will cause a significant increase in parasitic absorption, which is not conducive to improving the photoelectric conversion efficiency of the solar cell 100.

[0070] In some embodiments, step S121 includes the following steps:

[0071] Step S1211: forming an initial tunneling layer and an initial silicon layer on a first surface of a substrate; an initial doped conductive layer is located on a side of the initial tunneling layer facing away from the substrate.

[0072] Specifically in some embodiments, Figure 3 As shown, the initial tunneling layer 121 covers all areas of the first surface 110a of the substrate 110. The material forming the initial tunneling layer 121 can be silicon oxide, titanium oxide, silicon nitride, aluminum oxide, hafnium oxide, etc. The method of forming the initial tunneling layer 121 can be a thermal oxidation process, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, etc.

[0073] The initial silicon layer 131 is used to form an initial doped conductive layer 132 in a subsequent process. The initial silicon layer 131 is stacked on a side of the initial tunneling layer 121 facing away from the substrate 110 and completely covers the initial tunneling layer 121 .

[0074] The step of forming the initial silicon layer 131 includes: forming the initial silicon layer from at least one of amorphous silicon or microcrystalline silicon. The process of forming the initial silicon layer can adopt chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

[0075] Step S1212: using a phosphorus diffusion process to dope the initial silicon layer with a high concentration to form an initial doped conductive layer.

[0076] like Figure 4 As shown, in one embodiment, the phosphorus diffusion process can utilize a phosphorus source (such as POC l3 ) reacts with the surface of the initial silicon layer 131 to form phosphorus atoms that diffuse into the interior of the initial silicon layer 131. At the same time, the high temperature during the diffusion process can convert amorphous silicon into polycrystalline silicon, thereby converting the initial silicon layer 131 into an initial doped conductive layer 132.

[0077] The initial doped conductive layer 132 can have a field passivation effect. A built-in electric field can be formed in the direction of the initial doped conductive layer 132 pointing to the substrate 110, causing minority carriers to escape, thereby reducing the concentration of minority carriers and reducing the carrier recombination rate at the interface of the substrate 110, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell 100, and improving the photoelectric conversion efficiency of the solar cell 100.

[0078] Specifically, in one embodiment, the phosphorus doping concentration of the initial doped conductive layer 132 is 3.5×10 20 atom / cm 3 to 6×10 20 atom / cm 3 Alternatively, the phosphorus doping concentration of the initial doped conductive layer 132 is 4×10 20 atom / cm 3 to 5×10 20 atom / cm 3 .

[0079] After step S121 , the method further includes step S122 : removing portions of the initial tunneling layer and the initial doped conductive layer located in the second region to form a tunneling layer and a doped conductive layer.

[0080] Please combine Figure 5 As shown, in one embodiment, a laser etching process can be used to remove the portions of the initial tunneling layer 121 and the initial doped conductive layer 132 located in the second region, exposing a portion of the second surface 110b of the substrate 110. The portion not laser-etched forms the tunneling layer 122 and the doped conductive layer 133 located only in the first region. In other words, the first region of the first surface 110a of the substrate 110 is covered by the tunneling layer 122 and the doped conductive layer 133, while the second region of the first surface 110a of the substrate 110 is not covered by the tunneling layer 122 and the doped conductive layer 133. In some embodiments, the width of the initial tunneling layer 121 and the initial doped conductive layer 132 is 250 μm to 350 μm. Optionally, the width of the initial tunneling layer 121 and the initial doped conductive layer 132 is 300 μm.

[0081] Specifically, in one embodiment, the laser scanning speed used in the laser etching process is 50,000 mm / s to 70,000 mm / s, the laser power is 60 W to 70 W, and the laser frequency is 850 kHz to 900 kHz. It will be appreciated that the laser etching process parameters can be set as needed to meet different processing requirements.

[0082] After step S120 , the method further includes step S130 : removing the polysilicon on the second surface of the substrate.

[0083] Since polysilicon wraparound is formed on the second surface 110b of the substrate 110 when the doped conductive layer 133 is formed on the first surface 110a of the substrate 110, it is necessary to remove the polysilicon wraparound on the second surface 110b. Specifically, in one embodiment, the polysilicon wraparound on the second surface 110b of the substrate 110 can be removed by chain cleaning.

[0084] After step S130 , the method further includes step S140 : forming a receiving groove on a surface of the doped conductive layer that is away from the tunneling layer.

[0085] Please combine Figure 6As shown, in some embodiments, a laser etching process can be used to form a receiving groove 133a on a surface of the doped conductive layer 133 facing away from the tunneling layer 122. The receiving groove 133a has a groove bottom wall and groove sidewalls circumferentially surrounding the groove bottom wall. In one embodiment, the laser scanning speed used in the above-mentioned laser etching process is 50,000 mm / s to 70,000 mm / s, the laser power is 60W to 70W, and the laser frequency is 850Khz to 900Khz. It will be understood that the process parameters of the laser etching process can be set as needed to meet different processing requirements.

[0086] The longitudinal cross-section of the receiving groove 133a is rectangular. The depth H2 of the receiving groove 133a in the thickness direction of the substrate 110 is between 10 nm and 50 nm, and the width W of the receiving groove 133a is between 22 μm and 32 μm. It will be appreciated that the shape, depth, and width of the receiving groove 133a can be customized to meet different electrode placement requirements. For example, in some other embodiments, the longitudinal cross-section of the receiving groove 133a is U-shaped with a curved bottom.

[0087] Step S150: forming a first passivation layer on the side of the substrate where the doped conductive layer is provided.

[0088] Please combine Figure 7 As shown, the first passivation layer 140 has the functions of fixing negative charges, eliminating parasitic capacitance effects, and improving passivation effects. Specifically, in one embodiment, a material such as aluminum oxide can be deposited on the side of the substrate 110 where the doped conductive layer 133 is provided using thermal atomic deposition to form the first passivation layer 140.

[0089] Specifically, the first passivation layer 140 covers the second region of the first surface 110a of the substrate 110 and the surface of the doped conductive layer 133 facing away from the substrate 110, specifically including the surface of the doped conductive layer 133 not provided with the receiving groove 133a and the groove wall of the receiving groove 133a. It will be understood that the process for forming the first passivation layer 140 is not limited to this and can be configured as needed to meet different requirements.

[0090] More specifically, the first passivation layer 140 may be a double-layer structure, wherein the film layer close to the doped conductive layer 133 is formed of an aluminum oxide layer, and the film layer away from the doped conductive layer 133 is formed of one or more materials selected from silicon nitride, silicon oxynitride, and silicon oxide.

[0091] Step S160: forming a second passivation layer on the second surface of the substrate.

[0092] Please combine Figure 7As shown, the functions of the second passivation layer 150 include fixing negative charges, eliminating parasitic capacitance effects, and improving the passivation effect. Specifically, in one embodiment, a thermal atomic deposition method can be used to deposit a material such as aluminum oxide on the surface of the doped conductive layer 133 facing away from the tunneling layer 122 to form the second passivation layer 150. More specifically, the second passivation layer 150 can have a double-layer structure, with the film layer close to the substrate 110 being formed of an aluminum oxide layer, and the film layer away from the substrate 110 being formed of one or more materials selected from silicon nitride, silicon oxynitride, and silicon oxide.

[0093] Step S170: forming a first electrode in ohmic contact with the doped conductive layer on a side of the doped conductive layer away from the tunneling layer; the orthographic projection of the first electrode on the first surface at least partially overlaps with the orthographic projection of the receiving groove on the first surface.

[0094] Specifically, a metal paste is printed on the second passivation layer 150 using screen printing. The metal paste printed on the tunneling layer 122 partially fills the receiving groove 133a. The metal paste is then sintered to form the first electrode 160 that is in ohmic contact with the doped conductive layer 133. These first electrodes 160 are used to collect and transmit current from the solar cell 100. It will be understood that because the metal paste corrodes the doped conductive layer 133, the actual thickness of the receiving groove 133a after the first electrode 160 is formed is greater than its initial thickness.

[0095] Since the orthographic projection of the first electrode 160 on the first surface 110a at least partially overlaps with the orthographic projection of the accommodating groove 133a on the first surface 110a, the first electrode 160 can achieve better ohmic contact with the doped conductive layer 133. At the same time, since the accommodating groove 133a has undergone a high-concentration doping treatment of phosphorus diffusion, the contact resistance between the metal paste and the accommodating groove 133a can be further reduced, thereby improving the efficiency of the solar cell 100.

[0096] Moreover, since the doped conductive layer 133 adopts a thickened design, although a receiving groove 133a is opened on the doped conductive layer 133, the doped conductive layer 133 below the receiving groove 133a still has a certain thickness. Therefore, when printing metal paste, although the metal paste will corrode the doped conductive layer 133, it can still be ensured that the doped conductive layer 133 has a sufficient thickness.

[0097] Specifically in some embodiments, one end of the first electrode 160 is located in the receiving groove 133a, and the other end of the first electrode 160 protrudes out of the receiving groove 133a. The height of the first electrode 160 is 3 um to 7 um. Optionally, the height of the first electrode 160 is 5 um.

[0098] Step S180: forming a second electrode in ohmic contact with the substrate on the side of the substrate where the second surface is provided.

[0099] Please combine Figure 8 As shown, specifically in one embodiment, metal paste is printed on the second passivation layer 150 by screen printing, and then the metal paste is sintered to form a second electrode 170 that is in ohmic contact with the boron diffusion layer of the substrate 110. These second electrodes 170 are used to collect and transmit current of the solar cell 100.

[0100] The above-mentioned method for preparing a solar cell thickens the doped conductive layer 133 so that the doped conductive layer 133 still has a certain thickness after the groove is opened. At the same time, the metal paste can be filled into the receiving groove 133a, so that the electrode and the doped conductive layer 133 have a larger contact area, thereby achieving better ohmic contact. At the same time, the high concentration of phosphorus doping at the receiving groove 133a can further reduce the contact resistance between the metal paste and the doped conductive layer 133, thereby improving the efficiency of the solar cell 100.

[0101] Specifically in one embodiment, a method for preparing a solar cell includes the following steps:

[0102] First, an N-type silicon wafer is provided. Double-sided texturing is performed on the N-type silicon wafer. Then, boron diffusion is performed on the textured silicon wafer, forming a boron diffusion layer and a borosilicate glass layer on both sides of the silicon wafer. The borosilicate glass layer on the back side of the silicon wafer is then removed and polished to form the substrate 110.

[0103] Then, an initial tunneling layer 121 and an initial silicon layer 131 are formed on the first surface 110a of the substrate 110. The initial silicon layer 131 is located on the side of the initial tunneling layer 121 facing away from the substrate 110. The thickness of the initial silicon layer 131 is 160nm to 200nm. Afterwards, a phosphorus diffusion process is used to dope the initial silicon layer 131 with a high concentration to form an initial doped conductive layer 132. The phosphorus doping concentration of the initial doped conductive layer 132 is 4×10 20 atom / cm 3 to 5×10 20 atom / cm 3 .

[0104] Then, a laser etching process is used to remove the portions of the initial tunneling layer 121 and the initial doped conductive layer 132 located in the second region, forming the tunneling layer 122 and the doped conductive layer 133. Thereafter, the polysilicon coating on the second surface 110b of the substrate 110 is removed, and a receiving groove 133a is formed on the side of the doped conductive layer 133 facing away from the tunneling layer 122. The depth of the receiving groove 133a is 10nm to 50nm, and the width of the receiving groove 133a is 22um to 32um. Then, a passivation layer is formed on the side of the doped conductive layer 133 facing away from the tunneling layer 122 and the second surface 110b of the substrate 110.

[0105] Finally, a first electrode 160 and a second electrode 170 are formed on both sides of the substrate 110 , respectively. One end of the second electrode 170 is located in the receiving groove 133 a , and the other end protrudes out of the receiving groove 133 a .

[0106] The present application also provides a solar cell 100 , which is prepared by the above-mentioned preparation method. The solar cell 100 includes a substrate 110 , a tunneling layer 122 , a doped conductive layer 133 , and electrodes.

[0107] The substrate 110 is a rectangular flat plate structure having a first surface 110a and a second surface 110b that are opposite and horizontally arranged along the thickness direction of the substrate 110. The first surface 110a is the surface of the substrate 110 facing the backlight side of the solar cell 100, and the second surface 110b is the surface of the substrate 110 facing the light-receiving side of the solar cell 100.

[0108] The first surface 110a has a first region and a second region. The first region is the region where the electrodes are located, and the second region is the region of the first surface 110a excluding the first region. The second surface 110b has a third region and a fourth region. The third region is the region where the electrodes are located, and the fourth region is the region of the second surface 110b excluding the third region. The positions of the first and third regions, and the second and fourth regions, can be completely aligned or offset in the thickness direction of the substrate 110, without limitation herein.

[0109] The tunneling layer 122 is disposed in a first region of the first surface 110a of the substrate 110. The doped conductive layer 133 is disposed on a side of the tunneling layer 122 facing away from the substrate 110. A receiving groove 133a is defined on the surface of the doped conductive layer 133 facing away from the tunneling layer 122. The electrodes include a first electrode 160 and a second electrode 170. The first electrode 160 is disposed on a side of the doped conductive layer 133 facing away from the tunneling layer 122. The orthographic projection of the first electrode 160 on the first surface 110a at least partially overlaps with the orthographic projection of the receiving groove 133a on the first surface 110a. The second electrode 170 is disposed on the second surface 110b of the substrate 110.

[0110] In this way, the first electrode 160 is partially located within the receiving groove 133a, and the first electrode 160 and the doped conductive layer 133 have a larger contact area, thereby achieving better ohmic contact. At the same time, by thickening the doped conductive layer 133, the doped conductive layer 133 below the first electrode 160 is ensured to have a sufficient thickness even when the receiving groove 133a is provided. This prevents the first electrode 160 from corroding the doped conductive layer 133 during the formation process, causing the doped conductive layer 133 to become too thin, or even penetrating the doped conductive layer 133.

[0111] In some embodiments, the thickness of the portion of the doped conductive layer 133 not provided with the receiving groove 133a ranges from 160 nm to 200 nm. This thickness is increased by 10 nm to 50 nm compared to the 150 nm thickness of the doped conductive layer 133 in the prior art. This increased thickness provides sufficient space for the provision of the receiving groove 133a. The receiving groove 133a has a rectangular or U-shaped cross-section. The depth H2 of the receiving groove 133a can range from 10 nm to 50 nm, and the width W of the receiving groove 133a ranges from 22 μm to 32 μm. The depth of the receiving groove 133a is proportional to the thickness of the doped conductive layer 133, thereby ensuring that the minimum thickness of the remaining doped conductive layer 133 is greater than 150 nm.

[0112] In some embodiments, the phosphorus doping concentration of the doped conductive layer 133 is 3.5×10 20 atom / cm 3 to 6×10 20 atom / cm 3 Alternatively, the phosphorus doping concentration of the doped conductive layer 133 is 4×10 20 atom / cm 3 to 5×10 20 atom / cm 3 , so that the receiving groove 133 a has a higher phosphorus doping concentration, which can further reduce the contact resistance between the first electrode 160 and the doped conductive layer 133 and improve the efficiency of the solar cell 100.

[0113] The present application also provides a tandem cell comprising a top cell, an intermediate connecting layer, and a bottom cell, wherein the intermediate connecting layer is connected between the bottom and top cells. The top cell is a perovskite cell, a cadmium telluride solar cell, a copper indium gallium selenide solar cell, or a gallium arsenide solar cell, and the bottom cell is the aforementioned solar cell 100. The intermediate connecting layer is typically selected from a transparent material with a high refractive index, such as a transparent conductive metal oxide film (ITO).

[0114] The present application also provides a photovoltaic module including the aforementioned solar cell 100 or laminated cell. In some embodiments, the photovoltaic module includes a laminate and a frame surrounding the laminate. Along the direction of illumination, the laminate includes a front sheet, a first encapsulating film, the solar cell 100, a second encapsulating film, and a back sheet, arranged in this order.

[0115] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A solar cell, characterized in that: include: A substrate having a first surface and a second surface disposed opposite to each other along a thickness direction of the substrate, wherein the first surface has a first area and a second area; a tunneling layer, disposed in the first region of the first surface of the substrate; a doped conductive layer, disposed on a side of the tunneling layer away from the substrate, wherein a surface of the doped conductive layer facing away from the tunneling layer is provided with a receiving groove; as well as An electrode is provided on a surface of the doped conductive layer facing away from the tunneling layer, and an orthographic projection of the electrode on the first surface at least partially overlaps with an orthographic projection of the receiving groove on the first surface.

2. The solar cell according to claim 1, wherein The thickness of the doped conductive layer in a region where the receiving groove is not provided is 160 nm to 200 nm.

3. The solar cell according to claim 1, wherein The depth of the receiving groove in the thickness direction of the substrate is 10 nm to 50 nm.

4. The solar cell according to claim 1, wherein The width of the accommodating groove is 22um to 32um.

5. The solar cell according to claim 1, wherein The longitudinal section of the accommodating groove parallel to the thickness direction of the base is rectangular.

6. The solar cell according to claim 1, wherein The phosphorus doping concentration of the doped conductive layer is 3.5×10 20 atom / cm 3 to 6×10 20 atom / cm 3 .

7. A method for preparing a solar cell, characterized in that: include: providing a substrate; The substrate has a first surface and a second surface arranged opposite to each other along a thickness direction of the substrate, and the first surface has a first area and a second area; forming a tunneling layer and a doped conductive layer on the first region of the first surface of the substrate; the doped conductive layer is located on a surface of the tunneling layer that is away from the substrate; A receiving groove is formed on a surface of the doped conductive layer that is away from the tunneling layer; forming an electrode in ohmic contact with the doped conductive layer on a surface of the doped conductive layer that is away from the tunneling layer; The orthographic projection of the electrode on the first surface at least partially overlaps with the orthographic projection of the receiving groove on the first surface.

8. The method for preparing a solar cell according to claim 7, wherein: The accommodating groove is opened on a surface of the doped conductive layer that is away from the tunneling layer by using a laser etching process.

9. The method for preparing a solar cell according to claim 7, wherein: The step of forming a tunneling layer and a doped conductive layer on the first region of the first surface of the substrate specifically includes: forming an initial tunneling layer and an initial doped conductive layer on the first surface of the substrate; the initial doped conductive layer is located on a side of the initial tunneling layer away from the substrate; Portions of the initial tunneling layer and the initial doped conductive layer located in the second region are removed to form the tunneling layer and the doped conductive layer.

10. The method for preparing a solar cell according to claim 9, wherein: The portions of the initial tunneling layer and the initial doped conductive layer located in the second region are removed by a laser etching process.

11. The method for preparing a solar cell according to claim 10, wherein: The scanning speed of the laser used in the laser etching process is 50,000 mm / s to 70,000 mm / s, the power of the laser is 60W to 70W, and the frequency of the laser is 850Khz to 900Khz.

12. The method for preparing a solar cell according to claim 7, wherein: After the step of forming a receiving groove on a surface of the doped conductive layer that is away from the tunneling layer, the method further includes: A passivation layer is formed in the second region of the first surface of the substrate and on a surface of the doped conductive layer facing away from the tunneling layer.

13. A stacked battery comprising a top battery and a bottom battery, characterized in that: The bottom cell is the solar cell according to any one of claims 1 to 6, or a solar cell prepared by the method for preparing a solar cell according to any one of claims 7 to 12.

14. A photovoltaic module, characterized in that: The invention comprises the solar cell according to any one of claims 1 to 6, or a solar cell prepared by the method for preparing a solar cell according to any one of claims 7 to 12, or the stacked cell according to claim 13.

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