Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, which are used for realizing light trapping, electric leakage prevention, minority carrier lifetime prolonging and cell efficiency improving. Comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer, the silicon substrate has a first surface, a second surface and a side surface. The first surface has a pyramid structure, and the side surface comprises a first region, a second region and a third region which are sequentially distributed; the first region is adjacent to the first surface and the third region is adjacent to the second surface. The second region is recessed towards the silicon substrate by a distance of 2-10 [mu] m relative to the first region; the first area is provided with a first pyramid structure, the second area is provided with a second pyramid structure, and the third area is provided with a third pyramid structure and / or a first texture structure; the first doped semiconductor layer and the second doped semiconductor layer with opposite conduction types are respectively arranged on the first surface and the second surface; the passivation layer is arranged on the first surface, the second surface and the side surface.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells are increasingly being used as a new energy alternative. They convert sunlight into electricity. Specifically, they utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0003] Due to the different structural designs on the surface of the silicon substrate, depending on the morphology and position, it can increase light trapping, prevent leakage and other functions, but it will also make the relatively flat silicon substrate surface more undulating and increase surface defects, thereby affecting the lifetime of minority carriers and reducing battery efficiency. Summary of the Invention

[0004] The object of the present invention is to provide a solar cell and a photovoltaic module that can achieve the effects of light trapping, preventing leakage, increasing minority carrier lifetime and improving cell efficiency.

[0005] In a first aspect, the present invention provides a solar cell comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer; The silicon substrate has a first surface, a second surface and a side surface connecting the first surface and the second surface; The first surface has a plurality of pyramid structures, and the side surface includes a first area, a second area, and a third area sequentially distributed from the first surface to the second surface; the first area is adjacent to the first surface, the third area is adjacent to the second surface, and the second area is located between the first area and the third area; The second region is recessed into the silicon substrate relative to the first region, and a first recessed distance is 2 μm to 10 μm; The first area has a plurality of first pyramid structures, the second area has a plurality of second pyramid structures, and the third area has a plurality of third pyramid structures and / or a plurality of first texture structures; The first doped semiconductor layer is disposed on the first surface; The second doped semiconductor layer is disposed on the second surface, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; The passivation layer is arranged on the first surface, the second surface and the side surface. The passivation layer is located on a surface of the first doped semiconductor layer and the second doped semiconductor layer away from the silicon substrate.

[0006] When the above technical solution is adopted, for bifacial solar cells, since doped semiconductor layers of opposite doping types are located on the front and back sides of the solar cell, respectively, leakage will occur if the doped semiconductor layers on the front and back sides overlap at the side. Due to area and position limitations, the side surfaces of solar cells are difficult to pattern using lasers to form isolation grooves during mass production. Therefore, by etching the side surfaces, the doped semiconductor layer deposited by plating around the side surfaces is removed, so that the second area of the side surfaces is recessed into the silicon substrate relative to the first area adjacent to the first surface. This ensures that the doped semiconductor layer deposited on the side surfaces during the coating process and the inner expansion layer formed by the doped semiconductor layer in the silicon substrate on the side surfaces are etched away. Secondly, the recessed second area increases the junction area near the first surface while preventing leakage risks caused by the small spacing between the first and second doped semiconductor layers along the thickness direction of the silicon substrate. The first recessed distance is greater than or equal to 2μm to ensure that the film layer and the inner expansion layer are removed to reduce leakage risks; however, it cannot be too large. The first recessed distance is less than or equal to 10μm to ensure continuous coverage of the passivation layer and ensure passivation performance. A second pyramid structure is set in the recessed second area. On the one hand, it can further etch toward the silicon substrate, increase the etching depth of the side surface, and ensure the removal of the inner expansion layer on the side of the battery cell. On the other hand, the undulating structure of the second pyramid velvet surface can effectively increase the randomness of the surface height, interrupt the continuity of the side surface, and further reduce the leakage risk caused by the overlap of different doping type film layers or inner expansion layers on the side.

[0007] In some possible implementations, the second surface includes alternating groove regions and doped regions, the groove regions are recessed into the silicon substrate relative to the doped regions, the second doped semiconductor layer is located in the doped regions, and the passivation layer is located in the groove regions and the doped regions; the groove regions are recessed into the silicon substrate relative to the doped regions, and the recessed distance is a second distance; wherein the first distance is greater than or equal to the second distance.

[0008] When the above technical solution is adopted, the second doped semiconductor layer is not provided in the groove area, which reduces the parasitic absorption caused by the second doped semiconductor layer. The depth of the downward depression can ensure that the inner expansion layer below the groove area is removed, reducing the compounding problem caused by the higher doping concentration in the non-power generation area. In addition, the groove area on the back and the depression formed by the second area on the side relative to the first area can increase the light trapping effect and improve the light absorption efficiency of the battery. In comparison, the groove area on the back does not need a deeper depression to avoid leakage problems because the doping type of the doped semiconductor layer in the adjacent doped areas is the same. And because the groove area is located on the second side and has a large distribution area, the shallower groove area can better take into account the mechanical strength of the battery and reduce damage to the silicon substrate. Therefore, the second distance is set to be smaller than the first distance. Since the depth of the second distance is smaller, the time for etching and removing the groove area can be reduced, thereby improving the preparation efficiency.

[0009] In some possible implementations, the second surface includes alternating groove regions and doped regions, the groove regions are recessed into the silicon substrate relative to the doped regions, and the groove regions include a fourth pyramid structure or a second texture structure; the second doped semiconductor layer is located in the doped region, and the passivation layer is located in the groove region and the doped region.

[0010] When using the above technical solution, the second doped semiconductor layer is not provided in the trench region, reducing the parasitic absorption caused by the second doped semiconductor layer. The depth of the downward depression ensures that the inner expansion layer below the trench region is removed, reducing the recombination problem caused by the high doping concentration in the non-power generation area. The fourth pyramid velvet structure provided in the trench region can further enhance the light trapping effect of the second side of the bifacial cell, increase the bifaciality of the overall cell, and comprehensively improve the cell performance. The second texture structure provided in the trench region can better meet the coverage of the passivation layer in the trench region, meet the passivation performance requirements of the trench region, and improve the fill factor of the solar cell.

[0011] In some possible implementations, the second distance is 0.5 μm to 9 μm. The second distance of the groove region is greater than or equal to 0.5 μm to ensure that the membrane layer and the inner expansion layer are removed to reduce parasitic absorption caused by the second doped semiconductor layer and reduce the recombination problem caused by the high doping concentration in the non-power generation area; however, it cannot be too large. The second distance of the groove is less than or equal to 9 μm to ensure continuous coverage of the passivation layer on the second surface, maintain passivation performance, maintain the mechanical strength of the battery, and minimize damage to the silicon substrate.

[0012] In some possible implementations, the second region is recessed into the silicon substrate relative to the third region, and a third distance of the recess is 0.1 μm to 5 μm.

[0013] When adopting the above technical solution, the depth of the second area recessed into the silicon substrate is smaller than that of the third area. Combined with the recessed depths on the front and back sides of the solar cell, the recessed depths can be set smaller, meeting the electrical isolation structure while taking into account the mechanical strength of the cell.

[0014] In some possible implementations, the third pyramid structure is recessed into the silicon substrate. That is, the opposing sides of the third pyramid structure in the third region face the recess within the silicon substrate. This inverted quadrangular pyramid structure allows light to be reflected multiple times within the third pyramid structure, increasing the optical path length and reducing the reflectivity of sunlight in the third region to between 2% and 20%. This allows more light to be absorbed by the solar cell, thereby improving the solar cell's photoelectric conversion efficiency.

[0015] In some possible implementations, the passivation layer includes a first passivation layer, and a thickness of the first passivation layer located on the first region is greater than a thickness of the first passivation layer located on the second region.

[0016] When adopting the above technical solution, the first area is closer to the edge of the solar cell than the second area. Therefore, the thickness of the first passivation layer located on the first area is greater than the thickness of the first passivation layer located on the second area, which can increase the passivation effect on the edge of the solar cell.

[0017] In some possible implementations, the difference between the thickness of the first passivation layer located on the first region and the thickness of the first passivation layer located on the second region is less than or equal to 2 nm. If the difference is greater than 2 nm, the thickness difference is too large, resulting in poor thickness uniformity of the first passivation layer and varying degrees of carrier recombination, which can easily affect the current density of the solar cell and reduce the open-circuit voltage of the solar cell. Therefore, to enhance edge passivation and overall solar cell performance, the thickness difference is less than or equal to 2 nm.

[0018] In some possible implementations, the thickness of the passivation layer over the trench region is thinner than that over the doped region. Due to the difference in surface roughness and surface height between the two regions, it is more difficult to deposit a thicker passivation layer in the trench region than in the doped region. This thickness setting, while still meeting performance requirements, simplifies the process.

[0019] In some possible implementations, the passivation layer includes a second passivation layer and a third passivation layer, the second passivation layer is arranged on the first surface and / or the second surface, and the third passivation layer is arranged on the side surface; wherein the thickness of the third passivation layer is greater than the thickness of the second passivation layer.

[0020] In the above technical solution, the third passivation layer covers the side of the battery. Due to its low conductivity, it can provide partial electrical isolation. Furthermore, due to the complexity of the side surface topography, a better passivation effect is required. Therefore, a thicker third passivation layer on the side can further enhance the electrical isolation effect, while also strengthening the passivation effect on the side and reducing recombination.

[0021] In some possible implementations, the difference between the thickness of the third passivation layer and the thickness of the second passivation layer is greater than or equal to 20 nm. Because the side surfaces have the first, second, and third regions, and the height difference is relatively complex, the morphology of the silicon substrate surface on the side surfaces is relatively complex, requiring a thicker passivation layer to passivate the side surfaces of the cell. Therefore, to enhance the side passivation effect and overall cell performance, the difference between the thickness of the third passivation layer and the second passivation layer is greater than or equal to 20 nm.

[0022] In some possible implementations, the passivation layer includes a second passivation layer, which is arranged on the first surface and / or the second surface; the second passivation layer located on the second surface is arranged on the surface of the doped area and the groove area, and the second passivation layer located in the doped area is arranged on the side of the second doped semiconductor layer away from the silicon substrate; the thickness of the second passivation layer located in the groove area is different from the thickness of the second passivation layer located in the doped area.

[0023] When using the above technical solution, the second passivation layer has different thicknesses in different areas on the second surface, which can flexibly adjust the battery membrane structure to match the requirements for improving different battery parameters, such as open circuit voltage, fill factor, or short-circuit current. Setting the thickness of the second passivation layer in the trench region to be greater than that in the doped region can better meet the passivation requirements for the silicon substrate surface in the trench region and improve the open circuit voltage of the solar cell. Alternatively, when the solar cell needs to improve the contact performance by increasing the burn-through performance of the electrode to the doped semiconductor layer, it is necessary to set a thicker passivation layer on the surface of the doped region to protect the non-electrode area above the doped region to balance the requirements of contact performance and passivation performance. However, blindly increasing the thickness of all passivation layers on the second surface will reduce the uniformity of the second passivation layer, resulting in different degrees of carrier recombination, which is easily affected by the current density of the solar cell. In this case, setting the thickness of the second passivation layer in the doped region to be greater than that in the trench region can balance the contact performance, passivation performance, and current density of the solar cell, ultimately improving the cell efficiency.

[0024] In some possible implementations, in the thickness direction of the solar cell, the length of the second region accounts for 50% to 95% of the thickness of the solar cell.

[0025] When using the above technical solution, if the length of the second region accounts for less than 50%, the length of the second region is too small to meet the side light trapping effect, and the isolation distance between the first doped semiconductor layer and the second doped semiconductor layer on the side is too small, posing a leakage risk. If the length of the second region accounts for more than 95%, the length is too large, resulting in a small proportion of the first region, which is not conducive to increasing the junction area on the side adjacent to the first surface, and increases damage to the first surface during the wet process, reducing the yield of battery production. Therefore, considering reducing the risk of leakage and increasing the side junction area, the length of the second region is selected to be 50% to 95%.

[0026] In some possible implementations, the doped region has a third texture structure, which presents a non-pyramid microstructure morphology and includes two or more first substructures that are at least partially stacked, and the bottom surface of the first substructure is a polygonal plane; wherein the one-dimensional dimension of the bottom surface of the outermost first substructure is greater than the one-dimensional dimension of the bottom surface of the fourth pyramid structure or the second texture structure in the groove region.

[0027] When the above technical solution is adopted, the fourth pyramid structure or the second texture structure is formed in the groove area and the non-pyramid texture structure is formed in the doped area, so that the formed battery has different levels of light trapping structures, increasing the effective contact area of light. Moreover, for the third texture structure formed in the doped area, the one-dimensional size of the bottom surface of the outermost first substructure is larger than the one-dimensional size of the bottom surface of the fourth pyramid structure or the second texture structure in the groove area, which is beneficial to improving the uniformity of the second doped semiconductor layer and further suppressing the local high doping concentration of the second doped semiconductor layer, reducing the contact resistivity, improving the open circuit voltage of the solar cell, and improving the fill factor and photoelectric conversion efficiency.

[0028] In some possible implementations, the size consistency of the pyramid structure located on the first surface is better than the size consistency of the second pyramid structure located in the second region.

[0029] When the above technical solution is adopted, by controlling the size consistency of the pyramid structures on the light-receiving surface and the side of the silicon substrate within a certain range, the consistency of the pyramid structure on the first side, i.e., the light-receiving side, is better controlled on the same solar cell. This can improve the light-trapping effect of the pyramid structure on the light-receiving side, and is conducive to improving the uniformity of the passivation layer formed on the pyramid structure. The performance of the formed passivation layer is better, and the open-circuit voltage of the solar cell is improved. The size consistency requirement of the second pyramid structure in the second area of the side is low. While improving the overall light-trapping effect of the solar cell, it can reduce the degree of etching of other areas of the solar cell when preparing the second pyramid structure, thereby reducing the difficulty of the preparation process. In other words, setting pyramid structures at different positions with the above-mentioned size consistency differences can take into account both the effects of improving the performance of the solar cell and reducing the difficulty of the preparation process.

[0030] In some possible implementations, when the trench region includes the fourth pyramid structure, the size consistency of the pyramid structure located on the first surface is better than the size consistency of the fourth pyramid structure located in the trench region.

[0031] When the above technical solution is adopted, by controlling the size consistency of the pyramid structures on the light-receiving surface and the backlight surface of the silicon substrate within a certain range, the consistency of the pyramid structure on the first surface, i.e., the light-receiving surface, is better controlled on the same solar cell. This can improve the light-trapping effect of the pyramid structure on the light-receiving surface, and is conducive to improving the uniformity of the passivation layer formed on the pyramid structure. The performance of the formed passivation layer is better, and the open-circuit voltage of the solar cell is improved. The size consistency requirement of the fourth pyramid structure on the backlight surface is low. While improving the overall light-trapping effect of the solar cell, it can reduce the degree of etching of other areas of the solar cell when preparing the fourth pyramid structure on the back, thereby reducing the difficulty of the preparation process. In other words, setting pyramid structures at different positions with the above-mentioned size consistency differences can take into account both the effects of improving the performance of the solar cell and reducing the difficulty of the preparation process.

[0032] In some possible implementations, when the trench region includes the fourth pyramid structure, the dimensional consistency of the second pyramid structure in the second region is comparable to the dimensional consistency of the fourth pyramid structure in the trench region. The similar dimensional consistency of the second pyramid structure and the pyramid structure in the trench region allows the texturing steps of the two regions to be performed in a single process, simplifying the solar cell process and reducing production costs.

[0033] In a second aspect, the present invention further provides a photovoltaic module, comprising: A battery string, wherein the battery string is formed by electrically connecting a plurality of solar cells as described in any one of the above items; an interconnection member electrically connected to the solar cell; and an encapsulation layer covering the surface of the battery string.

[0034] Since the photovoltaic assembly includes the solar cell of the first aspect, it has the same beneficial effects as the first aspect, which will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 A schematic cross-sectional view of a solar cell provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a solar cell according to an embodiment of the present invention, wherein the second region is recessed into the silicon substrate by a first distance relative to the first region; Figure 3 is a schematic diagram of a second distance by which the trench region of the solar cell is recessed relative to the doped region into the silicon substrate in an embodiment of the present invention; Figure 4A schematic cross-sectional view of another solar cell provided by an embodiment of the present invention; Figure 5 A schematic diagram of the side structure of a solar cell provided by an embodiment of the present invention; Figure 6 A three-dimensional diagram of a side tower base structure of a solar cell provided by an embodiment of the present invention; Figure 7 A schematic diagram of a pyramid structure in a trench region of a solar cell provided by an embodiment of the present invention; Figure 8 A schematic diagram of one-dimensional dimensions of a first texture structure or a second texture structure of a solar cell provided by an embodiment of the present invention; Figure 9 Another schematic diagram of one-dimensional size of a first texture structure or a second texture structure of a solar cell provided by an embodiment of the present invention; Figure 10 A schematic diagram of the one-dimensional size of a first substructure of a third texture structure of a solar cell provided by an embodiment of the present invention.

[0036] Figure numerals: 10 is a silicon substrate, 11 is a tunneling oxide layer, 12 is a second doped semiconductor layer, 13 is a passivation layer, 131 is an aluminum oxide layer, 132 is a silicon nitride layer, 14 is a first doped semiconductor layer, 15 is a second electrode, 16 is a first electrode, 101 is a first region, 102 is a second region, 103 is a third region, 104 is a doped region, 105 is a trench region, 106 is a first pyramid structure, 107 is a second pyramid structure, 108 is a fourth pyramid structure, 109 is a first texture structure, and 110 is a pyramid structure. DETAILED DESCRIPTION

[0037] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0040] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0041] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0042] In solar cells, the different structural designs of the silicon substrate surface can increase light trapping and prevent leakage, depending on the morphology and position. However, this can also increase the undulations on the relatively flat silicon substrate surface and increase surface defects, thereby affecting the lifetime of minority carriers and reducing battery efficiency.

[0043] In view of this, if Figures 1-6 As shown, an embodiment of the present invention provides a solar cell, including a silicon substrate 10, a first doped semiconductor layer 14, a second doped semiconductor layer 12 and a passivation layer 13; wherein the silicon substrate 10 has a first surface, a second surface and a side surface connecting the first surface and the second surface relative to each other, the first surface can be the light-receiving surface of the solar cell, that is, the front surface, and the second surface can be the backlight surface of the solar cell, that is, the back surface; or, the first surface can be the back surface of the solar cell, and the second surface can be the front surface of the solar cell.

[0044] The first surface of the silicon substrate 10 has a plurality of pyramid structures 110. The side surface of the silicon substrate 10 includes a first region 101, a second region 102, and a third region 103 distributed sequentially from the first surface to the second surface. The first region 101 is adjacent to the first surface, the third region 103 is adjacent to the second surface, and the second region 102 is located between the first region 101 and the third region 103. The second region 102 is recessed into the silicon substrate 10 relative to the first region 101, and a first recessed distance D1 is 2 μm to 10 μm, specifically 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, etc. The first region 101 has a plurality of first pyramid structures 106, and the second region 102 has a plurality of second pyramid structures 107. The third region 103 has multiple third pyramid structures and / or multiple first texture structures 109, the third pyramid structures are recessed in the silicon substrate 10, and the first texture structure 109 includes a pyramid base structure and / or a polishing structure, whose average roughness is less than the average roughness of the pyramid structure and the reflectivity is greater than the reflectivity of the pyramid structure; the first doped semiconductor layer 14 is arranged on the first surface; the second doped semiconductor layer 12 is arranged on the second surface, and the conductivity type of the first doped semiconductor layer 14 and the second doped semiconductor layer 12 are opposite; the passivation layer 13 is arranged on the first surface, the second surface and the side surface, and the passivation layer 13 is located on the side of the first doped semiconductor layer 14 and the second doped semiconductor layer 12 away from the silicon substrate 10.

[0045] It should be noted that the first distance D1 by which the second area 102 is recessed into the silicon substrate 10 relative to the first area 101 may be the distance difference between the top of the first pyramid structure 106 in the first area 101 and the top of the second pyramid structure 107 in the second area 102; or the distance difference between the bottom of the first pyramid structure 106 in the first area 101 and the bottom of the second pyramid structure 107 in the second area 102; or the distance difference between the top of the first pyramid structure 106 in the first area 101 and the bottom of the second pyramid structure 107 in the second area 102, as shown in FIG. Figure 2 or the distance difference between the side planes of the silicon substrate 10 where the first region 101 and the second region 102 are located. Further, the first distance D1 may be 3 μm to 6 μm, specifically 3 μm, 4 μm, 5 μm, 6 μm, etc.

[0046] The pyramid structure 110 on the first surface and the first pyramid structure 106 in the first area 101 on the side surface can be formed in the same step. During subsequent preparation, the first pyramid structure 106 in the first area 101 on the side surface may also be affected by other process steps, causing the first pyramid structure 106 to change and be different from the pyramid structure 110 on the first surface.

[0047] The pyramid structure 110, the first pyramid structure 106, the second pyramid structure 107, and the third pyramid structure have a base, a spire, and multiple sides connecting the base and the spire. The base can be at least one of a rectangle, a square, a rhombus, a trapezoid, an approximate rectangle, an approximate square, an approximate rhombus, an approximate trapezoid, or other polygons. The first texture structure 109 exhibits a non-pyramid microstructure morphology. The bottom surface of the first texture structure 109 is a polygonal plane. The shape of the polygonal plane includes at least one of a rectangle, a rhombus, a square, a trapezoid, an approximate rectangle, an approximate rhombus, an approximate square, and an approximate trapezoid. The first texture structure 109 includes a base structure and / or a polishing structure. Its average roughness is less than that of the pyramid structure and its reflectivity is greater than that of the pyramid structure. Multiple first texture structures 109 can exist independently or in a stacked state. It is understood that in the actual manufacturing process, the bottom surface of the first texture structure 109 presents an irregular polygonal plane, but overall presents morphological features similar to a rhombus, square, or trapezoid.

[0048] When the above technical solution is adopted, for bifacial solar cells, since doped semiconductor layers with opposite doping types are respectively located on the front and back sides of the solar cell, for example, the first doped semiconductor layer 14 located on the first side and the second doped semiconductor layer 12 located on the second side have opposite doping types, if the doped semiconductor layers on the front and back sides overlap at the side, leakage will occur. That is, when the first doped semiconductor layer 14 and the second doped semiconductor layer 12 are separately prepared, due to the characteristics of certain preparation processes (such as coating deposition), the first doped semiconductor layer and the second doped semiconductor layer may be formed on the side by wrap-around plating, so that the first doped semiconductor layer and the second doped semiconductor layer overlap each other at the side and leakage occurs; due to area and position limitations on the side of the solar cell, it is difficult to use laser patterning to form isolation grooves during mass production to isolate the first doped semiconductor layer and the second doped semiconductor layer on the side.

[0049] Therefore, the doped semiconductor layer deposited on the side by plating is removed by etching the side, so that the second area 102 on the side is recessed into the silicon substrate 10 relative to the first area 101 adjacent to the first surface. Firstly, the doped semiconductor layer deposited on the side during the plating process and the inner expansion layer formed by the doped semiconductor layer in the side silicon substrate are ensured to be etched and removed. The first doped semiconductor layer and the second doped semiconductor layer and the corresponding inner expansion layer do not exist on the recessed second area 102, thereby preventing the risk of leakage caused by the small spacing between the first doped semiconductor layer and the second doped semiconductor layer along the thickness direction of the silicon substrate. Secondly, only the second area 102 needs to be etched recessed, and the entire side does not need to be etched to the same depth. In this way, the first doped semiconductor layer 14 at the first area 101 adjacent to the first surface can be retained to increase the junction area close to the first surface and improve the carrier collection efficiency.

[0050] In addition, the first distance D1 of the second region 102 recessed into the silicon substrate 10 relative to the first region 101 is greater than or equal to 2 μm in order to ensure that the film layer and the inner expansion layer are removed to reduce the risk of leakage; however, it cannot be too large, and the first recessed distance D1 is less than or equal to 10 μm to ensure uniform and continuous coverage of the passivation layer 13 on the side, thereby ensuring the side passivation performance.

[0051] In addition, a second pyramid structure 107 is provided in the recessed second region 102. During the anisotropic etching process for forming the second pyramid structure 107, on the one hand, etching can be further performed toward the silicon substrate 10, thereby increasing the etching depth of the side surface, ensuring the removal of the inner expansion layer on the side of the silicon substrate, and reducing the mechanical strength damage caused by the entire recess of the second region 102. On the other hand, the undulating characteristics of the second pyramid structure 107 on the surface of the silicon substrate 10 can effectively increase the randomness of the surface height, interrupt the continuity of the side surface, and further reduce the risk of leakage caused by overlapping of different doping type film layers or inner expansion layers at the side.

[0052] like Figure 1 、 Figure 3 and Figure 4 As shown, in some embodiments, when the second surface includes alternatingly arranged trench regions 105 and doped regions 104, the distance that the trench regions 105 are recessed into the silicon substrate 10 relative to the doped regions 104 is a second distance D2; wherein the second distance D2 can be the distance difference between the top of the texture structure in the trench region 105 and the bottom of the third texture structure in the doped region 104, or the distance difference between the bottom of the texture structure in the trench region 105 and the bottom of the third texture structure in the doped region 104, or the distance difference between the planes of the silicon substrate 10 where the trench regions 105 and the doped regions 104 are located.

[0053] Since the second doped semiconductor layer 12 is not provided in the trench area 105, the parasitic absorption caused by the second doped semiconductor layer 12 is reduced. The depth of the downward depression can ensure that the inner expansion layer below the trench area 105 is removed, reducing the recombination problem caused by the higher doping concentration in the non-power generation area.

[0054] The first distance D1 is greater than or equal to the second distance D2 , that is, the depth of the second region 102 recessed relative to the first region 101 into the silicon substrate 10 is greater than or equal to the depth of the trench region 105 recessed relative to the doped region 104 into the silicon substrate 10 .

[0055] When the above technical solution is adopted, on the one hand, since the doping type of the second doped semiconductor layer 12 in the adjacent doping regions 104 on the second surface is the same, the groove region 105 does not need a deeper recess to avoid leakage problems, and because the groove region 105 is located on the second surface and has a large distribution area, the relatively shallow groove region 105 can better take into account the mechanical strength of the battery, so the second distance D2 is set to be less than or equal to the first distance D1; on the other hand, since the depth of the second distance D2 is small, the time for etching and removing the groove region 105 can be reduced, thereby improving the preparation efficiency.

[0056] like Figure 1 、 Figure 4 and Figure 7 As shown, in some embodiments, the second surface includes alternating groove regions 105 and doped regions 104, the groove regions 105 are recessed into the silicon substrate 10 relative to the doped regions 104, and the groove regions 105 include a fourth pyramid structure 108 or a second texture structure; the second doped semiconductor layer 12 is located in the doped region 104, and the passivation layer 13 is located in the groove region 105 and the doped region 104.

[0057] During the actual preparation process, etching is performed on a local area of the second surface to etch away the second doped semiconductor layer originally formed on the area until reaching the surface of the silicon substrate 10, thereby forming a groove area 105. The remaining areas of the second surface are not etched, and the second doped semiconductor layer 12 originally formed on the remaining areas is retained to form a doped area 104. The groove area 105 is recessed into the silicon substrate 10 relative to the doped area 104, and the surface of the groove area 105 is etched to form a texture structure.

[0058] In some embodiments, the trench region 105 includes a fourth pyramid structure 108 or a second texture structure. For example, the fourth pyramid structure 108 in the trench region 105 can further enhance light trapping on the second side of the bifacial cell, increasing the overall bifaciality of the cell and overall improving cell performance. The second texture structure in the trench region 105 can better ensure coverage of the passivation layer in the trench region 105, meet the passivation performance requirements of the trench region 105, and improve the fill factor of the solar cell.

[0059] For example, the second distance D2 can be 0.5 μm to 9 μm, specifically 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, etc. The second distance D2 of the groove region 105 is greater than or equal to 0.5 μm to ensure that the membrane layer and the inner expansion layer are removed to reduce parasitic absorption caused by the second doped semiconductor layer 12 and reduce the recombination problem caused by the high doping concentration in the non-power generation area; however, it cannot be too large. The second distance D2 of the groove region 105 is less than or equal to 9 μm to ensure continuous coverage of the passivation layer 13 on the second surface, ensure the passivation performance of the second surface, ensure the mechanical strength of the battery, and reduce damage to the silicon substrate 10.

[0060] In some embodiments, when the groove area 105 includes a second texture structure, the second distance D2 ranges from 0.5um to 3.5um. Since the second texture structure is a polygonal structure recessed into the silicon substrate 10, a smaller depth of the groove area 105 can accommodate the second texture structure. The shallower groove area 105 can better balance the mechanical strength of the battery and reduce damage to the silicon substrate 10.

[0061] In some embodiments, when the trench region 105 includes the fourth pyramid structure 108, the second distance D2 ranges from 3.5um to 9um. The deeper depth of the trench region 105 enables the top height of the fourth pyramid structure 108 to be lower than the surface of the doped region 104 bordering the trench region 105, thereby avoiding the height difference caused by the fourth pyramid structure 108 protruding from the second surface, which would negatively affect the gate line printing or passivation layer coating.

[0062] In order to further improve the light trapping effect of the groove area 105, the depth of the groove area 105 can be increased to accommodate fourth pyramid structures 108 of more sizes and types, reduce the reflectivity of the groove area 105, and avoid the height difference between the larger fourth pyramid structure 108 in the groove area 105 and the doped region 104. At the same time, considering the mechanical strength of the battery cell, the second distance D2 of the groove area 105 cannot be set too large. Exemplarily, the height of the fourth pyramid structure 108 in the groove area 105 can be 0.5 μm, 2 μm, 3.5 μm, 5 μm, etc., which increases the number of light reflections between the multiple fourth pyramid structures 108 and reduces the reflectivity of the fourth pyramid structure 108. If the height of the fourth pyramid structure 108 is less than 0.5 μm, the fluctuation amplitude of the fourth pyramid structure 108 is small, which will reduce the number of light reflections between the multiple fourth pyramid structures 108, resulting in an increase in the reflectivity of the texture structure of the groove area 105 and a reduction in the photoelectric conversion efficiency of the solar cell; if the height of the fourth pyramid structure 108 is greater than 5 μm, some light will fail to be reflected twice, which will increase the reflectivity of the texture structure of the groove area 105 and increase the stress inside the solar cell, thereby affecting the service life and stability of the solar cell.

[0063] In some embodiments, the second distance D2 can be set to be greater than the first distance D1. That is, the depth of the groove region 105 recessed into the silicon substrate 10 relative to the doped region 104 is greater than the depth of the second region 102 recessed into the silicon substrate 10 relative to the first region 101. The formation of the groove region 105 can be achieved by removing the surface protective layer using a laser, and then etching using a wet method or other methods. Therefore, the depth of the groove region 105 can be adjusted by controlling the laser energy. In the actual preparation process, the steps of wet etching the groove region 105 and partially forming the second region 102 can be placed in the same process step. In this case, the second distance D2 of the groove region 105 is set to be greater than the height of the fourth pyramid structure 108 and greater than the first distance D1. This can meet the requirements of improving the light trapping effect on the back side while simplifying the process steps, saving production time, and increasing production capacity. On this basis, the fourth pyramid structure 108 in the groove region 105 and the second pyramid structure 107 in the second region 102 on the side of the cell can jointly improve the light trapping effect of the solar cell.

[0064] In some embodiments, the second region 102 is recessed relative to the third region 103 into the silicon substrate 10, and a third distance D3 of the recess is in a range of 0.1 μm to 5 μm. The second region 102 is recessed relatively shallowly relative to the third region 103 into the silicon substrate 10. This allows for a relatively shallow recess depth, combined with the front and back recess depths of the solar cell, to ensure electrical isolation while maintaining mechanical strength.

[0065] In some embodiments, the third pyramid structure of the third region 103 is recessed into the silicon substrate 10. The top of the third pyramid structure resembles an inverted quadrangular pyramid structure and is recessed into the silicon substrate 10 with a depth of 0.1 μm to 4 μm. The third pyramid structure is an inverted quadrangular pyramid structure that enables multiple reflections of light within the third pyramid structure, increasing the optical path and reducing the reflectivity of the third region 103 to sunlight, reducing the reflectivity of the third region 103 to 20%. This allows more light to be absorbed by the solar cell, thereby improving the photovoltaic conversion efficiency of the solar cell.

[0066] In some embodiments, the first pyramid structure 106 of the first region 101 is recessed into the silicon substrate 10. The top of the first pyramid structure 106 is similar to an inverted quadrangular pyramid structure and is recessed into the silicon substrate 10 with a depth of 0.1 μm to 4 μm. The inverted quadrangular pyramid structure of the first pyramid structure 106 can cause light to reflect multiple times within the first pyramid structure 106, increasing the optical path and reducing the reflectivity of the first region 101 to sunlight, reducing the reflectivity of the first region 101 to 2% to 20%. This allows more light to be absorbed by the solar cell, thereby improving the photovoltaic conversion efficiency of the solar cell.

[0067] In some embodiments, the passivation layer 13 includes a first passivation layer, and the thickness of the first passivation layer located on the first region 101 is greater than the thickness of the first passivation layer located on the second region 102. In actual operation, for the first passivation layer prepared using processes such as atomic layer vapor deposition, physical vapor deposition, and electron evaporation, for example, the first passivation layer can be one or more of aluminum oxide, silicon oxide, and zinc oxide. When the first passivation layer is deposited, it is simultaneously deposited on the first surface, the second surface, and the side surface of the silicon substrate 10. Because the second region 102 is recessed into the silicon substrate 10 relative to the first region 101, the coating material of the first passivation layer is relatively easy to deposit at the protruding positions due to the presence of the recessed structure. At the recessed positions, the amount of coating material entering the recessed positions is reduced due to factors such as obstruction by the protruding positions, resulting in the coating thickness at the recessed positions being less than that at the non-recessed positions. That is, the thickness of the first passivation layer located on the first region 101 is greater than the thickness of the first passivation layer located on the second region 102.

[0068] When using the above technical solution, the first region 101 is closer to the edge of the solar cell than the second region 102. The edge of the solar cell has relatively more defects, which affect the overall passivation effect of the solar cell. Therefore, the thickness of the first passivation layer located on the first region 101 is greater than the thickness of the first passivation layer located on the second region 102, which can enhance the passivation effect on the edge of the solar cell. In addition, due to the height difference between the first region 101 and the second region 102, it is more difficult to deposit a thicker first passivation layer on the second region 102 than on the first region 101. This thickness setting, while meeting performance requirements, eliminates the need for control measures to maintain a consistent first passivation layer thickness in the two regions, further simplifying the process.

[0069] For example, the thickness of the first passivation layer can be 2nm to 20nm, specifically 2nm, 5nm, 8nm, 10nm, 12nm, 15nm, 18nm, 20nm, etc. The difference between the thickness of the first passivation layer located on the first area 101 and the thickness of the first passivation layer located on the second area 102 is less than or equal to 2nm. Specifically, the thickness difference can be 0.1nm, 0.3nm, 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.7nm, 2nm, etc. When the difference is greater than 2nm, the thickness difference is too large, the thickness uniformity of the first passivation layer on the side is poor, the degree of carrier recombination is different, the current density of the solar cell is easily affected, and the on-state voltage circuit of the solar cell is reduced. Therefore, considering the increase in edge passivation effect and the comprehensive performance of the solar cell, the thickness difference is less than or equal to 2nm.

[0070] In some embodiments, the thickness of the passivation layer 13 located on the trench region 105 is less than the thickness of the passivation layer 13 located on the doped region 104. Due to the difference in surface roughness and surface height between the two regions, it is more difficult to deposit a thicker passivation layer 13 in the trench region 105 than in the doped region 104. This thickness setting, while meeting performance requirements, eliminates the need for control measures to maintain a consistent thickness of the passivation layer 13 in the two regions, thereby simplifying the process.

[0071] like Figure 1 and Figure 4As shown, in other embodiments, the passivation layer 13 includes a second passivation layer and a third passivation layer, the second passivation layer is arranged on the first surface and / or the second surface, and the third passivation layer is arranged on the side surface; wherein the thickness of the third passivation layer is greater than the thickness of the second passivation layer. The materials of the second passivation layer and the third passivation layer can be materials such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride and silicon carbide. For example, the second passivation layer and the third passivation layer can be a silicon nitride layer 132, or a stack of an aluminum oxide layer 131 and a silicon nitride layer 132. It is understandable that the second passivation layer and the third passivation layer can be the same material or different materials, and the same or different materials can be selected according to the passivation requirements; the second passivation layer and the third passivation layer can be formed in different process steps or in the same process step. When formed in the same process step, the process can be simplified.

[0072] In some embodiments, a second passivation layer is provided on the side of the first passivation layer on the first and second surfaces facing away from the silicon substrate 10. The second passivation layer can reduce the reflection of light from the first and second surfaces, enhance the light absorption capacity, and improve the conversion efficiency of the solar cell. For example, the thickness of the second passivation layer on the first surface is 65nm~95nm, specifically 65nm, 68nm, 70nm, 72nm, 74nm, 76nm, 78nm, 80nm, 82nm, 85nm, 87nm, 89nm, 92nm, 95nm, etc., and / or the thickness of the second passivation layer on the second surface is 70nm~100nm, specifically 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc.

[0073] In the above technical solution, the third passivation layer covers the side of the battery. Due to its low conductivity, it can provide partial electrical isolation. In addition, due to the complexity of the side surface morphology, a better passivation effect is required. Therefore, the third passivation layer provided on the side is thicker than the second passivation layer provided on the first and / or second surfaces to further enhance the electrical isolation effect, while also strengthening the passivation effect on the side and reducing recombination.

[0074] For example, the difference between the thickness of the third passivation layer and the thickness of the second passivation layer is greater than or equal to 20 nm. Specific thickness differences can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, and so on. Because the side surface has the first region 101, the second region 102, and the third region 103, and has a height difference, the surface topography is relatively complex, requiring a thicker passivation layer to passivate the side surface of the cell. Therefore, to enhance the side passivation effect and overall battery performance, the difference in thickness between the third passivation layer and the second passivation layer is greater than or equal to 20 nm.

[0075] In some embodiments, the passivation layer 13 includes a second passivation layer, which is arranged on the first surface and / or the second surface; the second passivation layer located on the second surface is arranged on the surface of the doped region 104 and the groove region 105, and the second passivation layer located in the doped region 104 is arranged on the side of the second doped semiconductor layer 12 away from the silicon substrate 10; the thickness of the second passivation layer located in the groove region 105 is different from the thickness of the second passivation layer located in the doped region 104.

[0076] The thickness of the second passivation layer is different in different areas of the second surface, which can flexibly adjust the battery film structure to match the improvement requirements of different parameters of the battery, such as open circuit voltage, fill factor or short circuit current, etc. For example, when the doped region 104 and the groove region 105 are set on the second surface of the solar cell, while reducing the parasitic absorption problem caused by the second doped semiconductor layer 12, the requirements for passivation performance will be correspondingly improved. At this time, the thickness of the second passivation layer in the groove region 105 is set to be greater than the thickness of the second passivation layer in the doped region 104, which can better meet the passivation requirements for the surface of the silicon substrate 10 in the groove region 105 and improve the open circuit voltage of the solar cell; or when the solar cell needs to improve the contact performance by increasing the burn-through performance of the electrode to the second doped semiconductor layer 12, it is necessary to set a thicker second passivation layer on the surface of the doped region 104 to protect the non-electrode area on the doped region 104, so as to balance the requirements of contact performance and passivation performance. However, blindly increasing the thickness of all the second passivation layers on the second surface will reduce the uniformity of the second passivation layer, resulting in different degrees of carrier recombination, and the current density of the solar cell will be easily affected. At this time, the thickness of the second passivation layer in the doped area 104 is set to be greater than the thickness of the second passivation layer in the groove area 105, taking into account the balance between factors such as the contact performance, passivation performance and current density of the solar cell, and ultimately improving the battery efficiency.

[0077] like Figure 1 and Figure 5As shown, in some embodiments, the length of the second region 102 in the thickness direction of the solar cell accounts for 50% to 95% of the thickness of the solar cell, specifically 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, etc. If the length of the second region 102 accounts for less than 50%, the length of the second region 102 is too small, the separation distance between the first doped semiconductor layer 14 and the second doped semiconductor layer 12 on the side is too small, there is a risk of leakage, and the side light trapping effect cannot be satisfied. If the length of the second region 102 accounts for more than 95%, the length is too large, resulting in a small proportion of the first region 101, which is not conducive to increasing the junction area on the side adjacent to the first surface, and increases damage to the first surface during the wet process, reducing the yield rate of the battery production. Therefore, considering factors such as reducing the risk of leakage and battery production yield, the length of the second region 102 is selected to be 50% to 95%.

[0078] like Figure 5 As shown, in some embodiments, the boundary portion of the first region 101 and / or the third region 103 near the second region 102 is distributed in an island shape, that is, it presents a structure intermittently arranged with the main area of the first region 101 or the third region 103, and the intermittent portion extends into the second region 102. In this case, the length of the second region 102 refers to the length along the thickness direction of the silicon substrate 10 from the position where the second region 102 intersects with the main area of the first region 101 to the position where the second region 102 intersects with the main area of the third region 103. In actual applications, the boundary line between the first region 101 and the second region 102 is a wavy line, and the boundary line between the third region 103 and the second region 102 is also a wavy line. That is, the boundary line is not a regular straight line, but an irregular zigzag line. In this way, the specific surface area of the side surface can be increased, the light trapping effect can be enhanced, and the utilization rate of light by the side surface can be improved.

[0079] It should be noted that due to uncontrollable factors in the wet process, the first region or the third region may not exist on some edges of the side of the solar cell.

[0080] In some embodiments, the doped region 104 has a third texture structure, which exhibits a non-pyramid microstructure morphology and includes two or more first substructures that are at least partially stacked, and the bottom surface of the first substructure is a polygonal plane; wherein the one-dimensional size of the bottom surface of the first substructure is greater than the one-dimensional size of the bottom surface of the fourth pyramid structure 108 or the second texture structure of the trench region 105.

[0081] In some embodiments, by providing texture structures of different morphologies in the doping region 104 and the groove region 105, the texture structure formed in the groove region 105 and the non-pyramid texture structure formed in the doping region 104 can enable the formed battery to have light trapping structures at different levels, thereby increasing the effective contact area of light. Moreover, for the third texture structure formed in the doping region 104, the one-dimensional size of the bottom surface of the first substructure is larger than the one-dimensional size of the bottom surface of the texture structure in the groove region 105, which is beneficial to improving the uniformity of the second doped semiconductor layer 12, and further suppressing the high local doping concentration of the second doped semiconductor layer 12, thereby reducing the contact resistivity, improving the open circuit voltage of the solar cell, and improving the fill factor and photoelectric conversion efficiency.

[0082] It should be noted that the second texture structure and the third texture structure present a non-pyramid-shaped microstructure morphology, similar to the first texture structure 109, the bottom surface of the second texture structure, the third texture structure or the first substructure is a polygonal plane, and the shape of the polygonal plane includes at least one of a rectangle, a rhombus, a square, a trapezoid, an approximate rectangle, an approximate rhombus, an approximate square, and an approximate trapezoid. The second texture structure and the third texture structure include a tower base structure and / or a polishing structure, the average roughness of which is less than the average roughness of the pyramid structure, and the reflectivity is greater than the reflectivity of the pyramid structure. It can be understood that in the actual manufacturing process, the bottom surface morphology of the tower base structure presents an irregular polygonal plane, but generally presents morphological features similar to a rhombus, square, and trapezoid. As Figures 8-10 As shown, the one-dimensional size of the bottom surface or the pyramid bottom surface of the outermost first substructure of the first texture structure, the second texture structure and the third texture structure can specifically be the length, width, diagonal length, diameter of the circle or the distance between the two farthest end points of the surface or the bottom surface, etc., which is not limited here.

[0083] In some embodiments, the one-dimensional size of the bottom surface of the first substructure may be the average of the one-dimensional sizes of the bottom surfaces of multiple outermost first substructures within a predetermined range of the second surface. The average one-dimensional size of the bottom surface of the outermost first substructures may be 4 μm to 14 μm, and more specifically, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, etc. The average one-dimensional size of the bottom surfaces of the pyramid structure 110, the first pyramid structure 106, the second pyramid structure 107, the third pyramid structure and the fourth pyramid structure 108 can be 0.5μm to 6μm, specifically 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, etc.; the height of the pyramid structure is 0.5μm to 5μm, specifically 0.5μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.3μm, 2.5μm, 2.8μm, 3μm, 3.2μm, 3.4μm, 3.7μm, 4μm, 4.3μm, 4.6μm, 4.8μm, 5μm, etc. When the height of the pyramid structure is within 5 μm, the pyramid structure has the characteristics of low reflection, low recombination, and easy filling, which improves the photoelectric conversion efficiency of the battery.

[0084] In some instances, when measuring texture dimension features that characterize solar cells, such as the one-dimensional size of the bottom surface of the first pyramid structure 106, the film surface can be directly measured and calibrated using a testing instrument (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.). In one case, since the film thickness is at the nanometer level, the film measurement data corresponding to the first pyramid structure 106 can be directly used to obtain the film thickness. The film measurement data is the sum of the film thickness and the texture dimension. In another case, the film thickness data can also be subtracted from the aforementioned film measurement data to obtain the film thickness data. The above measurement methods are merely examples and are not limited in this application.

[0085] In some embodiments, the size of the pyramid structure 110 on the first surface is larger than the size of the second pyramid structure 107 in the second region 102, or the size of the pyramid structure 110 on the first surface is larger than the size of the fourth pyramid structure 108 in the groove region 105. The size of the pyramid structure 110, the second pyramid structure 107, and the fourth pyramid structure 108 on the first surface includes the one-dimensional size and height of the base surface, and can refer to the average value of the one-dimensional size of the base surface of multiple pyramid structures 110, the second pyramid structure 107, or the fourth pyramid structure 108 within a preset range of the area where each pyramid structure is located. Using the above technical solution, when the first surface is the light-receiving surface, the velvet structure of the light-receiving surface of the solar cell can better meet the characteristics of low reflection, low recombination, and easy filling.

[0086] In some embodiments, the dimensional consistency of the pyramid structure 110 located on the first surface is superior to the dimensional consistency of the second pyramid structure 107 located in the second area 102. The dimensions of a pyramid structure include a one-dimensional dimension of the base and a height. Dimensional consistency refers to the consistency of the one-dimensional dimension of the base and / or the height of the pyramid structure. Dimensional consistency is the difference between the dimensions of the pyramid structure within a certain area and the average value of the dimensions of the pyramid structures within that area. For example, statistics can be taken on the one-dimensional dimensions of the base of the pyramid structure 110 and the one-dimensional dimensions of the base of the second pyramid structure 107 within a unit area of the first surface, and the variance or range of the dimensions of the pyramid structures 110 and the variance or range of the dimensions of the second pyramid structures 107 can be calculated. Using the variance or range of the pyramid structures 110 and the second pyramid structures 107 as a reference for consistency, the variances or ranges of different pyramid structures can be compared to determine the consistency of the pyramid structures.

[0087] When the above technical solution is adopted, by controlling the size consistency of the pyramid structures on the light-receiving surface and the side of the silicon substrate 10 within a certain range, the consistency of the pyramid structure 110 on the first surface, i.e., the light-receiving surface, is better controlled on the same solar cell. This can improve the light-trapping effect of the pyramid structure 110 on the light-receiving surface, and is conducive to improving the uniformity of the passivation layer formed on the pyramid structure 110. The performance of the formed passivation layer is better, and the open-circuit voltage of the solar cell is improved. The size consistency requirements of the second pyramid structure 107 in the second area 102 on the side are low. While improving the overall light-trapping effect of the solar cell, it can reduce the degree of etching of other areas of the solar cell when preparing the second pyramid structure 107, thereby reducing the difficulty of the preparation process. In other words, setting pyramid structures with different positions having the above-mentioned size consistency differences can take into account both the effects of improving the performance of the solar cell and reducing the difficulty of the preparation process.

[0088] In some embodiments, when the trench region 105 includes the fourth pyramid structure 108 , the size consistency of the pyramid structures 110 located on the first side is better than the size consistency of the fourth pyramid structure 108 in the trench region 105 .

[0089] By controlling the size consistency of the pyramid structures on the light-receiving and backlight surfaces of the silicon substrate 10 within a certain range, on the same solar cell, the consistency of the pyramid structure 110 on the first surface, i.e., the light-receiving surface, is better controlled, which can improve the light-trapping effect of the pyramid structure 110 on the light-receiving surface, and is conducive to improving the uniformity of the passivation layer 13 formed on the pyramid structure 110, so that the performance of the formed passivation layer 13 is better, thereby improving the open-circuit voltage of the solar cell. The second surface, i.e., the fourth pyramid structure 108 on the backlight surface has low size consistency requirements, which can improve the overall light-trapping effect of the solar cell while reducing the degree of etching of other areas of the solar cell when preparing the fourth pyramid structure 108 on the back, thereby reducing the difficulty of the preparation process. In other words, setting pyramid structures at different positions with the above-mentioned size consistency differences can take into account both the effects of improving the performance of the solar cell and reducing the difficulty of the preparation process.

[0090] In some possible implementations, the difference between the one-dimensional size of the bases of different pyramid structures 110 within a certain region of the first surface and the average one-dimensional size of the bases of the pyramid structures 110 within that region is less than or equal to 1 μm. This improves the dimensional consistency of the pyramid structures 110, enhancing the light trapping effect and the uniformity of the passivation layer.

[0091] In some embodiments, when the trench region 105 includes the fourth pyramid structures 108 , the size consistency of the second pyramid structures 107 located in the second region 102 is comparable to the size consistency of the fourth pyramid structures 108 in the trench region 105 .

[0092] In this way, the second pyramid structure 107 and the fourth pyramid structure 108 in the groove area 105 have similar size consistency. In terms of technology, the texturing steps of the two areas can be carried out in the same process step, which simplifies the process of solar cells and saves production costs.

[0093] like Figure 7As shown, in some embodiments, the ratio of the height of the fourth pyramid structure 108 to the depth of the trench region 105 is 1:1.5 to 1:4, specifically 1:1.5, 1:2, 1:25, 1:3, 1:35, 1:4, etc. The depth of the trench region 105 is the height difference between the bottom of the trench region 105 and the surface of the doped region 104. The top of the fourth pyramid structure 108 in the trench region 105 is located within the recessed trench region 105 and does not extend beyond the top surface of the recess, that is, does not extend beyond the surface of the doped region 104. In other words, the trench region 105 on the second surface of the silicon substrate 10 is etched downward to a depth greater than the height of the fourth pyramid structure 108. The depth of the trench region 105 can be 1 μm to 10 μm, specifically 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc. In this way, it can ensure that the suede surface has good light trapping and passivation effects, while taking into account the requirements of the corrosion depth on the process difficulty, preparation efficiency and mechanical strength of the silicon substrate.

[0094] like Figure 7 As shown, in some embodiments, the ratio of the inclination angle β of the fourth pyramid structure 108 to the inclination angle α of the sidewall of the trench region 105 is 1:0.5 to 1:2. The inclination angle β of the fourth pyramid structure 108 refers to the inclination angle of the side surface connecting the bottom and top of the fourth pyramid structure 108 relative to the bottom of the pyramid, and the inclination angle α of the sidewall of the trench region 105 refers to the inclination angle of the sidewall of the trench region 105 relative to the bottom plane of the trench region 105 (i.e., the second surface). The inclination angle α of the sidewall of the trench region 105 relative to the second surface is 35° to 65°, and can specifically be 35°, 40°, 45°, 50°, 55°, 60°, 65°, etc. The inclination angle of the fourth pyramid structure 108 is slightly smaller than the inclination angle of the sidewall of the trench area 105, which is conducive to forming a uniform passivation layer 13 on the fourth pyramid structure 108 in the trench area 105, avoiding the sidewall of the trench area 105 from blocking the formation of the passivation layer 13, and increasing the specific surface area of the trench area 105, which is conducive to enhancing the light trapping effect.

[0095] like Figure 1 and Figure 4As shown, in some possible implementations, a tunneling oxide layer 11 is further provided on one side of the second surface. The tunneling oxide layer 11 is located between the silicon substrate 10 and the side of the second doped semiconductor layer 12 close to the silicon substrate 10. In this case, the second doped semiconductor layer 12 can be a doped polysilicon layer. The doped polysilicon layer and the tunneling oxide layer 11 form a tunneling passivation structure contact. The tunneling passivation contact structure partially covers the second surface of the silicon substrate 10, forming a certain pattern, such as a strip pattern arranged at intervals or a cross-shaped pattern with horizontal and vertical intersections. In a solar cell with a tunneling passivation contact structure, the tunneling oxide layer 11 located between the silicon substrate 10 and the second doped semiconductor layer 12 can allow electrons to pass through while blocking hole transmission, thereby achieving efficient charge separation, reducing interface recombination losses, and improving interface passivation effects, thereby improving photoelectric conversion efficiency. In addition, the tunneling oxide layer 11 can prevent metal crystals of the electrode from piercing the second doped semiconductor layer 12 and entering the silicon substrate 10, thereby preventing the passivation on the surface of the solar cell from being destroyed, thereby losing battery efficiency.

[0096] For example, the silicon substrate 10 can be made of N-type or P-type single crystal silicon, polycrystalline silicon, microcrystalline silicon, and the like. The materials of the first doped semiconductor layer 14 and the second doped semiconductor layer 12 can include doped single crystal silicon, doped polycrystalline silicon, doped microcrystalline silicon, doped nanocrystalline silicon, doped amorphous silicon, and the like. The materials and doping types of the silicon substrate and the doped semiconductor layer are reasonably selected according to the type of cell. For example, when the doped semiconductor layer is doped polycrystalline silicon, it can form a tunneling passivation contact structure with the tunneling oxide layer; when the doped semiconductor layer is doped amorphous silicon, it can form a heterojunction contact structure with intrinsic amorphous silicon. The solar cell formed can be a bifacial solar cell having a tunneling passivation contact structure and / or a heterojunction contact structure, which is not specifically limited here.

[0097] like Figure 1 and Figure 4 As shown, based on the solar cell described in any of the above embodiments, an embodiment of the present invention further provides a method for preparing a solar cell, comprising the following steps: In step S100 , a silicon substrate 10 is provided. The silicon substrate 10 has a first surface, a second surface, and a side surface connecting the first surface and the second surface.

[0098] For example, the silicon substrate 10 may be N-type or P-type single crystal silicon, polycrystalline silicon, or microcrystalline silicon. For example, the silicon substrate 10 may be an N-type single crystal silicon wafer.

[0099] Step S200: forming an integral and continuous pyramid structure 110 on the first surface and the side surface. The pyramid structure 110 may be formed during double-sided texturing of the silicon substrate 10, i.e., the pyramid structure 110 is formed on the first surface, the second surface, and the side surface during texturing.

[0100] For example, the silicon wafer is first pre-cleaned to remove impurities on the surface of the silicon wafer. The pre-cleaning solution can be an alkaline solution and hydrogen peroxide, wherein the volume ratio of the alkaline solution to the hydrogen peroxide is 1:1~1:6, the pre-cleaning temperature is 60℃~80℃, and the pre-cleaning time is 1min~4min. Afterwards, the silicon wafer is texturized, and the volume ratio of the alkaline solution to the texturizing additive required for texturizing is 2:1~8:1, the texturizing temperature is 60℃~85℃, and the texturizing time is 4min~8min. The one-dimensional size of the bottom surface of the obtained pyramid structure 110 is 1μm~6μm, the height of the pyramid structure 110 is 1μm~5μm, and the specific surface area of the pyramid structure 110 is 1~3.

[0101] In step S300 , a first doped semiconductor layer 14 and a first glass semiconductor layer are formed on the first surface, the first doped semiconductor layer 14 being located on a surface facing away from the silicon substrate 10 , and the first doped semiconductor layer 14 and the first glass semiconductor layer are formed on the side surface and a portion of the second surface.

[0102] For example, boron diffusion deposition is performed on the first surface to form a doped borosilicate layer (the first doped semiconductor layer), while a borosilicate glass layer (the first glass semiconductor layer) is grown on the surface of the doped borosilicate layer. Due to the presence of wrap-around plating, wrap-around plating occurs on the side surfaces of the silicon substrate and portions of the second surface to form doped borosilicate and borosilicate glass wrap-around layers. When boron is deposited on the first surface, the doping depth can be 300nm to 1000nm, the doping surface concentration can be 2E18 to 5E19, the thickness of the borosilicate glass layer (BSG) can be 40nm to 120nm, and the doping source can be BCl3. Of course, the first doped semiconductor layer can also be a doped phosphosilicate layer, and the first glass semiconductor layer can be a phosphosilicate glass layer.

[0103] In step S400, the first glass semiconductor layer and the first doped semiconductor layer are removed from the second surface and the side surface adjacent to the second surface, and the pyramid structure is removed from a portion of the side surface, so that the area on the side surface from which the pyramid structure is not removed and adjacent to the first surface becomes the first area 101, and the pyramid structure located within the first area 101 becomes the first pyramid structure 106.

[0104] For example, the borosilicate glass layer and the doped borosilicate layer coated on the second surface and the side surface adjacent to the second surface in step S300 are first removed. This step can be performed by a chain single-sided pickling device to remove the borosilicate glass layer on the second surface, using an HF aqueous solution at room temperature, with a ratio of HF to water of 1:0.3 to 1:3. Specifically, the second surface is placed on the chain single-sided pickling device with the first surface facing up, and only the second surface and the side surface adjacent to the second surface are removed to ensure that the borosilicate glass layer on the second surface is completely removed, while the doped borosilicate layer and the borosilicate glass layer on the first surface are not affected. Thereafter, an alkaline solution and / or hydrogen peroxide pre-cleaning is performed, wherein the volume ratio of the alkaline solution to hydrogen peroxide is 1:1 to 1:10, the pre-cleaning temperature is 60°C to 80°C, and the pre-cleaning time is 1 min to 5 min. Finally, the second surface and the side surface adjacent to the second surface are subjected to alkali polishing. The volume ratio of the alkali solution to the polishing additive in the alkali polishing solution can be 3:1 to 10:1. The alkali polishing temperature can be 60°C to 85°C, and the alkali polishing time is 3 to 8 minutes. After alkali polishing, the pyramid structures on the second surface are polished to obtain the third texture structure on the second surface. The pyramid structures on a portion of the side surface are partially polished to form a polished surface, leaving only the first pyramid structure 106 adjacent to the first surface, forming the first region 101. The remaining region, excluding the first region 101, is recessed into the silicon substrate 10 relative to the first region 101.

[0105] In step S500 , a second doped semiconductor layer 12 and a second glass semiconductor layer are formed on the second surface, and a second doped semiconductor layer and a second glass semiconductor layer are formed on the side surface and at least a portion of the first surface.

[0106] For example, a tunneling oxide layer 11 is grown on the second side of the alkali-polished silicon wafer, followed by a doped phosphosilicate layer (the second doped semiconductor layer). Simultaneously, a phosphosilicate glass layer (the second glass semiconductor layer) is grown on the surface of the doped phosphosilicate layer. This effectively separates minority carriers from majority carriers, enhancing passivation and reducing corrosion to the silicon substrate during printing, improving contact performance. The thickness of the doped phosphosilicate layer can range from 80 nm to 250 nm. At this point, the first side and side surfaces are coated with the doped phosphosilicate layer and the phosphosilicate glass layer.

[0107] In step S600, the second doped semiconductor layer and the second glass semiconductor layer are removed from the first area 101 of the side surface and the remaining area of the side surface, and a second pyramid structure 107 is formed in the area outside the first area 101 of the side surface to obtain the second area 102, and a third pyramid structure and / or a first texture structure 109 is formed in the area adjacent to the second surface outside the first area 101 and the second area 102 of the side surface to obtain the third area 103. Figure 6The first texture structure 109 is shown, wherein the second region 102 is recessed into the silicon substrate 10 relative to the first region 101 , and a first recessed distance D1 is 2 μm-10 μm.

[0108] For example, first remove the phosphorus silicon glass layer and the doped phosphorus silicon layer coated on the first surface and the side surface in step S500. This step can be removed by a chain single-sided cleaning device, wherein a chain pickling is performed at room temperature using an HF aqueous solution, and the ratio of HF to water is 1:3 to 1:15. Then, a part of the side surface is etched and textured, and the tower base structure on the original side surface is further etched, and the one-dimensional size of the tower base structure becomes larger, thereby obtaining a first texture structure 109, as shown in FIG. Figure 6 As shown, a part of the side area is textured to obtain a third pyramid structure, and a third area 103 is obtained which is a mixture of the first texture structure 109 and the third pyramid structure. Except for the first area 101 and the third area 103, the remaining areas are textured to form a second pyramid structure 107, forming a second area 102 that is recessed into the silicon substrate 10 relative to the first area 101, and the first distance D1 of the recess is 2μm~10μm. And the third distance D3 of the second area 102 recessed into the silicon substrate 10 relative to the third area 103 is 0.1μm~5μm. Among them, the volume ratio of the alkaline solution used for texturing to the texturing additive is 2:1~8:1, the alkaline texturing temperature is 60℃~85℃, and the texturing time is 3min~8min.

[0109] Step S700 : forming a passivation layer 13 on the first surface, the second surface, and the side surfaces.

[0110] For example, atomic layer deposition (ALD) technology is used to simultaneously grow an aluminum oxide layer 131 on the first, second, and side surfaces of a silicon wafer. The thickness of the aluminum oxide layer 131 can range from 2nm to 20nm. If it's too thick, it may cause film cracking, while if it's too thin, it won't effectively passivate the silicon substrate surface or the film surface of the solar cell. Then, a silicon nitride layer 132 is deposited on the front and back sides of the silicon wafer using plasma-enhanced chemical vapor deposition (PECVD) equipment to passivate the wafer surface, reduce surface recombination, and improve the open-circuit voltage and fill factor. The silicon nitride layer 132 also protects the wafer, reducing contamination and mechanical damage. The front side silicon nitride layer 132 can be 65nm to 85nm thick, with a refractive index of 1.7 to 2.2. The back side silicon nitride layer 132 can be 70nm to 100nm thick, with a refractive index of 2 to 2.4.

[0111] In step S800, a metallization structure is formed on the passivated silicon wafer by screen printing or electroplating, i.e., a first electrode 16 and a second electrode 15 are formed. The metal paste can be a silver alloy, a silver-copper alloy, a copper alloy, a nickel alloy, etc. The paste is solidified by a low-temperature sintering process, and the hydrogen passivation effect is enhanced by light injection. Finally, a good ohmic contact is formed using laser-assisted sintering contact technology (LECO), completing the production of the solar cell.

[0112] When the above technical solution is adopted, the solar cell described in the first aspect can be obtained by the solar cell preparation method. Therefore, it has the same beneficial effects as the solar cell described in any of the above embodiments, which will not be repeated.

[0113] In some embodiments, after forming the second doped semiconductor layer 12 and the second glass semiconductor layer on the side of the second doped semiconductor layer 12 facing away from the silicon substrate 10 in step S500, and before removing the second doped semiconductor layer and the second glass semiconductor layer on the first area 101 of the side surface and the remaining area of the side surface in step S600, the preparation method further includes the following steps: Step S501 : irradiating a portion of the second surface with laser light onto the second glass semiconductor layer.

[0114] For example, when a phosphosilicate glass layer is formed on the second surface, the phosphosilicate glass layer on the second surface is subjected to laser patterning. The laser-irradiated area is a non-metallized area for the subsequent formation of the groove area 105. Through high-energy laser irradiation, the laser acts on the phosphosilicate glass layer in a short period of time, causing the phosphosilicate glass to be modified, loosened, or vaporized, reducing the protective ability of the phosphosilicate glass layer in the laser-irradiated area. This ensures that during the subsequent alkaline corrosion process, a reaction rate gradient is formed between the laser-irradiated area and the non-laser-irradiated area. The laser-irradiated area can be corroded as required, while the non-laser-irradiated area is protected by the phosphosilicate glass layer and is not affected. The laser wavelength can be 300nm~600nm, and the laser film opening width can be 250μm~800μm.

[0115] Then, step S600 further includes removing the second glass semiconductor layer and the second doped semiconductor layer in the area irradiated by the laser on the second surface to obtain the trench area 105 , and forming a texture structure in the trench area 105 , the texture structure including the fourth pyramid structure 108 or the second texture structure.

[0116] For example, while removing the doped phosphosilicate layer and the phosphosilicate glass layer on the first area 101 of the side and the remaining areas of the side, and forming the second pyramid structure 107 in the partial area outside the first area 101 of the side, the second surface is etched. The doped phosphosilicate layer in the non-laser irradiated area of the second surface is not corroded due to the protection of the phosphosilicate glass layer, thereby forming a doped area 104. The laser irradiated area on the second surface is destroyed due to the destruction of the phosphosilicate glass layer, and the doped phosphosilicate layer corresponding thereto below is corroded by alkali, and the tunnel oxide layer 11 and the silicon substrate 10 are further corroded downward to form a trench area 105, which is then textured and etched to obtain a fourth pyramid structure 108 or a second texture structure of the trench area 105.

[0117] When the above technical solution is adopted, the second doped semiconductor layer is not provided in the groove area 105, thereby reducing the parasitic absorption caused by the second doped semiconductor layer. The depth of the downward depression can ensure that the inner expansion layer below the groove area 105 is removed, thereby reducing the recombination problem caused by the higher doping concentration in the non-power generation area. The fourth pyramid structure 108 is further provided in the groove area 105 to further increase the light trapping effect of the second side of the bifacial battery, increase the bifaciality of the overall battery, and comprehensively improve the battery performance.

[0118] Based on the solar cells described in any of the above embodiments, embodiments of the present invention further provide a photovoltaic module comprising a cell string, an interconnect, and an encapsulation layer, wherein the cell string is formed by electrically connecting a plurality of solar cells as described in any of the above embodiments; the interconnect is electrically connected to the solar cells; and the encapsulation layer covers the surface of the cell string. The encapsulation layer may include a cover plate and a back plate located on both sides of the cell string, as well as an encapsulation film and other structures for encapsulation. Because this photovoltaic module utilizes the solar cells described in any of the above embodiments, it has the same beneficial effects as any of the above embodiments.

[0119] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0120] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer; The silicon substrate has a first surface, a second surface and a side surface connecting the first surface and the second surface; The first surface has a plurality of pyramid structures, and the side surface includes a first area, a second area, and a third area sequentially distributed along a direction from the first surface to the second surface; the first area is adjacent to the first surface, the third area is adjacent to the second surface, and the second area is located between the first area and the third area; The second region is recessed into the silicon substrate relative to the first region, and a first recessed distance is 2 μm to 10 μm; The first area has a plurality of first pyramid structures, the second area has a plurality of second pyramid structures, and the third area has a plurality of third pyramid structures and / or a plurality of first texture structures; The first doped semiconductor layer is disposed on the first surface; The second doped semiconductor layer is disposed on the second surface, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; The passivation layer is disposed on the first surface, the second surface and the side surface. The passivation layer is located on a surface of the first doped semiconductor layer and the second doped semiconductor layer that is away from the silicon substrate.

2. The solar cell according to claim 1, wherein The second surface includes alternately arranged groove regions and doped regions, the groove regions are recessed into the silicon substrate relative to the doped regions, the second doped semiconductor layer is located in the doped regions, and the passivation layer is located in the groove regions and the doped regions; The trench region is recessed into the silicon substrate relative to the doped region, and the recessed distance is a second distance; wherein the first distance is greater than or equal to the second distance.

3. The solar cell according to claim 1, wherein The second surface includes alternately arranged groove regions and doped regions, the groove regions are recessed into the silicon substrate relative to the doped regions, and the groove regions include a fourth pyramid structure or a second texture structure; The second doped semiconductor layer is located in the doping region, and the passivation layer is located in the trench region and the doping region.

4. The solar cell according to claim 2, wherein The second distance is 0.5 μm to 9 μm.

5. The solar cell according to claim 1, wherein The second region is recessed relative to the third region into the silicon substrate. The recessed distance is a third distance, and the third distance is 0.1 μm to 5 μm.

6. The solar cell according to claim 1, wherein The top of the third pyramid structure is recessed in the silicon substrate.

7. The solar cell according to claim 1, wherein The passivation layer includes a first passivation layer, and a thickness of the first passivation layer located on the first region is greater than a thickness of the first passivation layer located on the second region.

8. The solar cell according to claim 7, characterized in that A difference between a thickness of the first passivation layer located on the first region and a thickness of the first passivation layer located on the second region is less than or equal to 2 nm.

9. The solar cell according to claim 2 or 3, characterized in that The thickness of the passivation layer located on the trench region is smaller than the thickness of the passivation layer located on the doping region.

10. The solar cell according to claim 1, wherein The passivation layer includes a second passivation layer and a third passivation layer, the second passivation layer is arranged on the first surface and / or the second surface, and the third passivation layer is arranged on the side surface; Wherein, the thickness of the third passivation layer is greater than the thickness of the second passivation layer.

11. The solar cell according to claim 10, characterized in that The difference between the thickness of the third passivation layer and the thickness of the second passivation layer is greater than or equal to 20 nm.

12. The solar cell according to claim 1, wherein The passivation layer includes a second passivation layer, and the second passivation layer is arranged on the first surface and / or the second surface; The second passivation layer located on the second surface is disposed on surfaces of the doped region and the trench region, and the second passivation layer located in the doped region is disposed on a side of the second doped semiconductor layer away from the silicon substrate; The thickness of the second passivation layer located in the trench region is different from the thickness of the second passivation layer located in the doping region.

13. The solar cell according to claim 1, wherein In the thickness direction of the solar cell, the length of the second region accounts for 50% to 95% of the thickness of the solar cell.

14. The solar cell according to claim 3, characterized in that The doped region has a third texture structure, the third texture structure presents a non-pyramid microstructure morphology, and includes two or more first substructures at least partially stacked, wherein the bottom surface of the first substructure is a polygonal plane; The one-dimensional size of the bottom surface of the first substructure is larger than the one-dimensional size of the bottom surface of the texture structure in the groove area.

15. The solar cell according to claim 1, wherein The size consistency of the pyramid structures located on the first surface is better than the size consistency of the second pyramid structures located in the second area.

16. The solar cell according to claim 3, characterized in that When the trench region includes the fourth pyramid structure, the size consistency of the pyramid structure located on the first surface is better than the size consistency of the fourth pyramid structure located in the trench region.

17. The solar cell according to claim 3, characterized in that When the trench region includes the fourth pyramid structure, the size consistency of the second pyramid structure located in the second region is comparable to the size consistency of the fourth pyramid structure located in the trench region.

18. A photovoltaic module, characterized in that: include: A battery string, wherein the battery string is formed by electrically connecting a plurality of solar cells according to any one of claims 1 to 17; an interconnection member, electrically connected to the solar cell; and an encapsulation layer covering the surface of the battery string.

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