Laminated cell and preparation method thereof

Abstract

The invention relates to the field of solar cells, in particular to a laminated cell and a preparation method thereof. Only the N suede surface of the bottom cell of the laminated cell is of a smooth pyramid structure; the preparation method comprises the following steps: preparing a pyramid structure, performing alkali texturing on the pyramid structure, performing single-side rinsing on the pyramid structure subjected to alkali texturing by using an HNO3 / HF / H2O mixed solution to reduce the height of the pyramid structure, performing cleaning and smoothing on the reduced pyramid structure by using a DIO3 / HF solution, and removing porous silicon and silicate at the same time, thereby obtaining the silicon wafer with the uniform, tiny and smooth pyramid structure. The silicon wafer subjected to the suede smoothing treatment ensures that the subsequent perovskite thin film layer is completely and uniformly deposited on the pyramid suede, and porous silicon and silicate generated in HNO3 / HF / H2O rinsing are removed, so that not only is the passivation effect of the perovskite / crystalline silicon laminated solar cell improved, but also the open voltage and current of the cell are improved, and the performance of the solar cell is improved. And the battery performance is greatly optimized.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a stacked cell and a preparation method thereof. Background Art

[0002] Perovskite / crystalline silicon tandem solar cells, through a spectral segmented absorption mechanism, have achieved a theoretical efficiency limit exceeding 40%, and their laboratory efficiency has rapidly increased to 33%, becoming a key technical direction for breaking the efficiency limit of single-junction cells. However, their performance improvement is limited by the interface compatibility between the crystalline silicon bottom cell and the perovskite top cell. While the micron-scale pyramidal velvet (1-3μm height, reflectivity <10%) formed by traditional alkaline texturing methods (such as NaOH / KOH etching) can enhance light capture, the sharp pyramid tips (radius of curvature <50nm) and deep valleys lead to uneven coverage of the perovskite film, causing defects such as pinholes and cracks. At the same time, interfacial stress concentration and carrier transport obstruction cause the fill factor (FF) to drop by 5-8%, seriously restricting the efficiency improvement of the tandem cell.

[0003] To address the perovskite layer coverage issue, existing technologies use acid etching (such as immersion in HNO3 / HF / H2O solution) to perform a secondary treatment on the textured surface, reducing the pyramid height by 30-50% (to 0.5-1μm) and the roughness (Ra) from 200-300nm to 80-120nm. However, this immersion etching method creates pyramid structures of varying sizes, resulting in sharp pyramids that are not smooth. Furthermore, the porous silicon layer (20-50nm thick, 30-50% porosity) and silicate residues produced after immersion exacerbate phosphorus diffusion heterogeneity and increase the surface recombination rate, resulting in a drop of 8-12mV in the cell's open-circuit voltage (Voc) and a loss of 3-5 percentage points in fill factor, partially offsetting the efficiency gains.

[0004] Therefore, there is an urgent need to develop a perovskite crystalline silicon stacked solar cell that can overcome the above-mentioned defects, ensure the complete and uniform deposition of the subsequent perovskite thin film layer, and improve the battery passivation level, open circuit voltage and current transmission performance. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a laminated battery and a preparation method thereof.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A laminated battery comprising:

[0008] It includes a perovskite top cell and a bottom cell, wherein only the N-side velvet surface of the bottom cell is a smooth pyramid structure.

[0009] Furthermore, the height of the smooth pyramid structure is 0.3 μm-1.0 μm, and the radius of curvature is 100 nm-1000 nm.

[0010] Furthermore, the bottom cell is a silicon heterojunction cell or a TOPCon cell.

[0011] Furthermore, the TOPCon cell includes a semiconductor substrate layer with only the P side textured and the N side textured and then smoothed, a smooth pyramid structure arranged on the N side of the double-sided textured semiconductor substrate layer, a tunneling oxide layer, a phosphorus-doped layer, a passivation layer and an anti-reflection film layer stacked in sequence on the N side of the semiconductor substrate layer; and a boron-doped layer, a passivation film layer and a metal electrode stacked in sequence on the P side of the semiconductor substrate layer.

[0012] Furthermore, the perovskite top cell includes a carrier recombination layer, a hole transport layer, a perovskite layer, an electron transport layer, a transparent conductive layer, an anti-reflection film layer and a metal electrode stacked in sequence from the N side of the bottom cell.

[0013] Furthermore, the carrier recombination layer is a heavily doped tunnel junction or a transparent conductive film;

[0014] Furthermore, the carrier recombination layer has a thickness of 80 nm to 100 nm.

[0015] Furthermore, the hole transport layer is made of any one of PTAA, PEDOT:PSS, and NiOx.

[0016] Furthermore, the thickness of the hole transport layer is 30 nm to 100 nm.

[0017] Furthermore, the thickness of the perovskite layer is 800-1200 nm, and the perovskite material structure is ABX3, wherein A is any one of methylamine, formamidine, and Cs or a mixture of several cations, B is Pb or Sn, and X is any one of Cl, Br, and I or a mixture of three anions.

[0018] Furthermore, the material of the electron transport layer is C60 or PCBM.

[0019] Furthermore, the thickness of the electron transport layer is 15-40 nm.

[0020] Furthermore, the material of the transparent conductive layer is at least one of ITO, IWO, ICO, IZO, and AZO.

[0021] Furthermore, the thickness of the transparent conductive layer is 80-100 nm.

[0022] Furthermore, the metal electrode is Ag or a Ni / Cu / Ag composite electrode.

[0023] The present invention also provides a method for preparing a stacked battery, comprising the following steps:

[0024] (1) Double-sided texturing of single-crystal silicon wafers to form a pyramid textured surface structure;

[0025] (2) Smoothing the pyramid velvet structure on the N side: Using HNO3 / HF / H2O solution to rinse the front side of the single crystal silicon wafer, the mass percentage of HNO3 in the HNO3 / HF / H2O solution is 30wt%-50wt%, the mass percentage of HF is 0.5wt%~5wt%, and the rinsing time is 4s~30s; then using DIO3 / HF solution to clean the front side, the ozone concentration during the cleaning process is 20ppm-60ppm, the HF concentration is 2~10wt%, and the cleaning time is 100~1000s; the single-side rinsing is carried out using a chain machine, and the rollers of the chain machine are divided into three sections, respectively. The first liquid-carrying roller, the second liquid-carrying roller, and the drying roller are sequentially operated above the N-side of the single-crystal silicon wafer. The first liquid-carrying roller carries a HNO3 / HF / H2O mixed solution, which contacts the N-side to rinse the N-side. The first liquid-carrying roller operates at a speed of 1 m / min to 6 m / min. The second liquid-carrying roller carries H2O to clean the N-side after the rounding treatment. While the N-side is being rounded, the P-side of the single-crystal silicon wafer is protected by a water film. The drying roller dries the entire cleaned single-crystal silicon wafer.

[0026] (3) Using the single crystal silicon wafer processed in step (2) as the semiconductor substrate layer, a bottom cell is prepared;

[0027] (4) A perovskite top cell is stacked on the N side of the bottom cell.

[0028] Furthermore, the steps of preparing the bottom cell are: providing a single crystal silicon wafer, sequentially performing texturing, boron diffusion, and removing BSG from the N side; smoothing the N side, depositing a tunneling oxide layer and a polysilicon layer; performing phosphorus diffusion, removing the P side by wrapping, and cleaning with a cleaning solution; depositing a passivation film layer and an anti-reflection layer, and printing electrodes.

[0029] Furthermore, the texturing concentration is 0.5-10 wt % of an alkaline solution for etching, forming a pyramid structure on both sides of the single crystal silicon wafer, and the height of the pyramid structure is 0.7 μm-1.5 μm.

[0030] Furthermore, the alkaline solution is at least one of NaOH or KOH.

[0031] Furthermore, the boron diffusion uses BCl3 as a diffusion source, the diffusion temperature is 800°C-1000°C, and the diffusion square resistance is controlled at 200Ω / □-300Ω / □.

[0032] Furthermore, the N-side BSG removal is performed using an HF solution with a concentration of 5wt% to 20wt%.

[0033] Furthermore, the P-surface removal and wrap-around plating process uses an HF solution with a concentration of 3wt%-10wt%.

[0034] Furthermore, the tunnel oxide layer and the polysilicon layer are deposited using LPCVD technology, and the thickness of the tunnel oxide layer is 1 nm to 3 nm.

[0035] Furthermore, the phosphorus diffusion uses POCl3 as a diffusion source, the diffusion temperature is 800℃-900℃, and the doping concentration is 1~5E20cm -3 .

[0036] Furthermore, the cleaning solution is a mixed solution of HF and H2O2 and a mixed solution of NH3 and H2O2.

[0037] Furthermore, the passivation film is deposited by depositing a layer of AlO on both sides of the silicon wafer using AlD atomic deposition. x The thin film forms a passivation film layer; the deposited anti-reflection film layer is deposited on both sides by PECVD x The film layer forms an anti-reflection film layer.

[0038] Furthermore, the printed electrode is formed by printing AgAl paste or Ni / Cu / Ag paste on the N side of the silicon wafer and sintering it to form a metal electrode.

[0039] Beneficial effects of the present invention:

[0040] The bottom cell of the stacked battery of the present invention has only a smooth pyramid structure on the N side of the velvet surface, which successfully overcomes the problem of film defects caused by the sharp pyramid structure and the bottom of the pyramid when depositing the perovskite film on the N side, and greatly improves the quality and stability of the film.

[0041] By using a single-sided rinsing process with a mixed solution of HNO3 / HF / H2O, differentiated texturing effects on the N and P sides are effectively achieved, which has significant technical advantages. It avoids the disadvantages of the traditional immersion process that causes excessive porous silicon and hydrochloride on the surface of the silicon wafer. These impurities will seriously affect the subsequent diffusion steps of the battery, thereby effectively solving the problem of reduced battery conversion rate.

[0042] In addition, after rinsing on one side, it is then cleaned and smoothed with a DIO3 / HF solution. During the DIO3 / HF solution cleaning process, HF first reacts with the produced silicates to generate fluorosilicic acid and the corresponding hydrochloric acid. Then, as the porous silicon is exposed, the strongly oxidizing O3 oxidizes the porous silicon to form SiOx, and HF cleans the SiOx. During the oxidation and cleaning process, the velvet surface gradually becomes smooth and defects are removed, achieving deep removal of porous silicon and silicates on the surface of the silicon wafer. After this series of process treatments, a uniform and small-sized pyramid structure is formed, providing ideal basic conditions for the subsequent deposition of a complete and uniform perovskite film layer on the pyramid velvet surface. In addition, the effective removal of porous silicon and silicates on the surface of the silicon wafer greatly improves the passivation level, thereby increasing the open circuit voltage, increasing the current, and significantly improving the overall performance and conversion efficiency of the battery.

[0043] The single-side rinsing process achieves precise surface treatment through the coordinated action of three rollers on a chain machine. The first roller delivers a mixed HNO3 / HF / H2O solution at an adjustable speed of 1-6 m / min, applying controlled single-side rounding to the N-side of the silicon wafer, effectively controlling the pyramidal morphology and reducing surface reflectivity. The second roller simultaneously performs a gradient water wash to prevent residual acid corrosion, while the dynamic water film protection technology on the P-side fully preserves the electrical characteristics of the PN junction. The final drying roller achieves contactless rapid drying. This technology utilizes a differentiated N / P-side treatment strategy to effectively reduce the N-side reflectivity while ensuring the integrity of the P-side passivation layer. Furthermore, the coordinated control of roller speed and solution ratio allows for precise control of the rounding process, providing excellent conditions for the subsequent preparation of the perovskite stack and significantly improving the photovoltaic conversion efficiency of the cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is the preparation flow chart of TOPCon bottom cell;

[0045] Figure 2 Schematic diagram of the bottom battery structure with a smooth velvet structure;

[0046] Figure 3 Schematic diagram of the structure of a perovskite / crystalline silicon tandem solar cell with a smooth surface.

[0047] Among them: 1. bottom cell, 2. carrier recombination layer, 3. hole transport layer, 4. perovskite layer,

[0048] 5. Electron transport layer, 6. Transparent conductive layer, 7. Front anti-reflection layer, 8. Front metal electrode, 11. Semiconductor substrate layer, 12. Tunneling oxide layer, 13. Phosphorus-doped layer, 14. Front passivation layer, 15. Front anti-reflection film layer, 16. Boron-doped layer, 17. Rear passivation layer, 18. Rear anti-reflection layer, 19. Rear metal electrode. DETAILED DESCRIPTION

[0049] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0050] Unless otherwise specified, the materials used in the examples of the present invention can be obtained through commercial channels or prepared according to conventional methods well known to those skilled in the art.

[0051] The present invention provides a stacked cell, a perovskite top cell and a bottom cell, wherein only the N-side velvet surface of the bottom cell is a smooth pyramid structure.

[0052] In some preferred embodiments of the present invention, the height of the smooth pyramid structure is 0.3μm-1.0μm, specifically 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 0.9μm, 1.0μm or a range consisting of any two of these values; the radius of curvature is 100nm-1000nm, specifically 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 100nm or a range consisting of any two of these values.

[0053] The invention also provides a method for preparing the above-mentioned laminated battery, comprising the following steps:

[0054] (1) Double-sided texturing of single-crystal silicon wafers to form a pyramid textured surface structure;

[0055] (2) Smoothing the pyramid velvet structure on the N side: Using HNO3 / HF / H2O solution to rinse the front side of the single crystal silicon wafer, the mass percentage of HNO3 in the HNO3 / HF / H2O solution is 30wt%-50wt%, the mass percentage of HF is 0.5wt%~5wt%, and the rinsing time is 4s~30s; then using DIO3 / HF solution to clean the front side, the ozone concentration during the cleaning process is 20ppm-60ppm, the HF concentration is 2~10wt%, and the cleaning time is 100~1000s; the single-side rinsing is carried out using a chain machine, and the rollers of the chain machine are divided into three sections, respectively. The first liquid-carrying roller, the second liquid-carrying roller, and the drying roller are sequentially operated above the N-side of the single-crystal silicon wafer. The first liquid-carrying roller carries a HNO3 / HF / H2O mixed solution, which is brought into contact with the N-side to perform a rounding treatment on the N-side. The first liquid-carrying roller operates at a speed of 1 m / min to 6 m / min. The second liquid-carrying roller carries H2O to clean the N-side after the rounding treatment. While the N-side is being rounded, the P-side of the single-crystal silicon wafer is protected by a water film. The drying roller dries the entire cleaned single-crystal silicon wafer.

[0056] (3) Using the single crystal silicon wafer processed in step (2) as the semiconductor substrate layer, a bottom cell is prepared;

[0057] (4) A perovskite top cell is stacked on the N side of the bottom cell.

[0058] In some embodiments of the present invention, in the HNO3 / HF / H2O solution, the mass percentage of HNO3 is specifically 30 wt%, 32 wt%, 34 wt%, 35 wt%, 36 wt%, 38 wt%, 40 wt%, 42 wt%, 44 wt%, 45 wt%, 46 wt%, 48 wt%, 50 wt% or a range consisting of any two of these values.

[0059] In some embodiments of the present invention, the mass percentage of HF in the HNO3 / HF / H2O solution is specifically 0.5 wt%, 0.8 wt%, 1 wt%, 1.2 wt%, 1.5 wt%, 1.7 wt%, 2 wt%, 2.5 wt%, 2.8 wt%, 3 wt%, 3.3 wt%, 3.5 wt%, 3.8 wt%, 4 wt%, 4.2 wt%, 4.5 wt%, 4.7 wt%, 5 wt% or a range consisting of any two of these values.

[0060] In some embodiments of the present invention, the concentration of O3 in the DIO3 / HF solution is 20 ppm, 22 ppm, 24 ppm, 26 ppm, 28 ppm, 30 ppm, 32 ppm, 34 ppm, 36 ppm, 38 ppm, 40 ppm, 42 ppm, 44 ppm, 46 ppm, 48 ppm, 50 ppm, 52 ppm, 54 ppm, 56 ppm, 58 ppm, 60 ppm, or a range consisting of any two of these values.

[0061] In some embodiments of the present invention, the concentration of HF in the DIO3 / HF solution is specifically 2 wt%, 3 wt%, 4 wt%, 5 wt%, 6 wt%, 7 wt%, 8 wt%, 9 wt%, 10 wt% or a range consisting of any two of these values.

[0062] In some embodiments of the present invention, the running speed of the first liquid-carrying roller is specifically 1m / min, 1.5m / min, 2m / min, 2.5m / min, 3m / min, 3.5m / min, 4m / min, 4.5m / min, 5m / min, 5.5m / min, 6m / min or a range consisting of any two of these values.

[0063] In order to more clearly illustrate the technical solutions and advantages of the present invention, the present invention is further explained below in conjunction with embodiments and comparative examples.

[0064] Example 1

[0065] A stacked battery, including a bottom battery with only the N side being a smooth pyramid structure, such as Figure 2 As shown, the smooth pyramid structure on the N-side of the bottom cell is stacked in sequence with a carrier recombination layer 2, a hole transport layer 3, a perovskite layer 4, an electron transport layer 5, a transparent conductive layer 6, a front anti-reflection layer 7, and a front metal electrode 8 (silver electrode). The N-side velvet surface of the bottom cell is smooth and uniform, while the P-side of the bottom cell has a large pyramid velvet structure made by alkali velvet. The N-side velvet surface has a height of 0.5µm, and the radius of curvature of the pyramid top is 500nm.

[0066] The method for preparing the stacked battery of this embodiment includes the following steps:

[0067] S1 Preparation of TOPCon bottom battery (such as Figure 1 (shown):

[0068] (1) Texturing: Select an N-type single crystal silicon wafer with a resistivity of 4Ω·m and a thickness of 150μm. Place the N-type single crystal silicon wafer in a sodium hydroxide alkaline solution with a concentration of 1.3wt% and etch it for 500s at a temperature of 70℃. A 1.1μm pyramid structure is formed on both sides of the silicon wafer. The silicon wafer after texturing is cleaned with deionized water.

[0069] (2) Boron diffusion: BCl3 is used as the diffusion source and boron diffusion is carried out in a diffusion furnace. The diffusion temperature is controlled at 900℃ and the diffusion resistance is controlled between 250Ω / □. A boron diffusion layer with a thickness of 0.7μm and a doping concentration of 3E18cm is formed on the surface of the silicon wafer. -3 boron-doped layer.

[0070] (3) Remove N-side BSG: Use HF solution with a mass concentration of 13wt% to remove the wrap-around plating on the N-side of the silicon wafer.

[0071] (4) Only the N-side is smoothed: a mixed solution of HNO3, HF and water is prepared, wherein the mass percentage of HNO3 is 40wt% and the mass percentage of HF is 3wt%; single-side rinsing is performed using a chain machine, the rollers of the chain machine are divided into three sections, namely the first liquid roller, the second liquid roller and the drying roller, the first liquid roller, the second liquid roller and the drying roller run in sequence above the N-side of the single crystal silicon wafer, the first liquid roller carries the HNO3 / HF / H2O mixed solution, so that the HNO3 / HF / H2O mixed solution contacts the N-side and rinses the N-side, the rinsing time is 20s, the running speed of the first liquid roller is 4m / min, and the height of the weakened pyramid is controlled to be 0.5μm; the second liquid roller carries H2O to clean the N-side after the smoothing treatment; while the N-side is smoothed, the P-side surface of the single crystal silicon wafer is protected by a water film; the drying roller dries the entire cleaned single crystal silicon wafer. A mixed solution of O3, HF and deionized water was prepared, wherein the O3 concentration was 40 ppm and the HF mass concentration was 5 wt %. The N-side of the silicon wafer after rinsing was rinsed with the mixed solution of O3, HF and deionized water prepared above for 600 s. The result was a silicon wafer with a top curvature radius of 500 nm for the N-side velvet pyramid structure, and only the N-side was smoothed.

[0072] (5) Deposition of tunnel oxide layer and intrinsic polysilicon layer: Using LPCVD technology, a 2 nm thick tunnel oxide layer is deposited on the N side, and a 100 nm thick intrinsic polysilicon film is deposited on the surface of the tunnel oxide layer.

[0073] (6) Phosphorus diffusion: POCl3 was used as the diffusion source and phosphorus diffusion was carried out in a diffusion furnace. The diffusion temperature was controlled at 850°C and the doping concentration was controlled at 3E20cm -3, a phosphorus-doped layer with a doping thickness of 15 nm is formed in the intrinsic polysilicon layer.

[0074] (7) Remove the P-side plating: Use HF solution with a mass concentration of 13wt% to remove the P-side plating, and use HF / H2O2 and NH3 / H2O2 solutions to clean the silicon wafer in turn.

[0075] (8) Deposition of passivation layer and anti-reflection film: A layer of AlO is deposited on both sides of the silicon wafer using ALD atomic deposition method. x The film forms a passivation film layer with a thickness of 5nm; SiN is deposited on the surface of the passivation film layer using PECVD technology x film layer to form an anti-reflection film.

[0076] (9) Printing back metal electrode: Print AgAl paste on the back of the silicon wafer and form the front and back metal electrodes after sintering.

[0077] S2 uses acid to remove the anti-reflection film layer on the N side of the bottom battery, and then prepares a carrier recombination layer on the N side of the bottom battery using a transparent conductive film;

[0078] S3: A hole transport layer is prepared on the carrier recombination layer, using NiOx material with a thickness of 50 nm;

[0079] S4 prepared a perovskite layer on the hole transport layer using FAPbI3 with a thickness of 1000 nm;

[0080] S5 prepared a C60 electron transport layer on the perovskite thin layer with a thickness of 30nm;

[0081] S6 prepares an ITO transparent conductive layer on the electron transport layer with a thickness of 90 nm;

[0082] S7 prepares a front anti-reflection film and a front silver electrode on the transparent conductive layer.

[0083] Example 2

[0084] The structure of the laminated battery of Example 2 is basically the same as that of Example 1, except for the height of the N-side velvet surface and the radius of curvature of the pyramid top. Specifically, the height of the N-side pyramid structure after rounding is 0.3 μm and the radius of curvature is 1000 nm.

[0085] The preparation method of the stacked battery in Example 2 is essentially the same as that in Example 1, with the only differences being: the HNO3 and HF contents in the mixed solution of HNO3, HF, and water; the O3 and HF contents in the mixed solution of O3, HF, and deionized water; the rinsing reaction time and cleaning time, and the speed of the first liquid-carrying roller. Specifically, the HNO3 mass percentage of the mixed solution of HNO3, HF, and water is 50 wt% and the HF mass percentage is 5 wt%, with a cumulative rinsing reaction time of 25 s; the O3 mass percentage of the mixed solution of O3, HF, and deionized water is 60 ppm and the HF mass percentage is 8 wt%, with a cleaning time of 800 s; and the first liquid-carrying roller runs at a speed of 6 m / min.

[0086] Example 3

[0087] The structure of the perovskite silicon tandem solar cell with smoothed velvet surface in Example 3 is essentially the same as that in Example 1, except for the height of the velvet surface on the N side and the radius of curvature of the pyramid top. Specifically, the height of the smoothed N side pyramid structure is 1.0 μm and the radius of curvature is 100 nm.

[0088] The method for preparing a suede-smoothed perovskite silicon tandem solar cell in Example 3 is essentially the same as that in Example 1, with the only differences being: the different contents of HNO3 and HF in the mixed solution of HNO3, HF, and water; the different contents of O3 and HF in the mixed solution of O3, HF, and deionized water; the different rinsing reaction times and cleaning times; and the different operating speeds of the first liquid-carrying roller. Specifically, the HNO3 mass percentage in the mixed solution of HNO3, HF, and water is 30wt%, the HF mass percentage is 0.5wt%, and the cumulative rinsing reaction time is 4s; the O3 mass percentage in the mixed solution of O3, HF, and deionized water is 20ppm, the HF mass percentage is 2wt%, and the cleaning time is 100s; and the operating speed of the first liquid-carrying roller is 1 m / min.

[0089] Example 4

[0090] The structure of the perovskite silicon tandem solar cell with smoothed velvet surface in Example 4 is essentially the same as that in Example 1, except for the height of the velvet surface on the N side and the radius of curvature of the pyramid top. Specifically, the height of the smoothed N side pyramid structure is 0.8 μm and the radius of curvature is 300 nm.

[0091] The method for preparing a suede-smoothed perovskite silicon tandem solar cell in Example 4 is essentially the same as that in Example 1, with the only differences being: the different contents of HNO3 and HF in the mixed solution of HNO3, HF, and water; the different contents of O3 and HF in the mixed solution of O3, HF, and deionized water; the different rinsing reaction times and cleaning times; and the different operating speeds of the first liquid-carrying roller. Specifically, the HNO3 mass percentage in the mixed solution of HNO3, HF, and water is 30 wt%, the HF mass percentage is 1 wt%, and the rinsing reaction time is 20 s; the O3 mass percentage in the mixed solution of O3, HF, and deionized water is 30 ppm, the HF mass percentage is 10 wt%, and the cleaning time is 500 s; and the operating speed of the first liquid-carrying roller is 2.5 m / min.

[0092] Example 5

[0093] The structure of the perovskite silicon tandem solar cell with smoothed velvet surface in Example 5 is essentially the same as that in Example 1, except for the height of the velvet surface on the N side and the radius of curvature of the pyramid top. Specifically, the height of the smoothed N side pyramid structure is 0.4 μm and the radius of curvature is 850 nm.

[0094] The method for preparing a suede-smoothed perovskite silicon tandem solar cell in Example 5 is essentially the same as that in Example 1, with the only differences being: the HNO3 and HF contents in the mixed solution of HNO3, HF, and water; the O3 and HF contents in the mixed solution of O3, HF, and deionized water; the rinsing reaction time and the cleaning time; and the first liquid-carrying roller operating speed. Specifically, the HNO3 mass percentage and HF mass percentage in the mixed solution of HNO3, HF, and water are 45 wt %, 4.5 wt %, and the cumulative rinsing reaction time is 30 s; the O3 mass percentage and HF mass percentage in the mixed solution of O3, HF, and deionized water are 50 ppm and 7 wt %, respectively, and the cleaning time is 1000 s; and the first liquid-carrying roller operates at a speed of 2.5 m / min.

[0095] Comparative Example 1

[0096] Comparative Example 1 differs from Example 1 in the following method for texturing: A HNO3 / HF / H2O solution containing 40% HNO3 and 3% HF by weight was prepared; the alkaline texturing silicon wafer was immersed in the HNO3 / HF / H2O solution at a temperature of 25°C for 200 seconds. The resulting pyramidal structures had a height of 0.3 μm and a radius of curvature of 500 nm. This process was performed without a chain-type machine.

[0097] Comparative Example 2

[0098] Comparative Example 2 was prepared using essentially the same method as Example 1, differing only in the HNO₃ content of the HNO₃ / HF / H₂O solution. Specifically, the HNO₃ content was 25 wt %. The pyramidal structures, after suede-smoothing treatment, had a height of 1.1 μm and a radius of curvature of 80 nm. A chain-type machine was not used.

[0099] Comparative Example 3

[0100] Comparative Example 3 was prepared using essentially the same method as Example 1, differing only in the HF content of the HNO3 / HF / H2O solution. Specifically, the HF content was 0.3 wt%. The pyramidal structures, after suede rounding, had a height of 1.0 μm and a radius of curvature of 80 nm. A chain-type machine was not used.

[0101] Comparative Example 4

[0102] Comparative Example 4 was prepared using essentially the same method as Example 1, differing only in the O3 content in the mixed solution of O3, HF, and deionized water. Specifically, the O3 content was 70 ppm by weight. The pyramidal structures after the velvet-smoothing treatment had a height of 0.6 μm and a radius of curvature of 80 nm. A chain-type machine was not used.

[0103] Comparative Example 5

[0104] Comparative Example 5 was prepared using a method essentially identical to Example 1, differing only in the HF content of the mixed solution of O₃, HF, and deionized water. Specifically, the HF content was 12 wt %. The pyramidal structures, after suede rounding, had a height of 0.5 μm and a radius of curvature of 80 nm. A chain-type machine was not used.

[0105] Comparative Example 6

[0106] The difference between the stacked battery of Comparative Example 6 and the stacked battery of Example 1 is that the double-sided pyramid structures of the bottom battery of Comparative Example 6 are not rounded.

[0107] Cell performance tests were conducted on Examples 1-5 and Comparative Examples 1-6. The performance parameters included cell conversion efficiency (Eta), open-circuit voltage (Uoc), current (Isc), and fill factor (FF). Eta (efficiency) represents the ratio of solar energy converted to electrical energy by the cell. The test results are shown in Table 1.

[0108] Table 1

[0109] Example / Comparative Example Eta (%) Uoc (V) Isc (A) FF (%) Example 1 30.51 1.753 25.86 78.91 Example 2 28.52 1.739 24.69 77.71 Example 3 27.38 1.718 23.96 76.36 Example 4 26.55 1.733 24.95 73.56 Example 5 26.46 1.735 24.06 75.67 Comparative Example 1 23.86 1.733 20.32 72.11 Comparative Example 2 22.06 1.726 20.69 72.99 Comparative Example 3 21.26 1.713 20.13 70.36 Comparative Example 4 20.38 1.668 21.57 65.18 Comparative Example 5 22.49 1.710 22.12 70.26 Comparative Example 6 18.99 1.612 18.36 75.69

[0110] As shown in Table 1, the conversion efficiency of the TOPCon perovskite tandem cells prepared by the preparation methods provided in Examples 1 to 5 is higher than that of Comparative Examples 1 to 6. It can be seen that the methods provided in Examples 1 to 5 of the present invention can all produce perovskite / TOPCon tandem cells with high conversion efficiency.

[0111] As shown in Table 1, compared with Example 1, Comparative Example 1 uses the immersion method instead of the rinsing method to treat the pyramid surface of the silicon wafer. The pyramid surface of the P-side is also greatly reduced. The filling and current parameters of the prepared perovskite / TOPCon stacked battery are lower than those of Example 1. It can be seen that when the P-side pyramid is too low, it will affect the current and filling, resulting in a decrease in the conversion efficiency of the prepared perovskite / TOPCon stacked battery.

[0112] Compared with Example 1, Comparative Examples 2 and 3 differ in the HNO3 / HF / H2O solution content of HNO3 and HF. The resulting n-side pyramids are taller and have a smaller radius of curvature. The opening voltage and current parameters of the resulting perovskite / TOPCon tandem cells are lower than those of Example 1. This shows that when the n-side pyramids are too tall and too sharp, they significantly affect the current, resulting in a lower conversion efficiency of the resulting perovskite / TOPCon tandem cell.

[0113] Compared with Example 1, the contents of O3 and HF acid in Comparative Examples 4 and 5 are set differently, and the resulting curvature radius is small. It can be seen that when the curvature radius is too small, the resulting pyramid is sharper, which affects the subsequent coating of the perovskite layer, resulting in a decrease in the opening voltage, current and filling of the perovskite stack battery.

[0114] Compared with Example 1, in Comparative Example 6, the double-sided pyramid structures are not rounded, resulting in the N-side pyramid being too high and too sharp, affecting the subsequent coating of the perovskite layer, and reducing the opening voltage, current and filling of the perovskite stack battery.

[0115] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in this field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A laminated battery, characterized in that: It includes a perovskite top cell and a bottom cell, wherein only the N-side velvet surface of the bottom cell is a smooth pyramid structure.

2. The laminated battery according to claim 1, characterized in that: The height of the smooth pyramid structure is 0.3 μm-1.0 μm, and the radius of curvature is 100 nm-1000 nm.

3. The laminated battery according to claim 1, characterized in that: The bottom cell is a silicon heterojunction cell or a TOPCon cell.

4. The laminated battery according to claim 3, characterized in that: The TOPCon cell includes a semiconductor substrate layer with only the P side textured and the N side textured and then smoothed, a smooth pyramid structure arranged on the N side of the double-sided textured semiconductor substrate layer, a tunneling oxide layer, a phosphorus-doped layer, a passivation layer and an anti-reflection film layer stacked in sequence on the N side of the semiconductor substrate layer; and a boron-doped layer, a passivation film layer and a metal electrode stacked in sequence on the P side of the semiconductor substrate layer.

5. The laminated battery according to claim 1, characterized in that: The perovskite top cell includes a carrier recombination layer, a hole transport layer, a perovskite layer, an electron transport layer, a transparent conductive layer, an anti-reflection film layer and a metal electrode stacked in sequence from the N side of the bottom cell.

6. A method for preparing a laminated battery according to any one of claims 1 to 5, characterized in that: The following steps are involved: (1) Double-sided texturing of single-crystal silicon wafers to form a pyramid textured surface structure; (2) Smoothing the pyramid velvet structure on the N side: Using HNO3 / HF / H2O solution to rinse the N side of the single crystal silicon wafer, the HNO3 mass percentage of the HNO3 / HF / H2O solution is 30wt%-50wt%, the HF mass percentage is 0.5wt%~5wt%, and the rinsing time is 4s~30s; then using DIO3 / HF solution to clean the front side, during the cleaning process, the ozone concentration is 20ppm-60ppm, the HF concentration is 2~10wt%, and the cleaning time is 100~1000s; the single-side rinsing is carried out using a chain machine, and the rollers of the chain machine are divided into three sections, a first liquid-carrying roller, a second liquid-carrying roller, and a drying roller, wherein the first liquid-carrying roller, the second liquid-carrying roller, and the drying roller are sequentially operated above the N-side of the single-crystal silicon wafer; the first liquid-carrying roller carries a HNO3 / HF / H2O mixed solution, so that the HNO3 / HF / H2O mixed solution contacts the N-side to rinse the N-side; the first liquid-carrying roller operates at a speed of 1 m / min to 6 m / min; the second liquid-carrying roller carries H2O to clean the N-side after the rounding treatment; while the N-side is being rounded, the P-side surface of the single-crystal silicon wafer is protected by a water film; the drying roller dries the entire cleaned single-crystal silicon wafer; (3) Using the single crystal silicon wafer processed in step (2) as the semiconductor substrate layer, a bottom cell is prepared; (4) A perovskite top cell is stacked on the N side of the bottom cell.

7. The method for preparing a laminated battery according to claim 6, wherein: The steps of preparing the bottom cell are: providing a single crystal silicon wafer, sequentially performing texturing, boron diffusion, and removing BSG from the N side; performing rounding treatment on the N side, depositing a tunneling oxide layer and a polysilicon layer; performing phosphorus diffusion, removing the P side from the plating, and cleaning with a cleaning solution; depositing a passivation film layer and an anti-reflection layer, and printing electrodes.

8. The method for preparing a laminated battery according to claim 6, wherein: The texturing is performed by etching with an alkaline solution having a concentration of 0.5-10 wt % to form a pyramid structure on both sides of the single crystal silicon wafer, wherein the pyramid structure has a height of 0.7 μm-1.5 μm; and / or, The boron diffusion adopts BCL3 as the diffusion source, the diffusion temperature is 800°C-1000°C, and the diffusion square resistance is controlled at 200Ω / □-300Ω / □; and / or, The N-side BSG removal is performed using a HF solution with a concentration of 5% to 20%; and / or, The P-surface de-plating is performed by using an HF solution with a concentration of 3wt%-10wt%, and a cleaning solution composed of HF / H2O2 and NH3 / H2O2 is used to clean the silicon wafer.

9. The method for preparing a laminated battery according to claim 6, wherein: The passivation film is deposited by using ALD atomic deposition to deposit a layer of AlO on both sides of the silicon wafer. x The thin film forms a passivation film layer; the deposited anti-reflection film layer is deposited on both sides by PECVD x The film layer forms an anti-reflection film layer.

10. The method for preparing a laminated battery according to claim 6, wherein: The printed electrode is formed by printing AgAl paste or Ni / Cu / Ag paste or Ag paste on the N side of the silicon wafer and sintering it to form a metal electrode.

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