Display device

Abstract

A display device includes a substrate, pixels each including at least one transistor, a storage capacitor connected to the at least one transistor, and a light emitting element connected to the at least one transistor, a scan line connected to each of the pixels, a data line connected to each of the pixels, and a power line connected to each of the pixels. A data line is connected to each of the pixels, and a power line supplies a first power supply voltage to the light emitting element. The at least one transistor includes: an active pattern; a source electrode and a drain electrode each connected to the active pattern; a gate electrode disposed on the active pattern; an insulating intermediate layer covering the gate electrode and including a first insulating intermediate layer, a second insulating intermediate layer, and a third insulating intermediate layer that are sequentially stacked; and a protective layer disposed on the insulating intermediate layer. At least one of the plurality of scan lines is disposed on the second insulating intermediate layer and is connected to the gate electrode via the contact hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2018-0116601, filed on September 28, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate generally to display devices, and more particularly, to organic light emitting display devices. Background Art

[0004] Among display devices, organic light-emitting display devices generally include two electrodes and an organic light-emitting layer located between the two electrodes. In an organic light-emitting display device, electrons injected from one of the two electrodes and holes injected from the other electrode recombine in the organic light-emitting layer to form excitons, and the excitons emit light through energy.

[0005] As the size, resolution, and desired driving frequency of a display device increase, resistance-capacitance (RC) delay increases. As the size and desired brightness of a display device increase, voltage (IR) drop increases. Recently, research has been conducted on display panel structures for preventing RC delay and IR drop. Summary of the Invention

[0006] Example embodiments provide a display device having improved line resistance of a power line.

[0007] Example embodiments also provide a display device having improved resistance-capacitance ("RC") delay of a scan signal.

[0008] In an exemplary embodiment of the present invention, a display device is provided, which includes a substrate, a plurality of pixels, a plurality of scan lines, a data line, and a power line, wherein: the substrate includes a display area and a non-display area; the plurality of pixels are located in the display area, and the plurality of pixels each include at least one transistor, a storage capacitor connected to the at least one transistor, and a light-emitting element connected to the at least one transistor; the plurality of scan lines are connected to each of the plurality of pixels, and the plurality of scan lines extend in a first direction; the data line is connected to each of the plurality of pixels, and the data line extends in a second direction; the power line supplies a first power supply voltage to the light-emitting element, wherein the at least one transistor includes an active pattern provided on the substrate, a source electrode and a drain electrode each connected to the active pattern, and a capacitor provided on the substrate. A gate electrode on the source pattern, an insulating interlayer, and a protective layer arranged on the insulating interlayer, a gate insulating layer overlapping the active pattern is inserted between the gate electrode and the active pattern, the insulating interlayer includes a first insulating interlayer, a second insulating interlayer, and a third insulating interlayer covering the gate electrode and stacked in sequence, wherein the power line includes a first conductive pattern extending in a first direction, a second conductive pattern extending in the first direction, and a third conductive pattern extending in a second direction, the first conductive pattern is arranged on the first insulating interlayer, the second conductive pattern is arranged on the second insulating interlayer, the second conductive pattern is connected to the first conductive pattern via a first contact hole, the third conductive pattern is arranged on the third insulating interlayer, and the third conductive pattern is connected to the second conductive pattern via a second contact hole.

[0009] In example embodiments, the storage capacitor may include a lower electrode disposed in the same layer as the gate electrode and an upper electrode overlapping the lower electrode, the upper electrode being disposed on the first insulating interlayer.

[0010] In example embodiments, the first and second conductive patterns may overlap at least a portion of a lower electrode of the storage capacitor.

[0011] In example embodiments, an area of the first conductive pattern overlapping the lower electrode may be greater than an area of the second conductive pattern overlapping the lower electrode.

[0012] In example embodiments, the upper electrode may not have an opening defined therein in a plan view.

[0013] In exemplary embodiments, the power line may have a mesh structure through the connection of the first conductive pattern to the third conductive pattern.

[0014] In example embodiments, at least one of the scan lines may be disposed in the same layer as the second conductive pattern and connected to the gate electrode.

[0015] In example embodiments, the gate electrode may be a conductive pattern having an island shape.

[0016] In an exemplary embodiment, at least one of the scan lines may include an aluminum alloy.

[0017] In an exemplary embodiment, the display device may further include an emission control line connected to each of the pixels, the emission control line extending in the first direction.

[0018] In example embodiments, the emission control line may be disposed in the same layer as the gate electrode.

[0019] In exemplary embodiments, the emission control line may be disposed in the same layer as the second conductive pattern.

[0020] In an exemplary embodiment, the display device may further include an initialization line that supplies an initialization voltage to the pixel. The initialization line may include a first initialization conductive pattern disposed in the same layer as the second conductive pattern, the first initialization conductive pattern extending in the first direction.

[0021] In exemplary embodiments, the initialization line may further include a second initialization conductive pattern disposed in the same layer as the third conductive pattern, the second initialization conductive pattern extending in the second direction.

[0022] In exemplary embodiments, the display device may further include a shielding pattern disposed in the same layer as the first conductive pattern, the shielding pattern being connected to the first initialization conductive pattern.

[0023] In an exemplary embodiment, the at least one transistor may include a driving transistor that controls a driving current flowing through the light emitting element. In a plan view, the shielding pattern may include a portion between the data line and a gate node of the driving transistor.

[0024] In another exemplary embodiment of the present invention, a display device is provided, which includes a substrate, a plurality of pixels, a plurality of scan lines, a data line, and a power line, wherein: the substrate includes a display area and a non-display area; the plurality of pixels are located in the display area, each of the plurality of pixels including at least one transistor, a storage capacitor connected to the at least one transistor, and a light-emitting element connected to the at least one transistor; the plurality of scan lines are connected to each of the pixels, the plurality of scan lines extending in a first direction; the data lines are connected to each of the pixels, the data lines extending in a second direction; the power line supplies a first power supply voltage to the light-emitting element, wherein the at least one transistor includes an active pattern disposed on the substrate, a source electrode and a drain electrode each connected to the active pattern, a gate electrode disposed on the active pattern, an insulating interlayer, and a protective layer disposed on the insulating interlayer, a gate insulating layer overlapping the active pattern being interposed between the gate electrode and the active pattern, the insulating interlayer including a first insulating interlayer, a second insulating interlayer, and a third insulating interlayer covering the gate electrode and stacked in sequence, wherein at least one of the scan lines is disposed on the second insulating interlayer and connected to the gate electrode via a contact hole.

[0025] In example embodiments, the gate electrode connected to the at least one of the scan lines may be a conductive pattern having an island shape.

[0026] In an exemplary embodiment, the power line may include a first conductive pattern extending in a first direction, a second conductive pattern extending in the first direction, and a third conductive pattern extending in a second direction, wherein the first conductive pattern is arranged on a first insulating interlayer, the second conductive pattern is arranged on a second insulating interlayer, the second conductive pattern is connected to the first conductive pattern, and the third conductive pattern is arranged on a third insulating interlayer, and the third conductive pattern is connected to the second conductive pattern.

[0027] In example embodiments, an area of the first conductive pattern may be greater than an area of the second conductive pattern.

[0028] Resistances of the second and third conductive patterns may be lower than resistance of the first conductive pattern.

[0029] In an exemplary embodiment, the display device may further include an emission control line connected to each of the pixels, the emission control line extending in the first direction.

[0030] In example embodiments, the emission control line may be disposed in the same layer as the gate electrode.

[0031] In an exemplary embodiment, the storage capacitor may include a lower electrode disposed in the same layer as the gate electrode and an upper electrode overlapping the lower electrode, the upper electrode being disposed on the first insulating interlayer. In a plan view, the upper electrode has no opening defined therein.

[0032] In an exemplary embodiment, the display device may further include an initialization line for supplying an initialization voltage to the pixel. The initialization line may include a first initialization conductive pattern disposed on the second insulating interlayer and a second initialization conductive pattern disposed on the third insulating interlayer, the first initialization conductive pattern extending in the first direction and the second initialization conductive pattern extending in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings.

[0034] Figure 1 is a block diagram illustrating an exemplary embodiment of a display device according to the present invention.

[0035] Figure 2 It shows Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0036] Figure 3 It shows Figure 2 A plan view of an example of pixels.

[0037] Figure 4 yes Figure 3 A cross-sectional view of a pixel taken along line II'.

[0038] Figure 5 yes Figure 3 A cross-sectional view of a pixel taken along line II-II'.

[0039] Figure 6 yes Figure 3 A cross-sectional view of a pixel taken along line III-III'.

[0040] Figure 7 It shows Figures 3 to 6 A plan view of the active pattern, source electrode, and drain electrode shown in FIG.

[0041] Figure 8 It shows Figures 3 to 6 A plan view of the gate electrode and emission control line shown in FIG.

[0042] Figure 9 It shows Figures 3 to 6 1 is a plan view of a first conductive pattern of electric force lines shown in FIG.

[0043] Figure 10 It shows Figures 3 to 6 1 to 3 scan lines, a second conductive pattern of the power line, and a plan view of the first initialization line shown in FIG.

[0044] Figure 11 It shows Figures 3 to 6 1 is a plan view of a third conductive pattern of a data line, a second initialization line, and a power line shown in FIG.

[0045] Figure 12 It shows Figure 2 A plan view of another example of a pixel.

[0046] Figure 13 It is along Figure 12 A sectional view taken along line IV-IV'.

[0047] Figure 14 It shows Figure 1 A plan view of an example of electric power lines included in a display device.

[0048] Figure 15 It shows Figure 1 A plan view of an example of scan lines included in a display device.

[0049] Figure 16 It shows Figure 1 A plan view of another example of scan lines included in a display device.

[0050] Figure 17 It shows Figure 2 A plan view of an example of pixels.

[0051] Figure 18 It shows Figure 1 A plan view of an example of electric power lines included in a display device.

[0052] Figure 19 It shows Figure 1 FIG. 1 is a plan view of an example of an initialization line included in a display device of FIG. DETAILED DESCRIPTION

[0053] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In all drawings, the same reference numerals are given to the same elements, and their repeated description will be omitted.

[0054] For clarity of explanation, in the accompanying drawings, dimensions may be exaggerated. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, identical reference numerals represent identical elements.

[0055] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0056] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, the "first element," "first component," "first region," "first layer," or "first section" discussed below may be referred to as a second element, second component, second region, second layer, or second section without departing from the teachings herein.

[0057] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will also be understood that when the terms "include" and / or "including" or "comprising" and / or "comprising" are used in this description, it refers to the presence of the stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0058] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation described in the accompanying drawings. For example, if the device in one of the figures in the accompanying drawings is turned over, the element described as being on the "lower" side of the other element will then be oriented as being on the "upper" side of the other element. Thus, the exemplary term "lower" may include both "lower" and "upper" orientations, depending on the specific orientation of the accompanying drawings. Similarly, if the device in one of the figures in the accompanying drawings is turned over, the element described as being "below" or "beneath" the other element will then be oriented as being "above" the other element. Thus, the exemplary terms "lower" or "beneath" may include both "upper" and "lower" orientations.

[0059] For ease of description, spatially relative terms such as "below," "beneath," "down," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary term "below" can include both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0060] As used herein, "about" or "approximately" includes the stated value and the mean within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0062] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, variations in the shapes in the drawings due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but rather should include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or non-linear features. In addition, sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the appended claims.

[0063] Figure 1 is a block diagram illustrating an exemplary embodiment of a display device according to the present invention.

[0064] refer to Figure 1The display device 1000 may include a substrate SUB, a plurality of pixels PX, a driving unit for driving the pixels PX, and scan lines SL1 to SLn, emission control lines EL1 to ELn, data lines DL1 to DLm, and power lines (not shown), where n is a natural number, m is a natural number, and the power lines connect the pixels PX and the driving unit.

[0065] The substrate SUB may have various shapes. In an exemplary embodiment, for example, the substrate SUB may have a closed polygonal shape including linear edges. In an exemplary embodiment, the substrate SUB may have a shape including curved edges, such as a circle or an ellipse. In an exemplary embodiment, the substrate SUB may have a shape including linear edges and curved edges, such as a semicircle or a semi-ellipse. The substrate SUB may include a display area DA and a non-display area NDA located at the periphery of the display area DA, wherein the display area DA includes pixels PX.

[0066] The pixels PX may be arranged in the display area DA of the substrate SUB. Each of the pixels PX may include at least one transistor, a storage capacitor, and a light-emitting element. In an exemplary embodiment, the light-emitting element may be, for example, an organic light-emitting diode ("OLED"). However, this is merely illustrative, and the light-emitting element is not limited thereto.

[0067] The driving unit may include a scan driver 200, an emission driver 300, a data driver 400, and a timing controller 500. Figure 1 3 shows a case where the scan driver 200 , the emission driver 300 , and the data driver 400 are disposed on the substrate SUB, but the location of the driving unit is not limited thereto.

[0068] Scan lines SL1 to SLn, data lines DL1 to DLm, and power lines may be connected to the pixels PX. The scan lines SL1 to SLn may provide scan signals to the pixels PX, and the data lines DL1 to DLm may provide data signals to the pixels PX.

[0069] The pixel PX can be supplied with a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization power supply voltage VINT from an external power source (power supply). The first power supply voltage ELVDD can be supplied via a power line PL (reference Figure 2 ) is applied to the pixel PX, and the initialization power supply voltage VINT can be applied to the pixel PX through the initialization line VIL (reference Figure 2 ) is applied to the pixel PX.

[0070] The scan driver 200 may supply scan signals to the scan lines SL1 to SLn in response to a scan start signal SFLM received from the timing controller 500 .

[0071] The emission driver 300 may supply emission control signals to the emission control lines EL1 to ELn in response to the emission control start signal EFLM received from the timing controller 500 .

[0072] The data driver 400 may supply analog data signals RGB to the data lines DL1 to DLm in response to the data control signal DCS received from the timing controller 500 .

[0073] The timing controller 500 may supply a scan start signal SFLM to the scan driver 200 , an emission control start signal EFLM to the emission driver 300 , and a data control signal DCS and analog data signals RGB to the data driver 400 based on a timing signal supplied from the outside.

[0074] Figure 2 It shows Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0075] Figure 2 The pixel PX is, for example, a pixel connected to the j-th data line DLj and the i-th scan line SLi (j and i are natural numbers).

[0076] refer to Figure 1 and Figure 2 , the pixel PX may include an organic light emitting diode OLED, first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0077] The anode electrode of the organic light emitting diode OLED may be connected to the first transistor T1 via the sixth transistor T6, and the cathode electrode of the organic light emitting diode OLED may receive the second power voltage ELVSS. The organic light emitting diode OLED may generate light having a predetermined brightness corresponding to the amount of current supplied from the first transistor T1.

[0078] The first power voltage ELVDD supplied to the first transistor T1 may be set to a voltage higher than the second power voltage ELVSS so that current may flow through the organic light emitting diode OLED.

[0079] The seventh transistor T7 may be connected between the initialization power supply voltage VINT and the anode electrode of the organic light emitting diode OLED. In an exemplary embodiment, the gate electrode of the seventh transistor T7 may be connected to the i-th scan line SLi. The seventh transistor T7 may be turned on when a scan signal is supplied to the i-th scan line SLi to supply the initialization power supply voltage VINT to the anode electrode of the organic light emitting diode OLED. In other words, the seventh transistor T7 may be a transistor for initializing the anode voltage of the organic light emitting diode OLED.

[0080] The initialization power supply voltage VINT may be set to a voltage lower than the data voltage. However, the scan line connected to the gate electrode of the seventh transistor T7 is merely illustrative, and the present invention is not limited thereto. In an exemplary embodiment, for example, one of the (i-2) scan line SLi-2, the (i-1) scan line SLi-1, and the (i+1) scan line SLi+1 may be connected to the gate electrode of the seventh transistor T7.

[0081] The sixth transistor T6 may be connected between the first transistor T1 and the organic light emitting diode OLED. A gate electrode of the sixth transistor T6 may be connected to the i-th emission control line ELi.

[0082] The fifth transistor T5 may be connected between the first power voltage ELVDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be connected to the i-th emission control line ELi.

[0083] A first electrode of a first transistor (also referred to as a driving transistor) T1 may receive a first power supply voltage ELVDD via a fifth transistor T5, and a second electrode of the first transistor T1 may be connected to an anode electrode of the organic light emitting diode OLED via a sixth transistor T6. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may control the amount of current flowing through the organic light emitting diode OLED.

[0084] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the i-th scan line SLi. The third transistor T3 may be turned on when a scan signal is supplied to the i-th scan line SLi to electrically connect the second electrode of the first transistor T1 and the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be diode-connected, and the threshold voltage of the first transistor T1 may be compensated. In other words, the third transistor T3 may be a transistor for compensating the threshold voltage of the first transistor T1.

[0085] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply voltage VINT. The gate electrode of the fourth transistor T4 may be connected to the (i-1)th scan line SLi-1. The fourth transistor T4 may be turned on when a scan signal is supplied to the (i-1)th scan line SLi-1 to supply the initialization power supply voltage VINT to the first node N1. In other words, the fourth transistor T4 may be a transistor for initializing the gate voltage of the first transistor T1.

[0086] The second transistor T2 may be connected between the j-th data line DLj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the i-th scan line SLi. The second transistor T2 may be turned on when a scan signal is supplied to the i-th scan line SLi to electrically connect the j-th data line DLj and the first electrode of the first transistor T1.

[0087] The storage capacitor Cst may be connected between the first power voltage ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0088] Figure 3 It shows Figure 2 A plan view of an example of pixels. Figure 4 yes Figure 3 A cross-sectional view of a pixel taken along line II'. Figure 5 yes Figure 3 A cross-sectional view of a pixel taken along line II-II'. Figure 6 yes Figure 3 A cross-sectional view of a pixel taken along line III-III'.

[0089] Hereinafter, the scan line SLi connected to the second transistor T2 and the third transistor T3 may be understood as the gate write line GW, the scan line SLi-1 connected to the fourth transistor T4 may be understood as the gate initialization control line GI, and the scan line SLi connected to the seventh transistor T7 may be understood as the anode initialization control line GB.

[0090] refer to Figures 1 to 6 , the display device 1000 may include a substrate SUB, a plurality of conductive lines, and pixels PX connected to the conductive lines.

[0091] For ease of description, Figure 3 、 Figure 5 and Figure 6 The organic light emitting diode is omitted, and Figure 4 Schematically shows the stacking structure of an organic light emitting diode (OLED).

[0092] The pixel PX may include a pixel circuit including first to seventh transistors T1 to T7 and a storage capacitor Cst, and an organic light emitting diode connected to the pixel circuit. The pixel circuit may be electrically connected to scan lines SLi and SLi-1, a data line DLj, a power line PL, and an initialization line VIL.

[0093] The substrate SUB may be provided as a backplane substrate or a base substrate. The substrate SUB may include a transparent insulating material to allow light to pass through the substrate SUB. In an exemplary embodiment, the substrate SUB may be, for example, a flexible substrate. In an exemplary embodiment, the substrate SUB may be one of a film substrate including a polymer organic material and a plastic substrate. In an exemplary embodiment, the substrate SUB may include, for example, polyimide.

[0094] In an exemplary embodiment, a buffer layer and / or a barrier layer may be provided on the substrate SUB. The buffer layer and / or the barrier layer may prevent diffusion of impurities, moisture, etc. generated from the substrate SUB and may be used to adjust the propagation speed of heat during the crystallization process for forming the semiconductor pattern. In an exemplary embodiment, for example, the buffer layer and / or the barrier layer may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ). The buffer layer and / or the barrier layer may have a single layer or multi-layer structure including a silicon compound.

[0095] The first to seventh transistors T1 to T7 may be disposed on a substrate SUB. Each of the first to seventh transistors T1 to T7 may include an active pattern disposed on the substrate SUB, a source electrode and a drain electrode each connected to the active pattern, a gate electrode disposed on the active pattern, an insulating interlayer including a first insulating interlayer IL1, a second insulating interlayer IL2, and a third insulating interlayer IL3, and a protective layer PSV disposed on the insulating interlayer, wherein a gate insulating layer GIL overlapping the active pattern is interposed between the gate electrode and the active pattern, and the first insulating interlayer IL1, the second insulating interlayer IL2, and the third insulating interlayer IL3 cover the gate electrode and are sequentially stacked.

[0096] The power line PL may include first, second, and third conductive patterns PL1, PL2, and PL3. For ease of description, the first, second, and third conductive patterns PL1, PL2, and PL3 may be understood as first, second, and third power lines PL1, PL2, and PL3, respectively.

[0097] The first conductive pattern PL1 may extend in the first direction DR1 and be disposed on the first insulating interlayer IL1. The second conductive pattern PL2 may extend in the first direction DR1 and be disposed on the second insulating interlayer IL2. The first conductive pattern PL1 and the second conductive pattern PL2 may be connected to each other via the first contact hole CNT1. In an exemplary embodiment, the first conductive pattern PL1 and the second conductive pattern PL2 may overlap at least a portion of the lower electrode LE of the storage capacitor Cst. Furthermore, the area of the first conductive pattern PL1 overlapping the lower electrode LE may be greater than the area of the second conductive pattern PL2 overlapping the lower electrode LE.

[0098] In an exemplary embodiment, for example, the first conductive pattern PL1 may include molybdenum (Mo) or an alloy thereof. However, this is merely illustrative, and the material included in the first conductive pattern PL1 is not limited thereto. In an exemplary embodiment, for example, the first conductive pattern PL1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.

[0099] In an exemplary embodiment, the second conductive pattern PL2 may include a low resistance material. The second conductive pattern PL2 may have a resistance lower than that of the first conductive pattern PL1. In an exemplary embodiment, for example, the second conductive pattern PL2 may have an aluminum alloy structure in which titanium (Ti), aluminum ("Al"), and titanium (Ti) are sequentially stacked. However, this is merely illustrative, and the material of the second conductive pattern PL2 is not limited thereto. In an exemplary embodiment, for example, the second conductive pattern PL2 may include gold (Au), silver (Ag), Al, platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN x ), silver alloy, tungsten (W), tungsten nitride (WN x ), copper alloy, molybdenum alloy, titanium nitride (TiN x ), tantalum nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x ), indium tin oxide ("ITO"), tin oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide ("IZO"), etc. They may be used alone or in combination.

[0100] In example embodiments, the first and second conductive patterns PL1 and PL2 may overlap with the first transistor T1 .

[0101] The third conductive pattern PL3 may extend in the second direction DR2 and be disposed on the third insulating interlayer IL3. The third conductive pattern PL3 may be connected to the second conductive pattern PL2 via the second contact hole CNT2. The third conductive pattern PL3 may include a low-resistance metal. In an exemplary embodiment, for example, the third conductive pattern PL3 may have an aluminum alloy structure in which titanium (Ti), Al, and titanium (Ti) are sequentially stacked. In an exemplary embodiment, for example, the third conductive pattern PL3 may have the same material as the second conductive pattern PL2.

[0102] The first and second conductive patterns PL1 and PL2 may extend in a horizontal direction (e.g., a first direction DR1), and the third conductive pattern PL3 may extend in a vertical direction (e.g., a second direction DR2). By connecting the first to third conductive patterns PL1 to PL3, the power line PL may have a mesh structure having three conductive layers.

[0103] The first conductive pattern PL1, the second conductive pattern PL2, and the third conductive pattern PL3 can be electrically connected to each other via the first contact hole CNT1 and the second contact hole CNT2. That is, the first conductive pattern PL1, the second conductive pattern PL2, and the third conductive pattern PL3 can transmit the same first power supply voltage ELVDD. In addition, the power line PL can have a dual wiring structure including the first conductive pattern PL1 and the second conductive pattern PL2 extending in a horizontal direction to partially overlap each other. The voltage drop (i.e., IR drop) of the first power supply voltage ELVDD in the first direction DR1 can be reduced due to the dual wiring structure and the second conductive pattern PL2 including a low-resistance metal. Therefore, the brightness uniformity of the display device 1000 can be improved.

[0104] The scan lines SLi and SLi-1 may extend in the first direction DR1. In an exemplary embodiment, for example, the scan lines SLi and SLi-1 may be arranged in the order of the gate initialization control line GI, the gate write line GW, and the anode initialization control line GB along the second direction DR2. Hereinafter, the gate initialization control line GI, the gate write line GW, and the anode initialization control line GB will be described as a first scan line GI, a second scan line GW, and a third scan line GB, respectively.

[0105] At least one of the scan lines GI, GW, and GB may be disposed in the same layer as the second conductive pattern PL2 , and the scan lines GI, GW, and GB may be connected to gate electrodes corresponding to the transistors via contact holes, respectively.

[0106] In an exemplary embodiment, Figure 3 and Figure 4 As shown in FIG, the first scan line GI, the second scan line GW, and the third scan line GB can be arranged in the same layer as the second conductive pattern PL2. Accordingly, the first scan line GI, the second scan line GW, and the third scan line GB can include the same material as the second conductive pattern PL2. In an exemplary embodiment, for example, the first scan line GI, the second scan line GW, and the third scan line GB can include a low-resistance metal material such as an aluminum alloy. As a result, the resistance of the first scan line GI, the second scan line GW, and the third scan line GB is reduced, so that the resistance-capacitance ("RC") delay of the scan signal can be reduced. In addition, the scan lines GI, GW, and GB are provided by a bridge structure between the gate electrode and the conductive pattern on the second insulating interlayer IL2, so that the influence of external interference and static electricity can be reduced.

[0107] The first scan line GI may be connected to the gate electrode of the fourth transistor T4 via the third contact hole CNT3. The second scan line GW may be connected to the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3 via the fourth contact hole CNT4 and the fifth contact hole CNT5, respectively. In an exemplary embodiment, the second scan line GW may be connected to the gate electrode of the third transistor T3 of the pixel on the (j-1)th column and the gate electrode of the second transistor T2 of the pixel on the jth column via the fourth contact hole CNT4, and connected to the gate electrode of the third transistor T3 of the pixel on the jth column and the gate electrode of the second transistor T2 of the pixel on the (j+1)th column via the fifth contact hole CNT5.

[0108] The third scan line GB may be connected to the gate electrode of the seventh transistor T7 through the sixth contact hole CNT6 .

[0109] The emission control line ELi may be provided in the same layer as the gate electrode. However, this is merely illustrative, and the emission control line ELi may be provided in the same layer as the second conductive pattern PL2. Thus, the emission control line ELi may be connected to the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 via contact holes. When the emission control line ELi is provided in the same layer as the low-resistance second conductive pattern PL2, the RC delay of the emission control signal may be reduced due to the resistance of the emission control line ELi.

[0110] Initialization line VIL (reference Figure 2) can supply an initialization power supply voltage VINT to the pixel PX. The initialization line VIL may include a first initialization conductive pattern VIL1 extending in a first direction DR1 and a second initialization conductive pattern VIL2 extending in a second direction DR2. That is, the initialization line VIL may have a mesh structure in which the first initialization conductive pattern VIL1 and the second initialization conductive pattern VIL2 intersect each other. For ease of description, the first initialization conductive pattern VIL1 and the second initialization conductive pattern VIL2 may be understood as the first initialization line VIL1 and the second initialization line VIL2, respectively.

[0111] The first initialization conductive pattern VIL1 may be provided in the same layer as the second conductive pattern PL2 and extend in the first direction DR1. In an exemplary embodiment, the first initialization conductive pattern VIL1 may be connected to the drain electrode (or source electrode) of the fourth transistor T4 and the drain electrode (or source electrode) of the seventh transistor T7 via the seventh contact hole CNT7. In an exemplary embodiment, Figure 3 As shown in , the first initialization conductive pattern VIL1 located at the lower end of the i-th pixel may be simultaneously connected to the seventh transistor T7 of the i-th pixel and the fourth transistor T4 of the (i+1)-th pixel through the seventh contact hole CNT7 .

[0112] The second initialization conductive pattern VIL2 may be disposed in the same layer as the third conductive pattern PL3 , and the second initialization conductive pattern VIL2 may be connected to the first initialization conductive pattern VIL1 through the eighth contact hole CNT8 .

[0113] When the initialization conductive patterns VIL1 and VIL2 are provided as described above, non-uniformity in parasitic capacitance caused by connection between existing initialization conductive patterns may be minimized.

[0114] Each of the first to seventh transistors T1 to T7 may include a source electrode, a drain electrode, and an active pattern provided by patterning a semiconductor layer, and a gate electrode provided by patterning a gate electrode layer. In an exemplary embodiment, the active pattern, the source electrode, and the drain electrode may include a semiconductor layer that is undoped with impurities or doped with impurities. In an exemplary embodiment, for example, the source electrode and the drain electrode may include a semiconductor layer doped with impurities, and the active pattern may include a semiconductor layer that is undoped with impurities. The drain electrode and the source electrode may be arbitrarily defined according to the voltage applied to each of the first to seventh transistors T1 to T7.

[0115] The storage capacitor Cst may include a lower electrode LE disposed in the same layer as the gate electrode and an upper electrode UE disposed on the first insulating interlayer IL1 while overlapping the lower electrode LE. The lower electrode LE may be provided as the gate electrode of the first transistor T1. The upper electrode UE may be provided as the first conductive pattern PL1.

[0116] No opening is defined in the upper electrode UE that overlaps with the lower electrode LE. That is, the first conductive pattern PL1 constituting the upper electrode UE is not connected to any components other than the components forming the power line PL (e.g., a transistor), and therefore, the upper electrode UE and the lower electrode LE are not short-circuited with any other components. Therefore, in the storage capacitor Cst according to the exemplary embodiment of the present invention, the opening present in the existing storage capacitor is removed, so that the capacitance change caused by the formation of the opening is eliminated, and the capacitance (i.e., the area of the electrode) can be increased. Accordingly, display spots and image crosstalk caused by the capacitance change of the storage capacitor Cst can be minimized.

[0117] In the following, reference will be made to Figures 4 to 6 The structure of the display device according to the exemplary embodiment of the present invention is described in stacking order.

[0118] Active patterns ACT1 to ACT7 (hereinafter, referred to as ACT) may be provided on the substrate SUB. The active pattern ACT (refer to Figure 7 ) may include first to seventh active patterns ACT1 to ACT7. The first to seventh active patterns ACT1 to ACT7 may include semiconductor materials. The active patterns ACT may include inorganic semiconductors (eg, amorphous silicon or polycrystalline silicon), organic semiconductors, etc.

[0119] The gate insulating layer GIL may be provided on the substrate SUB on which the active pattern ACT is provided. The gate insulating layer GIL may include at least one of an organic insulating layer and an inorganic insulating layer. In an exemplary embodiment, for example, the gate insulating layer GIL may include an inorganic material including silicon oxide (SiO x ), silicon nitride (SiN x ) and at least one of silicon oxynitride (SiON).

[0120] The emission control line ELi and the first to seventh gate electrodes GE1 to GE7 of the corresponding first to seventh transistors T1 to T7 may be disposed on the gate insulating layer GIL. In an exemplary embodiment, the gate electrodes GE1 to GE7 (hereinafter, referred to as GE) may be conductive patterns having an island shape. In an exemplary embodiment, for example, the gate electrodes GE (refer to Figure 8 ) and the emission control line ELi may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. They may be used alone or in combination.

[0121] The first gate electrode GE1 may be a lower electrode LE of the storage capacitor Cst. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be integral with the emission control line ELi.

[0122] The first insulating interlayer IL1 may be provided on the gate insulating layer GIL on which the gate electrode GE is provided. The first insulating interlayer IL1 may include at least one of an organic insulating layer and an inorganic insulating layer. In an exemplary embodiment, for example, the first insulating interlayer IL1 may include the same material as that of the gate insulating layer GIL.

[0123] The upper electrode UE of the storage capacitor Cst and the first power line (first conductive pattern) PL1 may be disposed on the first insulating interlayer IL1. The upper electrode UE may cover the lower electrode LE. The upper electrode UE and the lower electrode LE together may constitute the storage capacitor Cst, with the first insulating interlayer IL1 interposed between the upper electrode UE and the lower electrode LE. The upper electrode UE may be part of the first power line PL1. The first power line PL1 may extend in a first direction DR1. The first power line PL1 may transmit a first power supply voltage ELVDD.

[0124] The upper electrode UE and the first power line PL1 may include the same material. In an exemplary embodiment, for example, the upper electrode UE and the first power line PL1 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0125] The second insulating interlayer IL2 may be disposed on the first insulating interlayer IL1 on which the upper electrode UE and the first power line PL1 are disposed. The second insulating interlayer IL2 may include at least one of an organic insulating layer and an inorganic insulating layer.

[0126] The first scan line GI, the second scan line GW, and the third scan line GB (i.e., SLi-1 and SLi), the second power line (second conductive pattern) PL2, and the first initialization line (first initialization conductive pattern) VIL1 may be disposed on the second insulating interlayer IL2. The first scan line GI, the second scan line GW, and the third scan line GB, the second power line PL2, and the first initialization line VIL1 may extend in the first direction DR1. The first scan line GI, the second scan line GW, and the third scan line GB, the second power line PL2, and the first initialization line VIL1 may include the same material, which may include a low-resistance metal. In an exemplary embodiment, the low-resistance metal may have an aluminum alloy structure in which titanium (Ti), Al, and titanium (Ti) are sequentially stacked. However, this is merely illustrative, and the low-resistance metal is not limited thereto.

[0127] The first scan line GI, the second scan line GW, and the third scan line GB (i.e., SLi-1 and SLi) can be connected to the gate electrodes corresponding to the first scan line GI, the second scan line GW, and the third scan line GB via contact holes CNT3 to CNT6 that penetrate the first insulating interlayer IL1 and the second insulating interlayer IL2. The second power line PL2 can be connected to the first power line PL1 via a first contact hole CNT1 that penetrates the second insulating interlayer IL2. The first initialization line VIL1 can be connected to the fourth gate electrode GE4 and the seventh gate electrode GE7 via a seventh contact hole CNT7 that penetrates the first insulating interlayer IL1 and the second insulating interlayer IL2.

[0128] The third insulating interlayer IL3 may be disposed on the second insulating interlayer IL2 on which the first, second, and third scan lines GI, GW, and GB, the second power line (second conductive pattern) PL2, and the first initialization line VIL1 are disposed. The third insulating interlayer IL3 may include at least one of an organic insulating layer and an inorganic insulating layer.

[0129] The third power line (third conductive pattern) PL3, the second initialization line (second initialization conductive pattern) VIL2, and the data line DLj may be disposed on the third insulating interlayer IL3. The third power line PL3, the second initialization line VIL2, and the data line DLj may extend in the second direction DR2. The third power line PL3, the second initialization line VIL2, and the data line DLj may include the same material, which may include a low-resistance metal.

[0130] The third power line PL3 may be connected to the second power line PL2 via a second contact hole CNT2 penetrating the third insulating interlayer IL3. The second initialization line VIL2 may be connected to the first initialization line VIL1 via an eighth contact hole CNT8 penetrating the third insulating interlayer IL3. The data line DLj may be connected to the source electrode SE2 (or drain electrode DE2) of the second transistor T2 via a twelfth contact hole CNT12 penetrating the third insulating interlayer IL3.

[0131] The protective layer PSV may be disposed on the third insulating interlayer IL3 on which the third power line PL3, the second initialization line VIL2, and the data line DLj are disposed. The protective layer PSV may include at least one of an organic insulating layer and an inorganic insulating layer. In an exemplary embodiment, for example, the protective layer PSV may include an organic insulating layer.

[0132] The organic light emitting diode OLED may be disposed on the protective layer PSV. The organic light emitting diode OLED may include a first electrode AD, a second electrode CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD.

[0133] The first electrode AD may be disposed on the protective layer PSV. The first electrode AD may be connected to the first bridge pattern BRP1 via a tenth contact hole CNT10 that penetrates the protective layer PSV. The first bridge pattern BRP1 may be a conductive pattern for connecting the source electrode SE7 of the seventh transistor T7 and the first electrode AD. The first bridge pattern BRP1 may be disposed on the third insulating interlayer IL3.

[0134] The first bridge pattern BRP1 may be connected to the second bridge pattern BRP2 via a ninth contact hole CNT9 penetrating the third insulating interlayer IL3. The second bridge pattern BRP2 may be a conductive pattern disposed on the second insulating interlayer IL2. The second bridge pattern BRP2 may be connected to the source electrode SE7 of the seventh transistor T7 (and the drain electrode DE6 of the sixth transistor T6) via an eleventh contact hole CNT11 sequentially penetrating the gate insulating layer GIL, the first insulating interlayer IL1, and the second insulating interlayer IL2.

[0135] Therefore, the first electrode AD may be finally connected to the source electrode SE7 of the seventh transistor T7 and the drain electrode DE6 of the sixth transistor T6 via the first and second bridge patterns BRP1 and BRP2 .

[0136] A pixel-defining layer (PDL) that defines a light-emitting range corresponding to each pixel may be disposed on the protective layer (PSV) on which the first electrode (AD) is disposed. The pixel-defining layer (PDL) may expose the upper surface of the first electrode (AD) and protrude from the protective layer (PSV) along the perimeter of the pixel (PX). In an exemplary embodiment, the light-emitting range may be defined as the upper surface of the first electrode (AD) exposed by the pixel-defining layer (PDL).

[0137] An emission layer EML may be disposed on the exposed first electrode AD, and a second electrode CD may be disposed on the emission layer EML. An encapsulation layer ECL covering the second electrode CD may be disposed over the second electrode CD.

[0138] One of the first electrode AD and the second electrode CD may be an anode electrode, and the other of the first electrode AD and the second electrode CD may be a cathode electrode. In an exemplary embodiment, for example, the first electrode AD may be an anode electrode, and the second electrode CD may be a cathode electrode.

[0139] The first electrode AD may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination. The pixel defining layer PDL may include an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer PDL may be formed using an organic material. The second electrode CD may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination.

[0140] The emission layer EML may have a multi-layer thin film structure including a light generating layer ("LGL"). The emission layer EML may include a hole injection layer ("HIL"), a hole transport layer ("HTL"), the LGL, a hole blocking layer ("HBL"), an electron transport layer ("ETL"), and an electron injection layer ("EIL"). In addition, the HIL, HTL, HBL, ETL, and EIL in the emission layer EML may be common layers commonly provided in adjacent pixels PX.

[0141] In an exemplary embodiment, the color of light generated in the LGL may be one of red, green, blue, and white, but the present invention is not limited thereto. In an exemplary embodiment, for example, the color of light generated in the LGL may be one of magenta, cyan, and yellow.

[0142] Figure 7 It shows Figures 3 to 6 A plan view of the active pattern, source electrode, and drain electrode shown in FIG. Figure 8 It shows Figures 3 to 6 A plan view of the gate electrode and emission control line shown in FIG.

[0143] refer to Figures 2 to 8 A semiconductor layer including first to seventh active patterns ACT1 to ACT7 , first to seventh source electrodes SE1 to SE7 , and first to seventh drain electrodes DE1 to DE7 may be disposed on the substrate SUB.

[0144] The first to seventh active patterns ACT1 to ACT7 may be provided in the same layer through the same process. The first to seventh active patterns ACT1 to ACT7 may correspond to the first to seventh transistors T1 to T7, respectively.

[0145] The first to seventh source electrodes SE1 to SE7 may correspond to the first to seventh transistors T1 to T7, respectively. The first to seventh drain electrodes DE1 to DE7 may correspond to the first to seventh transistors T1 to T7, respectively.

[0146] In example embodiments, the first to seventh active patterns ACT1 to ACT7 may include a semiconductor layer not doped with impurities, and the first to seventh source electrodes SE1 to SE7 and the first to seventh drain electrodes DE1 to DE7 may include a semiconductor layer doped with impurities.

[0147] One end of the first active pattern ACT1 may be connected to the first source electrode SE1, and the other end of the first active pattern ACT1 may be connected to the first drain electrode DE1. One end of the second active pattern ACT2 may be connected to the second source electrode SE2, and the other end of the second active pattern ACT2 may be connected to the second drain electrode DE2. One end of the third active pattern ACT3 may be connected to the third source electrode SE3, and the other end of the third active pattern ACT3 may be connected to the third drain electrode DE3. One end of the fourth active pattern ACT4 may be connected to the fourth source electrode SE4, and the other end of the fourth active pattern ACT4 may be connected to the fourth drain electrode DE4. One end of the fifth active pattern ACT5 may be connected to the fifth source electrode SE5, and the other end of the fifth active pattern ACT5 may be connected to the fifth drain electrode DE5. One end of the sixth active pattern ACT6 may be connected to the sixth source electrode SE6, and the other end of the sixth active pattern ACT6 may be connected to the sixth drain electrode DE6. One end of the seventh active pattern ACT7 may be connected to the seventh source electrode SE7, and the other end of the seventh active pattern ACT7 may be connected to the seventh drain electrode DE7.

[0148] The first active pattern ACT1 may have a rod shape extending in a first direction DR1 and having a shape that bends multiple times along the extended length. In a plan view, the first active pattern ACT1 may overlap with the first gate electrode GE1. The first active pattern ACT1 is configured to be elongated, so that the channel region of the first transistor T1 can be configured to be elongated. Accordingly, the driving range of the gate voltage applied to the first transistor T1 can be widened.

[0149] In an exemplary embodiment, the third transistor T3 and the fourth transistor T4 may be provided in a dual-gate structure to prevent leakage current. The third transistor T3 may include a 3a transistor and a 3b transistor. The 3a transistor may include a 3a gate electrode GE3a, a 3a active pattern ACT3a, a 3a source electrode SE3a, and a 3a drain electrode DE3a. The 3b transistor may include a 3b gate electrode GE3b, a 3b active pattern ACT3b, a 3b source electrode SE3b, and a 3b drain electrode DE3b. The fourth transistor T4 may include a 4a transistor and a 4b transistor. The 4a transistor may include a 4a gate electrode GE4a, a 4a active pattern ACT4a, a 4a source electrode SE4a, and a 4a drain electrode DE4a. The 4b transistor may include a 4b gate electrode GE4b, a 4b active pattern ACT4b, a 4b source electrode SE4b, and a 4b drain electrode DE4b.

[0150] The first to seventh gate electrodes GE1 to GE7, the lower electrode LE of the storage capacitor Cst, and the emission control line ELi may be disposed on the gate insulating layer GIL on which the semiconductor layer is disposed. The first to seventh active patterns ACT1 to ACT7 may correspond to portions of the semiconductor layer overlapping with the first to seventh gate electrodes GE1 to GE7, respectively.

[0151] The first to seventh gate electrodes GE1 to GE7 , the lower electrode LE of the storage capacitor Cst, and the emission control line ELi may include the same material in the same layer through the same process.

[0152] In an exemplary embodiment, the first gate electrode GE1 , the second gate electrode GE2 , the third gate electrode GE3 , the fourth gate electrode GE4 , and the seventh gate electrode GE7 may be conductive patterns having an island shape. Accordingly, the influence caused by the undesirable antenna effect may be reduced.

[0153] That is, unlike the conventional arrangement of scan lines disposed in the same layer as the gate electrodes, the scan lines may be disposed in a layer different from the layer in which the gate electrodes are disposed. The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, the fourth gate electrode GE4, and the seventh gate electrode GE7 may be connected to the upper scan lines via contact holes, respectively.

[0154] The first gate electrode GE1 may be integral with the lower electrode LE, and the fifth and sixth gate electrodes GE5 and GE6 may be integral with the emission control line ELi.

[0155] However, this is merely illustrative, and the arrangement of the emission control line ELi is not limited thereto. In an exemplary embodiment, the emission control line ELi may include the same material as the scan line and the second conductive pattern (second power line) PL2 in the same layer as the scan line and the second conductive pattern (second power line) PL2 through the same process as the scan line and the second conductive pattern (second power line) PL2. In an exemplary embodiment, for example, the emission control line ELi may be disposed on the second insulating interlayer IL2 and electrically connected to the fifth gate electrode GE5 and the sixth gate electrode GE6 via predetermined contact holes.

[0156] Figure 9 It shows Figures 3 to 6 1 is a plan view of a first conductive pattern of electric force lines shown in FIG.

[0157] refer to Figures 2 to 9 The first power line (first conductive pattern) PL1 and the upper electrode UE of the storage capacitor Cst may be disposed on the first insulating interlayer IL1 covering the first to seventh gate electrodes GE1 to GE7, the lower electrode LE of the storage capacitor Cst, and the emission control line ELi.

[0158] In the exemplary embodiment, although not in Figure 3 As shown in FIG, however, a shielding pattern SDP and a repair line pattern RLP ( Figure 12 and Figure 13 ). The first power line PL1, the upper electrode UE of the storage capacitor Cst, the shielding pattern SDP, and the repair line pattern RLP may include the same material in the same layer through the same process.

[0159] The first power line PL1 may extend in a first direction DR1 and transmit a first power voltage ELVDD.

[0160] The upper electrode UE may be integral with the first power line PL1. That is, the storage capacitor Cst may be formed by the lower electrode LE and the upper electrode UE, which are arranged with the first insulating interlayer IL1 interposed therebetween. In an exemplary embodiment, the upper electrode UE may have an area larger than that of the lower electrode LE. In addition, no opening (hole) is defined in the upper electrode UE.

[0161] In a plan view, the shield pattern SDP may be disposed between the data line DLj and the gate node (gate electrode GE1) of the first transistor T1, spaced apart from the data line DLj and the gate node (gate electrode GE1) of the first transistor T1. The arrangement of the shield pattern SDP can reduce electrical influences (e.g., coupling capacitance) between the data line DLj and the gate node. Thus, image crosstalk can be minimized.

[0162] The repair line pattern RLP may extend in the first direction DR1. The repair line pattern RLP may connect an organic light emitting diode connected to a pixel circuit determined to be a defective pixel circuit to a repair pixel circuit outside the display area. In an exemplary embodiment, for example, the defective pixel circuit is disconnected from the organic light emitting diode, and the corresponding organic light emitting diode may be electrically connected to the repair pixel circuit via the repair line pattern RLP.

[0163] Figure 10 It shows Figures 3 to 6 A plan view of the first to third scan lines, the second conductive pattern of the power line, and the first initialization line shown in FIG.

[0164] refer to Figures 2 to 10 , the first scan line GI, the second scan line GW and the third scan line GB, the second power line (second conductive pattern) PL2 and the first initialization line (first initialization conductive pattern) VIL1 can be set on the second insulating interlayer IL2 covering the first power line PL1 and the upper electrode UE of the storage capacitor Cst.

[0165] In exemplary embodiments, second to fourth bridge patterns BRP2 to BRP4 may be further disposed on the second insulating interlayer IL2 .

[0166] The second to fourth bridge patterns BRP2 to BRP4 , the first, second, and third scan lines GI, GW, and GB, the second power line PL2 , and the first initialization line VIL1 may include the same material in the same layer and be electrically connected to underlying conductive layers via a plurality of contact holes.

[0167] The first scan line GI may extend in the first direction DR1 and may be connected to the fourth gate electrode GE4 through the third contact hole CNT3.

[0168] The second scan line GW may extend in the first direction DR1. The second scan line GW may be connected to the second gate electrode GE2 and the third gate electrode GE3 via the fourth contact hole CNT4 and the fifth contact hole CNT5, respectively. In an exemplary embodiment, for example, the second scan line GW may be connected to the gate electrode of the third transistor T3 of the pixel on the (j-1)th column and the gate electrode of the second transistor T2 of the pixel on the jth column via the fourth contact hole CNT4, and connected to the gate electrode of the third transistor T3 of the pixel on the jth column and the gate electrode of the second transistor T2 of the pixel on the (j+1)th column via the fifth contact hole CNT5.

[0169] The third scan line GB may extend in the first direction DR1 and may be connected to the seventh gate electrode GE7 through the sixth contact hole CNT6.

[0170] As described above, the first scan line GI, the second scan line GW, and the third scan line GB can be provided in a conductive layer (i.e., a layer different from the layer in which the gate electrode is provided) including a low-resistance material (e.g., an aluminum alloy) and connected to the gate electrode via a contact hole. Therefore, the resistance of the first scan line GI, the second scan line GW, and the third scan line GB is reduced, so that RC delay can be minimized.

[0171] The second power line PL2 may extend in the first direction DR1. The second power line PL2 may be connected to the first power line PL1 via the first contact hole CNT1. The second power line PL2 may be connected to the fifth source electrode SE5 via the thirteenth contact hole CNT13. In an exemplary embodiment, for example, the thirteenth contact hole CNT13 may penetrate the gate insulating layer GIL, the first insulating interlayer IL1, and the second insulating interlayer IL2.

[0172] In an exemplary embodiment, the area of the first power line PL1 overlapping the lower electrode LE may be greater than the area of the second power line PL2 overlapping the lower electrode LE. However, this is merely illustrative, and the areas of the first and second power lines PL1 and PL2 are not limited thereto.

[0173] The first power line PL1 and the second power line PL2 can be arranged in a dual wiring structure, in which at least portions of the first conductive pattern PL1 and the second conductive pattern PL2 extend horizontally to overlap each other. The dual wiring structure and the second conductive pattern PL2 including a low-resistance metal can reduce a voltage drop (i.e., an IR drop) of the first power voltage ELVDD in the first direction DR1. Consequently, the brightness uniformity of the display device 1000 can be improved.

[0174] The first initialization line VIL1 may extend in the first direction DR1. The first initialization line VIL1 may be connected to the seventh drain electrode DE7 (or the seventh source electrode SE7) and the fourth drain electrode DE4 (or the fourth source electrode SE4) via the seventh contact hole CNT7. In an exemplary embodiment, for example, the first initialization line VIL1 may be connected to the seventh drain electrode DE7 (or the seventh source electrode SE7) of the i-th pixel (i.e., the pixel on the i-th row) and the fourth drain electrode DE4 (or the fourth source electrode SE4) of the (i+1)-th pixel (i.e., the pixel on the (i+1)-th row) via the seventh contact hole CNT7.

[0175] In an exemplary embodiment, the first initialization line VIL1 may be connected to the shielding pattern SDP via the fourteenth contact hole CNT14 penetrating the second insulating interlayer IL2. Therefore, the shielding pattern SDP floats to the initialization power supply voltage VINT, which is a direct current (DC) voltage, and accordingly, the electrical influence between the data line DLj and the gate node may be eliminated.

[0176] The second bridge pattern BRP2 may be connected to the seventh source electrode SE7 (and the sixth drain electrode DE6) via an eleventh contact hole CNT11 penetrating the gate insulating layer GIL, the first insulating interlayer IL1, and the second insulating interlayer IL2. The second bridge pattern BRP2 may regulate electrical connection between the seventh source electrode SE7 and the first electrode AD of the organic light emitting diode OLED.

[0177] The third bridge pattern BRP3 may be connected to the second source electrode SE2 via a twelfth contact hole CNT12 penetrating the gate insulating layer GIL, the first insulating interlayer IL1, and the second insulating interlayer IL2. The third bridge pattern BRP3 may regulate electrical connection between the second source electrode SE2 and the data line DLj.

[0178] The fourth bridge pattern BRP4 may be connected to the first gate electrode GE1 via a fifteenth contact hole CNT15 penetrating the first insulating interlayer IL1 and the second insulating interlayer IL2. In addition, the fourth bridge pattern BRP4 may be connected to the third drain electrode DE3 (and the fourth source electrode SE4) via a sixteenth contact hole CNT16 penetrating the gate insulating layer GIL, the first insulating interlayer IL1, and the second insulating interlayer IL2. That is, the fourth bridge pattern BRP4 may be connected to the Figure 2 The fourth bridge pattern BRP4 may adjust the electrical connection between the first gate electrode GE1 and the third drain electrode DE3 (and the fourth source electrode SE4).

[0179] Figure 11 It shows Figures 3 to 6 1 is a plan view of a third conductive pattern of a data line, a second initialization line, and a power line shown in FIG.

[0180] refer to Figures 2 to 11 The data lines DLj-1, DLj, ..., the third power line (third conductive pattern) PL3 and the second initialization line (second initialization conductive pattern) VIL2 can be arranged on the third insulating intermediate layer IL3 covering the first scan line GI, the second scan line GW and the third scan line GB, the second power line PL2 and the first initialization line VIL1.

[0181] In exemplary embodiments, the first bridge pattern BRP1 may be further disposed on the third insulating interlayer IL3 .

[0182] The first bridge pattern BRP1, the data lines DLj-1, DLj, . . . , the third power line PL3, and the second initialization line VIL2 may include the same material in the same layer through the same process and be electrically connected to the underlying conductive layer through a plurality of contact holes.

[0183] The data line DLj may extend in the second direction DR2. The data line DLj may be connected to the third bridge pattern BRP3 via a contact hole CNT12' penetrating the third insulating interlayer IL3. Thus, the data line DLj may ultimately be connected to the second source electrode SE2. The data signal transmitted through the data line DLj may be supplied to the pixel PX via the second transistor T2 (e.g., the second source electrode SE2).

[0184] The third power line PL3 may extend in the second direction DR2 and may transmit the first power voltage ELVDD in the second direction DR2.

[0185] The third power line PL3 may be connected to the second power line PL2 via a second contact hole CNT2 penetrating the third insulating interlayer IL3 . The third power line PL3 may be ultimately connected to the first power line PL1 , the fifth source electrode SE5 , and the upper electrode UE of the storage capacitor Cst.

[0186] According to the connection relationship between the first power line PL1 to the third power line PL3, the power lines PL can be arranged in a mesh structure. Figure 1 in the display area DA.

[0187] The second initialization line VIL2 may extend in the second direction DR2. The second initialization line VIL2 may be connected to the first initialization line VIL1 via an eighth contact hole CNT8 penetrating the third insulating interlayer IL3. According to the connection relationship between the first initialization line VIL1 and the second initialization line VIL2, the initialization line VIL (refer to FIG. Figure 2 ) can be set in a mesh structure Figure 1 in the display area DA.

[0188] In an exemplary embodiment, one second initialization line VIL2 may be provided for every two pixel columns to ensure an aperture ratio.

[0189] The first bridge pattern BRP1 and the second bridge pattern BRP2 may be connected to each other via a ninth contact hole CNT9 penetrating the third insulating interlayer IL3 .

[0190] Figure 12 It shows Figure 2 A plan view of another example of a pixel. Figure 13 It is along Figure 12 A sectional view taken along line IV-IV'.

[0191] exist Figure 12 The same reference numerals are used to denote Figure 3 The components described above are identical to those described above, and their repeated description will be omitted. In addition, in addition to the shielding pattern SDP and the repair line pattern RLP, Figure 12 The pixels can have Figure 3 The configuration of the pixels is basically the same or a similar configuration.

[0192] refer to Figures 2 to 12 , the display device 1000 may include a substrate SUB, a plurality of conductive lines, and pixels PX connected to the conductive lines.

[0193] The shielding pattern SDP and the repair line pattern RLP may include the same material as the first power line PL1 and the upper electrode UE of the storage capacitor Cst in the same layer through the same process as the first power line PL1 and the upper electrode UE of the storage capacitor Cst.

[0194] In a plan view, the shielding pattern SDP may be formed at a gate node ( ) between the data line DLj and the first transistor T1 (eg, the fourth bridge pattern BRP4). Figure 2 The shielding pattern SDP may be connected to the first initialization line VIL1 via the fourteenth contact hole CNT14, and one end of the shielding pattern SDP may be floating.

[0195] According to the arrangement of the shielding pattern SDP, the electrical influence (eg, coupling capacitance) between the data line DLj and the gate node can be reduced, and thus, image crosstalk can be minimized.

[0196] The repair line pattern RLP may extend in the first direction DR1. The repair line pattern RLP may connect an organic light emitting diode connected to a pixel circuit determined to be a defective pixel circuit to a repair pixel circuit outside the display area. In an exemplary embodiment, for example, the defective pixel circuit is disconnected from the organic light emitting diode, and the corresponding organic light emitting diode may be electrically connected to the repair pixel circuit via the repair line pattern RLP.

[0197] Figure 14 It shows Figure 1 A plan view of an example of electric power lines included in a display device.

[0198] refer to Figure 1 、 Figure 3 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 14 , the display device 1000 may include a plurality of power lines PL that supply the first power voltage ELVDD to the pixels PX.

[0199] The power line PL may include first to third conductive patterns PL1 to PL3 (hereinafter, referred to as first to third power lines) electrically connected to each other.

[0200] The first power line PL1 may be disposed on the first insulating interlayer IL1 so as to extend in a first direction DR1. In an exemplary embodiment, for example, the first direction DR1 may be a horizontal direction (or a pixel row direction), and the second direction DR2 may be a vertical direction (a pixel column direction) intersecting the first direction DR1. In an exemplary embodiment, a portion of the first power line PL1 may be the upper electrode UE of the storage capacitor Cst. The area of the first power line PL1 may be larger than that of the second power line PL2. Thus, the resistance of the first power line PL1 may be reduced.

[0201] The second power line PL2 may be disposed on the second insulating interlayer IL2 to extend in the first direction DR1 and may be electrically connected to the first power line PL1 through the first contact hole CNT1.

[0202] Since the second power line PL2 includes a low-resistance metal, a width (or area) of the second power line PL2 in the second direction DR2 may be smaller than an area of the first power line PL1 in the second direction DR2.

[0203] The third power line PL3 may be arranged on the third insulating interlayer IL3 to extend in the second direction DR2. The third power line PL3 may be electrically connected to the second power line PL2 via the second contact hole CNT2. Thus, all of the first to third power lines PL1 to PL3 may be electrically connected to each other. However, this is merely illustrative, and the stacking order of the first to third power lines PL1 to PL3 is not limited thereto. In addition, the power lines extending in the second direction DR2 may have a dual wiring structure. In addition, the power lines may have three or more (i.e., multiple) overlapping wiring structures in one direction.

[0204] As described above, by connecting the first power line PL1 to the third power line PL3, the power lines PL can have a mesh structure provided with three conductive layers. The first power line PL1 and the second power line PL2 can be arranged in a dual wiring structure, in which at least portions of the first conductive pattern PL1 and the second conductive pattern PL2 extend in the first direction DR1 to overlap each other. Therefore, the voltage drop (i.e., IR drop) of the first power supply voltage ELVDD can be reduced. Consequently, the brightness uniformity of the display device 1000 can be improved.

[0205] Figure 15 It shows Figure 1 A plan view of an example of scan lines included in a display device.

[0206] refer to Figure 1 、 Figure 2 、 Figure 3 、 Figure 8 、 Figure 10 and Figure 15, the display device 1000 may include a plurality of scan lines GI, GW, and GB that provide scan signals to the pixels PX.

[0207] The first scan line GI, the second scan line GW, and the third scan line GB may extend in the first direction DR1 and be disposed on the second insulating interlayer IL2. The first scan line GI, the second scan line GW, and the third scan line GB may be electrically connected to the gate electrodes GE2, GE3, GE4, and GE7 corresponding to the first scan line GI, the second scan line GW, and the third scan line GB via predetermined contact holes CNT3, CNT4, CNT5, and CNT6.

[0208] The first, second, and third scan lines GI, GW, and GB include a conductive layer made of a low-resistance material, thereby reducing the resistance of the first, second, and third scan lines GI, GW, and GB. Therefore, the RC delay of the scan signals can be minimized. The scan lines GI, GW, and GB are provided by a bridge structure between the gate electrode and the conductive pattern on the second insulating interlayer IL2, thereby reducing the effects of external interference and static electricity.

[0209] In an exemplary embodiment, the emission control line ELi may also be disposed on the second insulating interlayer IL2. That is, the emission control line ELi may include the same material as the first scan line GI, the second scan line GW, and the third scan line GB in the same layer as the first scan line GI, the second scan line GW, and the third scan line GB.

[0210] Figure 16 It shows Figure 1 A plan view of another example of scan lines included in a display device.

[0211] exist Figure 16 The same reference numerals are used to denote Figure 15 The components described above are the same as those described above, and their repeated description will be omitted. In addition, except for the third scanning line GB, Figure 16 The scan lines can have Figure 15 The configurations of the scan lines are basically the same or similar configurations.

[0212] refer to Figure 16 , the third scan line GB may include the same material as the emission control line ELi in the same layer through the same process as the emission control line ELi.

[0213] The third scan line GB is used to control the initialization of the first electrode AD of the organic light-emitting diode OLED before or after data is written, and is less affected by RC delay. In addition, the emission control signal transmitted to the emission control line ELi has a sufficiently long on / off state, and therefore, the emission control line ELi is less affected by RC delay. Therefore, the third scan line GB and the emission control line ELi can be integrated with the predetermined gate electrode in the same layer as the gate electrode.

[0214] However, this is merely illustrative, and at least one of the first scan line GI and the second scan line GW may be disposed in the same layer as the gate electrode. The scan line not disposed in the same layer as the gate electrode may be disposed in the same layer as the second conductive pattern PL2.

[0215] Figure 17 It shows Figure 2 A plan view of an example of pixels. Figure 18 It shows Figure 1 A plan view of an example of electric power lines included in a display device.

[0216] exist Figure 17 and Figure 18 The same reference numerals are used to denote Figure 3 The same components as those described above are described above, and their repeated description will be omitted. In addition, except for the positions where some of the conductive patterns are provided, Figure 17 The pixels can have Figure 3 The configuration of the pixels is basically the same or a similar configuration.

[0217] refer to Figure 1 、 Figure 17 and Figure 18 , the display device 1000 may include a substrate SUB, a plurality of conductive lines, and pixels PX connected to the conductive lines.

[0218] The pixel PX may include a pixel circuit including first to seventh transistors T1 to T7 and a storage capacitor Cst, and an organic light emitting diode connected to the pixel circuit. The pixel circuit may be electrically connected to scan lines SLi and SLi-1, a data line DLj, a power line PL, and an initialization line VIL.

[0219] Figure 17 The j-th data line DLj included in the pixel PX may be connected to the pixels on the odd rows, and the (j+1)-th data line DLj+1 may be connected to the pixels on the even rows. Therefore, the two data lines DLj and DLj+1 may overlap with one pixel.

[0220] like Figure 18As shown in FIG, the power lines PL may include first, second, and third power lines PL1, PL2, and PL3. The first and second power lines PL1 and PL2 may extend in a horizontal direction, and the third power line PL3 may extend in a vertical direction.

[0221] The first power line PL1 and the second power line PL2 may be provided in different layers and electrically connected to each other via the first contact hole CNT1 and the second contact hole CNT2. In an exemplary embodiment, for example, the first power line PL1 and the second power line PL2 may be electrically connected to each other via the first contact hole CNT1, and the second power line PL2 and the third power line PL3 may be electrically connected to each other via the second contact hole CNT2.

[0222] The first and second power lines PL1 and PL2 are arranged in a double wiring structure in a horizontal direction, so that the voltage drop (ie, IR drop) of the first power voltage ELVDD can be reduced. Therefore, the brightness uniformity of the display device 1000 can be improved.

[0223] As described above, the power lines PL of the display device 1000 according to the exemplary embodiment of the present invention have a double wiring structure in which at least portions of conductive patterns extend in the first direction to overlap each other, so that the voltage drop (ie, IR drop) of the first power voltage ELVDD can be reduced.

[0224] In addition, the first scan line GI, the second scan line GW, and the third scan line GB may include a low-resistance metal material such as an aluminum alloy. Thus, the resistance of the scan lines GI, GW, and GB is reduced, thereby reducing the RC delay of the scan signal. Furthermore, at least one of the scan lines GI, GW, and GB is disposed in a conductive layer (i.e., a layer different from the gate electrode) comprising a low-resistance material (such as an aluminum alloy) and is connected to the gate electrode via a contact hole. Thus, the resistance of the scan lines G1, GW, and GB is reduced, thereby minimizing the RC delay of the scan signal. Accordingly, the effects of external interference and static electricity can be reduced.

[0225] Furthermore, in the storage capacitor Cst according to the exemplary embodiment of the present invention, the opening present in the conventional storage capacitor is removed, so that the capacitance variation caused by the formation of the opening is eliminated, and the capacitance (i.e., the electrode area) can be increased. Accordingly, display spots and image crosstalk caused by the capacitance variation of the storage capacitor Cst can be minimized.

[0226] Figure 19 It shows Figure 1 FIG. 1 is a plan view of an example of an initialization line included in a display device of FIG.

[0227] refer to Figure 1 、 Figure 4 、 Figure 11 and Figure 19 , initialization line VIL (reference Figure 2 ) may include a first initialization line (first initialization conductive pattern) VIL1 extending in the first direction DR1 and a second initialization line (second initialization conductive pattern) VIL2 extending in the second direction DR2.

[0228] According to the connection relationship between the first initialization line VIL1 and the second initialization line VIL2, the initialization line VIL can be arranged in a mesh structure. Figure 1 in the display area DA.

[0229] In an exemplary embodiment, the first initialization line VIL1 may include the same material as the active pattern in the same layer as the active pattern. In an exemplary embodiment, for example, the first initialization line VIL1 may include a semiconductor layer doped with impurities.

[0230] The second initialization line VIL2 may be disposed on the third insulating interlayer IL3. The second initialization line VIL2 may include the same material as the third conductive pattern PL3 in the same layer as the third conductive pattern PL3.

[0231] In example embodiments, the second initialization line VIL2 may be connected to the first initialization line VIL1 via a contact hole CNT penetrating the first, second, and third insulating interlayers IL1, IL2, and IL3 and the gate insulating layer GIL.

[0232] However, this is merely illustrative, and the first initialization line VIL1 is not limited thereto. In an exemplary embodiment, for example, the first initialization line VIL1 may also be provided in the same layer as the second conductive pattern PL2 provided on the second insulating interlayer IL2. The first initialization line provided on the second insulating interlayer IL2 may be connected to the first initialization line VIL1 and / or the second initialization line VIL2 provided in the same layer as the active pattern via a predetermined contact hole.

[0233] The present invention can be applied to display devices and electronic devices including display devices. In exemplary embodiments, for example, the organic light-emitting display device can be applied not only to electronic devices such as computers, mobile phones, smartphones, and smart tablets, but also to vehicle navigation systems, head-mounted displays, and the like. Furthermore, the organic light-emitting display device can be applied to wearable display devices that can be worn on a user's body.

[0234] In the display device according to the present invention, the resistance of the power lines and scan lines is reduced, so that the RC delay of the scan signal and the voltage drop across the power lines can be minimized. In addition, the improved capacitance of the storage capacitor can be uniformly ensured. Therefore, the brightness uniformity and image quality of the display device can be improved.

[0235] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will become apparent to those skilled in the art upon submission of this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other exemplary embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display device comprising: A substrate including a display area and a non-display area; a plurality of pixels located in the display area, each of the plurality of pixels including at least one transistor, a storage capacitor connected to the at least one transistor, and a light emitting element connected to the at least one transistor; a plurality of scan lines connected to each of the plurality of pixels, the plurality of scan lines extending in a first direction; a data line connected to each pixel of the plurality of pixels, the data line extending in a second direction; as well as a power line for supplying a first power supply voltage to the light emitting element; Wherein, the at least one transistor comprises: an active pattern disposed on the substrate, a source electrode and a drain electrode, each connected to the active pattern; a gate electrode disposed on the active pattern, with a gate insulating layer interposed between the gate electrode and the active pattern and overlapping the active pattern; an insulating interlayer covering the gate electrode and comprising: a first insulating interlayer, a second insulating interlayer, and a third insulating interlayer stacked sequentially; and a protective layer disposed on the insulating intermediate layer, and At least one scan line among the plurality of scan lines is disposed on the second insulating interlayer and is connected to the gate electrode via a contact hole.

2. The display device according to claim 1, wherein The gate electrode connected to the at least one scan line among the plurality of scan lines is a conductive pattern having an island shape.

3. The display device according to claim 1, wherein The power line includes: a first conductive pattern extending in the first direction, wherein the first conductive pattern is disposed on the first insulating intermediate layer; a second conductive pattern extending in the first direction, the second conductive pattern being disposed on the second insulating interlayer and connected to the first conductive pattern; and A third conductive pattern extends in the second direction, the third conductive pattern is disposed on the third insulating interlayer, and the third conductive pattern is connected to the second conductive pattern.

4. The display device according to claim 3, wherein: An area of the first conductive pattern is greater than an area of the second conductive pattern.

5. The display device according to claim 3, wherein: Resistances of the second conductive pattern and the third conductive pattern are smaller than resistance of the first conductive pattern.

6. The display device according to claim 1, further comprising: An emission control line is connected to each of the plurality of pixels, and the emission control line extends in the first direction.

7. The display device according to claim 6, wherein: The emission control line is provided in the same layer as the gate electrode.

8. The display device according to claim 1, wherein The storage capacitor comprises: a lower electrode provided in the same layer as the gate electrode; and an upper electrode, overlapping with the lower electrode, and the upper electrode is arranged on the first insulating intermediate layer, Wherein, in a plan view, no opening is defined in the upper electrode.

9. The display device according to claim 1, further comprising: an initialization line for supplying an initialization voltage to the plurality of pixels; Wherein, the initialization line includes: a first initialization conductive pattern, disposed on the second insulating interlayer, the first initialization conductive pattern extending in the first direction; and The second initialization conductive pattern is disposed on the third insulating interlayer, and the second initialization conductive pattern extends in the second direction.

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