Phase locked loop (PLL) including digitally controlled oscillator (DCO) gain calibration circuit and related methods

Abstract

An interface between clock domains of an integrated circuit (IC) depends on synchronization of phase-locked loops (PLLs) that generate clocks in different domains and how each PLL responds to jitter in a shared reference clock. The same bandwidth (and loop dynamics) for good control of those PLLs is such that the reference jitter contributions are the same and thus negligible. As a critical component to determine digital PLL bandwidth, a digitally controlled oscillator (DCO) may have its gain varied with process, temperature, and supply IR drop from chip to chip or even module to module. The calibration circuit provides a gain correction factor to achieve a nominal gain in the DCO as well as a desired / target PLL loop bandwidth. In some examples, a calibration circuit in each PLL determines a gain correction factor that causes the PLLs to have a common jitter response, and stores the gain correction factor in the calibration circuit.

Description

Technical Field

[0001] The technology of this disclosure relates generally to phase-locked loops (PLLs), and more particularly, to jitter response in PLLs. Background Art

[0002] An integrated circuit (IC) can include multiple clock domains that communicate with each other, where each clock domain is a group of circuits that receive the same clock. Communication between circuits in different clock domains relies on the synchronization of their respective clocks. Each clock domain can have a dedicated phase-locked loop (PLL) to provide a clock to the circuits within the clock domain. The PLL includes a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO) that oscillates at a frequency corresponding to a reference clock. When the output clock generated by the PLL is not synchronized with the reference clock, a time difference is detected and used to generate a control signal to adjust the frequency of the output clock. In a PLL that includes a DCO, the control signal is a digital value generated by comparing a feedback signal based on the output clock with the reference clock. When the PLL is initially powered on, there is a time difference between the feedback signal and the reference clock, but this time difference gradually decreases until the PLL is locked (i.e., synchronized). However, variations in the reference clock, such as jitter, can interfere with the PLL output clock edges. The way the PLL responds to reference jitter can vary depending on the loop bandwidth. If PLLs in different clock domains of an IC receive the same reference clock but respond differently to jitter in the reference clock, the jitter can cause timing problems that degrade performance or cause communication failures. Summary of the Invention

[0003] Example aspects disclosed herein include a phase-locked loop (PLL) including a digitally controlled oscillator (DCO) gain calibration circuit. Also disclosed are related methods for DCO gain calibration. Synchronization of clocks in different clock domains of an integrated circuit (IC) is important in high-performance interfaces between those clock domains. PLLs can achieve synchronization between clock domains by generating domain clocks based on the same reference clock. However, if the PLLs do not respond to jitter in the same manner, jitter in the reference clock signal can disrupt synchronization. In the example PLLs disclosed herein, a calibration circuit provides a gain correction factor to achieve a nominal gain in the output clock generator for a desired loop bandwidth. In this manner, PLLs in different clock domains can be calibrated to have similar jitter responses. If the loop bandwidths of all PLLs in an IC are calibrated to the desired loop bandwidth, they will have similar responses to jitter in the reference clock, maintaining negligible relative timing uncertainty and a high-performance interface. The PLL feedback loop detects the time difference between the reference clock and a feedback signal based on the output clock. The PLL includes an output clock generator that adjusts the output clock to reduce the time difference. The gain of the output clock generator, determined in part by the DCO, is one factor that determines how the output clock generator responds to reference clock jitter. Due to differences in manufacturing processes and circuit environments, the DCO gain, and therefore the output clock generator gain, can vary from one PLL to another. Calibration circuitry can be used to determine and apply a gain correction factor that adjusts the output clock generator gain to a nominal gain corresponding to the desired loop bandwidth in the PLL.

[0004] In one exemplary aspect, a PLL is disclosed, comprising: a delta detector configured to receive a reference clock and a feedback signal and generate a delta value indicating a time difference between the reference clock and the feedback signal; and a frequency divider circuit configured to receive an output clock and generate a feedback signal based on the output clock. The PLL includes an output clock generator configured to receive the delta value, generate a control signal based on the delta value, and generate the output clock signal based on the control signal. The PLL also includes a calibration circuit configured to provide a gain correction factor to the output clock generator, wherein the output clock generator is further configured to adjust gain in response to the gain correction factor.

[0005] In another exemplary aspect, a method for generating an output clock in a phase-locked loop is disclosed. The method includes: receiving a reference clock and a feedback signal in a delta detector; generating a delta value indicative of a time difference between the reference clock and the feedback signal in the delta detector; receiving an output clock in a frequency divider circuit; and generating the feedback signal based on the output clock. The method also includes: receiving the delta value in an output clock generator; generating a control signal based on the delta value; and generating the output clock based on the control signal. The method also includes: providing a gain correction factor to the output clock generator by a calibration circuit; and adjusting the gain of the output clock generator in response to the gain correction factor.

[0006] In another exemplary aspect, an IC is disclosed. The IC includes logic circuitry arranged in multiple clock domains, each clock domain including multiple PLLs configured to generate clocks to be provided to the logic circuitry in the corresponding clock domain. Each PLL in the IC includes: an increment detector configured to receive a reference clock and a feedback signal and generate an increment value indicating a time difference between the reference clock and the feedback signal; and a divider circuit configured to receive an output clock and generate a feedback signal based on the output clock. The PLL includes an output clock generator configured to receive the increment value, generate a control signal based on the increment value, and generate an output clock signal based on the control signal. The PLL also includes a calibration circuit configured to provide a gain correction factor to the output clock generator, wherein the output clock generator is further configured to adjust gain in response to the gain correction factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

[0008] Figure 1A is a block diagram of a phase-locked loop (PLL) configured for two-point injection;

[0009] Figure 1B and Figure 1C They are Figure 1A 1 is a diagram of a signal injected into a PLL and an output signal modulated on an output clock based on the injected signal;

[0010] Figure 2 is a first example of an exemplary PLL including a calibration circuit configured to provide a gain correction factor to adjust an output clock generator to a nominal gain corresponding to a desired PLL loop bandwidth;

[0011] Figure 3is a flow chart of a method of generating an output clock in a PLL, the method comprising providing a gain correction factor to adjust the output clock generator to a nominal gain;

[0012] Figure 4 is a second example of an exemplary PLL including a calibration circuit configured to provide a gain correction factor to adjust an output clock generator to a nominal gain corresponding to a desired PLL loop bandwidth;

[0013] Figure 5 yes Figure 2 An example of a PLL in a system configured to determine and store gain correction factors for a plurality of frequencies of an output clock generator in the PLL;

[0014] Figure 6 yes Figure 4 An example of a PLL in a PLL configured to determine and store gain correction factors for multiple frequencies of an output clock generator in the PLL; and

[0015] Figure 7 is a block diagram of an exemplary processor-based system including a plurality of devices coupled together via a system bus, wherein the processor-based system includes at least one integrated circuit (IC), the IC including a plurality of clock domains, each clock domain having a PLL including a calibration circuit configured to provide a gain correction factor to adjust an output clock generator to a nominal gain to normalize a jitter response on the IC. DETAILED DESCRIPTION

[0016] Several exemplary aspects of the present disclosure are described with reference to the accompanying drawings. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0017] Example aspects disclosed herein include a phase-locked loop (PLL) including a digitally controlled oscillator (DCO) gain calibration circuit. Also disclosed are related methods for DCO gain calibration. Synchronization of clocks in different clock domains of an integrated circuit (IC) is important in high-performance interfaces between those clock domains. PLLs can achieve synchronization between clock domains by generating domain clocks based on the same reference clock. However, if the PLLs do not respond to jitter in the same manner, jitter in the reference clock signal can disrupt synchronization. In the example PLLs disclosed herein, a calibration circuit provides a gain correction factor to achieve a nominal gain in the output clock generator for a desired loop bandwidth. In this manner, PLLs in different clock domains can be calibrated to have similar jitter responses. If the loop bandwidths of all PLLs in an IC are calibrated to the desired loop bandwidth, they will have similar responses to jitter in the reference clock, maintaining negligible relative timing uncertainty and a high-performance interface. The PLL feedback loop detects the time difference between the reference clock and a feedback signal based on the output clock. The PLL includes an output clock generator that adjusts the output clock to reduce the time difference. The gain of the output clock generator, determined in part by the DCO, is one factor that determines how the output clock generator responds to reference clock jitter. Due to differences in manufacturing processes and circuit environments, the DCO gain, and therefore the output clock generator gain, can vary from one PLL to another. Calibration circuitry can be used to determine and apply a gain correction factor that adjusts the output clock generator gain to a nominal gain corresponding to the desired loop bandwidth in the PLL.

[0018] Figure 1A Is to Figure 2 1. Block diagram of a phase-locked loop (PLL) 100 referenced in the following explanation of two-point injection employed in a calibration circuit 202 in a PLL 200 in FIG.

[0019] The PLL 100 includes a delta detector 102, an output clock generator 104, and a frequency divider circuit 106. The delta detector 102 receives a reference clock CLK_REF and a feedback signal FB from the frequency divider circuit 106. The reference clock CLK_REF is received from an external source such as a crystal controlled oscillator and is fed back at a reference frequency F REF The feedback signal FB is at the same frequency F as the reference clock CLK_REF. REF Same or very close frequency F FB The delta detector 102 determines a delta time DT, which is the time difference between the reference clock CLK_REF and the feedback signal FB. The delta time DT is digitally quantized into a delta value DV (eg, a binary number) generated by the delta detector 102 .

[0020] The output clock generator 104 receives the increment value DV and generates an output clock CLK_OUT based on the increment value DV. The output clock CLK_OUT includes the phase difference and frequency difference information between CLK_REF and CLK_OUT, so that the output clock frequency F OUT Generates the output clock CLK_OUT, which has a frequency of F OUT is the reference frequency F REF The frequency divider circuit 106 outputs the clock frequency F OUT Receive the output clock CLK_OUT and divide the output clock CLK_OUT (eg, divide by an integer multiple N) to generate a reference frequency F REF A feedback signal FB is generated.

[0021] In more detail, the delta detector 102 includes a phase frequency detector (PFD) 108 and a time-to-digital converter (TDC) 110. The PFD 108 receives a reference clock CLK_REF and a feedback signal FB, detects a delta time DT, and indicates the delta time DT as the time difference between a start signal STRT and a stop signal STOP provided to the TDC 110. For example, the delta time DT may be the time between a rising edge (e.g., a rising edge of a voltage) of the start signal STRT and a rising edge of the stop signal STOP. The TDC 110 quantizes the delta time DT in digital form into a binary value, which is provided to the output clock generator 104 as a delta value DV. The delta value DV may be positive or negative, depending on whether the feedback signal FB leads or lags the reference clock CLK_REF.

[0022] Output clock generator 104 includes a digital low-pass filter (DLF) 112 that generates output clock CLK_OUT and a digitally controlled oscillator (DCO) 114. DLF 112 receives delta value DV from TDC 110, filters out high-frequency noise, and provides a control signal DCO_CTL to DCO 114. DCO 114 adjusts the frequency of output clock CLK_OUT based on control signal DCO_CTL.

[0023] As described above, the PLL 100 is configured for two-point injection. In this regard, the output clock generator 104 further includes a first adder 116 between the DLF 112 and the DCO 114. A second adder 118 is coupled between the frequency divider circuit 106 and the delta detector 102. The positions of the first adder 116 and the second adder 118 are selected to provide a full-pass transfer function for the injected signal 120. The injection from the first adder 116 to the output clock CLK_OUT has only the DCO 114 in the feedforward path, thereby generating a high-pass transfer function that boosts higher frequency inputs above the first "corner" frequency. From the second adder 118 to the output clock CLK_OUT, the PLL 100 has a low-pass transfer function that filters out high-frequency inputs above the second "corner" frequency. By adding the injected signal 120 to the feedback signal FB in the second adder 118 and also adding the injected signal 120′ to the control signal DCO_CTL in the first adder 116, the combination of the high-pass and low-pass filtering of the loop produces an all-pass transfer function if the first corner frequency and the second corner frequency are aligned at the same frequency. The injected signal 120′ is a weighted version of the injected signal 120 multiplied by the coefficients required for injection at the first adder 116.

[0024] The injected signal 120 may be added to the output clock CLK_OUT. This may include, for example, adding the function N(z) (see Figure 1B ) and a weighted version (W×N(z)) of the function N(z) is added to the control signal DCO_CTL at the first adder 116. The coefficient W is used at the first adder 116 to account for the difference in injection points. In the transmitter, the two-point injection can be used to modulate the carrier signal (e.g., CLK_OUT) by adding the injected signal 120 (N(z)) as the data signal to be transmitted. The injected signal 120 with the function N(z) can be seen as N(z) on the output clock CLK_OUT (e.g., by modulation). OUT (See Figure 1C ). Output signal N(z) OUT The relationship with the injected signal 120 depends on the match between the weight factor W and the gain of the DCO 114. When the other components of the PLL are well gain-controlled, it can also be said that the relationship depends on the match between the nominal / target loop bandwidth and the actual loop bandwidth of the PLL 100. In general, the loop bandwidth (LBW) of the PLL 100 is expressed by the following equation:

[0025] LBW=K DD ×K DLF ×K DCO ×1 / 2πN; where:

[0026] K DD = gain of the delta detector 102;

[0027] K DLF = proportional component of the gain of the DLF 112;

[0028] K DCO =frequency gain of DCO 114; and

[0029] N=clock divisor by which the output clock CLK_OUT is divided in the divider circuit 106 to generate the feedback signal FB. Some variables are not illustrated in FIG1 .

[0030] Figure 1B is an example of an injected signal 120 (N(z)) added at the second summer 118 with a weight W applied to the injected signal 120 at the first summer 116 as 120 ′. Figure 1C 1 shows the output signal N(z) that can be generated on the output clock CLK_OUT in response to the injected signal 120 (N(z)) under three different loop bandwidth conditions of the PLL 100. OUT This may be due to the three different gains (K DCO ). Figure 1C The solid line 124 in FIG. 1 illustrates the expected output signal N(z) OUT , the output signal N(z) OUT best corresponds to Figure 1B The injected signal 120 (N(z)) in FIG. 1 is a block diagram of the output signal N(z) generated on the output clock CLK_OUT in the example. OUT , in this example, because the gain K of DCO 114 DCO is lower than expected, so the loop bandwidth is not the desired loop bandwidth. Here, the DCO 114 has a weak response to changes in the injected signal 120, rising and falling slower than expected. In contrast, the long dashed line 128 illustrates the output signal N(z) when the loop bandwidth is not the desired loop bandwidth. OUT , because the gain K DCO is higher than expected, causing the DCO 114 to produce a stronger response than expected (ie, a larger rise and fall than expected). However, the gain K of the DCO 114 DCOThe gain of DCO 114 in PLL 100 may vary from one clock domain to another in an IC in response to these factors, resulting in differences in loop bandwidth and causing PLLs in different clock domains to respond differently to noise or jitter on the reference clock or other points in PLL 100.

[0031] Figure 2 is a block diagram of one example of an exemplary PLL 200 in an IC 201 including a calibration circuit 202 that provides a gain correction factor K CF To achieve a nominal gain K in output clock generator 204 for the desired loop bandwidth in PLL 200 NOM (not shown). IC 201 may include multiple PLLs, each of which may be exemplary PLL 200, each of which provides an output clock to a clock domain of a digital logic circuit. In the calibration method, calibration circuit 202 is first used to determine the gain correction factor K CF And the gain correction factor K CF Stored in the gain control circuit 206 in the calibration circuit 202. After calibration, the output clock generator 204 receives the gain correction factor K from the gain control circuit 206 CF , and adjust the gain of the output clock generator 204 to the nominal gain K NOM , to achieve the desired loop bandwidth.

[0032] Before describing the calibration circuit 202 and the calibration method, details of the PLL 200 are first presented. The PLL 200 corresponds to the PLL 100 configured for two-point injection in FIG1 . The PLL 200 includes a delta detector 208 that receives a reference clock CLK_REF and a feedback signal FB. The delta detector 208 determines a delta value DV that indicates a time difference between the reference clock CLK_REF and the feedback signal FB. The delta detector 208 includes a phase frequency detector 207 and a time-to-digital converter 209. The PLL 200 also includes a frequency divider circuit 210 that receives an output clock CLK_OUT generated by the output clock generator 204 and divides the output clock CLK_OUT to generate the feedback signal FB. The frequency F of the output clock CLK_OUT is 0.01 Hz. OUT Can be tuned to the frequency F of the reference clock CLK_REF REF The frequency divider circuit 210 divides the output clock CLK_OUT by the clock divisor DVSR (eg, N), so that the frequency F of the feedback signalFB The frequency F of the reference clock CLK_REF REF Same or very close.

[0033] The output clock generator 204 receives the delta value DV from the delta detector 208 and generates a control signal DCO_CTL. The DCO 214 in the output clock generator 204 generates the output clock CLK_OUT based on the control signal DCO_CTL. The PLL 200 includes a calibration circuit 202, which includes a gain control circuit 206. The gain control circuit 206 further includes a gain correction accumulator circuit 220 ("accumulator 220") to generate and store the gain correction factor K. CF The gain K of the output clock generator 204 is 204 In response to the gain correction factor K CF Specifically, if the gain K of DCO 214 is DCO Instead of providing the nominal gain K of the desired loop bandwidth of PLL 200 DCO_NOM , then the gain correction factor K CF can be determined and applied to adjust the (total) gain K of the output clock generator 204 204 .

[0034] exist Figure 2 In the PLL 200, the output clock generator 204 includes a digital multiplier circuit 216 coupled to the gain control circuit 206 and the increment detector 208. The digital multiplier circuit 216 receives the gain correction factor K as a multi-bit digital value. CF and the delta value DV, and multiply them together to generate the adjusted delta value DV ADJ Multiply the increment value DV by the gain correction factor K CF The total gain K of the output clock generator 204 is 204 Adjust to the desired nominal gain value at which the PLL 200 has the desired loop bandwidth for all-pass transfer capability. Gain correction factor K CF can be applied to each PLL in the IC to provide similar (if not identical) responses to jitter in the reference clock CLK_REF. The consistent jitter response minimizes synchronization problems between clocks in different clock domains, thereby maintaining optimized interface conditions between clock domains. Within the output clock generator 204, the adjusted delta value DV ADJ is provided to a digital low pass filter (DLF) 218 which is based on the adjusted delta value DV ADJ Adder 234, discussed further below, does not modify control signal DCO_CTL during normal operation.

[0035] exist Figure 2 In an alternative to the illustrated example (not shown), the output clock generator 204 would not include the digital multiplier circuit 216. Alternatively, the DLF 218 could receive the delta value DV directly from the delta detector 208 and generate a value to be provided to the output clock generator 204. Figure 2 The multiplier receives the filtered incremental value FDV and the gain correction factor K. CF , and multiply them together to generate the control signal DCO_CTL that is provided to the DCO 214. In essence, the digital multiplier circuit 216 is simply moved from the input to the output of the DLF 218. This alternative example is possible because the gain correction factor K CF Can be applied to the incremental value DV (in Figure 2 in the example shown) or the filtered delta value FDV (in an alternative example).

[0036] Back to Figure 2 The features of the calibration circuit 202 are described in the context of a method of calibrating the PLL 200, the method including determining that the PLL 200 has a nominal gain K NOM Required gain correction factor K CF Gain correction factor K CF is stored in the accumulator 220. The calibration relies on aspects of the two-point injection method. Figures 1A to 1C As described above, if the first corner frequency of the high-pass transfer function of DCO 214 corresponds to the second corner frequency of the low-pass transfer function of PLL 200, the loop bandwidth of PLL 200 will provide a full-pass transfer function from N(z) to the output clock CLK_OUT. The alignment of the first corner frequency and the second corner frequency depends in part on the gain at the nominal value K. DCO_NOM The gain K of the DCO 214 DCO , but the gain K DCO Can vary due to various manufacturing and environmental factors. Determine the gain K DCO Is it at the nominal gain value K? DCO_NOM This may include monitoring the response of the PLL 200 to two-point injection of signals. At this point, corresponding calibration signals FB_CALSIG and DCO_CALSIG are injected into the feedback signal FB and the control signal DCO_CTL, respectively. DCO_CALSIG is a weighted version of FB_CALSIG, with a weight factor W=F REF / K DCO_NOM , that is, DCO_CALSIG=F REF / K DCO_NOM×FB_CALSIG. FB_CALSIG is added to the divisor DVSR of the frequency divider circuit 210 to obtain the value of F REF ×FB_CALSIG gives the value of F OUT At the same time, the gain calibration adjusts GCA (when K CF = 1, that is, when the gain control circuit 206 has not yet started, DCO_CALSIG) is injected into DCO_CTL to immediately use F REF / K DCO_NOM ×FB_CALSIG×K DCO Change F OUT If K DCO_NOM =K DCO , then the two injections contribute exactly the same frequency change to the full-pass transfer. Otherwise, the access gain of the low-pass or high-pass path will cause output distortion, such as Figure 1C This distortion will generate a time error (represented by the delta value DV), which is then collected by the gain control circuit 206 to generate an error gradient for the gain syndrome calculation in a least mean square (LMS) manner. After some iterations, the final gain syndrome K CF The value will be very close to K DCO_NOM / K DCO The calibration resolution is determined by the bit length used in the accumulator 220 .

[0037] In this example, the calibration input FB_CALSIG is a series of pulses (having only two levels, "0" and "1"). Each of these pulses has a duration of multiple cycles (e.g., M cycles) of the reference clock CLK_REF. As explained in more detail below, the pulses of the calibration signal FB_CALSIG cause the divider circuit 210 to increment the clock divisor DVSR (e.g., from N to N+1). The increment value DV is monitored / collected during the positive pulses of the calibration signal FB_CALSIG (implemented by an AND logic circuit ("gate") 228). The accumulator 220 adds the gain correction factor K CF Initialized to a value of “1”. In each cycle of FB_CALSIG, the accumulator 220 incrementally increases or decreases the gain correction factor K based on the error gradient (ie, the output of gate 228). CF , until K CF Pretty close to the target K with preset resolution DCO_NOM / K DCO .

[0038] Also occurring during a pulse of the calibration signal FB_CALSIG in each cycle of the reference clock CLK_REF, the gain correction factor K CFThe nominal calibration value DCO_CALSIG is multiplied by the nominal calibration value DCO_CALSIG to generate the gain calibration adjustment GCA, which is the product of the multiplication. The gain calibration adjustment GCA is injected (i.e., added) into the control signal DCO_CTL. The nominal calibration value DCO_CALSIG corresponds to a weighted version of the injected signal 120 in FIG. 1 discussed above, and the weighting factor is based on the frequency F of the reference clock CLK_REF. REF and the nominal gain K of the DCO 214 DCO_NOM , the nominal gain K DCO_NOM The nominal gain K of the output clock generator 204 further corresponds to the desired loop bandwidth of the PLL 200. NOM When the gain correction factor K CF The output clock generator 204 achieves a nominal gain K NOM When the gain correction factor K CF Stable (i.e., stops or nearly stops increasing).

[0039] The control signal DCO_CTL may depend on the gain correction factor K CF The sign of is increased or decreased by the gain calibration adjustment GCA. In this way, the gain correction factor K is adjusted in one cycle of the reference clock CLK_REF. CF The change of causes the control signal DCO_CTL to be adjusted, which causes the output clock CLK_OUT to be changed, and the increment value DV reflects the adjustment in the next cycle. After a number of cycles of the reference clock CLK_REF (during the pulse of the calibration signal FB_CALSIG), the gain correction factor K is changed. CF The effect of this is that the increment value DV decreases, so the accumulator 220 stops adjusting the gain correction factor K. CF .

[0040] The pulse of the calibration signal FB_CALSIG can be a period of time (for example, from 0V to the power supply voltage V DD Between pulses of the calibration signal FB_CALSIG (e.g., when at 0 volts), the clock divisor DVSR returns from N+1 to N, and the accumulator 220 does not modify the gain correction factor K in the accumulator circuit 220. CF , and the gain calibration adjustment GCA does not modify the control signal DCO_CTL. After repeating the above operation for multiple pulses of the calibration signal FB_CALSIG, the gain correction factor K CF remains stable and the desired loop bandwidth has been achieved. Upon completion of the calibration method, as described above, during normal operation (eg, thereafter), the gain correction factor K CF is provided to output clock generator 204 for operation of PLL 200 at the desired loop bandwidth.

[0041] As described above, the accumulator circuit 220 is included in the gain control circuit 206 in the calibration circuit 202 . Figure 2 Additional features of the illustrated calibration circuit 202 include the following. The calibration signal FB_CALSIG is generated by a signal divider 224 that receives the feedback signal FB and generates the calibration signal FB_CALSIG based on the feedback signal FB. During the pulse, the calibration signal FB_CALSIG is active and may be at the supply voltage V DD Between pulses, the calibration signal FB_CALSIG may be at a low voltage (eg, ground, V SS and / or 0 volts). When calibration is enabled by the calibration enable signal CALIB_EN, switch 226 couples the signal divider 224 to the divider circuit 210. The feedback signal FB can be divided by the integer value 2M to generate the calibration signal FB_CALSIG, where each pulse has a duration of M cycles of the feedback signal FB. In response to the calibration signal FB_CALSIG being active (e.g., during a pulse of the calibration signal FB_CALSIG), an AND gate 228 passes the incremental value DV to the accumulator 220. Another AND gate 230 determines whether the nominal calibration value DCO_CALSIG is multiplied by the gain correction factor K. CF , which causes the gain calibration adjustment GCA to be injected into the control signal DCO_CTL. The multiplier circuit 232 multiplies the nominal calibration value DCO_CALSIG by the gain correction factor K CF The adder 234 multiplies the nominal calibration value DCO_CALSIG by the gain correction factor K CF The gain calibration adjustment GCA of the product of is added to the control signal DCO_CTL. The specific details of the calibration circuit 202 and calibration method described above are non-limiting examples.

[0042] Figure 3 3 is a flow chart illustrating a method 300 for adjusting the gain of a PLL 200. The method includes receiving a reference clock CLK_REF and a feedback signal FB in a delta detector 208 (block 302) and generating a delta value DV indicating a time difference between the reference clock CLK_REF and the feedback signal FB (block 304). The method includes receiving an output clock CLK_OUT in a divider circuit 210 (block 306) and dividing the output clock CLK_OUT to generate a feedback signal FB (block 308). The method includes receiving the delta value DV in an output clock generator 204 (block 310), generating a control signal DCO_CTL based on the delta value DV (block 312), and generating an output clock CLK_OUT based on the control signal DCO_CTL (block 314). The method also includes storing a gain correction factor K in a gain control circuit 206 in the calibration circuit 202.CF (Block 316), the gain correction factor K CF Provided to the output clock generator 204 (block 318) and in response to the gain correction factor K CF The gain is adjusted in the output clock generator 204 (block 320 ).

[0043] Figure 4 is a block diagram of a second example of an exemplary PLL 400 that includes a calibration circuit 402 that converts a gain correction factor K DCF Provided to the output clock generator 404 to achieve a nominal gain K for the desired loop bandwidth NOM . With Figure 2 Features similar to functions Figure 4 As a reminder, in the above-described PLL 200, adjusting the gain of the output clock generator 204 includes multiplying the increment value DV by the gain correction factor K CF , to generate the adjusted increment value DV in the output clock generator 204 ADJ Adjustment increment value DV ADJ and the gain K of the DCO 214 DC0 Provides a nominal (eg, desired) gain K in the output clock generator 204 NOM In contrast, as described below, adjusting the gain of the output clock generator 404 in the PLL 400 includes adjusting the gain of the output clock generator 404 based on the gain correction factor K DCF To adjust the bias current of the ring oscillator 442 in the DCO 406 to achieve the nominal gain K in the DCO 406 DCO_NOM , the nominal gain K DCO_NOM Corresponding to the nominal gain K in the output clock generator 404 NOM .

[0044] PLL 400 includes components corresponding to those described in detail above. Figure 2 The incremental detector 408 and the frequency divider circuit 410 of the incremental detector 208 and the frequency divider circuit 210 in FIG. The incremental detector 408 includes a phase frequency detector 407 and a TDC circuit 409. The calibration circuit 402 includes Figure 2 features of the calibration circuit 202, but Figure 4 The gain correction factor K in DCF With Figure 2 The gain correction factor K in CF The gain of output clock generator 404 is adjusted in a different manner than the gain of output clock generator 204. In addition, output clock generator 404 does not include the same Figure 2In contrast, the gain control circuit 412 controls the bias current slices 414(1) to 414(X) in the DCO 406 to directly adjust the frequency response of the DCO 406 to the control signal DCO_CTL. The bias current slices 414(1) to 414(X) are each coupled to a supply voltage V DD Adjusting the gain of the output clock generator 404 includes adjusting the gain correction factor K based on the gain correction factor K. DCF is activated to provide power to the DCO 406 to achieve the gain K of the output clock generator 404. NOM The number of bias current slices 414(1) to bias current slices 414(X).

[0045] Regarding the structural details, the calibration circuit 402 includes a signal divider 416, which is based on the feedback signal FB with a reference Figure 2 The calibration signal FB_CALSIG is generated in the manner described above. The calibration circuit 402 further includes a switch 418 for coupling the signal divider 416 to the divider circuit 410 in response to the calibration enable signal CALIB_EN. During a pulse of the calibration signal FB_CALSIG, the divider circuit 410 increments the clock divisor DVSR (e.g., from N to N+1), causing the feedback signal FB to diverge from the reference clock CLK_REF and provide a first injection point in the two-point injection method.

[0046] AND gate 422 provides the delta value DV to an accumulator circuit ("accumulator") 420 in gain control circuit 412. As described above, accumulator 420 can implement an LMS algorithm to determine a stable gain indicator STBL over multiple cycles of reference clock CLK_REF that occur during pulses of calibration signal FB_CALSIG. Gain control circuit 412 includes multiplier circuit 426 and another AND logic circuit 428. In response to calibration signal FB_CALSIG (which is active), AND gate 428 multiplies DCO_CALSIG by a weighting factor F REF / K DCO_NOM is distributed to the multiplier circuit 426. The multiplier circuit 426 multiplies the nominal calibration value DCO_CALSIG by the stable gain indicator STBL to generate the gain calibration adjustment GCA. The adder circuit 430 coupled between the DLF 432 and the DCO 406 is provided to the second injection point in the PLL 400, as described above, where the gain calibration adjustment GCA is added to the control signal DCO_CTL. The calibration signal DCO_CALSIG is based on the frequency F of the reference clock CLK_REF. REF and the nominal gain K of the DCO 406 DCO_NOM(which in part determines the nominal gain K of the output clock generator 404 NOM ). When the output clock generator 404 responds to the gain correction factor K DCF To achieve the nominal gain K NOM (This corresponds to the DCO 406 achieving a nominal gain of K DCO_NOM ), the stable gain indicator STBL is stable.

[0047] Gain correction factor K DCF Based on the stable gain indicator STBL, a value is generated and stored in the second accumulator circuit 434 in the gain control circuit 412. Specifically, the gain control circuit 412 includes a clamp circuit 436 that receives the stable gain indicator STBL and generates an incremental adjustment INCR that is provided to the second accumulator circuit 434. The clamp circuit 436 also receives the high value and the low value of the desired range in which the stable gain indicator STBL will stabilize. In response to the stable gain indicator STBL being above the high value or below the low value, the clamp circuit 436 causes the incremental adjustment INCR to indicate whether the second accumulator circuit 434 should be increased, decreased, or remain unchanged (e.g., having a value of +1, -1, or 0) to achieve and remain between the high value and the low value.

[0048] As mentioned above, the gain correction factor K DCF The second accumulator circuit 434 generates a gain correction factor K. DCF As a digital signal, it determines how many current cells are activated. When the calibration of the output clock generator 404 is started, the gain correction factor K DCF In response to the incremental adjustment INCR, the second accumulator circuit 434 gradually increases or decreases the gain correction factor K based on the stable gain indicator STBL. DCF , the stable gain indicator STBL is based on the increment value DV. The change in the current flowing into the DCO 406 increases or decreases the frequency gain of the output clock CLK_OUT accordingly. After a number of cycles of the reference clock CLK_REF with the calibration signal FB_CALSIG active (i.e., during a pulse), the gain correction factor K stored in the second accumulator circuit 434 is DCF Increasing or decreasing the number of active bias current slices 414 ( 1 ) to active bias current slices 414 (X), the output clock CLK_OUT is adjusted, the delta value DV is reduced, and the stable gain indicator STBL stabilizes at a value in the desired range between the high value and the low value provided to the clamp circuit 436 .

[0049] Depending on the number X of bias current slices 414(1) to 414(X), the gain correction factor K DCF Can be a low granularity value (e.g. a binary word with a large number of decimal places). Gain correction factor K DCF is adjusted gradually because each incremental change can significantly change the amount of current going to the DCO 406. The gradual adjustment gives the PLL 400 enough time to respond to the gain correction factor K DCF In this regard, the gain control circuit 412 further includes a counter circuit 438 ("counter 438") that is incremented with each pulse of the feedback signal FB until the counter value reaches a maximum number, which indicates the expiration of the calibration period. After reaching the maximum number, the counter 438 is reset and begins counting again. The second accumulator circuit 434 is timed at each calibration period when the most significant bit (MSB) of the counter value of the counter 438 transitions (e.g., from 1 to 0). In this manner, the second accumulator circuit 434 adjusts the gain correction factor K only at each period between transitions of the MSB of the counter 438. DCF Once again, to ensure that the gain correction factor K DCF gradual adjustment.

[0050] Regarding DCO 406, Figure 4 The example includes a current matching circuit 440 controlled by a control signal DCO_CTL and a ring oscillator 442 tuned by bias current sheets 414(1) to 414(X). The bias current sheets 414(1) to 414(X) are coupled in parallel to a power rail (not shown) to provide a power supply voltage (e.g., V DD The number of bias current slices 414(1) to 414(X) activated to provide power to the DCO 406 is based on the gain correction factor K DCF The operation of these features will be understood by those skilled in the relevant art.

[0051] Figure 5 and 6 illustrate Figure 2 PLL 200 and Figure 4 A variation of the PLL 400 in FIG. 4 is modified to be configurable to a nominal gain K at multiple operating frequencies. NOM .

[0052] Figure 5 Corresponding to Figure 2Features of PLL 500 are similarly numbered and are not explained again here. Calibration circuit 502 includes a gain control circuit 504 corresponding to gain control circuit 206, including AND gates 228 and 230, multiplier circuit 232, and adder 234. In place of accumulator 220, gain control circuit 504 includes accumulators 506(1) through accumulator 506(K), where K is the number of frequencies for which PLL 500 can be calibrated. Multiplexer 508 and multiplexer 510 are controlled by control logic (not shown), which can be internal or external to PLL 500. Each of the multiple output clock frequencies for which PLL 500 is calibrated corresponds to an integer N1 through an integer NK used as a divisor DVSR. Multiplexer 508 is used to select one of the plurality of accumulators 506(1) to accumulator 506(K) at a time for storing a gain correction factor K determined at one of K different frequencies during calibration. CF (1) to gain correction factor K CF (K). The multiplexer 510 is controlled to select the gain correction factor K corresponding to the PLL operating frequency CF (1) to gain correction factor K CF At each of the calibration frequencies corresponding to integers N1 to NK, the operation of the calibration circuit 502 corresponds to Figure 2 The operation of the calibration circuit 202 in FIG.

[0053] Figure 6 The PLL 600 in FIG. 1 essentially corresponds to Figure 4 4, and therefore similar features are similarly numbered and not explained here. PLL 600 differs from PLL 400 in that calibration circuit 602 includes gain control circuit 604, because PLL 600 can also be calibrated at multiple frequencies corresponding to different integer clock divisors DVSR. Gain control circuit 604 corresponds to gain control circuit 412 at each of the multiple frequencies, but similar to PLL 500, PLL 600 can be calibrated to multiple (K) frequencies. In this regard, Figure 4 The second accumulator circuit 434 has been connected with Figure 5 The accumulators 506(1) to 506(K) and the multiplexers 508 and 510 in the frequency divider circuit 410 are replaced by second accumulator circuits 605 and multiplexers 608 and 610 corresponding to the accumulators 506(1) to 506(K) in the frequency divider circuit 410. The multiplexers 608 and 610 are used to select one of the accumulator circuits 606(1) to 606(K) for generating and storing the output clock frequency F at each integer clock divisor DVSR(N) provided to the frequency divider circuit 410.OUT The corresponding gain correction factor K DCF At each individual calibration frequency, the operation of the calibration circuit 602 corresponds to Figure 4 The operation of the calibration circuit 402 in FIG.

[0054] Figure 7 is a block diagram of an exemplary processor-based system 700 including a processor 702 (e.g., a microprocessor) that includes instruction processing circuitry 704. Processor-based system 700 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, processor-based system 700 includes processor 702. Processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, or the like. More specifically, processor 702 can be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming for communicating produced values resulting from the execution of producer instructions. Processor 702 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, processor 702 includes an instruction cache 706 for temporary, fast-access memory storage of instructions accessible by instruction processing circuitry 704. Instructions fetched or prefetched from memory, such as main memory 708, via system bus 710 are stored in instruction cache 706. Data may be stored in cache memory 712 coupled to system bus 710 for low-latency access by processor 702. Instruction processing circuitry 704 is configured to process instructions fetched into instruction cache 706 and process the instructions for execution.

[0055] The processor 702 and main memory 708 are coupled to a system bus 710 and may be coupled to peripheral devices included in the processor-based system 700. As is well known, the processor 702 communicates with these other devices by exchanging address, control, and data information via the system bus 710. For example, the processor 702 may communicate bus transaction requests to the memory controller 714 in the main memory 708 as an example of a slave device. Although not shown in FIG. Figure 77. Although not illustrated in FIG. 7 , multiple system buses 710 may be provided, each of which may be configured differently. In this example, a memory controller 714 is configured to provide memory access requests to a memory array 716 in the main memory 708. The memory array 716 includes an array of memory bit cells for storing data. As non-limiting examples, the main memory 708 may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and / or static memory (e.g., flash memory, SRAM, etc.).

[0056] Other devices may be connected to the system bus 710. Figure 7 As described in , these devices may include, by way of example, main memory 708, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. The input device(s) 718 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 720 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The modem 722 may be any device configured to allow data to be exchanged with a network 726. The network 726 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH TM The modem 722 may be configured to support any desired communication protocol. The processor 702 may also be configured to access the display controller(s) 724 via the system bus 710 to control information sent to one or more displays 728. The display 728 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, and the like.

[0057] Figure 7 The processor-based system 700 in FIG. 7 may include a set of instructions 730 to be executed by the processor 702 for any application desired according to the instructions. The instructions 730 may be stored in the main memory 708, the processor 702, and / or the instruction cache 706 (as examples of non-transitory computer-readable media 732). The instructions 730 may also reside completely or at least partially within the main memory 708 and / or within the processor 702 during execution thereof. The instructions 730 may also be transmitted or received over the network 726 via the modem 722, such that the network 726 includes the computer-readable media 732.

[0058] like Figure 2 、 Figure 4 、 Figure 5and Figure 6 As described in , any circuit in the processor-based system 700 (particularly the modem 722 and the output device 720) may include multiple clock domains, each clock domain including a PLL including a calibration circuit configured to provide a gain correction factor to adjust the output clock generator to a nominal gain to normalize the jitter response on the IC.

[0059] Although the computer-readable medium 1132 is shown as a single medium in the exemplary embodiment, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium that can store, encode, or carry a set of instructions for execution by a processing device and cause the processing device to perform any one or more of the methods of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0060] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be implemented in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0061] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), disk storage media, optical storage media, flash memory devices, etc.), etc.

[0062] Unless specifically stated otherwise, and as is apparent from the foregoing discussion, it should be understood that throughout this specification, discussions utilizing terms such as "process," "compute," "determine," "display," etc., refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memory and transforms it into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage, transmission, or display devices.

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The required structure for various such systems will be apparent from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that various programming languages may be used to implement the teachings of the embodiments as described herein.

[0064] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination thereof. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How to implement this functionality depends on specific applications, design choices, and / or the design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but these implementation decisions should not be interpreted as departing from the scope of the embodiments of the present invention.

[0065] The various illustrative logical blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, the controller may be a processor. The processor may be a microprocessor, but in an alternative embodiment, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0066] The embodiments disclosed herein may be implemented in hardware and in instructions stored in hardware and may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside as discrete components in a remote station, a base station, or a server.

[0067] It should also be noted that the operational steps described in any exemplary embodiment herein are described to provide examples and discussions. The described operations can be performed in many different orders that are different from the illustrated order. In addition, the operations described in a single operational step can actually be performed in a plurality of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that any one of the various technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be cited throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields, light fields, or particles, or any combination thereof.

[0068] Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order. Therefore, in the absence of a method claim actually reciting the order in which its steps are to be followed, or in the absence of another specific statement in the claims or specification that the steps are to be limited to a specific order, it is in no way intended that any specific order be inferred.

[0069] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments that incorporate the spirit and substance of the present invention may occur to those skilled in the art, the present invention should be construed as including all within the scope of the appended claims and their equivalents.

Claims

1. A phase-locked loop, comprising: Delta detector, configured as: Receive reference clock (CLK_REF) and feedback signal (CLK_FB); as well as generating a delta value (DV) indicative of a time difference between the reference clock (CLK_REF) and the feedback signal (CLK_FB); The frequency divider circuit is configured as: Receive output clock (CLK_OUT); and generating the feedback signal (CLK_FB) based on the output clock (CLK_OUT); Output clock generator, configured as: receiving the delta value (DV); generating a control signal (DCO_CTL) based on the delta value (DV); and generating the output clock (CLK_OUT) based on the control signal (DCO_CTL); as well as The calibration circuit is configured to convert the gain correction factor (K CF ) is provided to the output clock generator, The output clock generator is further configured to respond to the gain correction factor (K CF ) and adjust the gain (K 204 ).

2. The phase-locked loop according to claim 1 , wherein the output clock generator further comprises: a first multiplier circuit coupled to the calibration circuit and the delta detector and configured to multiply the delta value by the gain correction factor to generate an adjusted delta value; as well as A digital low-pass filter is coupled to the first multiplier circuit and configured to generate the control signal based on the adjusted delta value.

3. The phase-locked loop according to claim 1 , wherein the output clock generator further comprises: a digital low-pass filter configured to generate a filtered delta value based on the delta value; A first multiplier circuit is configured to multiply the increment value by the gain correction factor to generate the control signal.

4. The phase-locked loop of claim 1 , the output clock generator comprising a digitally controlled oscillator (DCO), the DCO including bias current slices coupled in parallel with a power rail, wherein the number of bias current slices activated to provide power to the DCO is based on the gain correction factor. 5 . The phase-locked loop of claim 4 , the DCO further comprising a ring oscillator circuit, wherein the number of activated bias current slices provides power to the ring oscillator circuit.

6. The phase-locked loop according to claim 1 , wherein the calibration circuit further comprises: calibrating the multiplier circuit; as well as Adder circuit, in: The frequency divider circuit is configured as: dividing the output clock by a clock divisor to generate the feedback signal; and incrementing the clock divisor in response to a calibration signal; and The calibration circuit is further configured to: in response to the calibration signal: in the calibration multiplier circuit, multiplying the gain correction factor by a nominal calibration value to generate an injected calibration adjustment; adding the injected calibration adjustment to the control signal in the adder circuit; and In each of a plurality of cycles of the reference clock, the gain correction factor is incrementally adjusted based on the delta value in each of the plurality of cycles.

7. The phase-locked loop according to claim 1 , wherein the calibration circuit further comprises: an accumulator circuit configured to store the gain correction factor; calibrating the multiplier circuit; Injection circuit, in: The frequency divider circuit is configured as: dividing the output clock by a clock divisor to generate the feedback signal; and incrementing the clock divisor in response to a calibration signal; and The calibration circuit is configured to: in response to the calibration signal: multiplying the gain correction factor by a nominal calibration value by the calibration multiplier circuit to generate a gain calibration adjustment; adding, by the injection circuit, the gain calibration adjustment to the control signal; and The gain correction factor stored in the accumulator circuit is adjusted based on the increment value during each of a plurality of cycles of the reference clock.

8. The phase-locked loop according to claim 7, wherein the calibration circuit further comprises: Clamping circuit; as well as Counter circuit, in: The clamp circuit is configured to: determining whether the gain correction factor is within an expected range; and generating a gain adjustment in response to the determining; The counter circuit is configured to count the number of cycles of the reference clock; and The calibration circuit is configured to adjust the gain correction factor based on the gain adjustment in each cycle.

9. The phase-locked loop according to claim 6, wherein the calibration circuit further comprises: Signal divider, configured as: receiving the feedback signal; generating a calibration signal based on the feedback signal; as well as changing the clock divisor provided to the frequency divider circuit in response to the calibration signal; as well as a first logic circuit configured to provide the increment value to the accumulator circuit in response to the calibration signal; as well as A second logic circuit is configured to provide the nominal calibration value to the calibration multiplier circuit in response to the calibration signal.

10. The phase-locked loop according to claim 7, wherein the calibration circuit further comprises: Signal divider, configured as: receiving the feedback signal; generating a calibration signal based on the feedback signal; as well as changing the clock divisor provided to the frequency divider circuit in response to the calibration signal; as well as a first logic circuit configured to provide the increment value to the accumulator circuit in response to the calibration signal; as well as A second logic circuit is configured to provide the nominal calibration value to the calibration multiplier circuit in response to the calibration signal.

11. The phase-locked loop of claim 1, wherein the calibration circuit comprises a plurality of accumulators, each accumulator corresponding to one of a plurality of output clock frequencies.

12. A method of generating an output signal (CLK_OUT) in a phase-locked loop, the method comprising: Receive a reference clock (CLK_REF) and a feedback signal (CLK_FB) in a delta detector; generating, in the delta detector, a delta value (DV) indicating a time difference between the reference clock (CLK_REF) and the feedback signal (CLK_FB); receiving the output clock (CLK_OUT) in the divider circuit; generating the feedback signal (CLK_FB) based on the output clock (CLK_OUT); receiving said delta value (DV) in an output clock generator; generating a control signal (DCO_CTL) based on the delta value (DV); generating the output clock (CLK_OUT) based on the control signal (DCO_CTL); The gain correction factor (K CF ) is provided to the output clock generator; as well as In response to the gain correction factor (K CF ) and adjust the gain (K 204 ).

13. The method of claim 12 , wherein adjusting the gain of the output clock generator in response to the gain correction factor further comprises: multiplying the delta value by the gain correction factor to generate an adjusted delta value; as well as The control signal is generated based on the adjusted delta value.

14. The method of claim 12, wherein adjusting the gain of the output clock generator in response to the gain correction factor further comprises: generating a filtered delta value based on the delta value; as well as The increment value is multiplied by the gain correction factor to generate the control signal.

15. An integrated circuit (IC), comprising: A logic circuit is provided in a plurality of clock domains, each clock domain including a plurality of phase-locked loops (PLLs), the plurality of phase-locked loops (PLLs) being configured to generate a clock provided to the logic circuit in the corresponding clock domain, each PLL including: Delta detector, configured as: Receives a reference clock (CLK_REF) and a feedback signal (CLK_FB); and generating a delta value (DV) indicative of a time difference between the reference clock (CLK_REF) and the feedback signal (CLK_FB); The frequency divider circuit is configured as: Receive output clock (CLK_OUT); and generating the feedback signal (CLK_FB) based on the output clock (CLK_OUT); Output clock generator, configured as: receiving the delta value (DV); generating a control signal (DCO_CTL) based on the delta value (DV); and generating the output clock (CLK_OUT) based on the control signal (DCO_CTL); and A calibration circuit configured to provide a gain correction factor to the output clock generator (K CF ), The output clock generator is further configured to respond to the gain correction factor (K CF ) and adjust the gain (K 204 ).

Images