Method for improving NCO module code generation precision through dynamic weighted phase compensation

Abstract

The invention provides a method for improving NCO module code generation precision through dynamic weighted phase compensation, and the method specifically comprises the following steps: 1, carrying out the calculation in a DSP, and obtaining a frequency control word needed by an NCO module in an FPGA; 2, dividing the control word into an integer part and a decimal part, and transmitting the integer part of the control word to the FPGA through an interface; 3, enabling an error generated by the abandoned decimal part to participate in compensation accumulation every time; 4, distributing reasonable weights for the current moment and the accumulated initial phase; 5, performing dynamic regulation and rounding on a weighted compensation result to obtain a compensation result, and taking an actual residual error as an initial value of next decimal accumulation; sixthly, an interrupt signal is sent to the DSP every time a period of time is accumulated in the FPGA, and the control word is controlled to be updated; 7, combining the integer part of the current control word with the compensated phase compensation result by the FPGA to serve as an actual control word, and controlling an overflow result of the NCO module; and 8, repeating the steps 1 to 7, and performing phase compensation on the control word of the NCO every time.

Description

Technical Field

[0001] The present invention relates to the generation of code NCO, initial code phase and frequency control word phase compensation, FPGA phase spurious, etc., and specifically is a method for improving the NCO module code generation accuracy by dynamic weighted phase compensation. Technical Background

[0002] With the widespread application of the Global Positioning System (GPS) in navigation, surveying and mapping, traffic management, and other fields, the requirements for the accuracy of the ranging codes of global navigation and positioning systems are increasing. In particular, in emerging application areas such as unmanned driving, intelligent transportation systems, and precision agriculture, the demand for high-precision navigation and positioning is particularly prominent. As a core component of the satellite signal system, the accuracy of the ranging code directly affects the accuracy of terminal positioning and has a significant transmission and amplification effect. Therefore, in the design of satellite signal simulators, it is crucial to optimize the accuracy of the ranging code generation module. This not only helps to improve the quality of simulated satellite signals, but also provides more reliable technical support for scientific research and practical applications.

[0003] Based on the aforementioned social context and research needs, this study proposes an optimization method based on dynamic weighted phase compensation to improve the accuracy of ranging codes generated jointly by a DSP (digital signal processor) and an FPGA (field programmable gate array). This method primarily involves key technologies such as code NCO (numerically controlled oscillator) generation, dynamic weighted phase compensation, and FPGA phase spurious correction. Traditional FPGA implementations typically use a flooring method to avoid the computational complexity associated with floating-point number accumulation, but this approach introduces phase accuracy errors. To address this issue, this study proposes an improved solution: First, the frequency control word is decomposed into an integer and a fractional part within the DSP. The fractional part is then processed through dynamic weighted averaging and accumulation. Subsequently, upon the arrival of the next interrupt signal, the integer portion of the accumulated result is sent to the FPGA and added to the integer portion of the current frequency control word to achieve phase compensation. This mechanism effectively improves ranging code generation accuracy.

[0004] Improving the accuracy of analog-generated ranging codes is crucial for the research, development, testing, verification, and operation of global navigation and positioning systems. It not only significantly improves system performance but also reduces development costs and risks, thereby promoting the further development of satellite navigation technology. This research is innovative in that it overcomes the phase accuracy loss inherent in traditional FPGA implementations through the use of a dynamic weighted phase compensation algorithm, providing an effective technical path for generating high-precision ranging codes. Summary of the Invention

[0005] The present invention provides a method for improving the NCO module code generation accuracy through dynamic weighted phase compensation, aiming to solve the cumulative error in frequency control word accumulation caused by the FPGA's ability to perform floating-point number calculations, and thereby address the problem of deterioration of analog signal synchronization caused by ranging code overflow anomalies.

[0006] In order to solve the above problems, the present invention is achieved through the following technical solutions:

[0007] A method for improving NCO module code generation accuracy by dynamic weighted phase compensation includes the following steps:

[0008] Step 1: Calculate the initial phase and frequency control words required by the NCO module in the FPGA chip in the DSP chip;

[0009] Step 2: Divide the initial phase and frequency control words into integer and fractional parts, and pass the integer parts of the initial phase and frequency control words to the FPGA chip through the interface;

[0010] Step 3: Use the error diffusion method to allow the error caused by the fractional part discarded due to the phase spurious problem of the FPGA chip to participate in the compensation accumulation each time;

[0011] Step 4: Use the weighted average compensation method to assign reasonable weights to the current moment and the accumulated initial phase to make the compensation more timely;

[0012] Step 5: Dynamically adjust and round the weighted compensation result to obtain the final compensation result, and use the actual residual error as the initial value for the next decimal accumulation;

[0013] Step 6: The NCO module in the FPGA chip sends an interrupt signal to the DSP every time a period of ΔT is accumulated, which is used to control the update frequency control word;

[0014] Step 7: The FPGA chip combines the integer part of the current frequency control word with the compensated phase compensation result as the actual frequency control word to control the overflow result of the NCO module;

[0015] Step 8: Repeat steps 1 to 7 to perform phase compensation on the frequency control word of the NCO module each time, thereby improving the overflow accuracy of the NCO module and obtaining a higher-precision ranging code for result analysis.

[0016] Preferably, in order to facilitate observation of the results before and after phase compensation, the overflow result of this NCO module is used to generate the ranging code in the satellite navigation signal, and the operating frequency of the FPGA chip is f s , set the chip overflow frequency to f c , then its basic frequency control word The frequency control word contains an integer and a fractional part, wherein the integer part determines the main frequency of the NCO module, and the fractional part is used for the specified frequency adjustment.

[0017] Preferably, in the digital signal processing chip, the frequency control word in step 1 is decomposed into an integer part and a decimal part, that is, N=N int +N float The integer part is directly used to control the basic frequency output of the numerically controlled oscillator NCO module, and the decimal part is used to accurately compensate for the phase difference. The decimal part is accumulated through the accumulation operation. Achieve more continuous frequency adjustment on the time axis;

[0018] When the accumulated value reaches the preset time ΔT, the phase compensation mechanism is triggered to ensure the overall accuracy of the frequency control word. When phase compensation is triggered, the integer portion at this time is stored and transmitted to the current FPGA chip along with other relevant data when the next interrupt signal arrives. At the same time, the remaining decimal portion is retained for the next round of accumulation operation.

[0019] Optimally, given the long period and high precision requirements of the ranging code, we use the error diffusion method to address the fractional errors that were previously discarded due to FPGA phase spurious issues. The error diffusion method is an advanced rounding algorithm that diffuses the rounding error into the subsequent accumulation process, thereby offsetting the error in the long-term accumulation.

[0020] The specific implementation method is to accumulate the originally discarded decimal error part, SUM_N float (n) =SUM_N float (n-1) +N float (n) Then round the result to SUM_N 补 (n) =round(SUM_N float (n) ), retain e for the new error generated after rounding (n) =SUM_N float (n) -SUM_N 补 (n) , rejoin the next accumulation process SUM_N float (n+1) =e (n) +N (n+1) .

[0021] When compensating for fractional errors, introducing an error diffusion method can effectively reduce long-term system error accumulation and lower the overall system error level. However, this method can lead to the problem of delayed manifestation of fractional errors. For example, the error of a certain accumulation result may be within an acceptable range and require no compensation. However, due to the continuous accumulation of previous error values, the current accumulation result reaches the compensation threshold, resulting in a delayed error manifestation. This delay is not conducive to ensuring the overflow accuracy of the current code.

[0022] Using the weighted average compensation method, mSUM_N float (n) =mN(n)+(1-m)SUM_N float (n-1) , assigning more reasonable weights to the current moment and the accumulated initial error, improving the smoothness of the system, making the phase compensation more effective, and thus improving the accuracy of ranging code generation.

[0023] Preferably, the following dynamic hierarchical processing is performed on the decimal error value after weighted averaging. Each time the frequency control word is updated, the compensation result is sent in real time to complete the phase compensation process in the FPGA chip. The specific process is as follows:

[0024] |mSUM_N float (n) -[mSUM_N float (n) ]|<0.5,N 补 =0

[0025] mSUM_N float (n) -[mSUM_N float (n) ]≤-0.5,N 补 =-1

[0026] mSUM_N float (n) -[mSUM_N float (n) ]≥0.5,N 补 =1

[0027] Preferably, the FPGA chip generates an interrupt signal irq(n) based on the clock module at regular intervals and transmits it back to the DSP chip. The interval between two interrupts is ΔT, which is used to update the frequency control word in the DSP chip. While sending the new frequency control word, the DSP chip completes the decimal accumulation within the time period and adds the integer part N of the accumulated result. (n) int The current value is sent to the FPGA chip.

[0028] The NCO generation module in the FPGA chip adds the compensation result to the frequency control word of the current time period after receiving it, and obtains the compensated frequency control word N'(n)=N(n)+N (n) 补 , using it as the control word for the NCO module accumulator overflow result during this period. Specifically, the FPGA chip uses the integer portion of the new frequency control word to control the base frequency of the C / A code generation. Simultaneously, the fractional accumulation mechanism adds the fractional portion to the current adder to estimate and adjust the frequency control word. This compensates for the error caused by discarding the fractional portion of the frequency control word during this period due to phase spurious in the FPGA chip. This accumulation mechanism ensures that the signal phase is corrected even at very small frequency phases.

[0029] As described above, a method of the present invention for dynamically weighted phase compensation to improve the NCO module code generation accuracy has the following characteristics:

[0030] Beneficial effects:

[0031] (1) A phase compensation method is proposed at the theoretical level to solve the phase spurious problem when the NCO module is used to generate the ranging code in the FPGA chip, and to compensate as much as possible for the error caused by the original discard of the decimal part.

[0032] (2) The error diffusion method and dynamic graded rounding method are introduced in the error calculation, which well meets the requirements of long-period high-precision systems such as ranging code generation.

[0033] (3) A weighted average accumulation method is proposed in the error accumulation process to solve the problem of compensation lag caused by error accumulation, making the error compensation process more effective.

[0034] (4) In practical applications, phase compensation can effectively improve the CA code overflow accuracy, thereby improving the signal quality of satellite signal simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following is a brief introduction to the drawings required for use in the prior art. It is obvious that the drawings described below are only some embodiments of the present invention.

[0036] Figure 1 Compensation interrupt trigger timing diagram.

[0037] Figure 2 Flowchart of the phase compensation mechanism.

[0038] Figure 3 Block diagram of data interaction structure between DSP and FPGA.

[0039] Figure 4 Schematic diagram of the NCO module generating ranging codes.

[0040] Figure 5 Comparison chart before and after compensation of ranging code generation frequency accuracy error.

[0041] Figure 6 Algorithm structure flow chart. DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0043] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0044] An embodiment of the present invention provides a method for improving the accuracy of NCO module code generation through dynamic weighted phase compensation. Specifically, the frequency control word calculated in the DSP is divided into an integer and a decimal part. The decimal part that was originally discarded is accumulated through dynamic weighted averaging in the DSP. When the next interrupt signal arrives, the integer part of the result is sent to the FPGA and added to the integer part of the current frequency control word to complete phase compensation and generate a higher-precision ranging code.

[0045] Specific examples

[0046] like Figure 6 As shown, the method step 1: calculate in DSP the initial phase and frequency control words required by the NCO module in FPGA.

[0047] To facilitate observation of the phase compensation results before and after, the NCO overflow is used to generate the CA code. Each NCO overflow produces one CA code chip. The NCO's initial code phase ɑ0 is set to an integer to avoid affecting subsequent calculations. In this invention, ɑ0 is set to 0 during simulation in ModelSim to facilitate calculations.

[0048] The NCO accumulator register in the FPGA has a bit width of 36 and a maximum accumulator value of 2. 36=68719476736, the accumulator overflows once, indicating the generation of a CA code chip. The operating frequency of the FPGA is f s =68MHz, set the chip overflow frequency to f c Frequency = 1.023MHz, then its basic frequency control word Substitute into the calculation

[0049]

[0050] Then calculate the Doppler of the ranging code caused by the movement of the satellite and the user, and convert the Doppler into the carrier and code frequency control word. r ,y r , z r ) and satellite position (x s ,y s , z s ) Calculate geometric distance According to the ionospheric model Klobuchar and the Modified Hopfield tropospheric model, the tropospheric I and ionospheric T delays are calculated and compensated to the pseudorange calculation to calculate the pseudorange φ = λ -1 (r+δt u -δt (s) -I+T)+n+ε φ and the corresponding Doppler frequency shift Used to generate a new frequency control word. Then get the pseudo range φ'=λ at time t+Δt -1 (r'+δ't u -δ't (s) -I'+T')+N'+ε' φ , we get the code pseudorange difference Δφ between time t+Δt and time t. The Doppler frequency shift at each different time will also affect the frequency control word Where c is the speed of light in air, and ΔT = 4ms is the time difference between the two interrupts. The two are added together to form the frequency control word N = N0 + ΔN. This frequency control word consists of an integer and a fractional part. The integer part determines the main frequency of the NCO, while the fractional part is used for frequency regulation.

[0051] Step 2: Divide the initial phase and frequency control words into integer parts and fractional parts, and pass the integer parts of the initial phase and frequency control words to the FPGA through the interface.

[0052] In DSP, the frequency control word N in step 1 is divided into the integer part N int and the decimal part N float , that is, N = N int +N floatThe integer part is used to directly control the basic frequency output of the NCO module, while the decimal part is used to accurately compensate for the phase difference. The values of the decimal part are accumulated, that is, In order to achieve more continuous frequency adjustment on the time axis. When the accumulated time reaches ΔT, phase compensation will be triggered to ensure the overall accuracy of the frequency control word. The integer part SUM_N when the phase compensation is triggered float (n) int Store and transmit to FPGA together when the next interrupt signal comes, the fractional part SUM_N float (n) float Used to return and accumulate again. Compensation interrupt trigger timing is as follows Figure 1 shown.

[0053] Step 3: Use the error diffusion method to allow the error caused by the decimal part discarded due to the phase spurious problem of the FPGA chip to be compensated and accumulated each time.

[0054] Given the long period and high precision requirements of ranging codes, we employ an error diffusion method to address the fractional errors previously discarded due to FPGA phase spurious issues. This advanced rounding algorithm diffuses the rounding error into subsequent accumulation processes, thereby offsetting the error over long-term accumulation.

[0055] SUM_N float (n) =SUM_N float (n-1) +N float (n)

[0056] The above formula is the formula for the accumulation of decimal parts each time, where SUM_N float (n) It is the result of the accumulated error when this interrupt arrives, SUM_N float (n-1) is the cumulative error result of the last interruption moment, N float (n) is the decimal error value of this time.

[0057] The actual error results that should be compensated after reasonable rounding are as follows:

[0058] SUM_N 补 (n) =round(SUM_N float (n) )

[0059] The remaining fractional error after this compensation is not discarded directly, but used as the initial value when the next interrupt arrives and continues to be accumulated. This method effectively ensures that every fractional error value is included in the calculation without losing any data. In a long-cycle system, it can effectively reduce the overall error of the system. The specific implementation effect is as follows:

[0060] e (n) =SUM_N float (n) -SUM_N 补 (n)

[0061] SUM_N float (n+1) =e (n) +N (n+1)

[0062] Step 4: Use the weighted average compensation method to assign reasonable weights to the current moment and the accumulated initial phase to make the compensation more timely.

[0063] Introducing the error diffusion method when compensating for decimal errors can effectively reduce the error accumulation in the long-term system and reduce the overall error of the system, but it will lead to the problem of delayed manifestation of decimal errors. For example, if the error of the accumulated result is not large, it should not be compensated. However, due to the accumulation of previous errors, the accumulated result reaches the compensation threshold, resulting in delayed error manifestation, which is not conducive to the overflow accuracy of this code. To solve this problem, the weighted average compensation method can be used.

[0064] mSUM_N float (n) =mN(n)+(1-m)SUM_N float (n-1)

[0065] Wherein, m is a dynamically adjusted weighting coefficient, and its range is (0<m<1).

[0066] The value of m is determined by the size of each error. When the error is large, increase m to speed up the convergence. When the error is small, decrease m to improve smoothness.

[0067]

[0068] Assigning more reasonable weights to the current moment and the accumulated initial error improves the smoothness of the system, making phase compensation more effective and thus improving the accuracy of ranging code generation.

[0069] Step 5: Dynamically adjust and round the weighted compensation result to obtain the final compensation result, and use the actual residual error as the initial value for the next decimal accumulation.

[0070] For the decimal error value after weighted averaging, the following dynamic control rounding processing is performed. Each time the frequency control word is updated, the compensation result is sent in real time to complete the phase compensation process in the FPGA.

[0071] The following formula is the cumulative result of this interruption after weight processing and the hierarchical rounding threshold. Based on this result, the error value N for each compensation is determined 补 .

[0072] |mSUM_N float (n) -[mSUM_N float (n) ]|≤0.5,N 补 =0

[0073] mSUM_N float (n) -[mSUM_N float (n) ]≤-0.5,N 补 =-1

[0074] mSUM_N float (n) -[mSUM_N float (n) ]≥0.5,N 补 =1

[0075] The initial value for the next decimal part accumulation should be calculated using the actual error value processed by unweighted average, which is more consistent with the actual error. By dynamically adjusting the accumulation process of the decimal part, the accumulation result can be closer to the theoretical value of the continuous-time system.

[0076] SUM_N float (n) =mN(n)+(1-m)SUM_N float (n-1)

[0077] e (n) =SUM_N float (n) -SUM_N 补 (n)

[0078] The above formula is the process of using the actual diffusion error as the initial error value in preparation for the next interruption in this interruption. The phase mechanism process of steps 3, 4, and 5 is as follows: Figure 2 shown.

[0079] Step 6: The NCO module in the FPGA sends an interrupt signal to the DSP every time a period of time (ΔT) is accumulated to control the update frequency control word.

[0080] The FPGA generates an interrupt signal irq(n) based on the clock module at regular intervals and sends it back to the DSP. The interval between two interrupts is ΔT, which is used to update the frequency control word in the DSP. This new frequency control word N(n) represents the signal frequency to be used at the current moment to ensure the generation of the CA code overflow frequency. The data exchange between the DSP and the FPGA is controlled by interrupts. The timing of frequency control update and compensation is as follows: Figure 1 shown.

[0081] While sending the new frequency control word, DSP completes the decimal accumulation within this time period and converts the integer part N of the accumulated result into (n) int The current value is sent to the FPGA, and the fractional part N of the accumulated result is (n) float The initial value to be accumulated for the next frequency calculation. This small accumulated data can help achieve more accurate frequency control, making the generated signal more in line with the actual pseudo-range change and phase requirements. DSP sends the updated frequency control word and the current phase compensation value N (n) int The FPGA will then receive this data and prepare to apply these updates in the next step to complete the phase compensation adjustment.

[0082] Step 7: In the FPGA, the integer part of the current frequency control word is combined with the compensated phase compensation result as the actual frequency control word to control the overflow result of the NCO module.

[0083] The NCO generation module in the FPGA adds the compensation result to the frequency control word of the current time period after receiving it, and obtains the compensated frequency control word N'(n)=N(n)+N (n) 补 , and use it as the control word for the overflow result of the NCO accumulator during this period. Specifically, the FPGA uses the integer part of the new frequency control word to control the basic frequency of the C / A code generation. At the same time, the fractional accumulation mechanism is added to the current adder to estimate the cumulative adjustment of the frequency control word to compensate for the error caused by discarding the fractional part of the frequency control word during this period due to phase spurious in the FPGA. This accumulation mechanism can ensure that the signal phase can be corrected and compensated even at a small frequency phase. The data exchange structure diagram between DSP and FPGA is shown in the figure below. Figure 3 shown.

[0084] Step 8: Repeat steps 1 to 7 above to perform phase compensation on each frequency control word of the NCO to improve the NCO overflow accuracy and obtain a higher-precision ranging code for result analysis.

[0085] The ranging code generation in FPGA is implemented by NCO accumulator and addressing ROM. The frequency control word of the phase accumulator is continuously accumulated. When the phase accumulator overflows, a pulse signal of one cycle is generated. Then, the addressing count value is generated by the pulse signal, and the corresponding data is output by ROM addressing. In FPGA implementation, due to the existence of phase spurious problem, floating point accumulation is not used. Instead, the frequency control word is rounded down, which affects the reading timing of the C / A code and causes phase accuracy error. The specific generation process of the ranging code is as follows: Figure 4 shown.

[0086] At the same time, the code phase reduction comparison simulation of the above correction method and without any correction is carried out, such as Figure 5 The simulation results show that both initial phase compensation and frequency control word compensation can achieve the desired compensation effect. In the figure, c_code_ph_com and c_code_k_com are the C / A code outputs for initial phase compensation and frequency control word compensation, respectively. c_code_err is the uncompensated C / A code output. After a certain period of time, the uncompensated C / A code phase significantly lags behind the corrected C / A code phase by one clock cycle.

[0087] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for improving the accuracy of NCO module code generation by dynamic weighted phase compensation, characterized in that: The following steps are involved: Step 1: Calculate the initial phase and frequency control words required by the NCO module in the FPGA chip in the DSP chip; Step 2: Divide the initial phase and frequency control words into integer and fractional parts, and pass the integer parts of the initial phase and frequency control words to the FPGA chip through the interface; Step 3: Use the error diffusion method to allow the error caused by the fractional part discarded due to the phase spurious problem of the FPGA chip to participate in the compensation accumulation each time; Step 4: Use the weighted average compensation method to assign reasonable weights to the current moment and the accumulated initial phase to make the compensation more timely; Step 5: Dynamically adjust and round the weighted compensation result to obtain the final compensation result, and use the actual residual error as the initial value for the next decimal accumulation; Step 6: The NCO module in the FPGA chip sends an interrupt signal to the DSP every time a period of ΔT is accumulated, which is used to control the update frequency control word; Step 7: The FPGA chip combines the integer part of the current frequency control word with the compensated phase compensation result as the actual frequency control word to control the overflow result of the NCO module; Step 8: Repeat steps 1 to 7 to perform phase compensation on the frequency control word of the NCO module each time, thereby improving the overflow accuracy of the NCO module and obtaining a higher-precision ranging code for result analysis.

2. The method for improving NCO module code generation accuracy by dynamic weighted phase compensation according to claim 1, characterized in that: The specific process of step 1 is as follows: In order to facilitate the observation of the results before and after phase compensation, the overflow result of this NCO module is used to generate the ranging code in the satellite navigation signal. The operating frequency of the FPGA chip is f s , set the chip overflow frequency to f c , then its basic frequency control word The frequency control word contains an integer and a fractional part, wherein the integer part determines the main frequency of the NCO module, and the fractional part is used for the specified frequency adjustment.

3. The method for improving NCO module code generation accuracy by dynamic weighted phase compensation according to claim 1, characterized in that: The specific process of step 2 is: In the digital signal processing chip, the frequency control word in step 1 is decomposed into an integer part and a decimal part, that is, N=N int +N float The integer part is directly used to control the basic frequency output of the numerically controlled oscillator NCO module, and the decimal part is used to accurately compensate for the phase difference. The decimal part is accumulated through the accumulation operation. Achieve more continuous frequency adjustment on the time axis; When the accumulated value reaches the preset time ΔT, the phase compensation mechanism is triggered to ensure the overall accuracy of the frequency control word. When the phase compensation is triggered, the integer part at this time is stored and transmitted to the current FPGA chip together with other related data when the next interrupt signal arrives; at the same time, the remaining decimal part is retained for the next round of accumulation operation.

4. The method for improving NCO module code generation accuracy by dynamic weighted phase compensation according to claim 1, characterized in that: The specific process of step 3 is as follows: The specific implementation method is to accumulate the originally discarded decimal error part, SUM_N float (n) =SUM_N float (n-1) +N float (n) Then round the result to SUM_N 补 (n) =round(SUM_N float (n) ), retain e for the new error generated after rounding (n) =SUM_N float (n) -SUM_N 补 (n) , rejoin the next accumulation process SUM_N float (n+1) =e (n) +N (n+1) .

5. The method for improving NCO module code generation accuracy by dynamic weighted phase compensation according to claim 1, characterized in that: The specific process of step 4 is as follows: Using the weighted average compensation method, mSUM_N float (n) =m·N(n)+(1-m)SUM_N float (n-1) , assigning more reasonable weights to the current moment and the accumulated initial error, improving the smoothness of the system, making the phase compensation more effective, and thus improving the accuracy of ranging code generation.

6. The method for improving NCO module code generation accuracy by dynamic weighted phase compensation according to claim 1, characterized in that: The specific process of step 5 is as follows: For the decimal error value after weighted averaging, the following dynamic hierarchical processing is performed on it. Each time the frequency control word is updated, the compensation result is sent in real time to complete the phase compensation process in the FPGA chip. The specific process is as follows: |mSUM_N float (n) -[mSUM_N float (n) ]|<0.5,N 补 =0 mSUM_N float (n) -[mSUM_N float (n) ]≤-0.5,N 补 =-1 mSUM_N float (n) -[mSUM_N float (n) ]≥0.5,N 补 =1 7. The method for improving the NCO module code generation accuracy by using the dynamic weighted phase compensation method according to claim 1, characterized in that: The main processes of steps 6, 7, and 8 are as follows: The FPGA chip generates an interrupt signal irq(n) based on the clock module at regular intervals and sends it back to the DSP chip. The interval between the two interrupts is ΔT, which is used to update the frequency control word in the DSP chip. While sending the new frequency control word, the DSP chip completes the decimal accumulation within the time period and adds the integer part N of the accumulated result. (n) int The current value is sent to the FPGA chip; The NCO generation module in the FPGA chip adds the compensation result to the frequency control word of the current time period after receiving it, and obtains the compensated frequency control word N'(n)=N(n)+N (n) 补 , and use it as the control word for the overflow result of the NCO module accumulator during this period. Specifically, the FPGA chip uses the integer part of the new frequency control word to control the basic frequency generated by the C / A code; at the same time, the fractional accumulation mechanism part is added to the current adder to be used to estimate the cumulative adjustment of the frequency control word to compensate for the error caused by the decimal part of the frequency control word in this time period that was discarded due to phase spurs in the FPGA chip.

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