Data transmission method based on CAN controller, chip and equipment

Abstract

The invention relates to the technical field of data transmission, and particularly provides a data transmission method based on a CAN controller, a chip and equipment, the method is applied to a system-on-chip, and the system-on-chip is characterized in that a processor establishes communication connection with a programmable logic module, the programmable logic module establishes electric connection with the CAN controller, the CAN controller is externally connected with CAN equipment, and the CAN equipment is electrically connected with the programmable logic module. An address mapping relation between the processor and the CAN controller is stored in the programmable logic module; the processor writes the first data in the set address; the first data is transmitted to the CAN controller through the programmable logic module; and the CAN controller receives the first data and sends the first data to the target CAN device. The CAN channel is expanded in the mode that the programmable logic module is externally connected with the CAN controller, data transmission between the processor and the CAN device is achieved, and the problem that more logic resources of the programmable logic module are occupied due to the fact that the CAN channel is expanded through a CAN kernel in the related technology is solved.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission method, chip and device based on a CAN controller. Background Art

[0002] The ZYNQ series chips integrate an ARM (Advanced RISC Machine) processor and a Field-Programmable Gate Array (FPGA) chip, offering significant data processing capabilities. However, the ARM side only has two serial ports for external communication, which often falls short of actual usage requirements.

[0003] In order to expand multiple Controller Area Network (CAN) channels and transmit and receive CAN data, and realize communication between the ARM side and multiple CAN devices, the related technology deploys the Advanced eXtensible Interface (AXI)-CAN soft core in the FPGA chip, and realizes the expansion and transmission of CAN channels through the AXI-CAN soft core. The ARM side operates the CAN soft core through the AXI bus, and the CAN soft core realizes the control of the CAN devices.

[0004] In related technologies, when a large number of CAN channels are expanded, more FPGA-side logic resources will be occupied. Summary of the Invention

[0005] In order to solve the above technical problems, the present application provides a data transmission method, chip and device based on a CAN controller, which expands the CAN channel by connecting an external CAN controller to avoid occupying more logic resources of the programmable logic module.

[0006] In the first aspect, the present application provides a data transmission method based on a CAN controller, which is applied to a system-level chip. The system-level chip includes: a processor, a programmable logic module and a CAN controller. The processor establishes a communication connection with the programmable logic module, and an electrical connection is established between the programmable logic module and the CAN controller. The CAN controller is externally connected to at least one CAN device, and the programmable logic module stores an address mapping relationship between the processor and the CAN controller; the method includes: the processor writes first data to a set address; after the programmable logic module detects that the first data is written to the set address, it queries the target address that has a mapping relationship with the set address from the address mapping relationship; the programmable logic module sends the first data to the target address of the CAN controller; after the CAN controller receives the first data, it sends the first data to the target CAN device.

[0007] In the second aspect, the present application provides a system-level chip, which includes: a processor, a programmable logic module and a CAN controller, the processor establishes a communication connection with the programmable logic module, the programmable logic module establishes an electrical connection with the CAN controller, the CAN controller is externally connected to at least one CAN device, and the programmable logic module stores the address mapping relationship between the processor and the CAN controller; the processor is used to write first data in a set address; the programmable logic module is used to query the target address that has a mapping relationship with the set address from the address mapping relationship after monitoring that the first data is written to the set address, and send the first data to the target address of the CAN controller; the CAN controller is used to send the first data to the target CAN device after receiving the first data.

[0008] In a third aspect, the present application provides an electronic device, which includes a system-level chip, and the system-level chip is used to implement the data transmission method based on the CAN controller as in the first aspect above.

[0009] The technical solution provided by the embodiments of the present application has the following advantages compared with the prior art:

[0010] The present application provides a data transmission method, chip, and device based on a CAN controller. The method is applied to a system-on-chip (SoC), comprising: a processor establishing a communication connection with a programmable logic module; an electrical connection between the programmable logic module and a CAN controller; the CAN controller being externally connected to a CAN device; and a programmable logic module storing an address mapping relationship between the processor and the CAN controller. After the processor writes first data to a set address, the programmable logic module transparently transmits the first data to the CAN controller; the CAN controller receives the first data and sends it to a target CAN device. By externally connecting the programmable logic module to the CAN controller, the CAN channel is expanded to enable data transmission between the processor and the CAN device, avoiding the problem in related technologies of expanding the CAN channel through the CAN core, which occupies more logical resources of the programmable logic module. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic diagram of the structure of a system-on-chip provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of memory address allocation provided in an embodiment of the present application;

[0015] Figure 3 A flowchart of a data transmission method based on a CAN controller provided in an embodiment of the present application;

[0016] Figure 4 A flowchart of another data transmission method based on a CAN controller provided in an embodiment of the present application;

[0017] Figure 5 A flowchart of another data transmission method based on a CAN controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0019] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present application, not all of the embodiments.

[0020] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0021] It should be noted that the concepts of "first" and "second" mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0022] It should be noted that the modifications of "one" and "multiple" mentioned in this application are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0023] The key point detection method provided by the present application is described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] Figure 1 This is a schematic diagram of the structure of a system-on-chip in an embodiment of the present application. Figure 1 As shown, the system-level chip 10 includes: a processor 11, a programmable logic module 12 and a CAN controller 13. The processor establishes a communication connection with the programmable logic module, and an electrical connection is established between the programmable logic module and the CAN controller. The CAN controller is externally connected to at least one CAN device 20, and the programmable logic module stores the address mapping relationship between the processor and the CAN controller.

[0025] Optionally, the system-on-chip includes a fully programmable system-on-chip (SoC). The uniqueness of the system-on-chip is that it encapsulates a traditional software programmable processor and a hardware programmable logic module into a new product.

[0026] Optionally, the processor includes an ARM side, and the programmable logic module includes an FPGA chip.

[0027] A processor typically refers to the core component of an SoC responsible for executing software code, such as the CPU core in a chip. The processor primarily processes operating system instructions, runs applications, and manages the overall operation of the system. Furthermore, in a system-on-a-chip, the processor can be one or more CPU cores, supporting multithreading, significantly improving data processing capabilities.

[0028] Optionally, the programmable logic module includes a Field-Programmable Gate Array (FPGA) chip. An FPGA chip is an integrated circuit that can be configured by customers or designers after manufacturing. FPGA chips can be used to implement the design of any digital circuit. FPGA chips are programmed using a hardware description language, allowing users to customize hardware functions as needed, such as accelerating specific algorithms, creating custom interfaces or protocols, etc. In system-level chips, FPGA chips can provide flexible hardware acceleration options, enabling the system to complete specific tasks more efficiently.

[0029] A CAN controller is a hardware component specifically designed to enable communication in real-world applications. The CAN bus is a robust vehicle bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. The CAN controller manages data transmission over the CAN bus, including error detection, message frame construction, and parsing.

[0030] CAN devices refer to any electronic device that supports the CAN protocol, including but not limited to sensors, actuators, electronic control units, gateways, and diagnostic tools.

[0031] Furthermore, the ARM side and the FPGA chip communicate via an Advanced eXtensible Interface (AXI) bus.

[0032] The AXI bus is widely used in system-on-chips (SoCs) to connect different processing units and hardware devices. In the SoCs provided in the embodiments of the present application, the AXI bus is used to enable high-speed data exchange between the processor and the programmable logic module. This allows the processor to efficiently control the custom hardware accelerators in the programmable logic module and obtain computational results from them.

[0033] An electrical connection is established between the programmable logic module and the CAN controller. An electrical connection refers to the physical connection between electronic devices or components that allows electrical signals to be transmitted from one point to another. This typically involves wires, cables, connectors, sockets, and other types of interface devices to ensure efficient and reliable flow of electrical current.

[0034] The electrical connection between the programmable logic module and the CAN controller can be understood as connecting the programmable logic module and the CAN controller to each other through physical wires or traces on a printed circuit board (PCB) so that the programmable logic module and the CAN controller can send and receive electrical signals to and from each other.

[0035] The electrical connections between the programmable logic module and the CAN controller include, but are not limited to, the following types of connections: power and ground connections, which primarily provide the necessary power and reference ground potential for the device; data signal lines, which are used for data transmission; and control signal lines, which are primarily used to manage CAN device operations, such as chip select signals and read / write signals.

[0036] In an embodiment of the present application, the programmable logic module not only acts as a bridge device to connect the processor and the CAN controller, but also stores custom logic for processing specific CAN protocol operations or data conversion tasks.

[0037] To enable the processor to access the CAN controller through the FPGA, the corresponding address mapping relationship must be configured in the FPGA. In other words, an address mapping table is pre-stored within the FPGA chip. This address mapping table specifies which AXI addresses correspond to which registers in the CAN controller. For example, a specific address range (such as 0x4000_0000 to 0x4000_FFFF) can be defined for operations related to the CAN controller.

[0038] For example, Figure 2As shown, the corresponding write enable bit in memory address 0x0-0x4, the corresponding write data bit in memory address 0x4-0x8, the corresponding write address bit in memory address 0x8-0xc, the corresponding read address bit in memory address 0xc-0x10, the corresponding read enable bit in memory address 0x10-0x14, the corresponding busy status bit in memory address 0x14-0x18, and the corresponding read data bit in memory address 0x18-0x1c.

[0039] Furthermore, the CAN controller is also used to convert the logic signals inside the FPGA chip into electrical and protocol signals that the CAN controller can recognize. In other words, it defines how to perform read and write operations on the CAN controller through these signals.

[0040] based on Figure 1 The system-level chip shown in the embodiment of the present application provides a data transmission method based on a CAN controller, such as Figure 3 As shown, the data transmission method based on the CAN controller provided in the embodiment of the present application includes:

[0041] S101: The processor writes first data into a set address.

[0042] A set address is a predefined memory address or a set of memory addresses used for communication between the processor and the programmable logic module. A set address is the address used by the processor to send commands or data to the FPGA chip.

[0043] First data refers to the information that the processor wants to send to the CAN controller. The first data can be any type of data, including but not limited to control instructions, configuration parameters, and messages to be sent. Specifically, the first data can have different formats depending on the application requirements. For example, the first data can be a CAN message frame or a set of parameters used to configure a CAN device.

[0044] In one possible implementation, a configuration file may be used to specify the connection information and address mapping relationship between hardware components. The configuration file may be read and loaded into memory when the system starts up for use by the processor or other software components.

[0045] The configuration file includes a preset address mapping between the processor and the CAN controller. This configuration file can be stored in the programmable logic module 12. During system startup, the processor reads the address mapping from the programmable logic module 12 and loads it into memory. When data needs to be sent to a CAN device, the memory address corresponding to the CAN device is read from the address mapping and used as the set address.

[0046] In one possible implementation, on the processor side, program code is written to perform a write operation on a set address. This can be accomplished through direct memory access instructions, such as using pointer operations or dedicated I / O functions in the C language. When the above code is executed, the processor writes the first data to the location pointed to by the set address.

[0047] S102 : After the programmable logic module 12 detects that the first data is written into the set address, it searches the address mapping relationship for a target address that has an address mapping relationship with the set address.

[0048] The target address refers to a specific register address within the CAN controller. This register is used to receive and process the first data from the processor. For example, if the first data written by the processor is to configure the operating mode of the CAN controller, the first data will be directed to the corresponding control register address.

[0049] A monitoring function is configured in the programmable logic module 12, which can detect the write operation from the processor to the set address. Therefore, the programmable logic module 12 listens to the write operation on this preset address. Therefore, when the processor performs a write operation at the set address, the corresponding logic in the programmable logic module 12 will be activated, and then the target address that has an address mapping relationship with the set address will be queried from the address mapping relationship.

[0050] S103 : The programmable logic module 12 sends first data to a target address of the CAN controller 13 .

[0051] After determining the target address, the first data must be processed to ensure that it complies with the CAN controller interface specification. This may include adjusting the length of the first data to ensure it matches the CAN controller's expectations. The first data is then encapsulated into a frame format recognizable by the CAN controller. For example, identifiers, control bits, and CRC checks may be added.

[0052] Specifically, after the first data is ready, the programmable logic module 12 sends the first data to the CAN controller 13 according to the CAN protocol. During this process, the CAN controller is responsible for managing the entire transmission process, including conflict detection and retransmission mechanisms, to ensure that the data reaches the destination reliably.

[0053] S104 , after receiving the first data, the CAN controller 13 sends the first data to the target CAN device 20 .

[0054] The target CAN device refers to a CAN device that ultimately receives the first data or executes an instruction corresponding to the first data.

[0055] Specifically, after receiving the data, the CAN controller processes the first data according to its internal logic. If the first data is a message frame, the CAN controller encodes it into a format suitable for transmission on the CAN bus and sends it out at the appropriate time. This message is then sent to the designated target CAN device.

[0056] An embodiment of the present application provides a data transmission method based on a CAN controller. The method is applied to a system-on-chip (SoC). The SoC includes: a processor and a programmable logic module establishing a communication connection; an electrical connection between the programmable logic module and a CAN controller; the CAN controller being externally connected to a CAN device; and the programmable logic module storing an address mapping relationship between the processor and the CAN controller. After the processor writes first data to a set address, the programmable logic module transparently transmits the first data to the CAN controller; the CAN controller receives the first data and sends it to a target CAN device. By externally connecting the programmable logic module to the CAN controller, the CAN channel is expanded to enable data transmission between the processor and the CAN device, avoiding the problem in related technologies of expanding the CAN channel through the CAN core, which occupies more logic resources on the FPGA side.

[0057] Based on the above-mentioned embodiment, the present embodiment further optimizes the data transmission method based on the CAN controller. The main optimization direction in this embodiment is to determine whether data transmission is to be performed based on the register status query results fed back by the CAN controller. It should be noted that the main steps of the optimized data transmission method based on the CAN controller provided in this embodiment are executed before the above-mentioned "S101, processor 11 writes the first data to the set address".

[0058] like Figure 4 As shown, the optimized data transmission method based on the CAN controller provided by this application mainly includes:

[0059] S201 , the processor 11 transparently transmits a status query instruction to the CAN controller 13 through the programmable logic module 12 .

[0060] The status query instruction can be understood as an instruction for querying whether the CAN device is online, whether the CAN bus is idle, and whether the data buffer of the CAN controller is ready.

[0061] The processor transparently transmits status query instructions to the CAN controller through the programmable logic module. This involves the processor writing the status query instruction to a memory address. The FPGA chip detects the status query instruction and then searches the address mapping for the target address corresponding to the memory address. The FPGA chip transmits the status query instruction to the CAN controller through an electrical connection with the CAN controller.

[0062] S202 : After receiving the status query instruction, the CAN controller 13 queries the status related to the target CAN device.

[0063] The status related to the target CAN device includes: whether the bus connected to the target CAN device is in an idle state, whether the data buffer of the CAN controller is in an idle state, whether the target CAN device is online, etc.

[0064] The bus connected to the target CAN device being in an idle state can be understood as the bus connected to the target CAN device not performing data transmission.

[0065] The CAN controller's data buffer is used to temporarily store data frames to be sent or received. Whether a CAN controller's data buffer is idle refers to whether there is any unprocessed data in the data buffer. Optionally, the data buffer is a transmit buffer. An idle transmit buffer means that there are no data frames waiting to be sent, or that a data frame previously placed in the buffer for transmission has been successfully sent and confirmed as complete (i.e., cleared from the buffer).

[0066] Whether the target CAN device is online refers to whether the target CAN device has been successfully connected to the CAN controller and is in normal working state, able to send and receive data.

[0067] Specifically, the status related to the target CAN device includes: a first identification bit, a second identification bit and a third identification bit in the status register corresponding to the target CAN device; the first identification bit is used to indicate whether the bus connected to the target CAN device is in an idle state; the second identification bit is used to indicate whether the data buffer of the CAN controller is in an idle state; the third identification bit is used to indicate whether the target CAN device is online.

[0068] In an embodiment of the present application, at least one status register is provided in the CAN controller, which is used to record the relevant status of the target CAN device. The first flag bit in the status register is used to indicate whether the bus connected to the target CAN device is in an idle state. For example, when the first flag bit is in the first state value, it indicates that the bus connected to the target CAN device is in an idle state. When the first flag bit is in the fourth state value, it indicates that the bus connected to the target CAN device is in a non-idle state.

[0069] The second flag bit in the status register is used to indicate whether the CAN controller's data buffer is in an idle state. For example, when the second flag bit is in the third state value, it indicates that the CAN controller's data buffer is in an idle state. When the second flag bit is in the fifth state value, it indicates that the CAN controller's data buffer is in a non-idle state.

[0070] The third flag in the status register is used to indicate whether the target CAN device is online. For example, when the third flag is in the third state value, it indicates that the target CAN device is online; when the third flag is in the third state value, it indicates that the target CAN device is offline.

[0071] Specifically, after receiving the status query instruction, the CAN controller reads the identification bit in the register related to the target CAN device, and feeds the identification bit in the register back to the processor through the FPGA chip.

[0072] S203 : The CAN controller 13 feeds back a status query result related to the target CAN device to the processor 11 through the programmable logic module 12 .

[0073] The status query result related to the target CAN device may include: an identification bit in a register related to the target CAN device.

[0074] In an embodiment of the present application, the CAN controller transparently transmits the identification bit in the register related to the target CAN device to the processor through the programmable logic module.

[0075] S204 : When the status query result is an idle state, the processor 11 writes first data into the set address, where the first data is data to be transmitted to the target CAN device.

[0076] The status query result is an idle state including: the first identification bit is the first state value, the second identification bit is the second state value, and the third identification bit is the third state value; the first identification bit is the first state value indicating that the bus connected to the target CAN device is in an idle state; the second identification bit is the second state value indicating that the data buffer of the CAN controller is in an idle state; the third identification bit is the third state value indicating that the target CAN device is online.

[0077] The first state value, the second state value, and the third state value may be the same or different. Optionally, the first state value, the second state value, and the third state value are logic values 0.

[0078] After the processor receives the flag bit in the register corresponding to the target CAN device fed back by the CAN controller, if the first flag bit is the first state value, the second flag bit is the second state value, and the third flag bit is the third state value, it is determined that the target CAN device is qualified to receive data, and then the processor writes the first data in the set address to enable the processor to transparently transmit data to the CAN processor through the FPGA chip.

[0079] In a possible implementation, when the status query result indicates a non-idle state, the processor prohibits writing the first data into the set address.

[0080] After the processor receives the flag bit in the register corresponding to the target CAN device fed back by the CAN controller, if the first flag bit is not the first state value, or the second flag bit is not the second state value, or the third flag bit is not the third state value, it is determined that the target CAN device does not have the conditions to receive data, and the processor is prohibited from writing the first data to the set address, that is, the processor is prohibited from transmitting data to the CAN controller to avoid the problem of data packet loss.

[0081] In one possible implementation, after the processor receives the flag bit in the register corresponding to the target CAN device fed back by the CAN controller, it determines whether the first flag bit is the first state value. If the first flag bit is the first state value, it determines whether the second flag bit is the second state value. If the first flag bit is not the first state value, it exits the judgment process, prohibits data transmission to the CAN controller, and resends the status query instruction after a certain interval.

[0082] If the second flag bit is the second state value, determine whether the third flag bit is the third state value. If the second flag bit is not the second state value, exit the judgment process, prohibit data transmission to the CAN controller, and resend the status query instruction after a certain period of time.

[0083] If the third identification bit is the third state value, the processor writes the first data in the set address to enable the processor to transparently transmit data to the CAN processor through the FPGA chip. If the third identification bit is not the third state value, the judgment process is exited, data transmission to the CAN controller is prohibited, and the status query instruction is resent after a certain interval.

[0084] In an embodiment of the present application, the processor determines that the bus connected to the target CAN device is in an idle state and the data buffer of the CAN controller is in an idle state. When the target CAN device is online, data is transmitted to the CAN controller to avoid data packet loss caused by failure to meet data transmission conditions.

[0085] On the basis of the above embodiment, the embodiment of the present application further optimizes the data transmission method based on the CAN controller. The optimization direction of the embodiment of the present application is the process of the CAN controller feeding back data to the processor. Specifically, Figure 5 As shown, the optimized CAN controller-based data transmission method in the embodiment of the present application mainly includes S301-S303.

[0086] S301 : The programmable logic module 12 detects whether the CAN controller 13 receives second data.

[0087] The second data is data collected by the target CAN device and needs to be transmitted to the processor. For example, when the target CAN device is a current sensor, the second data may be a current value collected by the current sensor.

[0088] Programmable logic modules can be used to implement customized hardware functions. Programmable logic modules can be configured using a hardware description language (such as VHDL or Verilog) to perform specific tasks, such as processing and detecting whether a CAN controller has received the second data. Furthermore, the programmable logic module can include an FPGA or a CPLD.

[0089] In one possible implementation, taking the programmable logic module as an FPGA chip, the FPGA chip is configured to monitor the receive buffer of the CAN controller in real time. When data is received in the receive buffer of the CAN controller, the programmable logic module detects that the CAN controller has received second data. When no data is received in the receive buffer of the CAN controller, the programmable logic module detects that the CAN controller has not received the second data.

[0090] In one possible implementation, the programmable logic module detects whether the CAN controller has received the second data, including: after the CAN controller receives the second data sent by the target CAN device, the CAN controller stores the second data in a receive buffer and sets the read data flag bit to a set state value; the programmable logic module determines whether the CAN controller has received the second data by monitoring the read data flag bit in the CAN controller.

[0091] In a CAN communication system, the receive buffer refers to a memory area within the CAN controller that is used to temporarily store data frames transmitted from a CAN device. When the target CAN device sends second data to the CAN controller, the second data is transmitted to the CAN controller.

[0092] When a target CAN device sends data to the CAN network, the CAN controller is responsible for receiving this data. This data is typically stored in the CAN controller's internal receive buffer. The receive buffer is a temporary storage area used to hold information received from the CAN network until it can be read and processed. Using the receive buffer as a temporary storage area ensures that data is not lost due to untimely processing.

[0093] In order to help the FPGA chip identify whether new data has arrived, the CAN controller uses one or more status flags, namely the read data identification bit. When the CAN controller successfully receives the second data from the target CAN device, the CAN controller not only stores the second data in its receive buffer, but also updates the status of the read data identification bit. For example, if the status before receiving the second data is the status value of "not received", it will be set to the status value of "received" after receiving the second data. For example: use logic "1" as the status value of "received" and use logic "0" as the status value of "not received". The status value of the data identification bit can be set according to actual conditions, and is no longer specifically limited in the embodiments of the present application.

[0094] The programmable logic module is configured to function as a monitor. The programmable logic module can periodically or based on an event trigger to check the status of a read data flag in the CAN controller. By monitoring changes in the status of the read data flag, the programmable logic module determines whether the CAN controller has received the second data.

[0095] Specifically, the programmable logic module continuously or periodically checks the read data identification bit. Once it is found that the read data identification bit is set to a set state value, indicating that the new second data has been stored in the receive buffer by the CAN controller, the programmable logic module can take corresponding execution measures. Furthermore, if the programmable logic module monitors that the read data identification bit of the CAN controller is set to a state value of "received", it indicates that the new second data has been stored in the receive buffer by the CAN controller, and the programmable logic module can take corresponding execution measures. If the programmable logic module monitors that the read data identification bit of the CAN controller is set to a state value of "not received", it indicates that the new second data has not been received by the CAN controller, and the programmable logic module continuously or periodically checks the read data identification bit.

[0096] The receive buffer is where the CAN controller stores "secondary data" received from the target CAN device. Once data is successfully received and stored in this buffer, the CAN controller notifies the system that new data is available for processing by setting the read data flag. This mechanism ensures that data can be effectively managed and responded to, even if the arrival time of the data is uncertain.

[0097] S302: When the programmable logic module detects that the CAN controller receives the second data, it sends a data read signal to the processor.

[0098] The data read signal is a communication mechanism or trigger used to notify the processor that new data is available for reading. Specifically, it tells the processor that one or more data frames are ready and stored in the CAN controller's receive buffer, awaiting processing.

[0099] Specifically, when the programmable logic module detects that the CAN controller receives the second data, the programmable logic module generates and sends a read signal to the processor to tell the processor that one or more data frames are now ready and stored in the receive buffer of the CAN controller, waiting for processing by the processor.

[0100] In one possible implementation, the programmable logic module sends a data read signal to the processor, which can be implemented through a hardware interrupt. Specifically, the data read signal is actually an interrupt request (IRQ), which immediately interrupts the processor's current task flow and forces it to jump to a predefined interrupt service routine (ISR). In this ISR, the processor will execute the necessary code to read the newly arrived second data from the CAN controller.

[0101] Alternatively, the programmable logic module can use a polling mechanism to send data read signals to the processor. This data read signal can simply be a flag bit change in a status register. The processor periodically checks these flag bits. Once a specific flag bit is set, indicating that new data is available, the processor executes the appropriate operation to read and process the data.

[0102] In a possible implementation, the programmable logic module sends a data read signal to the processor, including: the programmable logic module sets an interrupt line connected to the processor to a set level state.

[0103] The interrupt line is the physical line connecting the programmable logic module to the processor, used to transmit interrupt signals. When an interrupt occurs, the state change of the interrupt line triggers the processor to suspend the current task and handle the interrupt event.

[0104] The set level state refers to a pre-set level state indicating an interrupt signal, wherein the set level state can be a high level state or a low level state, and can be set according to actual conditions. The high level state can be represented by a logic 1, and the low level state can be represented by a logic 0.

[0105] Setting an interrupt line to a set level means setting the interrupt line to a high or low level. The set level depends on the interrupt triggering method specified in the system design. For example, rising edge triggering, falling edge triggering, high level triggering, or low level triggering.

[0106] In one possible implementation, the programmable logic module first monitors the read data flag in the CAN controller to determine whether the second data sent by the target CAN device has been received. Upon detecting that the specified second data has been received by the CAN controller, the programmable logic module sends an interrupt request to the processor. Specifically, the programmable logic module sets an interrupt line connected to the processor to a predetermined level. For example, if a high level triggers an interrupt, the programmable logic module pulls the interrupt line high; if a low level triggers an interrupt, the programmable logic module pulls the interrupt line low.

[0107] In this way, the programmable logic module can effectively notify the processor of new data that needs to be processed, ensuring timely and efficient data processing. This is particularly suitable for application scenarios that require rapid response to external events.

[0108] S303: After receiving the data read signal, the processor reads the second data from the CAN controller through the programmable logic module.

[0109] In response to the data read signal, the processor issues a read command to a specific address in its own memory address space. The specific address is selected according to the above address mapping relationship and represents a location on the target CAN controller.

[0110] After receiving a read request from the processor, the programmable logic module interprets the request based on pre-stored address mappings and converts it into a valid command for the CAN controller. This includes, but is not limited to, determining the correct physical address, setting necessary control signals, and ensuring the security and integrity of data transmission.

[0111] The programmable logic module then executes the data exchange process with the CAN controller, including sending a read command to the CAN controller and waiting for a response. After receiving the read command, the CAN controller feeds the second data back to the programmable logic module. After receiving the second data from the CAN controller, the programmable logic module correctly routes the second data back to the memory location specified by the processor based on the address mapping. This allows the processor to access data from the CAN controller as easily as accessing local memory.

[0112] This application greatly simplifies the processor's operation process on the CAN controller by introducing an address mapping mechanism in the programmable logic module, and improves data access efficiency and reliability.

[0113] In one possible implementation, after receiving the data read signal, the processor reads the second data from the CAN controller through the programmable logic module, including: when the processor detects that the interrupt line is in a set level state, it suspends the current task and jumps to the interrupt service routine; in the interrupt service routine, the processor accesses the receive buffer of the CAN controller through the programmable logic module and reads the second data.

[0114] An interrupt service routine is a piece of code specifically designed to handle a specific type of interrupt. When the processor receives an interrupt request, it pauses the current task and jumps to the corresponding interrupt service routine to execute the relevant processing logic.

[0115] Specifically, when the programmable logic module detects that the CAN controller has successfully received the second data sent by the target CAN device and stored it in the receive buffer, the programmable logic module sets the interrupt line connected to the processor to a set level state, indicating that a new interrupt request has been generated and is waiting to be processed by the processor.

[0116] The processor detects that the interrupt line is at a set level, indicating a pending interrupt request. The processor immediately suspends its current task and saves context for later resumption. The processor then determines the address of the corresponding interrupt service routine from the interrupt vector table and jumps to that address to begin execution.

[0117] Within the interrupt service routine, the processor first performs necessary initialization tasks, such as confirming that the interrupt source is indeed from the intended programmable logic module and ensuring that all necessary hardware resources are ready for data transmission. Furthermore, the processor configures the programmable logic module to act as an intermediary to assist in reading the second data from the CAN controller's receive buffer. The processor issues a read command to the CAN controller via the programmable logic module using a pre-established address mapping. The programmable logic module acts as a bridge, correctly translating the processor's command into a format understandable by the CAN controller and initiating the actual data read operation. After extracting the second data from the receive buffer, the programmable logic module can forward the second data back to the processor's designated memory location.

[0118] After the processor completes the data reading, the processor decodes, analyzes or performs other necessary processing on the second data read in the interrupt service routine. Finally, the processor clears the interrupt status, restores the previously saved field information, and returns to the task before being interrupted to continue execution.

[0119] In the embodiment of the present application, after receiving an interrupt signal, the processor can safely and reliably read the required data from the receive buffer of the CAN controller through the programmable logic module, thereby improving the real-time response capability and overall efficiency of the system.

[0120] The embodiment of the present application provides a system-on-chip, such as Figure 1 As shown, the system-level chip 10 includes: a processor 11, a programmable logic module 12 and a CAN controller 13. The processor establishes a communication connection with the programmable logic module, and an electrical connection is established between the programmable logic module and the CAN controller. The CAN controller is externally connected to at least one CAN device 20, and the programmable logic module stores the address mapping relationship between the processor and the CAN controller.

[0121] The processor is used to write the first data into the set address; the programmable logic module is used to query the target address that has a mapping relationship with the set address from the address mapping relationship after detecting that the first data is written into the set address; and send the first data to the target address of the CAN controller; the CAN controller is used to send the first data to the target CAN device after receiving the first data.

[0122] In one possible implementation, the processor is further configured to, before writing the first data into the set address, transparently transmit a status query instruction to the CAN controller through the programmable logic module; when the status query result is an idle state, write the first data into the set address, the first data being data to be transmitted to the target CAN device; and when the status query result is a non-idle state, prohibit writing the first data into the set address;

[0123] The CAN controller is further configured to query the current status of the target CAN device after receiving a status query instruction; and to feed back the status query result related to the target CAN device to the processor through the programmable logic module;

[0124] In one possible implementation, the status related to the target CAN device includes: a first identification bit, a second identification bit, and a third identification bit in the status register corresponding to the target CAN device; the first identification bit is used to indicate whether the bus connected to the target CAN device is in an idle state; the second identification bit is used to indicate whether the data buffer of the CAN controller is in an idle state; and the third identification bit is used to indicate whether the target CAN device is online.

[0125] In one possible implementation, the status query result is an idle state including: the first identification bit is a first state value, the second identification bit is a second state value, and the third identification bit is a third state value; the first identification bit is a first state value indicating that the bus connected to the target CAN device is in an idle state; the second identification bit is a second state value indicating that the data buffer of the CAN controller is in an idle state; the third identification bit is a third state value indicating that the target CAN device is online.

[0126] In one possible implementation, the programmable logic module is further configured to detect whether the CAN controller has received the second data; when the programmable logic module detects that the CAN controller has received the second data, the programmable logic module sends a data read signal to the processor;

[0127] The processor is further configured to read the second data from the CAN controller through the programmable logic module after receiving the data read signal.

[0128] In one possible implementation, the CAN controller is further used to store the second data in a receive buffer after receiving the second data sent by the target CAN device, and to set the read data identification bit to a set state value; the programmable logic module is specifically used to determine whether the CAN controller has received the second data by monitoring the read data identification bit in the CAN controller.

[0129] In one possible implementation, the programmable logic module is specifically configured to set an interrupt line connected to the processor to a set level state;

[0130] The processor is specifically used to suspend the current task and jump to the interrupt service program when detecting that the interrupt line is in the set level state; in the interrupt service program, access the receiving buffer of the CAN controller through the programmable logic module and read the second data.

[0131] In one possible implementation, the processor includes an ARM end, the programmable logic module includes an FPGA chip, and the ARM end and the FPGA chip communicate via an AXI bus.

[0132] The system-level chip provided in the embodiments of the present application can execute the data transmission method based on the CAN controller provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method.

[0133] This embodiment provides an electronic device, which includes a system-level chip. The system-level chip can execute the data transmission method based on the CAN controller provided in any embodiment of the present application, and has functional modules and beneficial effects corresponding to the execution method.

[0134] Through the above description of the implementation methods, those skilled in the art can clearly understand that the present application can be implemented with the help of software and necessary general-purpose hardware, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer's floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0135] It is worth noting that in the embodiment of the above-mentioned search device, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application.

[0136] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0137] The above are merely specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to these embodiments herein, but is intended to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A data transmission method based on a CAN controller, characterized in that: The method is applied to a system-on-chip, which includes: a processor, a programmable logic module, and a controller area network (CAN) controller; the processor establishes a communication connection with the programmable logic module, the programmable logic module establishes an electrical connection with the CAN controller, the CAN controller is externally connected to at least one CAN device, and the programmable logic module stores an address mapping relationship between the processor and the CAN controller; The method comprises: The processor writes first data into a set address; After the programmable logic module detects that the set address has written the first data, it searches the address mapping relationship for a target address that has a mapping relationship with the set address; The programmable logic module sends the first data to the target address of the CAN controller; After receiving the first data, the CAN controller sends the first data to a target CAN device.

2. The method according to claim 1, characterized in that Before the processor writes the first data into the set address, the processor further includes: The processor transparently transmits a status query instruction to the CAN controller through the programmable logic module; After receiving the status query instruction, the CAN controller queries the status related to the target CAN device; The CAN controller feeds back a status query result related to the target CAN device to the processor through the programmable logic module; When the status query result is an idle state, the processor writes first data into a set address, where the first data is data to be transmitted to the target CAN device; When the status query result is a non-idle state, the processor prohibits writing the first data into the set address.

3. The method according to claim 2, characterized in that The state related to the target CAN device includes: a first identification bit, a second identification bit and a third identification bit in a status register corresponding to the target CAN device; The first flag is used to indicate whether the bus connected to the target CAN device is in an idle state; The second flag is used to indicate whether the data buffer of the CAN controller is in an idle state; The third flag is used to indicate whether the target CAN device is online.

4. The method according to claim 3, characterized in that The state query result is an idle state, including: the first flag bit is a first state value, the second flag bit is a second state value, and the third flag bit is a third state value; The first flag bit being a first state value indicates that the bus connected to the target CAN device is in an idle state; The second flag bit being a second state value indicates that the data buffer of the CAN controller is in an idle state; The third flag bit being a third state value indicates that the target CAN device is online.

5. The method according to claim 1, wherein Also includes: The programmable logic module detects whether the CAN controller receives second data; When the programmable logic module detects that the CAN controller receives the second data, sending a data read signal to the processor; After receiving the data reading signal, the processor reads the second data from the CAN controller through the programmable logic module.

6. The method according to claim 5, characterized in that The programmable logic module detects whether the CAN controller receives the second data, including: After receiving the second data sent by the target CAN device, the CAN controller stores the second data in a receiving buffer and sets a read data flag bit to a set state value; The programmable logic module determines whether the CAN controller has received the second data by monitoring the read data identification bit in the CAN controller.

7. The method according to claim 5, characterized in that The programmable logic module sends a data read signal to the processor, comprising: The programmable logic module sets an interrupt line connected to the processor to a set level state; After receiving the data read signal, the processor reads the second data from the CAN controller through the programmable logic module, including: When the processor detects that the interrupt line is in a set level state, it suspends the current task and jumps to the interrupt service routine; In the interrupt service program, the processor accesses the receiving buffer of the CAN controller through the programmable logic module and reads the second data.

8. The method according to any one of claims 1 to 7, characterized in that: The processor includes an ARM end, the programmable logic module includes an FPGA chip, and the ARM end and the FPGA chip communicate with each other via an AXI bus.

9. A system-on-chip, characterized in that: The system-on-chip includes: a processor, a programmable logic module, and a controller area network (CAN) controller, wherein the processor establishes a communication connection with the programmable logic module, the programmable logic module establishes an electrical connection with the CAN controller, the CAN controller is externally connected to at least one CAN device, and the programmable logic module stores an address mapping relationship between the processor and the CAN controller; The processor is configured to write first data into a set address; The programmable logic module is configured to, after detecting that the set address has written the first data, query a target address that has a mapping relationship with the set address from the address mapping relationship; and send the first data to the target address of the CAN controller; The CAN controller is configured to send the first data to a target CAN device after receiving the first data.

10. An electronic device, characterized in that: The electronic device includes a system-on-chip, and the system-on-chip is used to implement the data transmission method based on the CAN controller according to any one of claims 1 to 8.

Images