A PIO communication device and computing equipment for computing network fusion computing architecture

Abstract

This invention discloses a PIO communication device and computing device for a converged computing architecture. The PIO communication device includes an interconnected protocol conversion module and a PIO transaction processing module. The protocol conversion module is connected to the computing unit on the Network-on-Chip (NoC) via an AXI interface. When the computing unit initiates a PIO read / write request, the protocol conversion module performs the conversion between the AXI protocol and the PIO protocol and maps the response status. The PIO transaction processing module parses the converted PIO read / write request, initiates register access and write descriptor operations to the network protocol processing unit, and receives the returned register read response data. This invention adopts a decoupled design of address, data, and response channels to complete the conversion of PIO read / write transactions between the AXI interface and the network protocol interface, realizing high-bandwidth, low-latency, non-blocking PIO data transmission and processing.

Description

Technical Field

[0001] This invention relates to the field of converged computing technology, specifically to a PIO communication device and computing equipment for a converged computing architecture. Background Technology

[0002] To address the explosive growth in computing power and diverse integration requirements of high-performance computing and artificial intelligence applications, traditional CPU+GPU heterogeneous computing architectures, which use the PCIe bus to interconnect CPUs, accelerators, and network cards, face limitations in data transmission bandwidth and energy efficiency. Against this backdrop, heterogeneous computing architectures that integrate computing and network components, employing on-chip heterogeneous integration or multi-chip integration, have become a significant development trend. These converged computing architectures utilize AXI interfaces to achieve on-chip integration between computing and network components, reducing transmission latency and improving data transmission bandwidth and energy efficiency. How to achieve and improve the communication efficiency between the AXI interfaces of computing components and the network protocol interfaces of network components has become a critical technical problem that urgently needs to be solved in converged computing architectures. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a PIO communication device and computing device for a computing-network converged computing architecture, which addresses the above-mentioned problems in the prior art. The present invention adopts a decoupled design of address, data and response channels to complete the conversion of PIO read and write transactions between the AXI interface and the network protocol interface, thereby realizing high-bandwidth, low-latency non-blocking PIO data transmission and processing.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A PIO communication device for a converged computing architecture includes a protocol conversion module and a PIO transaction processing module connected to each other. The protocol conversion module is connected to computing components on a network-on-chip (NoC) via an AXI interface. The computing components include at least one of general-purpose computing components and accelerated computing components. When a computing component initiates an AXI read / write request, the protocol conversion module performs the conversion of the read / write request between the AXI protocol and the PIO protocol and maps the response status. The PIO transaction processing module parses the converted PIO read / write request, initiates register access and write descriptor operations to the network protocol processing component, and receives the returned register read response data.

[0006] Optionally, the protocol conversion module includes a transaction request conversion unit, a transaction data conversion unit, and a transaction state conversion unit. The transaction request conversion unit is used to perform handshake signal parsing, address mapping, and data length calculation to complete the conversion from AXI read / write request to PIO read / write request. The transaction data conversion unit is used to complete the conversion between AXI transaction data and PIO write request data and PIO read response data. The state conversion unit is used to convert the PIO transaction processing result into an AXI response and feed it back to the processor through the AXI bus.

[0007] Optionally, the protocol conversion module further includes a protocol conversion state machine for controlling protocol conversion. The protocol conversion state machine includes four stages: initial state, address resolution state, data transmission state, and response adaptation state. After power-on reset, the protocol conversion module is in the initial state, waiting for AXI transaction requests. When an AXI read / write transaction request signal is detected, the module enters the address resolution state to complete the PIO request conversion. In the address resolution state, the transaction request conversion unit performs address offset processing, address space encoding, and PIO data length calculation conversion. After the conversion is completed, the module enters the data transmission state to realize PIO data conversion. In the data transmission state, the transaction data conversion unit performs data endianness conversion according to the transaction type: if it is a write transaction request, the protocol conversion module waits for the AXI data to be valid and then performs Big / Little Endian conversion on the AXI interface data; if it is a read transaction request, the protocol conversion module waits for the PIO read data feedback to be valid before performing the conversion. After the transmission is completed, the protocol conversion module enters the response adaptation state to provide feedback on the PIO processing status and generate an AXI response signal. In the response adaptation state, the protocol conversion module waits for the transaction processing signal of the PIO request, completes the AXI response encoding, and then returns to the initial state.

[0008] Optionally, when the transaction request conversion unit performs address offset processing, address space encoding, and PIO data length calculation, the address offset processing and address space encoding include: the transaction request conversion unit registers the address and data length of each write descriptor request; if the request address is the same as the previous request address, it uses the address and data length of the previous request to generate an offset address and PIO address space information, and updates the registered address and data length to ensure that the data is written to the correct address space; the calculation of the PIO data length includes: for the case where AXI Burst is not 1, the PIO data length is calculated based on the product of Burst in the AXI address signal and the data granularity, where the data granularity is the AXI bus data bit width; otherwise, the valid bits of the statistical data byte are used as the PIO data length.

[0009] Optionally, the PIO transaction processing module includes a request arbitration unit, a read / write control unit, and a read response unit. The request arbitration unit is used to arbitrate and allocate resources for PIO read / write transaction requests converted by the protocol conversion module. The read / write control unit is used to control register access or write descriptor operations on the network protocol processing component and to perform different processing on read / write requests according to the arbitration result of the request arbitration unit. The read response unit is used to receive read response data from the network protocol processing component and read request information to be responded to from the read / write control unit. After combining the data and related information, it returns the data to the protocol conversion module in the form of a PIO read response.

[0010] Optionally, the PIO transaction processing module further includes a transaction processing state machine for controlling PIO transaction processing. The transaction processing state machine includes four stages: initial state, arbitration state, response state, and read / write data transmission state. After power-on reset, the transaction processing state machine is in the initial state, indicating that the PIO transaction processing module is idle. When the PIO transaction processing module receives a valid PIO read / write transaction request signal, it parses the request address, data length, and transaction type. If read / write transaction request signals are detected simultaneously, the transaction processing state machine transitions to the arbitration state to arbitrate the read / write request. If only a single request is received and no read / write data transmission is occurring, the transaction processing state machine transitions to the response state to respond to the request. If only a single request is received but read / write data transmission is in progress, the new request is temporarily stored in the request waiting queue, waiting for the current data transmission to complete. When the transaction processing state machine is in the arbitration state, the received read / write transaction requests are arbitrated by the request arbitration unit based on transaction priority and system credit value. If the credit value is insufficient, the state machine remains in the arbitration state until resources are restored. If the credit value is sufficient, the state machine processes high-priority requests first, while temporarily storing low-priority requests in the request waiting queue. When the transaction processing state machine is in the response state, the PIO transaction processing module responds to read / write transaction requests. After the data transmission preparation for the relevant requests is completed, the state machine transitions to the read / write data transmission state to perform data transmission. When the transaction processing state machine is in the read / write data transmission state, the read / write control unit performs different data processing operations according to the type of read / write request: if it is a read request, it obtains read data from the network protocol processing component; if it is a write request, it writes data to the network protocol processing component according to the target address. After the data transmission is completed, the read response unit feeds back the processing status of the read / write transaction to the protocol conversion module. Then, the PIO transaction processing module makes a judgment: if the request waiting queue is empty, it transitions to the initial state to receive new requests; if the request waiting queue is not empty, it continues to respond to the requests temporarily stored in the request waiting queue.

[0011] Optionally, obtaining read data from the network protocol processing unit includes: the read / write control unit first reduces the credit of the read request after detecting the read request enable signal and stores the read request in the read request register; then, the read / write control unit makes a judgment based on the read response status fed back by the read response unit: if the FIFO of the read request to be responded to is not full in the read response status, the read / write control unit transmits the read request ID and address information representing the transaction number to the read response unit, and at the same time, the read / write control unit reads the required register data from the network protocol processing unit according to the read address and data length, and waits for the read response unit to feed back the read response completion; if the FIFO of the read request to be responded to is full, the read / write control unit no longer sends read requests to the network protocol processing unit until the FIFO of the read request to be responded to is not full; after completing the current transaction processing, the read / write control unit feeds back the read / write status to the request arbitration unit and restores the corresponding read / write request credit.

[0012] Optionally, the step of writing data to the network protocol processing unit based on the target address includes: the read / write control unit first decrements the write request credit after detecting a write request enable signal and registers the write request in the write request register; then, the read / write control unit determines the corresponding target based on the write request address. If the target is a descriptor, the write descriptor is enabled after descriptor combination is completed, and the data is written to the descriptor space; if the target is a register, the write register is enabled, and the data is written to the register. During the transmission process, the unit's built-in counter tracks the transmission progress in real time, decrements according to the data length, and sets the PIO last data flag bit when the counter decrements to zero, indicating that the write request is completed; after completing the current transaction processing, the read / write control unit feeds back the read / write status to the request arbitration unit and restores the corresponding read / write request credit.

[0013] Optionally, the read response unit includes a read request FIFO awaiting response and a read data FIFO. The step of using the read response unit to feedback the processing status of read / write transactions to the protocol conversion module includes: when the read response unit detects the read request ID and address offset sent by the read / write control unit, the read response unit enables the write function of the read request FIFO awaiting response and caches the read request ID and address offset; when a valid read response enable signal is detected from the network protocol processing unit, the read response unit enables the write function of the read data FIFO and writes the read response data into the read data FIFO; when the read data FIFO is not empty, it indicates that the network protocol processing unit has returned the read response data from the register; simultaneously, the read response unit enables the read function of both the read request FIFO awaiting response and the read data FIFO, and retrieves the response data, read request ID, and offset address from the FIFO according to the first-in-first-out principle; the read response unit notifies the protocol conversion module to receive the read data and read completion signal based on the read request ID, returns the read response status to the read / write control unit, and then releases the occupied peripheral resources to prepare for the processing of subsequent new transactions.

[0014] In addition, the present invention also provides a computing-network converged computing device, including a processor chip and a memory interconnected, wherein the processor chip includes the PIO communication device for the computing-network converged computing architecture described above.

[0015] Compared with existing technologies, this invention mainly achieves the following beneficial effects: In a converged computing architecture, the processor accesses the register space of the network protocol processing unit and submits network request descriptors through PIO requests. Based on this architecture, this invention proposes an AXI interface PIO communication device to complete the PIO communication conversion and processing between the computing unit and the network protocol processing unit. This device mainly consists of two modules: a protocol conversion module and a PIO transaction processing module. When the processor initiates a PIO read / write request, the protocol conversion module performs the conversion of the read / write request between the AXI protocol and the PIO protocol and maps the response status; the PIO transaction processing module parses the converted PIO read / write request, initiates register access and write descriptor operations to the network protocol processing unit, and receives the returned register read response data. This invention adopts a decoupling design of address, data, and response channels to complete the conversion of PIO read / write transactions between the AXI interface and the network protocol interface, realizing high-bandwidth, low-latency, non-blocking PIO data transmission and processing. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the PIO communication device in an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram illustrating the principle of protocol conversion in an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of the PIO transaction processing flow in an embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of the PIO transaction processing architecture in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] like Figure 1As shown, the PIO communication device for the converged computing architecture in this embodiment includes a protocol conversion module and a PIO transaction processing module that are interconnected. The protocol conversion module is connected to the computing components connected to the on-chip network (NoC) via an AXI interface. The computing components include at least one of general-purpose computing components and accelerated computing components. When the computing components initiate AXI read / write requests, the protocol conversion module performs the conversion of read / write requests between the AXI protocol and the PIO protocol and maps the response status. The PIO transaction processing module parses the converted PIO read / write requests, initiates register access and write descriptor operations to the network protocol processing component, and receives the register read response data returned by it.

[0022] like Figure 1 As shown, the protocol conversion module in this embodiment includes a transaction request conversion unit, a transaction data conversion unit, and a transaction state conversion unit. The transaction request conversion unit is used to perform handshake signal parsing, address mapping, and data length calculation to complete the conversion from AXI read / write requests to PIO read / write requests. The transaction data conversion unit is used to convert AXI transaction data, PIO write request data, and PIO read response data. The state conversion unit is used to convert the PIO transaction processing result into an AXI response and feed it back to the processor via the AXI bus. Specifically, the transaction request conversion unit parses the AXI request signal (including the request handshake signal, address information, and data length), maps it to the PIO read / write request address, and calculates the PIO request data length using the AXI request's Burst and data granularity, completing address offset processing, PIO address space information generation, and PIO data length adaptation calculation. The transaction data conversion unit completes the Big / Little Endian conversion of PIO communication data to ensure cross-protocol data consistency. The transaction state conversion unit is used to monitor the processing progress of the PIO request, parse the processing status of the PIO request, convert it into an AXI response request, and finally feed the result back to the processor via the AXI response handshake signal.

[0023] In this embodiment, the protocol conversion module further includes a protocol conversion state machine for controlling protocol conversion. The protocol conversion state machine comprises four stages: initial state (IDLE), address resolution state (ADDR_PARSE), data transmission state (DATA_XFER), and response adaptation state (RESP_ADAPT). After power-on reset, the protocol conversion module is in the initial state (IDLE), waiting for AXI transaction requests. When an AXI read / write transaction request signal is detected, the module enters the address resolution state (ADDR_PARSE) to complete the PIO request conversion. In the address resolution state (ADDR_PARSE), the transaction request conversion unit performs address offset processing, address space encoding, and PIO data length calculation conversion. After the conversion is completed, the module enters the data transmission state (DATA_XFER) to realize PIO data conversion. In the data transmission state (DATA_XFER), the transaction data conversion unit performs endianness conversion based on the transaction type: if it is a write transaction request, the protocol conversion module waits for the AXI data to be valid and then converts the AXI interface data to Big / Little. Endian conversion; if it is a read transaction request, the protocol conversion module waits for the PIO read data to be valid before performing the conversion. After the transmission is completed, the protocol conversion module enters the response adaptation state (RESP_ADAPT) to provide feedback on the PIO processing status and generate an AXI response signal. In the response adaptation state (RESP_ADAPT), the protocol conversion module waits for the transaction processing signal requested by the PIO, completes the AXI response encoding, and returns to the initial state (IDLE).

[0024] like Figure 2As shown, the transaction request conversion unit performs handshake signal parsing, address mapping, and data length calculation to complete the conversion from AXI read / write requests to PIO read / write requests. When the processor initiates an AXI read / write transaction request through the AXI bus, the transaction request conversion unit parses the request interface signals, generates and sends a PIO transaction request. For address information, in addition to transmitting the physical address, the transaction request conversion unit generates PIO address space signals based on the AXI interface address. When performing address offset processing, address space encoding, and PIO data length calculation, the transaction request conversion unit performs address offset processing and address space encoding as follows: Considering the possibility of multiple consecutive write requests to the same address for PIO write descriptors, the transaction request conversion unit registers the address and data length of each write descriptor request. If the request address is the same as the previous request address, the offset address and PIO address space information are generated using the address and data length of the previous request, and the registered address and data length are updated to ensure that the data is written to the correct address space. The calculation of the PIO data length includes: for cases where AXIBurst is not 1, the PIO data length is calculated based on the product of Burst and data granularity in the AXI address signal (e.g., if Burst is 8 and the bus data width is 32 bits, then the data length is 4 bytes × 8 = 32 bytes), where the data granularity is the AXI bus data width; otherwise, the valid bits of the statistical data byte are used as the PIO data length. In addition, when the transaction request conversion unit receives a PIO transaction request response signal, it performs PIO transaction data conversion and responds to AXI read / write transaction requests via the AXI bus.

[0025] like Figure 2 As shown, the transaction data conversion unit completes the conversion between PIO write request data and PIO read response data. For write transactions, the transaction data conversion unit initiates a write data request and waits for the PIO read data enable signal. When the PIO read data enable signal is valid, the data undergoes Big / Little Endian conversion, and the counter starts counting the amount of data transmitted. If the length of the data to be transmitted is less than the data bus width, the transaction data conversion unit sets the last data signal to valid, notifying the network component that data transmission has ended. For read transactions, the transaction data conversion unit waits for the PIO write data enable signal. When the PIO write data enable signal is valid, the data undergoes Big / Little Endian conversion. If the length of the data to be transmitted is less than the data bus width, the transaction data conversion unit sets the last data signal to valid, notifying the processor that data transmission has ended. After data transmission is completed, the transaction data conversion unit invalidates the write data request.

[0026] like Figure 2As shown, the transaction status transition unit is responsible for converting the PIO transaction processing result into an AXI response and feeding it back to the processor via the AXI bus. In write transaction processing, after the write data request is acknowledged, the transaction status transition unit waits for the data transmission to complete before initiating an AXI response request, encoding the PIO transaction processing status (success / error) into an AXI response signal to notify the processor of the data transmission status. In read transaction request processing, the PIO transaction processing status (success / failure) is encoded into an AXI response signal and sent to the processor simultaneously with the completion of PIO data feedback.

[0027] like Figure 1 As shown, the PIO transaction processing module in this embodiment includes a request arbitration unit, a read / write control unit, and a read response unit. The request arbitration unit arbitrates and allocates resources for PIO read / write transaction requests converted by the protocol conversion module. The read / write control unit controls register access or descriptor write operations on the network protocol processing component and performs different processing on read / write requests based on the arbitration result of the request arbitration unit. The read response unit receives read response data from the network protocol processing component and read request information to be responded to from the read / write control unit. After combining the data and related information, it returns the response to the protocol conversion module as a PIO read response. The PIO transaction processing module includes a request arbitration unit, a read / write control unit, and a read response unit. The arbitration unit arbitrates read and write requests based on credit value and request priority to determine the processing order. The read and write control unit performs register access or write descriptor operations on the network protocol processing unit based on the successful arbitration request information (target address and data length), and simultaneously stores the unsuccessful arbitration requests. The read response unit caches the processed read request information and the data returned by the network protocol processing unit, and notifies the read and write control unit and the protocol conversion module of the transaction processing status and releases resources based on the status of the read request cache and the data cache, respectively.

[0028] Figure 3 This is a flowchart illustrating the PIO transaction processing in this embodiment. See [link / reference] Figure 3In this embodiment, the PIO transaction processing flow includes: S101, receiving a PIO request; S102, determining the request type of the PIO request; if only a single request is received and no read / write data transmission is performed, proceed to step S104; if only a single request is received but read / write data transmission is in progress, proceed to step S105; if read / write transaction request signals are detected simultaneously, i.e., read / write requests are received simultaneously, proceed to step S103; S103, arbitrating the PIO request; if the arbitration is successful, proceed to step S104; otherwise, proceed to step S105; S104, responding to the PIO request, preparing for data transmission, executing read / write data transmission until data transmission is complete, and jumping to step S106; S105, registering the PIO request, and proceeding to step S106; S106, determining whether the request waiting queue is not empty; if it is, jump to step S104; otherwise, proceed to step S101.In this embodiment, the PIO transaction processing module also includes a transaction processing state machine for controlling PIO transaction processing. The transaction processing state machine includes four stages: initial state (IDLE), arbitration state (ARB), response state (ACK), and read / write data transmission state (OPERATION). After power-on reset, the transaction processing state machine is in the initial state (IDLE), indicating that the PIO transaction processing module is idle. When the PIO transaction processing module receives a valid PIO read / write transaction request signal, it parses the request address, data length, and transaction type. If read / write transaction request signals are detected simultaneously, the transaction processing state machine transitions to the arbitration state (ARB) to arbitrate the read / write request. If only a single request is received and no read / write data transmission is occurring, the transaction processing state machine transitions to the response state (ACK) to respond to the request. If only a single request is received but read / write data transmission is in progress, the new request is temporarily stored in the request waiting queue, waiting for the current data transmission to complete. When the transaction processing state machine is in the arbitration state (ARB), the request arbitration unit arbitrates the received read / write transaction requests based on transaction priority and system credit value. Arbitration is requested. If the credit value is insufficient, the state machine remains in the Arbitration (ARB) state until resources are restored. If the credit value is sufficient, the state machine processes high-priority requests first, while temporarily storing low-priority requests in the request waiting queue. When the transaction processing state machine is in the ACK state, the PIO transaction processing module responds to read / write transaction requests. After the data transmission preparation for the relevant requests is completed, the state machine transitions to the read / write data transmission state (OPERATION) for data transmission. When the transaction processing state machine is in the read / write data transmission state (OPERATION), the read / write control unit performs different data processing operations according to the type of read / write request: if it is a read request, read data is obtained from the network protocol processing component; if it is a write request, data is written to the network protocol processing component according to the target address. After the data transmission is completed, the read acknowledgment unit feeds back the processing status of the read / write transaction to the protocol conversion module. Then, the PIO transaction processing module makes a judgment: if the request waiting queue is empty, it transitions to the initial state (IDLE) to receive new requests; if the request waiting queue is not empty, it continues to respond to the requests temporarily stored in the request waiting queue.

[0029] like Figure 4As shown, the request arbitration unit in this embodiment is mainly responsible for arbitrating and allocating resources for PIO read and write transaction requests converted by the protocol conversion module. During the arbitration process, if the PIO transaction processing module has sufficient credit value, arbitration is conducted according to the request priority. High-priority requests directly enter the request processing flow, while low-priority requests are temporarily stored in the request waiting queue. When the system credit value is insufficient, the request arbitration unit maintains the arbitration state until resources are restored. During this process, the request arbitration unit will promptly return read / write request reception signals and synchronously receive write data for write requests. If the arbitration result is that the write request passes, the write request enable, write request address, write data length, and write data are delivered to the read / write control unit, and the read / write control unit stores the relevant information of the read request; if the arbitration result is that the read request passes, the read request ID, read request enable, read request address, and read data length are delivered to the read / write control unit, and the read / write control unit stores the relevant information of the write request.

[0030] like Figure 4As shown, in this embodiment, the read / write control unit controls register access or descriptor write operations on the network protocol processing unit, and performs different processing on read / write requests according to the arbitration result of the request arbitration unit. For read requests, the read / write control unit obtains read data from the network protocol processing unit by: firstly, after detecting a read request enable signal, the read / write control unit reduces the credit of the read request and stores the read request in the read request register; then, the read / write control unit judges according to the read response status fed back by the read response unit: if the FIFO of read requests to be responded to is not full in the read response status, the read / write control unit transmits the read request ID and address information representing the transaction number to the read response unit, and at the same time, the read / write control unit reads the required register data from the network protocol processing unit according to the read address and data length, and waits for the read response unit to feed back the read response completion; if the FIFO of read requests to be responded to is full, the read / write control unit no longer sends read requests to the network protocol processing unit until the FIFO of requests to be responded to is not full; after completing the current transaction processing, the read / write control unit feeds back the read / write status to the request arbitration unit and restores the corresponding read / write request credit. For write requests, the read / write control unit writes data to the network protocol processing unit based on the target address, including: First, upon detecting a write request enable signal, the read / write control unit decrements the write request credit and registers the write request in the write request register; then, the read / write control unit determines the corresponding target based on the write request address. If the target is a descriptor, after completing the descriptor combination, the write descriptor enable is enabled, and the data is written to the descriptor space; if the target is a register, the write register enable is enabled, and the data is written to the register. During transmission, the unit's built-in counter tracks the transmission progress in real time, decrementing according to the data length. When the counter decrements to zero, the PIO last data flag is set, indicating that the write request is complete; after completing the current transaction processing, the read / write control unit reports the read / write status to the request arbitration unit and restores the corresponding read / write request credit.

[0031] like Figure 4As shown, in this embodiment, the read response unit receives read response data from the network protocol processing component and read request information to be responded to from the read / write control unit. After combining the data and related information, it returns the data to the protocol conversion module in the form of a PIO read response. Specifically, the read response unit in this embodiment includes a read request FIFO awaiting response and a read data FIFO. The read response unit provides feedback on the processing status of read / write transactions to the protocol conversion module, including: when the read response unit detects the read request ID and address offset sent by the read / write control unit, it enables the write function of the read request FIFO awaiting response and caches the read request ID and address offset; when it detects a valid read response enable signal from the network protocol processing unit, it enables the write function of the read data FIFO and writes the read response data into the read data FIFO; when the read data FIFO is not empty, it indicates that the network protocol processing unit has returned the read response data from the register; simultaneously, the read response unit enables the read function of both the read request FIFO awaiting response and the read data FIFO, and retrieves the response data, read request ID, and offset address from the FIFO according to the first-in-first-out principle; the read response unit notifies the protocol conversion module to receive the read data and read completion signal based on the read request ID, returns the read response status to the read / write control unit, and then releases the occupied peripheral resources to prepare for the processing of subsequent new transactions.

[0032] In addition, this embodiment also provides a converged computing device, including a processor chip and a memory connected to each other, wherein the processor chip includes the PIO communication device for the converged computing architecture described above.

[0033] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A PIO communication device for a converged computing architecture, characterized in that, The system includes an interconnected protocol conversion module and a PIO transaction processing module. The protocol conversion module is connected to a computing unit on the on-chip network NoC via an AXI interface. The computing unit includes at least one of a general-purpose computing unit and an accelerated computing unit. When the computing unit initiates a PIO read / write request, the protocol conversion module performs the conversion between the AXI protocol and the PIO protocol and maps the response status. The PIO transaction processing module parses the converted PIO read / write request, initiates register access and write descriptor operations to the network protocol processing unit, and receives the register read response data returned by the unit. The protocol conversion module includes a transaction request conversion unit, a transaction data conversion unit, and a transaction state conversion unit. The transaction request conversion unit is used to perform handshake signal parsing, address mapping, and data length calculation to complete the conversion from AXI read / write request to PIO read / write request. The transaction data conversion unit is used to convert AXI transaction data, PIO write request data, and PIO read response data. The state conversion unit is used to convert the PIO transaction processing result into an AXI response and feed it back to the processor through the AXI bus. The PIO transaction processing module includes a request arbitration unit, a read / write control unit, and a read response unit. The request arbitration unit is used to arbitrate and allocate resources for PIO read / write transaction requests converted by the protocol conversion module. The read / write control unit is used to control register access or descriptor write operations on the network protocol processing component and performs different processing on read / write requests according to the arbitration result of the request arbitration unit. The read response unit is used to receive read response data from the network protocol processing component and read request information to be responded to from the read / write control unit. After combining the data and related information, it returns the data to the protocol conversion module in the form of a PIO read response.

2. The PIO communication device for a converged computing architecture according to claim 1, characterized in that, The protocol conversion module also includes a protocol conversion state machine for controlling protocol conversion. This state machine comprises four stages: initial state, address resolution state, data transmission state, and response adaptation state. After power-on reset, the protocol conversion module is in the initial state, waiting for AXI transaction requests. When an AXI read / write transaction request signal is detected, the module enters the address resolution state to complete the PIO request conversion. In the address resolution state, the transaction request conversion unit performs address offset processing, address space encoding, and PIO data length calculation. After conversion, the module enters the data transmission state to implement PIO data conversion. In the data transmission state, the transaction data conversion unit performs endianness conversion based on the transaction type: for write transaction requests, the protocol conversion module waits for valid AXI data and then performs Big / Little Endian conversion on the AXI interface data; for read transaction requests, the protocol conversion module waits for valid PIO read data feedback before performing the conversion. After transmission, the protocol conversion module enters the response adaptation state to provide feedback on the PIO processing status and generate an AXI response signal. In the response adaptation state, the protocol conversion module waits for the transaction processing signal for the PIO request, completes the AXI response encoding, and then returns to the initial state.

3. The PIO communication device for a converged computing architecture according to claim 2, characterized in that, When performing address offset processing, address space encoding, and PIO data length calculation, the transaction request conversion unit performs address offset processing and address space encoding as follows: The transaction request conversion unit registers the address and data length of each write descriptor request. If the request address is the same as the previous request address, it generates an offset address and PIO address space information using the address and data length of the previous request, and updates the registered address and data length to ensure that the data is written to the correct address space. The calculation of the PIO data length includes: for the case where AXI Burst is not 1, the PIO data length is calculated based on the product of Burst in the AXI address signal and the data granularity, where the data granularity is the AXI bus data bit width; otherwise, the valid bits of the statistical data byte are used as the PIO data length.

4. The PIO communication device for a converged computing architecture according to claim 1, characterized in that, The PIO transaction processing module also includes a transaction processing state machine for controlling PIO transaction processing. The transaction processing state machine includes four stages: initial state, arbitration state, response state, and read / write data transmission state. After power-on reset, the transaction processing state machine is in the initial state, indicating that the PIO transaction processing module is idle. When the PIO transaction processing module receives a valid PIO read / write transaction request signal, it parses the request address, data length, and transaction type of the transaction. If read and write transaction request signals are detected simultaneously, the transaction processing state machine transitions to the arbitration state to arbitrate the read and write requests. If only a single request is received and no read or write data transmission has occurred, the transaction processing state machine transitions to the response state to respond to the request. If only a single request is received but read or write data transmission is in progress, the new request is temporarily stored in the request waiting queue, waiting for the current data transmission to complete. When the transaction processing state machine is in the arbitration state, the received read and write transaction requests are arbitrated by the request arbitration unit based on transaction priority and system credit value. If the credit value is insufficient, the state machine remains in the arbitration state until resources are restored. If the credit value is sufficient, the state machine processes high-priority requests first, while temporarily storing low-priority requests in the request waiting queue. When the transaction processing state machine is in the response state, the PIO transaction processing module responds to read / write transaction requests. After the data transmission preparation for the relevant request is completed, the state machine transitions to the read / write data transmission state to perform data transmission. When the transaction processing state machine is in the read / write data transmission state, the read / write control unit performs different data processing operations according to the type of read / write request: if it is a read request, it obtains read data from the network protocol processing component; if it is a write request, it writes data to the network protocol processing component according to the target address. After the data transmission is completed, the read response unit sends feedback on the processing status of the read / write transaction to the protocol conversion module. Then, the PIO transaction processing module makes a judgment: if the request waiting queue is empty, it will move to the initial state to receive new requests. If the request waiting queue is not empty, continue to respond to requests temporarily stored in the request waiting queue.

5. The PIO communication device for a converged computing architecture according to claim 4, characterized in that, The process of obtaining read data from the network protocol processing unit includes: First, upon detecting a read request enable signal, the read / write control unit reduces the read request credit and stores the read request in the read request register. Then, the read / write control unit determines the status based on the read response status fed back by the read response unit: if the pending read request FIFO is not full, the read / write control unit transmits the read request ID (representing the transaction number) and address information to the read response unit. Simultaneously, the read / write control unit reads the required register data from the network protocol processing unit based on the read address and data length, and waits for the read response unit to report read response completion. If the pending read request FIFO is full, the read / write control unit stops sending read requests to the network protocol processing unit until the pending FIFO is not full. After completing the current transaction processing, the read / write control unit reports the read / write status to the request arbitration unit and restores the corresponding read / write request credit.

6. The PIO communication device for a converged computing architecture according to claim 5, characterized in that, The process of writing data to the network protocol processing unit based on the target address includes: First, upon detecting a write request enable signal, the read / write control unit decrements the write request credit and registers the write request in the write request register. Then, the read / write control unit determines the corresponding target based on the write request address. If the target is a descriptor, the write descriptor enable is enabled after descriptor combination, and the data is written to the descriptor space. If the target is a register, the write register enable is enabled, and the data is written to the register. During transmission, a built-in counter tracks the transmission progress in real time, decrementing according to the data length. When the counter decrements to zero, the PIO last data flag is set, indicating that the write request is complete. After completing the current transaction processing, the read / write control unit reports the read / write status to the request arbitration unit and restores the corresponding read / write request credit.

7. The PIO communication device for a converged computing architecture according to claim 4, characterized in that, The read response unit includes a read request FIFO awaiting response and a read data FIFO. The process of using the read response unit to feedback the processing status of read / write transactions to the protocol conversion module includes: when the read response unit detects the read request ID and address offset sent by the read / write control unit, the read response unit enables the write function of the read request FIFO awaiting response and caches the read request ID and address offset; when a valid read response enable signal is detected from the network protocol processing unit, the read response unit enables the write function of the read data FIFO and writes the read response data into the read data FIFO; when the read data FIFO is not empty, it indicates that the network protocol processing unit has returned the read response data from the register; simultaneously, the read response unit enables the read function of both the read request FIFO awaiting response and the read data FIFO, and retrieves the response data, read request ID, and offset address from the FIFO according to the first-in-first-out principle; the read response unit notifies the protocol conversion module to receive the read data and read completion signal based on the read request ID, returns the read response status to the read / write control unit, and then releases the occupied peripheral resources to prepare for the processing of subsequent new transactions.

8. A converged computing device, comprising interconnected processor chips and memory, characterized in that, The processor chip includes the PIO communication device for a converged computing architecture as described in any one of claims 1 to 7.

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