Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a plurality of driving signal lines which are located in a display area and extend in the first direction and at least one testing signal line extending in the second direction, and the first direction intersects with the second direction; the test signal line comprises a first test signal line branch and a second test signal line branch which are electrically connected in different layers; the first test signal line branch and the driving signal line are arranged on different layers; and along the thickness direction of the display panel, the first test signal line subsections and the driving signal lines are at least partially overlapped. According to the display panel, the testing signal lines are subjected to overline design, the distance between the testing signal lines and the driving signal lines is reduced, the stray capacitance between the testing signal lines and the driving signal lines is reduced, signal crosstalk is reduced, and the display effect of the display panel is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As an important part of the information industry, display technology has played an important role in the development of information technology. With the development of display technology, display panels such as borderless spliced display panels have been widely used.

[0003] However, the display performance of the display panel in the related art is insufficient. Summary of the Invention

[0004] The present invention provides a display panel and a display device, which can reduce parasitic capacitance between signal lines, lower crosstalk between signals, and ensure the display effect of the display panel.

[0005] In a first aspect, the present invention provides a display panel, comprising a plurality of drive signal lines extending along a first direction and at least one test signal line extending along a second direction in a display area, wherein the first direction intersects the second direction;

[0006] The test signal line includes a first test signal line section and a second test signal line section electrically connected in different layers; the first test signal line section and the drive signal line are arranged in different layers;

[0007] Along a thickness direction of the display panel, the first test signal line section and the driving signal line at least partially overlap.

[0008] In a second aspect, the present invention provides a display device comprising the display panel according to any one of the first aspects.

[0009] The technical solution of an embodiment of the present invention is that a display panel includes multiple drive signal lines extending along a first direction and at least one test signal line extending along a second direction in a display area, wherein the first direction intersects the second direction; the test signal line includes a first test signal line section and a second test signal line section electrically connected to each other in different layers; the first test signal line section and the drive signal line are arranged in different layers; and along the thickness direction of the display panel, the first test signal line section and the drive signal line at least partially overlap. By designing the test signal line as a cross-line, the distance between the test signal line and the drive signal line is reduced, the parasitic capacitance between the test signal line and the drive signal line is reduced, and signal crosstalk is reduced, thereby ensuring the display effect of the display panel.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0013] Figure 2 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 3 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0015] Figure 4 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0016] Figure 5 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0017] Figure 6 A schematic structural diagram of an active layer provided in an embodiment of the present invention;

[0018] Figure 7 A schematic structural diagram of a first metal layer provided in an embodiment of the present invention;

[0019] Figure 8 A schematic structural diagram of a second metal layer provided in an embodiment of the present invention;

[0020] Figure 9 A schematic structural diagram of a third metal layer provided in an embodiment of the present invention;

[0021] Figure 10 A schematic structural diagram of a first via hole provided by an embodiment of the present invention;

[0022] Figure 11 A schematic structural diagram of a second via hole provided by an embodiment of the present invention;

[0023] Figure 12 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0024] Figure 13 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0025] Figure 14 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0026] Figure 15 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0027] Figure 16 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0028] Figure 17 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0029] Figure 18 A schematic structural diagram of another display device provided by an embodiment of the present invention;

[0030] Figure 19 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 2 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 1 and Figure 2As shown, the display panel includes a plurality of drive signal lines 102 extending along a first direction X and at least one test signal line 103 extending along a second direction Y, located in a display area 101, wherein the first direction X intersects the second direction Y; the test signal line 103 includes a first test signal line section 1031 and a second test signal line section 1032 electrically connected in different layers; the first test signal line section 1031 and the drive signal line 102 are arranged in different layers; along the thickness direction Z of the display panel, the first test signal line section 1031 and the drive signal line 102 at least partially overlap.

[0034] The display panel includes a plurality of drive signal lines 102 extending along a first direction X. The drive signal lines 102 are generally located at the edge of the display area 101. The drive signal lines 102 can be understood as signal buses, such as high voltage lines, low voltage lines, clock signal lines, signal input lines, and other signal buses, so as to transmit corresponding drive signals from the edge of the display area 101 to the display sub-area 10 of the display panel. The drive signal lines include the signals necessary for driving the display panel, and there are dozens of them. Figure 1In the example, 7 drive signal lines are used for display. A plurality of light-emitting elements and pixel circuits can be provided in the display sub-area, and the light-emitting elements can include Micro LEDs or Mini LEDs. The test signal line 103 is usually located in the lower frame area of the display panel. The test signal line 103 can be retained after the test is completed. A fixed signal can be passed into the test signal line 103 to avoid interference with the remaining signal lines in the display panel or interference from the remaining signal lines, thereby affecting the display effect of the display panel. Typically, the test signal line 103 can be a metal trace for providing power for testing, and can be exemplarily a PVDD constant voltage signal line and a PVEE constant voltage signal line. Since the driving signal line 102 and the test signal line 103 extend in different directions and overlap in space, and the test signal line 103 is usually larger, the spatial overlapping area between the driving signal line 102 and the test signal line 103 is relatively large. Both the driving signal line 102 and the test signal line 103 are metal lines, which will produce a large parasitic capacitance. When both the driving signal line 102 and the test signal line 103 are in a signal transmission state, it is easy to cause signal interference, affect the signal transmission effect, and thus affect the test effect. In view of the above technical problems, the test signal line 103 can be set differently, and the test signal line 103 can be set to include a first test signal line division 1031 and a second test signal line division 1032 electrically connected in different layers. For example, the test signal line 103 can include a second test signal line division 1032, a first test signal line division 1031 and a second test signal line division 1032 arranged in sequence, and the first test signal line division 1031 and the second test signal line division 1032 are arranged in different layers. The test signal line 103 is designed to cross the line so that along the thickness direction Z of the display panel, the first test signal line division 1031 and the second test signal line division 1032 are electrically connected in different layers. The line section 1031 and the driving signal line 102 at least partially overlap, and the first test signal line section 1031 and the driving signal line 102 are respectively located in different metal layers, so that along the thickness direction Z of the display panel, the distance between the first test signal line section 1031 and the driving signal line 102 is greater than the distance between the second test signal line section 1032 and the driving signal line 102, thereby reducing the parasitic capacitance between the first test signal line section 1031 and the driving signal line 102, ensuring the signal transmission effect between the test signal line 103 and the driving signal line 102, ensuring the test effect, and thus ensuring the display effect of the display panel.

[0035] In an embodiment of the present invention, a display panel is provided with a plurality of drive signal lines extending along a first direction and at least one test signal line extending along a second direction in a display area, wherein the first direction intersects the second direction. The test signal line includes a first test signal line section and a second test signal line section electrically connected to each other in different layers. The first test signal line section and the drive signal line are provided in different layers. The first test signal line section and the drive signal line at least partially overlap along the thickness direction of the display panel. By designing the test signal line as a cross-line, the distance between the test signal line and the drive signal line is reduced, the parasitic capacitance between the test signal line and the drive signal line is reduced, and signal crosstalk is reduced, thereby ensuring the display effect of the display panel.

[0036] Optional, Figure 3 A schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 4 A schematic diagram of another display panel structure provided by an embodiment of the present invention, referring to Figure 1 、 Figure 2 、 Figure 3 and Figure 4 As shown, the second test signal line section 1032 and the driving signal line 102 are arranged in different layers. Figure 1 and Figure 2 As shown, the test signal line 103 and the driving signal line 102 extend in different directions and do not overlap. The second test signal line section 1032 in the test signal line 103 and the driving signal line 102 can be arranged on the same layer, and the two can be arranged at intervals to avoid contact short circuit, or as shown in FIG. Figure 3 and Figure 4 As shown, the first test signal line section 1031 and the second test signal line section 1032 in the test signal line 103 and the driving signal line 102 can be prepared in different metal layers to avoid interference between the signal lines and ensure the signal transmission effects of the test signal line 103 and the driving signal line 102.

[0037] Optional, continue to refer to Figure 4 The display panel includes a substrate 104; a first metal layer 105 located on one side of the substrate 104, a second metal layer 106 located on a side of the first metal layer 105 away from the substrate 104, and a third metal layer 107 located on a side of the second metal layer 106 away from the substrate 104; wherein, the second test signal line branch 1032 is located in the first metal layer 105; the driving signal line 102 is located in the second metal layer 106; the first test signal line branch 1031 is located in the third metal layer 107, and the first test signal line branch 1031 is electrically connected to the second test signal line branch 1032 through a first via 108.

[0038] Among them, the substrate 104 can be a rigid substrate or a flexible substrate. The specific type of substrate 104 can be set according to actual design requirements. A shielding metal layer 20 located on one side of the substrate and an active layer located on the side of the shielding metal layer 20 away from the substrate 104 are set in the display panel. The shielding metal layer 20 prevents external interference from affecting the threshold voltage of the transistor, thereby ensuring the working stability of the transistor. The display panel also includes a first metal layer 105, a second metal layer 106 and a third metal layer 107 located on one side of the substrate 104. Between the first metal layer 105 and the second metal layer 106, there is a first inorganic layer 11 covering the first metal layer 105 and a second inorganic layer 12 located between the first inorganic layer 11 and the second metal layer 106. Between the second metal layer 106 and the third metal layer 107, there is a third inorganic layer 13 covering the second metal layer 106 and a first organic layer 14 located between the third inorganic layer 13 and the third metal layer 107. Usually, the thickness of the first organic layer 14 is greater than the thickness of the first inorganic layer 11, the second inorganic layer 12 and the third inorganic layer 13. The first metal layer 105 may include a gate metal layer, a first plate of a capacitor and a portion of the first test signal line 103, the second metal layer 106 may include a source / drain metal layer and a drive signal line 102 extending along the first direction X, the third metal layer 107 may include a portion of the first test signal line 103, and the test signal line 103 is set across the line so that the first test signal line section 1031 overlapping with the drive signal line 102 is set in the third metal layer 107, and the second test signal line section 1032 is set in the first metal layer 105. The first test signal line section 1031 and the second test line section are electrically connected through the first via 108 to ensure the transmission of the test signal, and the drive signal line 102 and the first test signal line section 1031 are separated by a thicker dielectric layer formed by the third inorganic layer 13 and the first organic layer 14 to reduce the parasitic capacitance between the test signal line 103 and the drive signal line 102, reduce interference between signals, and ensure signal transmission quality.

[0039] Optional, Figure 5 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 5As shown, the display panel includes a substrate 104; a first metal layer 105 located on one side of the substrate 104, a second metal layer 106 located on a side of the first metal layer 105 away from the substrate 104, and a third metal layer 107 located on a side of the second metal layer 106 away from the substrate 104; the display panel also includes a first connecting line 109, the first connecting line 109 is located in the second metal layer 106; the second test signal line branch 1032 is located in the first metal layer 105; the driving signal line 102 is located in the second metal layer 106; the first test signal line branch 1031 is located in the third metal layer 107, the second test signal line branch 1032 is electrically connected to the first connecting line 109 through the second via 110, and the first test signal line branch 1031 is electrically connected to the first connecting line 109 through the third via 111.

[0040] The display panel is provided with a first metal layer 105, a second metal layer 106, and a third metal layer 107 located on the side of the active layer 21 away from the substrate 104. The first metal layer 105 and the second metal layer 106 include a first inorganic layer 11 covering the first metal layer 105 and a second inorganic layer 12 located between the first inorganic layer 11 and the second metal layer 106. The second metal layer 106 and the third metal layer 107 include a third inorganic layer 13 covering the second metal layer 106 and a third inorganic layer 13 located between the third inorganic layer 13 and the third metal layer 107. The first organic layer 14, the first metal layer 105 may include a gate metal layer 22, a first electrode of the capacitor 24 and a portion of the first test signal line 103, the second metal layer 106 may include a source / drain metal layer and a drive signal line 102 extending along the first direction X, the third metal layer 107 may include a portion of the first test signal line 103, the test signal line 103 is arranged across the line, so that the first test signal line segment 1031 overlapping with the drive signal line 102 is arranged on the third metal layer 107, and the second test signal line segment 1032 is arranged In the first metal layer 105, however, since the electrical connection between the second test signal line division 1032 and the first test signal line division 1031 needs to be made by setting a via in a thicker dielectric layer formed by the first inorganic layer 11, the second inorganic layer 12, the third inorganic layer 13 and the first organic layer 14, in order to avoid deep drilling and increase the difficulty of the process, a first connecting line 109 can be set in the same layer as the second metal layer 106, and a second via 110 can be set on the first inorganic layer 11 and the second inorganic layer 12 between the first metal layer 105 and the second metal layer 106. A third via 111 is provided on the third inorganic layer 13 and the first organic layer 14 between the layer 106 and the third metal layer 107, so that the second test signal line section 1032 located in the first metal layer 105 is electrically connected to the first connecting line 109 located in the second metal layer 106 through the second via 110, and the first connecting line 109 located in the second metal layer 106 is electrically connected to the first test signal line section 1031 located in the third metal layer 107 through the third via 111, and the transmission effect of the test signal in the test signal line 103 is ensured by multi-level punching.

[0041] The display panel is formed by stacking patterned film layers, and various signal lines are distributed in the film layers. Therefore, each film layer includes test signal lines and drive signal lines, as well as various signal lines of the pixel circuit. The test signal lines and drive signal lines can be prepared on the same layer as some signals in the pixel circuit, simplifying the preparation process. Figures 6 to 9 An exemplary structure of a single film layer is given in sequence, wherein: Figure 6 A schematic structural diagram of an active layer provided in an embodiment of the present invention is shown. Figure 7 A schematic structural diagram of a first metal layer provided in an embodiment of the present invention is shown. Figure 8A schematic structural diagram of a second metal layer provided in an embodiment of the present invention is shown. Figure 9 A schematic structural diagram of a third metal layer provided in an embodiment of the present invention, referring to Figure 6 、 Figure 7 、 Figure 8 and Figure 9 As shown, the display panel includes a first semiconductor layer, and the semiconductor traces in the first semiconductor layer usually form a channel layer of the thin film transistor in the area where they overlap with the signal lines in the first metal layer. The signal lines related to the pixel circuit are not shown in the figure. Optionally, the display panel also includes an anti-static structure 123, and along the thickness direction Z of the display panel, the anti-static structure 123 at least partially overlaps with the second test signal line section 1032. Among them, the display panel is also provided with an anti-static structure 123 that at least partially overlaps with the second test signal line section 1032 along the thickness direction Z of the display panel, so that when the test signal line 103 is cut and edged, static electricity generated during the edge grinding process is prevented from damaging the circuit, thereby ensuring the display effect of the display panel. The shape of the anti-static structure 123 can be straight, curved or irregular, and the specific shape can be selected according to actual design requirements, and the embodiment of the present invention does not make specific limitations.

[0042] Optional, continue to refer to Figure 5 The display panel includes a pixel circuit, which includes multiple thin film transistors 30. The anti-static structure 123 is arranged on the same layer as the active layer 21 of the thin film transistor 30. The display panel is provided with a pixel circuit that provides a driving signal for the light-emitting element 40. The pixel circuit is usually provided with multiple thin film transistors 30. The thin film transistor 30 is composed of an active layer 21, a gate metal layer 22, a source and drain metal layer 23, a capacitor plate layer 24, etc. Considering the space of each film layer, the anti-static structure 123 can be set in the active layer 21. The anti-static structure 123 can be made of a metal material or the same material as the active layer 21, such as a metal oxide, to achieve the purpose of conducting static electricity in the display panel, preventing damage to the circuit caused by static electricity, and ensuring the display effect of the display panel.

[0043] refer to Figure 7 、 Figure 8 and Figure 9 As shown, when the pixel circuit is a 7T1C pixel circuit, the second scan line, the light emitting control signal line, the first scan line and the first plate of the storage capacitor (not shown in the figure) in the pixel circuit can be set in the first metal layer 104. Figure 7Two test signal lines 103 are exemplarily shown in the figure. The first metal layer 104 may also be provided with a second test signal line portion 1032 of the test signal line 103. The second metal layer 105 may be provided with a data signal line in a pixel circuit (not shown in the figure). A sub-metal layer is further included between the first metal layer 104 and the second metal layer 105. The sub-metal layer includes a first initialization signal line and a second initialization signal line in the pixel circuit and a second plate of the capacitor (not shown in the figure). The second metal layer 105 may be provided with a drive signal line 102 and a first connection structure 109. The third metal layer 107 may include a power signal line (not shown in the figure). The third metal layer 107 may also be provided with a first test signal line portion 1031 of the test signal line 103. Figure 10 A schematic structural diagram of a first via hole provided by an embodiment of the present invention is shown. Figure 11 A schematic structural diagram of a second via hole provided by an embodiment of the present invention is shown in FIG. Figure 10 and Figure 11 As shown, the second test signal line segment 1032 is electrically connected to the first connection line 109 through the second via 110. The first test signal line segment 1031 is electrically connected to the first connection line 109 through the third via 111, ensuring the connection of the test signal line 103 and the transmission of the test signal.

[0044] Optional, Figure 12 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 12 As shown, the display panel includes a substrate 104; a first metal layer 105 located on one side of the substrate 104, a second metal layer 106 located on a side of the first metal layer 105 away from the substrate 104, a third metal layer 107 located on a side of the second metal layer 106 away from the substrate 104, and a fourth metal layer 112 located on a side of the third metal layer 107 away from the substrate 104; wherein, the second test signal line division 1032 is located in the first metal layer 105; the driving signal line 102 is located in the second metal layer 106; the first test signal line division 1031 is located in the fourth metal layer 112, and the first test signal line division 1031 is electrically connected to the second test signal line division 1032 through the fourth via 113.

[0045] Among them, the display panel can also be provided with a first metal layer 105, a second metal layer 106, a third metal layer 107 and a fourth metal layer 112 located on one side of the substrate 104, and between the first metal layer 105 and the second metal layer 106, a first inorganic layer 11 covering the first metal layer 105 and a second inorganic layer 12 located between the first inorganic layer 11 and the second metal layer 106 are included, between the second metal layer 106 and the third metal layer 107, a third inorganic layer 13 covering the second metal layer 106 and a first organic layer 14 located between the third inorganic layer 13 and the third metal layer 107 are included, and between the fourth metal layer 112 and the third metal layer 107, a second organic layer 15 is included. Usually, the thickness of the first organic layer 14 and the second organic layer 15 are greater than the thickness of the first inorganic layer 11, the second inorganic layer 12 and the third inorganic layer 13. The first metal layer 105 may include a gate metal layer 22, a first electrode of the capacitor 24 and a portion of the first test signal line 103, the second metal layer 106 may include a source / drain metal layer 23 and a drive signal line 102 extending along the first direction X, the fourth metal layer 112 may include a portion of the first test signal line 103, and the test signal line 103 is set across the line so that the first test signal line section 1031 overlapping with the drive signal line 102 is set in the fourth metal layer 112, and the second test signal line section 1032 is set in the first metal layer 105. The first test signal line section 1031 and the second test line section are electrically connected through the fourth via 113 to ensure the transmission of the test signal, and the drive signal line 102 and the first test signal line section 1031 are separated by a thicker dielectric layer formed by the third inorganic layer 13, the first organic layer 14 and the second organic layer 15, thereby further effectively reducing the parasitic capacitance between the test signal line 103 and the drive signal line 102, reducing interference between signals, and ensuring signal transmission quality.

[0046] Optional, Figure 13 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 13As shown, the display panel includes a substrate 104; a first metal layer 105 located on one side of the substrate 104; a second metal layer 106 located on a side of the first metal layer 105 away from the substrate 104; a third metal layer 107 located on a side of the second metal layer 106 away from the substrate 104; and a fourth metal layer 112 located on a side of the third metal layer 107 away from the substrate 104; a second test signal line branch 1032 located on the first metal layer 105; a drive signal line 102 located on the second metal layer 106; and a first test signal line branch 1031 located on the second metal layer 106. In the fourth metal layer 112; wherein, the display panel also includes a second connecting line 114 and a third connecting line 115, the second connecting line 114 is located in the second metal layer 106, and the third connecting line 115 is located in the third metal layer 107; the second test signal line branch 1032 is electrically connected to the second connecting line 114 through the fifth via 116, the second connecting line 114 branch is electrically connected to the third connecting line 115 through the sixth via 117, and the first test signal line branch 1031 is electrically connected to the third connecting line 115 through the seventh via 118.

[0047] The display panel is provided with a first metal layer 105, a second metal layer 106 and a third metal layer 107 located on one side of the substrate 104, wherein the first metal layer 105 and the second metal layer 106 include a first inorganic layer 11 covering the first metal layer 105 and a second inorganic layer 12 located between the first inorganic layer 11 and the second metal layer 106, and the second metal layer 106 and the third metal layer 107 include a third inorganic layer 13 covering the second metal layer 106, a first organic layer 14 located between the third inorganic layer 13 and the third metal layer 107, and a second organic layer 15 located between the third metal layer 107 and the fourth metal layer 112. 105 may include a gate metal layer 22, a first plate of the capacitor 24 and a portion of the first test signal line 103, the second metal layer 106 may include a source / drain metal layer 23 and a drive signal line 102 extending along the first direction X, the fourth metal layer 112 may include a portion of the first test signal line 103, the test signal line 103 is arranged across the line, so that the first test signal line section 1031 overlapping with the drive signal line 102 is arranged in the fourth metal layer 112, and the second test signal line section 1032 is arranged in the first metal layer 105, but due to the electrical connection between the second test signal line section 1032 and the first test signal line section 1031 It is necessary to set via holes in the thicker dielectric layer formed by the first inorganic layer 11, the second inorganic layer 12, the third inorganic layer 13, the first organic layer 14 and the second organic layer 15 to avoid deep drilling that increases the difficulty of the process. A second connecting line 114 can be set on the same layer as the second metal layer 106 and a third connecting line 115 can be set on the same layer as the third metal layer 107. A fifth via hole 116 is set on the first inorganic layer 11 and the second inorganic layer 12 between the first metal layer 105 and the second metal layer 106. A sixth via hole 117 is set on the third inorganic layer 13 and the first organic layer 14 between the second metal layer 106 and the third metal layer 107. A seventh via 118 is provided on the second organic layer 15 between the fourth metal layers 112, so that the second test signal line section 1032 located in the first metal layer 105 is electrically connected to the second connection line 114 located in the second metal layer 106 through the fifth via 116, the third connection line 115 located in the second metal layer 106 is electrically connected to the third connection line 115 of the second metal layer 106 through the sixth via 117, and the first test signal line section 1031 located in the third metal layer 107 is electrically connected to the third connection line 115 of the second metal layer 106 through the seventh via 118. The transmission effect of the test signal in the test signal line 103 is ensured by multi-level punching.

[0048] Optional, Figure 14 A schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 15 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 14and Figure 15 As shown, the first test signal line segment 1031 includes a first connection end 118 along the second direction Y close to the edge of the first metal layer 105 , and the first connection end 118 is flush with the edge of the third metal layer 107 .

[0049] Among them, the first test signal line division 1031 is located in the first metal layer 105, and the first test signal line division 1031 includes a first connection end 118 located at the edge of the first metal layer 105 along the second direction Y, so as to extend to the second test signal line division 1032 of the different layer through punching to be electrically connected, and the first connection end 118 is set flush with the edge of the third metal layer 107 to reduce the risk of static electricity generated by the protruding metal end.

[0050] Optional, continue to refer to Figure 14 and Figure 15 The first test signal line portion 1031 includes a first connection end 118 close to the edge of the third metal layer 107 along the second direction Y. Along the thickness direction Z of the display panel, the first connection end 118 overlaps the third metal layer 107.

[0051] Among them, the first connection end 118 near the edge of the third metal layer 107 in the first test signal line section 1031 may not overlap with the edge of the third metal layer 107, that is, the first connection end 118 does not exceed the positive projection of the edge of the third metal layer 107 along the thickness direction Z of the display panel, so that the first connection end 118 is cut off at a position close to the edge of the third metal layer 107, thereby preventing the first connection end 118 from exceeding the edge of the metal layer and causing an electrostatic risk.

[0052] Optional, continue to refer to Figure 14 and Figure 15 The display panel further includes a first metal portion located in the third metal layer 107 , and the first metal portion wraps the first connection end 118 .

[0053] Among them, the first connection end 118 of the first test signal line division 1031 located in the third metal layer 107 can be wrapped by the first metal division (not shown in the figure) to form an independent metal structure so that it does not contact the surrounding metal in the same layer, avoiding short circuit with the other surrounding metal lines and causing signal interference.

[0054] Optional, continue to refer to Figure 14 and Figure 1 The first test signal line segment 1031 includes a second connection end 119 along the second direction Y and away from the edge of the third metal layer 107 . The display panel further includes a second metal segment located in the third metal layer 107 , which wraps around the second connection end 119 .

[0055] Among them, since the first test signal line division 1031 is a metal structure located in the third metal layer 107 and extending along the second direction Y, the first test signal line division 1031 includes a first connection end 118 close to the edge of the third metal layer 107 and a second connection end 119 away from the edge of the third metal layer 107. The second connection end 119 can be wrapped with a second metal division (not shown in the figure), so that the first test signal line division 1031 becomes an independent metal structure and does not contact with other metal structures in the same layer, thereby reducing the risk of short circuit.

[0056] Optional, Figure 16 A schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 17 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 16 and Figure 17 As shown, the driving signal line 102 includes at least one of a first high voltage signal line, a first low voltage signal line, a second high voltage signal line, a second low voltage signal line, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal.

[0057] Among them, exemplary, Figure 16 As shown, the pixel driving circuit in the display panel can be a 7T1C pixel driving circuit or an 8T1C pixel driving circuit. In this case, the corresponding driving signal line 102 can include a first high voltage signal line VGH, a first low voltage signal line VGL and a first output terminal STV, and then the driving signal line 102 is used to provide signals to each pixel driving circuit in the display panel, ensuring that the pixel driving circuit can provide driving signals to the light-emitting element, thereby ensuring the display effect of the display panel.

[0058] For example, Figure 17 As shown, the pixel driving circuit in the display panel can also be a pixel driving circuit including an amplitude modulation circuit and a pulse width modulation circuit. In this case, the corresponding driving signal line 102 can include a first high voltage signal line PWM_VGH, a first low voltage signal line PWM_VGL, a second high voltage signal line PAM_VGH, a second low voltage signal line PAM_VGH, a first output terminal STV_PWM_SCAN1, a second output terminal STV_PWM_SCAN2, a third output terminal STV_PAM_SCAN1 and a fourth output terminal STV_PAM_SCAN2, so as to realize the signal output by each driving signal line 102 for the operation of each pixel driving circuit in the display panel, thereby enabling the pixel driving circuit to provide a driving signal to the corresponding light-emitting element, thereby ensuring the display effect of the display panel.

[0059] Optional, continue to refer to Figure 15The display panel further includes a common signal line 122 , which at least partially surrounds the display area 101 of the display panel. Along the thickness direction Z of the display panel, the common signal line 122 at least partially overlaps with the first test signal line portion 1031 .

[0060] Among them, a common signal line 122 is set in the display panel. The common signal line 122 can be inserted into a fixed voltage signal. The common signal line 122 is set to at least partially surround the display area 101, so as to avoid static electricity accumulation that causes static electricity to break down the circuits in the display area 101 and the circuits around the display area 101, thereby avoiding poor display and improving the display effect of the display panel. Since the extension direction of some common signal lines 122 is the same as the extension direction of the drive signal lines 102, the common signal lines 122 and the drive signal lines 102 can be set in the same layer, and the common signal lines 122 can be set around the periphery of the drive signal lines 102, simplifying the preparation process. Along the thickness direction Z of the display panel, the common signal lines 122 and the test signal lines 103 overlap. Therefore, the common signal lines 122 can be set to at least partially overlap with the first test signal line section 1031, reducing the parasitic capacitance between the common signal lines 122 and the first test signal line section 1031, and ensuring the test effect of the display panel.

[0061] Figure 18 A structural diagram of another display device provided by an embodiment of the present invention is shown in FIG. Figure 18 As shown, the display device provided by the embodiment of the present invention may be a spliced display device, such as a frameless spliced display device, which includes at least two of the above-mentioned display panels 200 and is suitable for a large-screen display device with a display function.

[0062] The at least two display panels 200 may be arranged along the first direction X, or may be arranged along the second direction Y, but the present invention is not limited thereto and does not impose any specific limitation thereto.

[0063] Figure 19 A schematic structural diagram of a display device provided by an embodiment of the present invention is shown in FIG. Figure 19 As shown, the display device 300 includes the display panel 200 described in the above embodiment.

[0064] It should be noted that since the display device provided in this embodiment has the same or corresponding beneficial effects as the display panel of the above embodiment, no further description is given here. The display device 300 provided in this embodiment of the present invention can be Figure 19The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0065] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of driving signal lines extending along a first direction and at least one test signal line extending along a second direction located in a display area, wherein the first direction intersects with the second direction; The test signal line includes a first test signal line section and a second test signal line section electrically connected in different layers; the first test signal line section and the drive signal line are arranged in different layers; Along a thickness direction of the display panel, the first test signal line section and the driving signal line at least partially overlap.

2. The display panel according to claim 1, wherein: The second test signal line section and the driving signal line are arranged in different layers.

3. The display panel according to claim 1, wherein: The display panel includes a substrate; a first metal layer located on one side of the substrate, a second metal layer located on a side of the first metal layer away from the substrate, and a third metal layer located on a side of the second metal layer away from the substrate; The second test signal line section is located in the first metal layer; the drive signal line is located in the second metal layer; the first test signal line section is located in the third metal layer, and the first test signal line section is electrically connected to the second test signal line section through a first via.

4. The display panel according to claim 1, wherein: The display panel includes a substrate; a first metal layer located on one side of the substrate, a second metal layer located on a side of the first metal layer away from the substrate, and a third metal layer located on a side of the second metal layer away from the substrate; The display panel further includes a first connecting line, wherein the first connecting line is located in the second metal layer; The second test signal line section is located in the first metal layer; the drive signal line is located in the second metal layer; the first test signal line section is located in the third metal layer, the second test signal line section is electrically connected to the first connecting line through a second via, and the first test signal line section is electrically connected to the first connecting line through a third via.

5. The display panel according to claim 1, wherein: The display panel includes a substrate; a first metal layer located on one side of the substrate, a second metal layer located on a side of the first metal layer away from the substrate, a third metal layer located on a side of the second metal layer away from the substrate, and a fourth metal layer located on a side of the third metal layer away from the substrate; Among them, the second test signal line branch is located in the first metal layer; the drive signal line is located in the second metal layer; the first test signal line branch is located in the fourth metal layer, and the first test signal line branch is electrically connected to the second test signal line branch through a fourth via.

6. The display panel according to claim 1, wherein: The display panel includes a substrate; a first metal layer located on one side of the substrate, a second metal layer located on a side of the first metal layer away from the substrate, a third metal layer located on a side of the second metal layer away from the substrate, and a fourth metal layer located on a side of the third metal layer away from the substrate; The second test signal line is partially located in the first metal layer; the driving signal line is located in the second metal layer; the first test signal line is partially located in the fourth metal layer; Wherein, the display panel further includes a second connecting line and a third connecting line, the second connecting line is located in the second metal layer, and the third connecting line is located in the third metal layer; The second test signal line section is electrically connected to the second connection line through a fifth via hole, the second connection line section is electrically connected to the third connection line through a sixth via hole, and the first test signal line section is electrically connected to the third connection line through a seventh via hole.

7. The display panel according to claim 3, wherein: The first test signal line section includes a first connection end along the second direction and close to an edge of the first metal layer. The first connection end is flush with an edge of the third metal layer.

8. The display panel according to claim 3, wherein: The first test signal line section includes a first connection end along the second direction and close to an edge of the third metal layer. Along the thickness direction of the display panel, the first connection end overlaps with the third metal layer.

9. The display panel according to claim 8, wherein: The display panel further includes the first metal section located in the third metal layer, and the first metal section wraps the first connection end.

10. The display panel according to claim 8, wherein The first test signal line section includes a second connection end along the second direction and away from the edge of the first metal layer; The display panel further includes the second metal section located in the third metal layer, and the second metal section wraps the second connection end.

11. The display panel according to claim 1, wherein The driving signal line includes at least one of a first high voltage signal line, a first low voltage signal line, a second high voltage signal line, a second low voltage signal line, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal.

12. The display panel according to claim 1, wherein The display panel further includes a common signal line, which at least partially surrounds a display area of the display panel. Along a thickness direction of the display panel, the common signal line at least partially overlaps with a portion of the first test signal line.

13. The display panel according to claim 1, wherein: The display panel further includes an anti-static structure. Along a thickness direction of the display panel, the anti-static structure at least partially overlaps with the second test signal line portion.

14. The display panel according to claim 13, wherein: The display panel includes a pixel circuit, the pixel circuit includes a plurality of thin film transistors, and the antistatic structure is arranged in the same layer as the active layer of the thin film transistors.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 14.

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