Drive circuit control methods, electronic devices and computer-readable storage media

Abstract

This application relates to the field of display technology, providing a driving circuit control method, an electronic device, and a computer-readable storage medium. The driving circuit includes a driving transistor. The method includes: sequentially outputting control signals for a first number of frames to the driving circuit according to a first frame rate; then, sequentially outputting control signals for a second number of frames to the driving circuit according to a second frame rate, where the second frame rate is less than the first frame rate; then, sequentially outputting control signals for a first number of other frames to the driving circuit according to a first other frame rate, where the first other frame rate is less than the second frame rate; the sum of the product of the reciprocal of the first frame rate and the first number of frames, the product of the reciprocal of the second frame rate and the second number of frames, and the product of the reciprocals of the first other frame rates and other products of the first other number of frames is a first sum value; the difference between the characteristic recovery time of the driving transistor and the first sum value is less than or equal to a preset duration threshold, where the preset duration threshold is a positive number. This method can eliminate afterimages on white screens.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driving circuit control method, electronic device, and computer-readable storage medium. Background Technology

[0002] As people's demands for screen display quality increase, the functions of the pixel driving circuits in the screen are becoming more and more sophisticated, enabling them to meet people's requirements for display quality.

[0003] LTPO (Low-Temperature Point of Sale) screens are widely used in terminal devices. In LTPO screens, the pixel driving circuits can be configured as 8T1C (Electronic Tolerancing Circuits). Using an 8T1C driving circuit allows for pixel compensation and resetting, thereby improving display quality.

[0004] However, in low refresh rate scenarios, if the screen switches from an interface with black and white images to another dark interface, a ghost image of the white image from the previous interface will be displayed in the dark interface, affecting the user's viewing experience. Summary of the Invention

[0005] This application provides a driving circuit control method, device, chip, electronic device, computer-readable storage medium, and computer program product that can eliminate the afterimage of white screen in the previous interface.

[0006] Firstly, a driving circuit control method is provided for controlling a driving circuit. The driving circuit includes a driving transistor. The method includes: sequentially outputting control signals for a first number of frames to the driving circuit according to a first frame rate; after sequentially outputting control signals for the first number of frames to the driving circuit according to the first frame rate, sequentially outputting control signals for a second number of frames to the driving circuit according to a second frame rate, wherein the second frame rate is less than the first frame rate; after sequentially outputting control signals for the second number of frames to the driving circuit according to the second frame rate, sequentially outputting control signals for a first other number of frames to the driving circuit according to a first other frame rate, wherein the first other frame rate is less than the second frame rate; the product of the reciprocal of the first frame rate and the first number of frames is a first product; the product of the reciprocal of the second frame rate and the second number of frames is a second product; the product of the reciprocal of the first other frame rate and the first other number of frames is a first other product; the sum of the first product, the second product, and the first other product is a first sum; the difference between the characteristic recovery time of the driving transistor and the first sum is less than or equal to a preset duration threshold, wherein the preset duration threshold is a positive number.

[0007] The control signal output by DDIC to the driving circuit can be a control voltage. DDIC outputs the control voltage to the driving circuit according to a certain frame rate, which is used to control the display status of the pixels driven by the driving circuit.

[0008] The aforementioned first other frame rate may include one subframe rate or multiple subframe rates. The first other frame number may include one subframe number or multiple subframe numbers. The first other product may include one subproduct or multiple subproducts. When the first other frame rate is one subframe rate, the first other frame number is one subframe number, and the first other product includes one subproduct.

[0009] When the first other frame rate includes multiple subframe rates, the first other frame number includes multiple subframe numbers, and the first other product includes multiple subproducts. The first other frame rate is less than the second frame rate. The first sum can be the sum of the first product, the second product, and the multiple subproducts.

[0010] Whether the first other frame rate includes one frame rate or multiple sub-frame rates, the difference between the characteristic recovery duration of the driving transistor and the first sum value is less than or equal to a preset duration threshold. It can be understood that the total playback duration from the start of DDIC outputting the control signal for the first frame number until the output of the control signal for the first other frame number is the first sum value. Optionally, the number of multiple sub-frame rates can be one, two, three, or four, and they must be different from each other.

[0011] When the DDIC detects a low refresh rate and enters a self-downclocking state (or self-downclocking scenario), it refreshes the voltage of the driver circuit according to transition frames. These transition frames include multiple gradually decreasing frame rates (also called refresh rates), each frame rate representing a level and corresponding to a number of frames. When the DDIC outputs a control signal to the driver circuit according to a frame rate, the output frame number is the number of frames corresponding to that frame rate. The DDIC sequentially downclocks (or downclocks) the frame rate according to the multiple gradually decreasing frame rates in the transition frames, and then enters a low refresh rate hold frame scenario.

[0012] When the voltage difference changes, the characteristics of the driving transistor need a certain time to recover. This time is related to the physical characteristics of the driving transistor and can also be called the characteristic recovery time.

[0013] Since the preset duration threshold is a positive number, if the difference between the characteristic recovery time of the driving transistor and the first sum is less than or equal to 0, it will necessarily be less than the preset duration threshold. In this case, it means that the characteristic recovery time is less than or equal to the playback time. After the DDIC finishes playing the transition frame, the characteristics of the driving transistor have recovered, and the user will not observe the afterimage of the white area appearing in the dark image.

[0014] If the difference between the characteristic recovery time and the first sum is greater than 0, the characteristics of the driving transistor are not fully recovered. However, since the difference is less than the preset time threshold, it indicates that the characteristics of the driving transistor have recovered to a certain extent. Because the human eye has limited ability to distinguish brightness, although there is still a brightness difference between the original white and black areas in a dark image, the user cannot perceive this difference with the naked eye. Therefore, the user will not see any afterimage of the white image and it will not affect the viewing experience.

[0015] In some possible implementations, the first sum is greater than or equal to the feature recovery time.

[0016] Since the preset duration threshold is a positive number, if the difference between the characteristic recovery time of the driving transistor and the first sum is less than or equal to 0, it will necessarily be less than the preset duration threshold. In this case, it means that the characteristic recovery time is less than or equal to the playback time. After the DDIC finishes playing the transition frame, the characteristics of the driving transistor have recovered, and the user will not observe the afterimage of white areas appearing in dark images, thus improving the user's viewing experience.

[0017] In some possible implementations, the first sum is less than the feature recovery time, and the difference between the feature recovery time and the first sum is less than or equal to a preset time threshold.

[0018] The first sum is less than the feature recovery time, meaning the difference between the feature recovery time and the first sum is greater than 0. A difference greater than 0 indicates that although the characteristics of the driving transistors have not fully recovered after the transition frame is played, the difference is less than a preset time threshold, meaning the characteristics of the driving transistors have recovered to a certain extent. Because the human eye has limited ability to distinguish brightness, although there is still a brightness difference between the original white and black areas in a dark image, the user cannot perceive this difference with the naked eye, and therefore cannot see any afterimage of the white image, thus not affecting the user's viewing experience.

[0019] In some possible implementations, the first other frame rate includes at least one subframe rate, the first other frame number includes at least one subframe number, the first other product includes at least one subproduct, the at least one subproduct, the at least one subframe rate, and the at least one subframe number correspond one-to-one, each of the at least one subframe rate is less than the second frame rate, and the control signal for the first other frame number is output to the driving circuit in sequence according to the first other frame rate, including: outputting the control signal for the first subframe number to the driving circuit in sequence according to the first subframe rate, wherein the first subframe rate is any one of the at least one subframe rate, the first subframe number is the subframe number corresponding to the first subframe rate among the at least one subframe number, the product of the reciprocal of the first subframe rate and the first frame number is the first subproduct, and the first subproduct is the subproduct corresponding to the first subframe number and the first frame rate among the at least one subproduct.

[0020] In some possible implementations, the number of at least one subframe rate is at least two, and the at least one subframe rate also includes a second subframe rate, which is less than the first subframe rate. After the control signal for the number of first subframes is sequentially output to the driving circuit according to the first subframe rate, the method further includes: sequentially outputting control signals for the number of second subframes to the driving circuit according to the second subframe rate, wherein the number of second subframes is the number of subframes corresponding to the second subframe rate among the at least one number of subframes.

[0021] The aforementioned first other frame rate may include one subframe rate or multiple subframe rates. The first other frame number may include one subframe number or multiple subframe numbers. The first other product may include one subproduct or multiple subproducts. When the first other frame rate is one subframe rate, the first other frame number is one subframe number, and the first other product includes one subproduct.

[0022] When the first other frame rate includes multiple subframe rates, the first other frame number includes multiple subframe numbers, and the first other product includes multiple subproducts. The first other frame rate is less than the second frame rate. The first sum can be the sum of the first product, the second product, and the multiple subproducts.

[0023] Whether the first other frame rate includes one frame rate or multiple subframe rates, the difference between the characteristic recovery time of the driving transistor and the first sum value is less than or equal to a preset duration threshold. It can be understood that the total playback time from the start of DDIC outputting the control signal for the first frame number until the output of the control signal for the first other frame number is the first sum value. Optionally, the number of multiple subframe rates can be one, two, three, or four, and the multiple subframe rates are all different. The number of frames corresponding to each subframe rate can be the same or different.

[0024] When the first other frame rate includes multiple sub-frame rates, DDIC outputs the corresponding frame number control signal in descending order of the frame rate of these multiple sub-frame rates.

[0025] The specific size and type of frame rate that DDIC operates on can be flexibly determined according to specific needs and are not limited.

[0026] In some possible implementations, before sequentially outputting control signals for a first number of frames to the driving circuit according to a first frame rate, the method includes: controlling the screen to display a first image, the first image including light-colored pixel areas and dark-colored pixel areas; after sequentially outputting control signals for a first other number of frames to the driving circuit according to a first other frame rate, controlling the screen to display a second image, the second image being a dark image; in the first image, the difference between the first brightness corresponding to the light-colored pixel areas and the second brightness corresponding to the dark-colored pixel areas satisfies a preset brightness difference requirement.

[0027] Optionally, light-colored pixel areas can be areas of a white image, and dark-colored pixel areas can be areas of a black image. A dark image can be a black image, or more commonly, the darkest color.

[0028] After the DDIC outputs the control signal as described above, when displaying a dark image, the brightness of the original light-colored pixel area is the first brightness, and the brightness of the original dark image is the second brightness. When the difference between the first brightness and the second brightness meets the preset brightness difference requirement, the user cannot distinguish the difference in brightness with the naked eye, and therefore will not observe any afterimages on the white image.

[0029] In some possible implementations, the ratio of the difference between the first brightness and the second brightness to the second brightness is less than the brightness difference threshold.

[0030] The preset brightness difference requirement can be the ratio of the difference between the first brightness and the second brightness to the second brightness, which must be less than the brightness difference threshold. Optionally, the brightness difference threshold can be 2%, 3%, or other smaller values. The smaller the brightness difference threshold, the less likely the user is to observe afterimages in the white screen. The larger the brightness difference threshold, the shorter the time DDIC enters the hold frame, thus saving power.

[0031] In some possible implementations, the grayscale of the light-colored pixel region of the first image is L1, the grayscale of the dark-colored pixel region of the first image is L5, and the grayscale of the second image is L17.

[0032] With this grayscale setting, users will not observe any white image ghosting, and they will not observe any white image ghosting under other common grayscale settings either.

[0033] In some possible implementations, the reference voltage of the driving circuit is a first voltage. The method further includes: when a self-downsampling scenario is detected, controlling the reference voltage of the driving circuit to be a second voltage, and sequentially outputting a control signal for a third frame number according to a first frame rate to the driving circuit, wherein the second voltage is greater than the first voltage; after sequentially outputting the control signal for a third frame number to the driving circuit according to the first frame rate, sequentially outputting a control signal for a fourth frame number to the driving circuit according to the second frame rate; after sequentially outputting the control signal for a fourth frame number to the driving circuit according to the second frame rate, sequentially outputting a control signal for a second other frame rate to the driving circuit according to other frame rates. The control signal for the second other frame rate is output, where the second other frame rate is less than the second frame rate; the product of the reciprocal of the first frame rate and the third frame rate is the third product, the product of the reciprocal of the second frame rate and the fourth frame rate is the fourth product, the product of the reciprocal of the second other frame rate and the second other frame rate is the second other product, and the sum of the third product, the fourth product and the second other product is the second sum value; if the third frame rate is less than the first frame rate, and / or the fourth frame rate is less than the second frame rate, and / or the second other frame rate is less than the first other frame rate, the difference between the feature recovery time and the second sum value is less than or equal to the preset time threshold.

[0034] By increasing the reference voltage of the control drive circuit, DDIC applies forward bias stress to the drive transistors for both white and black pixels. The DTFTs in the drive circuit will then recover their characteristics in the forward bias direction, which is more effective in eliminating brightness differences caused by black / white images. Therefore, the faster recovery speed of the drive transistors shortens the recovery time. Consequently, even by shortening the playback duration of transition frames, ghosting on white images can be avoided.

[0035] DDIC can reduce the number of frames at one frame rate or multiple frame rates, thereby shortening the playback duration of transitional frames. This application does not limit this aspect.

[0036] By increasing the reference voltage of the control drive circuit and reducing the number of transition frames, DDIC can ensure that there is no white image ghosting while also reducing power consumption.

[0037] In a second aspect, a drive circuit control device is provided, comprising a unit composed of software and / or hardware, the unit being used to execute any one of the methods described in the first aspect.

[0038] Thirdly, embodiments of this application provide a chip including a processor; the processor is used to read and execute a computer program stored in a memory to perform any one of the methods described in the first aspect.

[0039] Optionally, the chip further includes a memory, which is connected to the processor via a circuit or wire.

[0040] Alternatively, the chip may further include a communication interface.

[0041] In some embodiments, the chip is a display driver IC (DDIC).

[0042] Fourthly, an electronic device is provided, comprising a screen, the screen including multiple driving circuits, the driving circuits including a driving transistor DTDT, and the electronic device further comprising a processor, a memory, and an interface; the processor, memory, and interface cooperate with each other to enable the electronic device to execute any one of the methods of the technical solution described in the first aspect.

[0043] Fifthly, an electronic device is provided, which includes any one of the chips described in the third aspect.

[0044] In a sixth aspect, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, the processor performs any one of the methods described in the first aspect.

[0045] In a seventh aspect, a computer program product is provided, the computer program product comprising: computer program code, which, when executed on an electronic device, causes the electronic device to perform any one of the methods described in the first aspect. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of a terminal device 100 provided in an embodiment of this application;

[0047] Figure 2 This is a software structure block diagram of the terminal device 100 provided in the embodiments of this application;

[0048] Figure 3 This is a schematic diagram of the circuit structure of an example driving circuit provided in an embodiment of this application;

[0049] Figure 4 This is a schematic diagram of an interface where a white image appears during interface switching, as provided in an embodiment of this application.

[0050] Figure 5 This is a brightness curve diagram of a white image ghosting that appears during interface switching, provided in an embodiment of this application.

[0051] Figure 6 This is a brightness curve diagram of an example of a driving circuit control method provided in the embodiments of this application;

[0052] Figure 7This is another example of a brightness curve obtained by using a driving circuit control method provided in the embodiments of this application;

[0053] Figure 8 This is a schematic diagram of the current peak value after adopting a driving circuit control method according to an embodiment of this application;

[0054] Figure 9 This is a brightness curve provided in an embodiment of this application after reducing the Vrefp voltage;

[0055] Figure 10 This is a schematic flowchart of an example of a drive circuit control method provided in an embodiment of this application;

[0056] Figure 11 This is a schematic diagram of a drive circuit control device provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0058] Hereinafter, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature.

[0059] The driving circuit control method provided in this application embodiment can be applied to terminal devices such as mobile phones, tablets, wearable devices, vehicle devices, augmented reality (AR) / virtual reality (VR) devices, laptops, ultra-mobile personal computers (UMPCs), netbooks, and personal digital assistants (PDAs). This application embodiment does not impose any restrictions on the specific type of terminal device.

[0060] For example, Figure 1This is a schematic diagram of the structure of a terminal device 100 provided in an embodiment of this application. The terminal device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0061] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the terminal device 100. In other embodiments of this application, the terminal device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0062] Processor 110 may include one or more processing units, such as: application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, memory, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0063] The controller can serve as the central nervous system and command center of the terminal device 100. The controller can generate operation control signals based on the instruction opcode and timing signals to control the fetching and execution of instructions.

[0064] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0065] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0066] The MIPI interface can be used to connect the processor 110 to peripheral devices such as the display screen 194 and the camera 193. The MIPI interface includes a camera serial interface (CSI) and a display serial interface (DSI). In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to enable the shooting function of the terminal device 100. The processor 110 and the display screen 194 communicate via the DSI interface to enable the display function of the terminal device 100.

[0067] The GPIO interface can be configured via software. It can be configured as a control signal or a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 to a camera 193, a display screen 194, a wireless communication module 160, an audio module 170, a sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0068] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the terminal device 100. In other embodiments of this application, the terminal device 100 may also adopt different interface connection methods or a combination of multiple interface connection methods as described in the above embodiments.

[0069] Terminal device 100 implements display functions through a GPU, display screen 194, and application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0070] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a minimized display, a microLED, a micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, terminal device 100 may include one or N displays 194, where N is a positive integer greater than 1.

[0071] Internal memory 121 can be used to store computer executable program code, which includes instructions. Processor 110 executes various functional applications and data processing of terminal device 100 by running the instructions stored in internal memory 121. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback, image playback, etc.), etc. The data storage area may store data created during the use of terminal device 100 (such as audio data, phonebook, etc.). Furthermore, internal memory 121 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0072] Terminal device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0073] The software system of terminal device 100 can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment uses the layered architecture Android system as an example to exemplify the software structure of terminal device 100.

[0074] Figure 2 This is a software structure block diagram of the terminal device 100 according to an embodiment of this application. The layered architecture divides the software into several layers, each with a clear role and division of labor. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer. The application layer may include a series of application packages.

[0075] like Figure 2 As shown, the application package may include applications such as camera, gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, and SMS.

[0076] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0077] like Figure 2 As shown, the application framework layer may include a window manager, content provider, view system, phone manager, resource manager, notification manager, etc.

[0078] The window manager is used to manage windowed applications. It can retrieve screen size, determine the presence of a status bar, lock the screen, and capture screenshots, among other things.

[0079] Content providers store and retrieve data, making that data accessible to applications. This data may include videos, images, audio, made and received phone calls, browsing history and bookmarks, phone books, etc.

[0080] A view system includes visual controls, such as controls for displaying text and controls for displaying images. View systems can be used to build applications. A display interface can consist of one or more views. For example, a display interface including a text notification icon could include views for displaying text and views for displaying images.

[0081] The phone manager is used to provide communication functions for terminal device 100. For example, it manages call status (including connection, hang-up, etc.).

[0082] The file explorer provides applications with various resources, such as localized strings, icons, images, layout files, video files, and more.

[0083] The notification manager allows applications to display notification information in the status bar. It can be used to convey informational messages and can disappear automatically after a short time without user interaction.

[0084] The Android runtime consists of core libraries and a virtual machine. The Android runtime is responsible for scheduling and managing the Android system.

[0085] The core library consists of two parts: one part is the functionalities that need to be called by the Java language, and the other part is the Android core library.

[0086] The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0087] System libraries can include multiple functional modules. For example: surface manager, media libraries, 3D graphics processing libraries (e.g., OpenGL ES), 2D graphics engines (e.g., SGL), etc.

[0088] The Surface Manager is used to manage the display subsystem and provides the blending of 2D and 3D layers for multiple applications.

[0089] The media library supports playback and recording of various common audio and video formats, as well as still image files. It supports multiple audio and video encoding formats, such as MPEG4, H.264, MP3, AAC, AMR, JPG, and PNG.

[0090] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0091] A 2D graphics engine is a graphics engine for 2D drawing.

[0092] The kernel layer is the layer between hardware and software. The kernel layer contains at least the display driver, camera driver, audio driver, and sensor driver.

[0093] For ease of understanding, the following embodiments of this application will be described using the following methods: Figure 1 and Figure 2 Taking the terminal device with the structure shown as an example, and in conjunction with the accompanying drawings and application scenarios, the pixel driving circuit control method provided in this application embodiment will be specifically described.

[0094] As people's demands for screen display quality increase, the functions of the pixel driving circuits in screens are becoming more and more sophisticated, capable of meeting these requirements. Screens with LTPO (Low-Temperature Polycrystalline Oxide) technology are widely used in terminal devices. Figure 3 The circuit structure of a drive circuit in the form of an 8T1C using LTPO technology is shown.

[0095] Figure 3 The 8T1C driving circuit shown can compensate and reset pixels, thereby improving the display effect. However, in low refresh rate scenarios, if the screen interface switches from an interface with black and white images to another dark interface, a ghost image of the white image from the previous interface will be displayed in the dark interface after the switch, affecting the user's viewing experience.

[0096] Figure 4 Figure a in the text uses a clock interface with a white dial and a black background displayed on a terminal device screen as an example. When the terminal device displays... Figure 4 When the interface shown in Figure a is displayed, if a notification message from the chat application pops up on the screen, the user can enter the chat interface by clicking the notification message. This chat interface is in dark mode, for example... Figure 4 As shown in Figure b. Or, as the user... Figure 4 As shown in Figure a, by bringing up the sidebar and selecting the chat application from it, the screen switches to a dark chat interface. In dark mode, a white watch face ghosting gradually appears in the chat interface. If the screen remains in a low refresh rate hold frame displaying the chat interface, the white watch face area becomes brighter and the black background area becomes darker, making the white watch face ghosting more and more obvious. For example... Figure 4 As shown in Figure c.

[0097] The reason why Figure 4 The phenomenon shown in image c is due to the following: In low refresh rate scenarios, when the screen displays a clock interface with a white dial and a black background:

[0098] During the pixel writing stage, Vth = Vg - Vs. For example, when Vg is 1V and Vs is 3V, Vth is -2V. For the pixels in the white dial area, the driving TFT (drive thin film transistor, DTFT) in the driving circuit... Figure 3 In the light-emitting stage (T1), Vs is 4.6V, so Vg - Vs = 1 - 4.6 = -3.6V. At this time, Vth is less than the original Vth, resulting in a negative bias in Vth.

[0099] For pixels in the black background area, during the light-emitting phase of the DTFT in the driving circuit, Vg is 7V and Vs is 4.6V, so Vg-Vs=7-4.6=2.4V. At this time, Vth is greater than the original Vth, causing Vth to be in a forward bias state.

[0100] When the screen switches from a white dial and black background clock interface to a dark chat interface, the DDIC's refresh rate returns from the hold frame to the refresh frame due to the change in screen display. Afterwards, the DDIC gradually switches back from the refresh frame to the hold frame. This switching period is called the dimming interval. During the dimming interval, the refresh rate undergoes a self-downsizing process. For example, with a refresh rate of 120Hz and a hold frame of 1Hz, upon entering the dimming interval, the DDIC initially reduces the refresh rate to 30Hz, then gradually decreases it to 15Hz, 10Hz, and finally the hold frame of 1Hz. It's important to note that the screen's refresh rate is controlled by the DDIC, which sends images to the screen according to the refresh rate, that is, writes the corresponding voltage to the pixel drive circuit according to the refresh rate.

[0101] During the Dimming interval, the DTFT is in a continuous high-frequency reset compensation phase. This means that the Data voltage (Vg) of the driving circuit will change with the characteristics of the DTFT, so that the characteristics of the DTFT in the driving circuit of all pixels will tend to recover in the same direction, and Vg will continue to be written continuously.

[0102] However, when the dimming interval ends and the hold frame is entered, the Data voltage of the DTFT in the driving circuit no longer writes a new Vg voltage value; Vg will remain the last written Vg. At this time, T7 and T8 in the driving circuit still use 360Hz for high-frequency reset compensation of the DTFT, and the DTFT characteristics are continuously recovering. Immediately upon entering the hold frame, the DTFT characteristics in the driving circuits for white pixels (pixels in the white dial area) and black pixels (pixels in the black background area) have not yet recovered to a consistent state.

[0103] For details, please refer to [link / reference]. Figure 5The brightness curves of pixels of different colors are shown. For the original white pixel, Vth is initially negatively biased. In the first frame of the transition frame, Vg written by DDIC is relatively small. However, when the dimming interval ends, the Data voltage of DTFT in the driving circuit no longer writes a new Vg voltage value, and the characteristics of DTFT continue to recover from the negative bias state. Vth becomes relatively positively biased, and the brightness of the white pixel increases, as shown by the dashed line corresponding to the white pixel.

[0104] For the original black pixel, Vth is in a positive bias state. In the first frame of the transition frame, the Vg written by DDIC is relatively large. However, when the dimming interval ends, the Data voltage of the DTFT in the driving circuit no longer writes a new Vg voltage value, and the characteristics of the DTFT continue to recover from the positive bias state. Vth becomes relatively negative biased, and the brightness of the black pixel decreases, as shown by the dashed line corresponding to the black pixel.

[0105] exist Figure 5 In the driving circuits for white and black pixels, the characteristics of the DTFT have not yet returned to a consistent state. This is manifested in the fact that at the end of the Dimming interval, the dashed lines corresponding to the white pixels and the dashed lines corresponding to the black pixels do not intersect.

[0106] Therefore, a white watch face ghosting gradually appears in a dark chat interface. If the frame rate remains at 0.1Hz, the white watch face ghosting will become increasingly noticeable within ten seconds of entering a dark chat interface, negatively impacting the user experience. Figure 5 As shown, when the screen displays a hold frame, the brightness difference between the original black pixels and the original white pixels is ΔL1, which is greater than the brightness difference that the human eye can tolerate. The human eye can clearly perceive the brightness difference between the white dial area and the black background area.

[0107] This application provides a driving circuit control method. By resetting the playback duration of transition frames to a longer duration, the characteristics of the DTFT in the driving circuit can be restored to a greater extent during the playback of the transition frames. This allows the characteristics of the DTFT in the driving circuit of black or white pixels to be restored to a closer state, avoiding the appearance of the white image in the dark interface when the screen switches from a black and white screen to a dark interface, thus improving the display effect and enhancing the user experience.

[0108] The driving circuit control method provided in this application can be used in the aforementioned 8T1C type driving circuit, as well as in 7T1C or other types of driving circuits; the embodiments of this application do not limit this application. This method can also be used in screens that include 8T1C or 7T1C type driving circuits.

[0109] Specifically, users can pre-adjust the refresh rate of the transition frames and the number of frames at different refresh rates to determine the final refresh rate and number of frames for the transition frames. The adjustment process includes:

[0110] First, the user operates the settings screen to display an image with white and black areas for a certain period of time, in order to simulate an image with white and black areas at a low refresh rate.

[0111] Optionally, in an image with white and black areas, the white area can be the area of ​​pixels with the maximum brightness supported by the screen, which has a brightness of 800 nits. Using an image with a white area of ​​maximum brightness can cover the brightness of all white areas, ensuring that the transition frames obtained during debugging can be applied to all scenes with white areas, greatly reducing the probability of white area ghosting.

[0112] Optionally, in an image with white and black areas (referred to as a black / white image), the white area can also be the region of the brightest pixel in a typical scene. A typical scene can be a scene that the user uses frequently. Optionally, the grayscale of the white area in a typical scene can be L1, and the grayscale of the black area can be L5. This can reduce the number of transition frames to some extent, thereby reducing power consumption. Here, an image of a clock interface with a white dial and a black background can be set as the desktop background and displayed for more than 10 seconds.

[0113] Then, the user interacts with the screen to switch from a black / white image to a dark image.

[0114] Optionally, the dark image can be displayed by the user opening a dark image from the gallery on the desktop. Optionally, the dark image can be a completely black image. Using a completely black image can cover the brightness of all dark images, ensuring that the transition frame obtained during debugging can be applied to all dark image scenes, and can also greatly reduce the probability of white area ghosting.

[0115] Optionally, the dark image can also be the image with the lowest brightness in a normal scene. Optionally, the dark image can be a dark image with an L17 grayscale. The normal scene can be a scene that the user uses frequently. This can reduce the number of transition frames to some extent, thereby reducing power consumption. For example, the dark image could be a screenshot of a chat application's interface in dark mode.

[0116] Alternatively, the dark image can be displayed by the user directly opening the chat application in dark mode from the desktop, or by the user bringing up the sidebar on the desktop to open the chat application in dark mode.

[0117] At this point, users will notice that white areas gradually appear as afterimages in dark-colored interfaces, for example... Figure 4 As shown in Figure c, during this process, when DDIC switches from a black / white image to a dark image, it first plays a transition frame. For example, the refresh rate and frame number of the transition frame here are as follows: 30Hz-15 frames, 15Hz-15 frames. After that, DDIC enters the hold frame. That is to say, when switching interfaces, DDIC first enters the Dimming interval. In the Dimming interval, DDIC controls the screen to first display 15 frames at a refresh rate of 30Hz, then display 15 frames at a refresh rate of 10Hz, and finally display at the refresh rate of the hold frame. In the case of transition frames of 30Hz, 15 frames (denoted as 30Hz (15 frames)) and 10Hz, 15 frames (denoted as 10Hz (15 frames)), the playback duration of the transition frame is (1%30)*15+(1%10)*15, which is approximately 2 seconds.

[0118] Taking a DTFT characteristic recovery time of 2.5 seconds as an example, the playback time of a 2-second transition frame is less than the DTFT characteristic recovery time of 2.5 seconds. Therefore, after the transition frame is played on the screen, the DTFT characteristic has not been fully recovered, and the user will observe a white afterimage appearing in the dark image.

[0119] At this point, the user can increase the playback duration of the transition frame and repeat the above operation of switching from black / white image to dark image, and then observe again whether the afterimage of the white area appears in the dark image.

[0120] Users can increase the playback duration of transition frames by increasing the types of refresh rates and the number of frames in the transition frames.

[0121] For example, a user can modify the transition frame from 30Hz (15 frames) - 10Hz (15 frames) to 30Hz (15 frames) - 10Hz (15 frames) - 1Hz (8 frames), adding a 1Hz refresh rate transition frame, and displaying a total of 8 frames at a 1Hz refresh rate. Based on the modified transition frame, when the user re-executes the above operation of switching from a black / white image to a dark image, DDIC first enters the Dimming interval during the interface switch. In the Dimming interval, it first controls the screen to display 15 frames at a 30Hz refresh rate, then 15 frames at a 10Hz refresh rate, then 8 frames at a 1Hz refresh rate, and finally displays at the refresh rate of the hold frame. When the transition frame is changed from 30Hz (15 frames) - 10Hz (15 frames) to 30Hz (15 frames) - 10Hz (15 frames) - 1Hz (8 frames), the playback duration of the transition frame is (1%30)*15 + (1%10)*15 + (1%1)*8, which is 10 seconds.

[0122] Taking a DTFT recovery time of 2.5 seconds as an example, the playback time of a 10-second transition frame is much longer than the DTFT recovery time. Therefore, after the screen finishes playing the transition frame, the DTFT characteristics have been fully recovered. Even if the display enters the refresh rate of the hold frame, the user will not observe a white afterimage appearing in a dark image.

[0123] Alternatively, the playback duration of transition frames can be increased by adding multiple transition frame levels. For example, changing 30Hz (15 frames) - 10Hz (15 frames) to 60Hz (15 frames) - 30Hz (15 frames) - 10Hz (15 frames) - 5Hz (5 frames) would result in a playback duration of 3.25 seconds for the transition frames. This 3.25-second playback duration is also longer than the 2.5-second recovery duration. Based on the transition frame 60Hz (15 frames) - 30Hz (15 frames) - 10Hz (15 frames) - 5Hz (5 frames), users will not observe any afterimages of white areas appearing in dark images.

[0124] Optionally, if the playback duration of the transition frame is greater than or equal to the recovery duration of the DTFT characteristic, the user will not observe a white afterimage appearing in a dark image. However, since the human eye has limited ability to distinguish brightness, when DDIC enters the hold frame, if the DTFT characteristic recovers to a certain extent, although there is still a brightness difference between the original white area and the original black area in the dark image, the user can no longer observe the brightness difference with the naked eye, and therefore will not see a white afterimage, thus not affecting the user's viewing experience. Based on this, the playback duration of the transition frame can be set to be less than the recovery duration of the DTFT characteristic, and the difference between the recovery duration of the DTFT characteristic and the playback duration of the transition frame is less than a preset duration threshold. Optionally, the preset duration threshold can be a short duration such as 0.2s or 0.3 seconds. For example, changing 30Hz (15 frames) - 10Hz (15 frames) to 60Hz (15 frames) - 30Hz (15 frames) - 10Hz (15 frames) results in a corresponding transition frame playback duration of 2.25 seconds. The playback duration of 2.25 seconds is less than the recovery duration of 2.5 seconds, and the difference between 2.5 seconds and 2.25 seconds is 0.25 seconds. When the preset duration threshold is 0.3 seconds, the difference between the recovery duration and the playback duration is less than 0.3 seconds. Therefore, based on the transition frame of 60Hz (15 frames) - 30Hz (15 frames) - 10Hz (15 frames) - 5Hz (5 frames), the user will not observe the afterimage of white areas appearing in dark images when switching interfaces, and the total playback duration of the transition frames is shortened, which can reduce power consumption.

[0125] Optionally, when the difference between the characteristic recovery time of the DTFT and the playback time of the transition frame is less than a preset duration threshold, in a dark image at L17 grayscale, the brightness Lw of the original white area and the brightness Lb of the original black area satisfy the following relationship: (Lw-Lb) / Lb is less than or equal to a preset brightness difference. Optionally, the preset brightness difference can be a small value such as two percent, three percent, or one percent. The brightness relationship that (Lw-Lb) / Lb is less than or equal to the preset brightness difference ensures that the user will not observe white area afterimages in the dark image.

[0126] The above implementation ensures that the playback duration of the transition frame is not significantly shorter than the recovery time of the DTFT characteristic, thus preventing the appearance of white image ghosting. Furthermore, compared to methods where the playback duration of the transition frame is greater than or equal to the recovery time of the DTFT characteristic, setting the playback duration of the transition frame to be less than the recovery time of the DTFT characteristic, and ensuring that the difference between the recovery time of the DTFT characteristic and the playback duration of the transition frame is less than a preset duration threshold, effectively reduces the number of transition frames while ensuring that the user does not observe white image ghosting, thereby reducing power consumption.

[0127] Optionally, the above example of setting the transition frame uses a 30Hz first frame. However, in actual applications, when switching from a black / white screen to a dark screen, the DDIC can enter a self-downclocking state in a low refresh rate scenario (i.e., after entering a low refresh rate scenario, the DDIC automatically starts from the initial refresh rate and gradually reduces the refresh rate to enter a hold frame state). In this state, the DDIC does not need to be controlled by the upper layer and can automatically reduce the refresh rate step by step. Furthermore, the DDIC's self-downclocking state in a low refresh rate scenario is compatible with various higher refresh rate scenarios in the upper layer. In other words, regardless of the refresh rate, when the DDIC enters the self-downclocking state in a low refresh rate scenario, it can adaptably switch to the initial refresh rate, thereby quickly transitioning to the hold frame and saving power.

[0128] Once the user has properly adjusted the transition frames, they can write the adjusted results into DDIC. DDIC can then play the transition frames according to the adjusted results when switching from a black / white screen to a dark screen.

[0129] During the playback of transition frames, specifically in the dimming interval, the characteristics of the DTFT gradually recover as the DDIC controls the playback of the transition frames. If the playback duration of the transition frame is greater than or equal to the recovery duration of the DTFT characteristics, then after the DTFT characteristics recover and enters the hold frame, there will be no brightness difference due to the difference in the characteristics of the DTFT in the driving circuits of black or white pixels. Therefore, when switching from an interface with a white screen to a dark screen at a low refresh rate, there will be no white image ghosting. If the playback duration of the transition frame is less than the recovery duration of the DTFT characteristics, then the difference between the recovery duration of the DTFT characteristics and the playback duration of the transition frame is less than a preset duration threshold. Therefore, even if the DTFT characteristics are not completely restored to a consistent state when entering the hold frame, the brightness difference between the original white pixels and the original black pixels is relatively small, imperceptible to the naked eye, and the user will not see white image ghosting, thus not affecting the user experience.

[0130] Figure 6 Figure a in the diagram illustrates the brightness curves of white and black pixels while maintaining a frame rate of 1Hz. It can be seen that at the end of the dimming interval, the brightness of the original white pixels increases, while the brightness of the original black pixels decreases, with a brightness difference of ΔL2. Optionally, ΔL2 ≦ (Lw - Lb) / Lb.

[0131] When the frame rate is kept at 0.1Hz, the brightness curves of white and black pixels can be seen in the diagram below. Figure 6 As shown in Figure b, it can be seen that at the end of the dimming interval, the brightness of the original white pixels increases, while the brightness of the original black pixels decreases, with a brightness difference of ΔL3. Optionally, ΔL3 ≦ (Lw - Lb) / Lb.

[0132] Compare the brightness curves at frame rates of 0.1Hz and 1Hz on the same graph; see, for example... Figure 7 As shown.

[0133] It's important to note that with a hold frame rate of 1Hz, the DTFT's Data voltage Vg resets every second, while with a hold frame rate of 0.1Hz, the DTFT's Data voltage Vg resets every 10 seconds. Therefore, the required playback duration of the transition frame is longer for the DTFT than in the 1Hz case. Consequently, for a hold frame with a higher refresh rate, the playback duration of the transition frame can be shorter compared to a hold frame with a lower refresh rate. Conversely, for a hold frame with a lower refresh rate, the playback duration of the transition frame is longer, resulting in higher power consumption.

[0134] Optionally, if the DTFT's characteristic recovery time is 2 seconds, when the hold frame is 1 Hz, the transition frame can be 30 Hz (15 frames) - 10 Hz (15 frames), followed by a hold frame of 1 Hz. Optionally, when the hold frame is 0.1 Hz, the transition frame can be 30 Hz (15 frames) - 10 Hz (15 frames) - 1 Hz (8 frames), followed by a hold frame of 0.1 Hz. Optionally, when the hold frame is at other refresh rates, the transition frame can be adjusted to follow the hold frame, as long as the duration of the hold frame is greater than or equal to the DTFT's characteristic recovery time, or the duration of the hold frame is less than the DTFT's characteristic recovery time, to ensure that the brightness difference between black and white pixels is within an acceptable range for the human eye.

[0135] Figure 8 This diagram illustrates the current peak value of the DDIC as it moves from the refresh frame, through the transition frame, and into the hold frame. Figure 8 The vertical axis represents current, and the horizontal axis represents time. It can be seen that a current peak occurs when the DDIC writes voltage to each pixel according to the frame rate. The more frames, the greater the power consumption.

[0136] Based on this, the embodiments of this application also provide a driving circuit control method based on DDIC, which dynamically adjusts the Vrefp voltage of the driving circuit and reduces the number of transition frames, thereby reducing the power consumption in the Dimming interval.

[0137] Before the Vrefp voltage of the drive circuit is dynamically adjusted based on DDIC, the reference voltage (Vrefp voltage) output by DDIC to the drive circuit can be referred to as the first voltage.

[0138] In this embodiment, when the DDIC detects a self-downclocking state at a low refresh rate, it increases the Vrefp voltage output to the driving circuit. This increased Vrefp voltage is denoted as the second voltage, which is greater than the first voltage. As the Vrefp voltage increases, the voltage difference between Vg and Vs of the DTFT increases. Therefore, regardless of whether the DTFT is in a forward-biased or negative-biased state, the increased Vrefp voltage will cause forward-biased stress. Consequently, for the entire screen, whether it's a white or black pixel, the DTFT in the driving circuit will recover its characteristics in the forward-biased direction, which is more conducive to eliminating brightness differences caused by black / white images. Therefore, the faster DTFT characteristic recovery speed can shorten the characteristic recovery time. Correspondingly, even if the playback time of transition frames is shortened, white image retention can be avoided.

[0139] Optionally, when the second voltage increases by 0.1V compared to the first voltage, the transition frame can be reduced by one frame. For example, the transition frame can be modified from 30Hz (15 frames) - 10Hz (15 frames) - 1Hz (8 frames) to 30Hz (15 frames) - 10Hz (15 frames) - 1Hz (7 frames), i.e., reducing the frame count by 1 frame (1Hz). When the second voltage increases by 0.2V compared to the first voltage, the transition frame can be reduced by two frames. For example, the transition frame can be modified from 30Hz (15 frames) - 10Hz (15 frames) - 1Hz (8 frames) to 30Hz (15 frames) - 10Hz (15 frames) - 1Hz (6 frames), i.e., reducing the frame count by 2 frames (1Hz).

[0140] Figure 9 The diagram illustrates a comparison of the brightness curves of white and black pixels after increasing the Vrefp voltage. It shows that when the Vrefp voltage is increased, the brightness difference between white and black pixels at the end of the dimming interval is smaller than when the Vrefp voltage is not increased. Furthermore, when the Vrefp voltage is increased, the time required for the DTFT characteristics in the driving circuits of white and black pixels to return to a consistent state is shorter.

[0141] It is understandable that the number of frames reduced during the transition is directly proportional to or positively correlated with the degree of increase in the second voltage. In other words, the number of frames during the transition is negatively correlated with the voltage value of the second voltage.

[0142] It should be noted that the maximum value of the Vrefp voltage will not exceed ELVDD. Optionally, the maximum value of the Vrefp voltage will not exceed 7.9V.

[0143] Figure 10 This is a flowchart illustrating an example of a drive circuit control method provided in an embodiment of this application. The method is used to control a drive circuit in a screen, the drive circuit including a drive transistor, and the method includes:

[0144] S1001: Output the control signal of the first frame number to the driving circuit in sequence according to the first frame rate.

[0145] S1002. After sequentially outputting control signals for the first number of frames to the driving circuit according to the first frame rate, sequentially outputting control signals for the second number of frames to the driving circuit according to the second frame rate, wherein the second frame rate is less than the first frame rate.

[0146] S1003. After sequentially outputting control signals for the second frame number to the driving circuit according to the second frame rate, sequentially outputting control signals for the first other frame number to the driving circuit according to the first other frame rate, wherein the first other frame rate is less than the second frame rate.

[0147] The product of the reciprocal of the first frame rate and the first frame number is the first product; the product of the reciprocal of the second frame rate and the second frame number is the second product; the product of the reciprocal of any other first frame rate and the other first frame number is the first other product; and the sum of the first product, the second product, and the first other product is the first sum. The difference between the characteristic recovery time of the driving transistor and the first sum is less than or equal to a preset duration threshold, which is a positive number.

[0148] The control signal output by DDIC to the driving circuit can be a control voltage. DDIC outputs the control voltage to the driving circuit according to a certain frame rate, which is used to control the display status of the pixels driven by the driving circuit.

[0149] The aforementioned first other frame rate may include one subframe rate or multiple subframe rates. The first other frame number may include one subframe number or multiple subframe numbers. The first other product may include one subproduct or multiple subproducts. When the first other frame rate is one subframe rate, the first other frame number is one subframe number, and the first other product includes one subproduct.

[0150] When the first other frame rate includes multiple subframe rates, the first other frame number includes multiple subframe numbers, and the first other product includes multiple subproducts. The first other frame rate is less than the second frame rate. The first sum can be the sum of the first product, the second product, and the multiple subproducts.

[0151] Whether the first other frame rate includes one frame rate or multiple sub-frame rates, the difference between the characteristic recovery duration of the driving transistor and the first sum value is less than or equal to a preset duration threshold. It can be understood that the total playback duration from the start of DDIC outputting the control signal for the first frame number until the output of the control signal for the first other frame number is the first sum value. Optionally, the number of multiple sub-frame rates can be one, two, three, or four, and they must be different from each other.

[0152] When the DDIC detects a low refresh rate and enters a self-downclocking state (or self-downclocking scenario), it refreshes the voltage of the driver circuit according to transition frames. These transition frames include multiple gradually decreasing frame rates (also called refresh rates), each frame rate representing a level and corresponding to a number of frames. When the DDIC outputs a control signal to the driver circuit according to a frame rate, the output frame number is the number of frames corresponding to that frame rate. The DDIC sequentially downclocks (or downclocks) the frame rate according to the multiple gradually decreasing frame rates in the transition frames, and then enters a low refresh rate hold frame scenario.

[0153] When the voltage difference changes, the characteristics of the driving transistor need a certain time to recover. This time is related to the physical characteristics of the driving transistor and can also be called the characteristic recovery time.

[0154] Since the preset duration threshold is a positive number, if the difference between the characteristic recovery time of the driving transistor and the first sum is less than or equal to 0, it will necessarily be less than the preset duration threshold. In this case, it means that the characteristic recovery time is less than or equal to the playback time. After the DDIC finishes playing the transition frame, the characteristics of the driving transistor have recovered, and the user will not observe the afterimage of the white area appearing in the dark image.

[0155] If the difference between the characteristic recovery time and the first sum is greater than 0, the characteristics of the driving transistor are not fully recovered. However, since the difference is less than the preset time threshold, it indicates that the characteristics of the driving transistor have recovered to a certain extent. Because the human eye has limited ability to distinguish brightness, although there is still a brightness difference between the original white and black areas in a dark image, the user cannot perceive this difference with the naked eye. Therefore, the user will not see any afterimage of the white image and it will not affect the viewing experience.

[0156] In some embodiments, the first sum is greater than or equal to the feature recovery time.

[0157] Since the preset duration threshold is a positive number, if the difference between the characteristic recovery time of the driving transistor and the first sum is less than or equal to 0, it will necessarily be less than the preset duration threshold. In this case, it means that the characteristic recovery time is less than or equal to the playback time. After the DDIC finishes playing the transition frame, the characteristics of the driving transistor have recovered, and the user will not observe the afterimage of white areas appearing in dark images, thus improving the user's viewing experience.

[0158] In some embodiments, the first sum is less than the feature recovery time, and the difference between the feature recovery time and the first sum is less than or equal to a preset time threshold.

[0159] The first sum is less than the feature recovery time, meaning the difference between the feature recovery time and the first sum is greater than 0. A difference greater than 0 indicates that although the characteristics of the driving transistors have not fully recovered after the transition frame is played, the difference is less than a preset time threshold, meaning the characteristics of the driving transistors have recovered to a certain extent. Because the human eye has limited ability to distinguish brightness, although there is still a brightness difference between the original white and black areas in a dark image, the user cannot perceive this difference with the naked eye, and therefore cannot see any afterimage of the white image, thus not affecting the user's viewing experience.

[0160] In some embodiments, the first other frame rate includes at least one subframe rate, the first other frame number includes at least one subframe number, the first other product includes at least one subproduct, the at least one subproduct, the at least one subframe rate, and the at least one subframe number correspond one-to-one, each of the at least one subframe rate is less than the second frame rate, and the control signal for the first other frame number is output to the driving circuit in sequence according to the first other frame rate, including: outputting the control signal for the first subframe number to the driving circuit in sequence according to the first subframe rate, wherein the first subframe rate is any one of the at least one subframe rate, the first subframe number is the subframe number corresponding to the first subframe rate among the at least one subframe number, the product of the reciprocal of the first subframe rate and the first frame number is the first subproduct, and the first subproduct is the subproduct corresponding to the first subframe number and the first frame rate among the at least one subproduct.

[0161] In some embodiments, the number of at least one subframe rate is at least two, and the at least one subframe rate further includes a second subframe rate, the second subframe rate being less than the first subframe rate. After the control signal for the number of first subframes is sequentially output to the driving circuit according to the first subframe rate, the method further includes: sequentially outputting a control signal for the number of second subframes to the driving circuit according to the second subframe rate, the number of second subframes being the number of subframes corresponding to the second subframe rate among the at least one number of subframes.

[0162] The aforementioned first other frame rate may include one subframe rate or multiple subframe rates. The first other frame number may include one subframe number or multiple subframe numbers. The first other product may include one subproduct or multiple subproducts. When the first other frame rate is one subframe rate, the first other frame number is one subframe number, and the first other product includes one subproduct.

[0163] When the first other frame rate includes multiple subframe rates, the first other frame number includes multiple subframe numbers, and the first other product includes multiple subproducts. The first other frame rate is less than the second frame rate. The first sum can be the sum of the first product, the second product, and the multiple subproducts.

[0164] Whether the first other frame rate includes one frame rate or multiple subframe rates, the difference between the characteristic recovery time of the driving transistor and the first sum value is less than or equal to a preset duration threshold. It can be understood that the total playback time from the start of DDIC outputting the control signal for the first frame number until the output of the control signal for the first other frame number is the first sum value. Optionally, the number of multiple subframe rates can be one, two, three, or four, and the multiple subframe rates are all different. The number of frames corresponding to each subframe rate can be the same or different.

[0165] When the first other frame rate includes multiple sub-frame rates, DDIC outputs the corresponding frame number control signal in descending order of the frame rate of these multiple sub-frame rates.

[0166] The specific size and type of frame rate that DDIC operates on can be flexibly determined according to specific needs and are not limited.

[0167] In some embodiments, before sequentially outputting control signals for a first number of frames to the driving circuit according to a first frame rate, the method includes: controlling the screen to display a first image, the first image including a light-colored pixel area and a dark-colored pixel area; after sequentially outputting control signals for a first other number of frames to the driving circuit according to a first other frame rate, controlling the screen to display a second image, the second image being a dark-colored image; in the first image, the difference between the first brightness corresponding to the light-colored pixel area and the second brightness corresponding to the dark-colored pixel area satisfies a preset brightness difference requirement.

[0168] Optionally, light-colored pixel areas can be areas of a white image, and dark-colored pixel areas can be areas of a black image. A dark image can be a black image, or more commonly, the darkest color.

[0169] After the DDIC outputs the control signal as described above, when displaying a dark image, the brightness of the original light-colored pixel area is the first brightness, and the brightness of the original dark image is the second brightness. When the difference between the first brightness and the second brightness meets the preset brightness difference requirement, the user cannot distinguish the difference in brightness with the naked eye, and therefore will not observe any afterimages on the white image.

[0170] In some embodiments, the ratio of the difference between the first brightness and the second brightness to the second brightness is less than the brightness difference threshold.

[0171] The preset brightness difference requirement can be the ratio of the difference between the first brightness and the second brightness to the second brightness, which must be less than the brightness difference threshold. Optionally, the brightness difference threshold can be 2%, 3%, or other smaller values. The smaller the brightness difference threshold, the less likely the user is to observe afterimages in the white image. The larger the brightness difference threshold, the shorter the time DDIC enters the hold frame, thus saving power.

[0172] In some embodiments, the grayscale of the light-colored pixel region of the first image is L1, the grayscale of the dark-colored pixel region of the first image is L5, and the grayscale of the second image is L17.

[0173] With this grayscale setting, users will not observe any white image ghosting, and they will not observe any white image ghosting under other common grayscale settings either.

[0174] In some embodiments, the reference voltage of the driving circuit is a first voltage. The method further includes: when a self-downsampling scenario is detected, controlling the reference voltage of the driving circuit to be a second voltage, and sequentially outputting a control signal of a third frame number to the driving circuit according to a first frame rate, wherein the second voltage is greater than the first voltage; after sequentially outputting the control signal of a third frame number to the driving circuit according to the first frame rate, sequentially outputting a control signal of a fourth frame number to the driving circuit according to the second frame rate; after sequentially outputting the control signal of a fourth frame number to the driving circuit according to the second frame rate, sequentially outputting a control signal of a second other frame rate to the driving circuit. The control signal for the second other frame rate is issued, and the second other frame rate is less than the second frame rate; the product of the reciprocal of the first frame rate and the third frame rate is the third product, the product of the reciprocal of the second frame rate and the fourth frame rate is the fourth product, the product of the reciprocal of the second other frame rate and the second other frame rate is the second other product, and the sum of the third product, the fourth product and the second other product is the second sum value; if the third frame rate is less than the first frame rate, and / or the fourth frame rate is less than the second frame rate, and / or the second other frame rate is less than the first other frame rate, the difference between the feature recovery time and the second sum value is less than or equal to the preset time threshold.

[0175] By increasing the reference voltage of the control drive circuit, DDIC applies forward bias stress to the drive transistors for both white and black pixels. The DTFTs in the drive circuit will then recover their characteristics in the forward bias direction, which is more effective in eliminating brightness differences caused by black / white images. Therefore, the faster recovery speed of the drive transistors shortens the recovery time. Consequently, even by shortening the playback duration of transition frames, ghosting on white images can be avoided.

[0176] DDIC can reduce the number of frames at one frame rate or multiple frame rates, thereby shortening the playback duration of transitional frames. This application does not limit this aspect.

[0177] By increasing the reference voltage of the control drive circuit and reducing the number of transition frames, DDIC can ensure that there is no white image ghosting while also reducing power consumption.

[0178] The foregoing has detailed examples of the methods provided in this application. It is understood that the corresponding apparatus, in order to achieve the above functions, includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0179] This application can divide the drive circuit control device into functional modules based on the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0180] Figure 11 A schematic diagram of a drive circuit control device provided in this application is shown. Device 1100 includes:

[0181] The first processing module 1101 is used to output control signals for the first number of frames to the driving circuit in sequence according to the first frame rate.

[0182] The second processing module 1102 is used to output control signals for the first number of frames to the driving circuit in sequence according to the first frame rate, and then output control signals for the second number of frames to the driving circuit in sequence according to the second frame rate, wherein the second frame rate is less than the first frame rate.

[0183] The third processing module 1103 is used to output control signals for the second frame number to the driving circuit in sequence according to the second frame rate, and then output control signals for the first other frame number to the driving circuit in sequence according to the first other frame rate, wherein the first other frame rate is less than the second frame rate; the product of the reciprocal of the first frame rate and the first frame number is the first product, the product of the reciprocal of the second frame rate and the second frame number is the second product, the product of the reciprocal of the first other frame rate and the first other frame number is the first other product, and the sum of the first product, the second product and the first other product is the first sum value; the difference between the characteristic recovery time of the driving transistor and the first sum value is less than or equal to a preset time threshold, wherein the preset time threshold is a positive number.

[0184] In some embodiments, the first sum is greater than or equal to the feature recovery time.

[0185] In some embodiments, the first sum is less than the feature recovery time, and the difference between the feature recovery time and the first sum is less than or equal to a preset time threshold.

[0186] In some embodiments, the first other frame rate includes at least one subframe rate, the first other frame number includes at least one subframe number, the first other product includes at least one subproduct, the at least one subproduct, the at least one subframe rate, and the at least one subframe number correspond one-to-one, each of the at least one subframe rate is less than the second frame rate, and the third processing module 1103 is specifically used to output a control signal for the first subframe number to the driving circuit in sequence according to the first subframe rate, the first subframe rate is any one of the at least one subframe rate, the first subframe number is the subframe number corresponding to the first subframe rate among the at least one subframe number, the product of the reciprocal of the first subframe rate and the first frame number is the first subproduct, and the first subproduct is the subproduct corresponding to the first subframe number and the first frame rate among the at least one subproduct.

[0187] In some embodiments, the number of at least one subframe rate is at least two, and the at least one subframe rate also includes a second subframe rate, the second subframe rate being less than the first subframe rate. The third processing module 1103 is specifically used to output control signals for the number of second subframes to the driving circuit in sequence according to the second subframe rate. The number of second subframes is the number of subframes corresponding to the second subframe rate among the at least one number of subframes.

[0188] In some embodiments, before the control signal for the first number of frames is sequentially output to the driving circuit according to the first frame rate, the first processing module 1101 is further configured to control the screen to display a first image, the first image including a light-colored pixel area and a dark-colored pixel area.

[0189] After the third processing module 1103 outputs the control signal of the first other frame number to the driving circuit in sequence according to the first other frame rate, the third processing module 1103 is also used to control the screen to display the second image, which is a dark image; in the first image, the difference between the first brightness corresponding to the light-colored pixel area and the second brightness corresponding to the dark-colored pixel area meets the preset brightness difference requirement.

[0190] In some embodiments, the ratio of the difference between the first brightness and the second brightness to the second brightness is less than the brightness difference threshold.

[0191] In some embodiments, the grayscale of the light-colored pixel region of the first image is L1, the grayscale of the dark-colored pixel region of the first image is L5, and the grayscale of the second image is L17.

[0192] In some embodiments, the reference voltage of the driving circuit is a first voltage. The first processing module 1101 is further configured to control the reference voltage of the driving circuit to a second voltage when a self-frequency reduction scenario is detected, and to output a control signal for a third frame number to the driving circuit in sequence according to the first frame rate. The second voltage is greater than the first voltage.

[0193] The second processing module 1102 is further configured to output a control signal for a fourth frame number to the driving circuit in sequence according to the second frame rate after sequentially outputting a control signal for a third frame number to the driving circuit in sequence according to the first frame rate.

[0194] The third processing module 1103 is further configured to, after sequentially outputting a control signal for the fourth frame number to the driving circuit according to the second frame rate, sequentially output control signals for the second other frame number to the driving circuit according to the second other frame rate, wherein the second other frame rate is less than the second frame rate; the product of the reciprocal of the first frame rate and the third frame number is the third product, the product of the reciprocal of the second frame rate and the fourth frame number is the fourth product, the product of the reciprocal of the second other frame rate and the second other frame number is the second other product, and the sum of the third product, the fourth product and the second other product is the second sum value; the third frame number is less than the first frame number, and / or the fourth frame number is less than the second frame number, and / or the second other frame number is less than the first other frame number, and the difference between the feature recovery time and the second sum value is less than or equal to a preset time threshold.

[0195] The specific manner in which the device 1100 executes the drive circuit control method and the beneficial effects thereof can be found in the relevant descriptions in the method embodiments, and will not be repeated here.

[0196] This application also provides an electronic device, including the processor described above. The electronic device provided in this embodiment may be... Figure 1 The terminal device 100 shown is used to execute the aforementioned drive circuit control method. When using integrated units, the terminal device may include a processing module, a storage module, and a communication module. The processing module can be used to control and manage the actions of the terminal device; for example, it can support the terminal device in executing the steps performed by the display unit, detection unit, and processing unit. The storage module can support the terminal device in executing stored program code and data. The communication module can support communication between the terminal device and other devices.

[0197] The processing module can be a processor or a controller. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a digital signal processor (DSP), and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, or other devices that interact with other terminal devices.

[0198] In one embodiment, when the processing module is a processor and the storage module is a memory, the terminal device involved in this embodiment can be a device having... Figure 1 The device with the structure shown.

[0199] Alternatively, the processor can be a DDIC.

[0200] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to perform the drive circuit control method described in any of the above embodiments.

[0201] This application also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the drive circuit control method described in the above embodiments.

[0202] In this embodiment, the electronic device, computer-readable storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding methods provided above, and will not be repeated here.

[0203] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between devices or units. The replaced units may or may not be physically separate. The component shown as a unit may be one physical unit or multiple physical units, that is, it may be located in one place or distributed in multiple different places. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0204] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0205] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0206] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for controlling a drive circuit, characterized in that, The driving circuit includes driving transistors, including: The first frame number of control signals are sequentially output to the driving circuit according to the first frame rate; After sequentially outputting the control signal of the first frame number to the driving circuit according to the first frame rate, the control signal of the second frame number is sequentially output to the driving circuit according to the second frame rate, wherein the second frame rate is less than the first frame rate; After sequentially outputting the control signal for the second number of frames to the driving circuit according to the second frame rate, the first other frame rate is sequentially output to the driving circuit according to the first other frame rate, wherein the first other frame rate is less than the second frame rate; The product of the reciprocal of the first frame rate and the first number of frames is the first product; the product of the reciprocal of the second frame rate and the second number of frames is the second product; the product of the reciprocal of the first other frame rate and the first other number of frames is the first other product; and the sum of the first product, the second product, and the first other product is the first sum. The difference between the characteristic recovery time of the driving transistor and the first sum is less than or equal to a preset time threshold, where the preset time threshold is a positive number.

2. The method according to claim 1, characterized in that, The first sum is greater than or equal to the characteristic recovery time.

3. The method according to claim 1, characterized in that, The first sum is less than the feature recovery time, and the difference between the feature recovery time and the first sum is less than or equal to a preset time threshold.

4. The method according to any one of claims 1 to 3, characterized in that, The first other frame rate includes at least one subframe rate, the first other frame number includes at least one subframe number, the first other product includes at least one subproduct, the at least one subproduct, the at least one subframe rate, and the at least one subframe number correspond one-to-one, each of the at least one subframe rate is less than the second frame rate, and the step of sequentially outputting control signals for the first other frame number to the driving circuit according to the first other frame rate includes: According to the first subframe rate, the driving circuit is sequentially output with a control signal for the number of first subframes. The first subframe rate is any one of the at least one subframe rate. The number of first subframes is the number of subframes corresponding to the first subframe rate among the at least one number of subframes. The product of the reciprocal of the first subframe rate and the number of first frames is the first sub-product. The first sub-product is the sub-product among the at least one sub-product that corresponds to the number of first subframes and the first subframe rate.

5. The method according to claim 4, characterized in that, The number of the at least one subframe rate is at least two, and the at least one subframe rate further includes a second subframe rate, the second subframe rate being less than the first subframe rate. After sequentially outputting control signals for the number of first subframes to the driving circuit according to the first subframe rate, the method further includes: According to the second subframe rate, the control signal for the second subframe number is sequentially output to the driving circuit, where the second subframe number is the number of subframes corresponding to the second subframe rate among the at least one subframe number.

6. The method according to any one of claims 1 to 3 and 5, characterized in that, Before sequentially outputting control signals for the first number of frames to the driving circuit according to the first frame rate, the method includes: The control screen displays a first image, which includes light-colored pixel areas and dark-colored pixel areas; After the control signal for the first other frame number is sequentially output to the driving circuit according to the first other frame rate, the screen is controlled to display the second image, which is a dark image. In the first image, the difference between the first brightness corresponding to the light-colored pixel area and the second brightness corresponding to the dark-colored pixel area meets the preset brightness difference requirement.

7. The method according to claim 6, characterized in that, The ratio of the difference between the first brightness and the second brightness to the second brightness is less than the brightness difference threshold.

8. The method according to claim 6, characterized in that, The grayscale of the light-colored pixel area in the first image is L1, the grayscale of the dark-colored pixel area in the first image is L5, and the grayscale of the second image is L17.

9. The method according to any one of claims 1 to 3, 5, 7, and 8, characterized in that, The reference voltage of the driving circuit is a first voltage, and the method further includes: When a self-frequency reduction scenario is detected, the reference voltage of the driving circuit is controlled to be the second voltage, and a control signal for the third frame number is sequentially output to the driving circuit according to the first frame rate, wherein the second voltage is greater than the first voltage; After sequentially outputting the control signal for the third frame number to the driving circuit according to the first frame rate, the control signal for the fourth frame number is sequentially output to the driving circuit according to the second frame rate. After sequentially outputting the control signal for the fourth frame number to the driving circuit according to the second frame rate, the control signal for the second other frame number is sequentially output to the driving circuit according to the second other frame rate, wherein the second other frame rate is less than the second frame rate; The product of the reciprocal of the first frame rate and the third frame number is the third product; the product of the reciprocal of the second frame rate and the fourth frame number is the fourth product; the product of the reciprocal of the second other frame rate and the second other frame number is the second other product; and the sum of the third product, the fourth product, and the second other product is the second sum. If the third frame number is less than the first frame number, and / or the fourth frame number is less than the second frame number, and / or the second other frame number is less than the first other frame number, the difference between the feature recovery duration and the second sum value is less than or equal to the preset duration threshold.

10. An electronic device, characterized in that, The electronic device includes a screen, the screen includes multiple driving circuits, the driving circuits include a DTFT, and the electronic device includes a processor, a memory, and an interface. The processor, the memory, and the interface cooperate with each other to enable the electronic device to perform the method as described in any one of claims 1 to 9.

11. The electronic device according to claim 10, characterized in that, The processor is a DDIC.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1 to 9.

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