Display device and driving method of display device
By controlling the cascading gate driving circuit in the display device to output the scan signal simultaneously in part of the time, the problem of picture interlaced in interlaced scanning driving is solved, and a higher quality display effect is achieved.
Patent Information
- Application Number
- CN202510630183.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-15
- Publication Date
- 2025-08-12
AI Technical Summary
In the interlaced scanning driving method, in the prior art, since even rows of data on the current screen are not scanned, the previous screen and the current screen are interlaced and superimposed, affecting the display effect.
When displaying the refreshed first subframe screen, the Nth and N+1st level gate driving circuits in the cascading output scan signals simultaneously for part of the time, and when displaying the refreshed first subframe screen, the individual Nth or N+1st level gate driving circuits output scan signals to ensure that data is written in each row of pixels.
This avoids overlapping and interleaving caused by some pixel rows not writing data when refreshing the display panel, and improves the display effect and display quality.
Smart Images
Figure CN120472802A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a display device and a method for driving the display device. Background Art
[0002] Interlaced scanning is a method of dividing a target image into two sub-frames. The first and second sub-frames are driven separately by controlling driving signals to display the target image. In interlaced scanning, the first sub-frame contains data for the odd-numbered rows of the target image, and the second sub-frame contains data for the even-numbered rows of the target image.
[0003] Currently, during the interlaced scanning process, when the even-numbered rows of the previous screen are refreshed and the odd-numbered rows of the current screen are refreshed, the even-numbered row pixels retain the even-numbered row data of the previous screen because the even-numbered row data of the current screen has not yet been scanned. This causes the previous screen and the current screen to be interlaced and superimposed, resulting in misalignment and affecting the display effect. Summary of the Invention
[0004] The embodiments of the present application provide a display device and a method for driving the display device, which avoids the misalignment phenomenon caused by the interlacing of display images by adjusting the scanning mode of different sub-frame images in the refreshed display image, thereby improving the display effect.
[0005] An embodiment of the present application provides a display device, including a display panel, a gate driving module and a timing controller, wherein the display panel includes multiple rows of pixels, the gate driving module includes a cascaded N-th level gate driving circuit and an N+1-th level gate driving circuit, each gate driving circuit is connected to a row of pixels, and the display frame displayed by the display panel includes an adjacent first sub-frame picture and a second sub-frame picture. The timing controller is electrically connected to the gate driving module; the timing controller is used to: when displaying the refreshed first sub-frame picture, control the N-th level gate driving circuit and the N+1-th level gate driving circuit to simultaneously output a scan signal for part of the time; when displaying the refreshed second sub-frame picture, control the N-th level gate driving circuit or the N+1-th level gate driving circuit to output a scan signal.
[0006] Optionally, the timing controller is further configured to sequentially control the Nth-stage gate driving circuit and the N+1th-stage gate driving circuit to output scanning signals when displaying the first sub-frame picture after refresh.
[0007] Optionally, the N+1th level scanning signal output by the N+1th level gate driving circuit is separated from the Nth level scanning signal output by the Nth level gate driving circuit by a first time; the N+2th level scanning signal output by the N+2th level gate driving circuit is separated from the N+1th level scanning signal output by the N+1th level gate driving circuit by a second time; wherein the sum of the first time and the second time is the charging time of a row of pixels.
[0008] Optionally, the first time is equal to the second time.
[0009] Optionally, the timing controller is further configured to: when displaying a refreshed second sub-frame image, control the Nth stage gate driving circuit or the N+1th stage gate driving circuit to output a scan signal.
[0010] Optionally, the timing controller is used to: when controlling the N+1-level gate driving circuit to output a scan signal, control the N+1-level gate driving circuit to output the N+1-level scan signal and the N+3-level gate driving circuit to output the N+3-level scan signal with a third time interval; when controlling the N-level gate driving circuit to output a scan signal, control the N-level gate driving circuit to output the N-level scan signal and the N+2-level gate driving circuit to output the N+2-level scan signal with a fourth time interval; wherein, the third time or the fourth time is equal to the charging time of a row of pixels.
[0011] The present application also provides a method for driving a display device, the display device comprising a display panel, a gate driving module, and a timing controller, the display panel comprising a plurality of rows of pixels, the gate driving module comprising a cascaded N-stage gate driving circuit and an N+1-stage gate driving circuit, each gate driving circuit being connected to a row of pixels; a display image displayed by the display panel comprising a first sub-frame image and a second sub-frame image that are adjacent, the timing controller being electrically connected to the gate driving module; the driving method comprising: when displaying a refreshed first sub-frame image, driving the N-stage gate driving circuit and the N+1-stage gate driving circuit to simultaneously output a scan signal for a portion of time;
[0012] When displaying the refreshed second sub-frame image, the Nth-stage gate driving circuit or the N+1th-stage gate driving circuit is driven to output a scan signal.
[0013] Optionally, driving the Nth-level gate driving circuit and the N+1th-level gate driving circuit to output scanning signals simultaneously during part of the time includes: driving the Nth-level gate driving circuit and the N+1th-level gate driving circuit to output scanning signals in sequence.
[0014] Optionally, the sequentially driving of the N-level gate driving circuit and the N+1-level gate driving circuit to output scanning signals includes: after the N-level gate driving circuit outputs the N-level scanning signal, delaying the output of the N+1-level scanning signal through the N+1-level gate driving circuit for a first time; after the N+1-level gate driving circuit outputs the N+1-level scanning signal, delaying the output of the N+2-level scanning signal through the N+2-level gate driving circuit for a second time; wherein the sum of the first time and the second time is the charging time of a row of pixels.
[0015] Optionally, the first time and the second time are equal.
[0016] Optionally, when displaying the refreshed first subframe image, the display data in the N+1th row of pixels includes first sub-display data obtained from the Nth row of pixels in the second time and second sub-display data obtained from the N+2th row of pixels in the first time.
[0017] Optionally, driving the N-th level gate driving circuit or the N+1-th level gate driving circuit to output a scanning signal includes: turning off the N-th level gate driving circuit and controlling the N+1-th level gate driving circuit to output a scanning signal; or, turning off the N+1-th level gate driving circuit and controlling the N-th level gate driving circuit to output a scanning signal.
[0018] Optionally, controlling the N+1-level gate driving circuit to output a scanning signal includes: after the N+1-level gate driving circuit outputs the N+1-level scanning signal, delaying the third time to output the N+3-level scanning signal through the N+3-level gate driving circuit; wherein the third time is the charging time of a row of pixels.
[0019] Optionally, controlling the N-level gate driving circuit to output the scanning signal includes: after the N-level gate driving circuit outputs the N-level scanning signal, delaying the fourth time to output the N+2-level scanning signal through the N+2-level gate driving circuit; wherein the fourth time is the charging time of a row of pixels.
[0020] In summary, in the technical solution provided in the embodiment of the present application, the display device includes a display panel, a gate drive module and a timing controller. The display panel includes multiple rows of pixels. The gate drive module includes a cascaded N-level gate drive circuit and an N+1-level gate drive circuit, and each gate drive circuit is connected to a row of pixels. The display screen displayed by the display panel includes adjacent first sub-frame screens and second sub-frame screens. The timing controller is electrically connected to the gate drive module. The timing controller is used to control the N-level gate drive circuit and the N+1-level gate drive circuit to simultaneously output a scan signal during part of the time when displaying the refreshed first sub-frame screen, and to control the N-level gate drive circuit or the N+1-level gate drive circuit to output a scan signal when displaying the refreshed second sub-frame screen.
[0021] When the display device of the embodiment of the present application displays the first sub-frame picture after the refresh, the cascaded N-th gate driving circuit and the N+1-th gate driving circuit simultaneously output the scanning signal at part of the time, so that each row of pixels of the display panel displays the data of the first sub-frame picture, avoiding the situation where some pixel rows overlap with the picture before the refresh due to the lack of written refreshed display picture data each time the picture to be displayed is refreshed, thereby improving the display effect of the display picture and the display quality of the display device. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 This is an architectural diagram of a display device provided in an embodiment of the present application;
[0023] Figure 2 is a schematic diagram of a gate drive module provided in an embodiment of the present application;
[0024] Figure 3 is a circuit diagram of a gate drive circuit provided in an embodiment of the present application;
[0025] Figure 4 1 is a timing diagram of the timing controller provided in an embodiment of the present application;
[0026] Figure 5 This is a flow chart of a driving method of a wiring harness device provided in an embodiment of the present application;
[0027] Figure 6 This is a schematic diagram of data splitting of a display screen provided by an embodiment of the present application;
[0028] Figure 7 This is another schematic diagram of data splitting of a display screen provided by an embodiment of the present application;
[0029] Figure 8 is a flow chart of another method for driving a display device provided in an embodiment of the present application;
[0030] Figure 9 It is a schematic diagram of the data display effect provided in the embodiment of the present application. DETAILED DESCRIPTION
[0031] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. The described technical solutions are only used to explain and illustrate the concept of the present application and should not be regarded as limiting the scope of protection of the present application.
[0032] In addition, the term "a plurality of" in the embodiments of the present application refers to two or more. The terms "first" and "second" in the embodiments of the present application are used to distinguish different technical features, and do not indicate any order, quantity or importance.
[0033] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.
[0034] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.
[0035] In a first aspect, an embodiment of the present application provides a display device. Figure 1 As shown, the display device includes a display panel 110, a gate driver module 120, a data driver module 130, and a timing controller 140. The display panel 110 includes multiple rows of pixels. The gate driver module 120 includes a cascaded N-stage gate driver circuit and an N+1-stage gate driver circuit, each of which is connected to a row of pixels. The display frame displayed by the display panel 110 includes a first sub-frame image and a second sub-frame image that are adjacent.
[0036] The timing controller 140 is electrically connected to the gate driver module 120 and / or the data driver module 130. When displaying the first sub-frame image after a refresh, the timing controller 140 controls the N-stage gate driver circuit and the N+1-stage gate driver circuit to simultaneously output scan signals for a portion of the time. When displaying the second sub-frame image after a refresh, the timing controller 140 controls the N-stage gate driver circuit or the N+1-stage gate driver circuit to output scan signals.
[0037] In some embodiments, the timing controller 140 is connected to the gate driving module 120 and the data driving module 130, respectively, and outputs a clock signal CK to the gate driving module 120 and a data signal DATA to the data driving module 130. The gate driving module 120 turns on the pixel rows of the display panel 110 under the control of the clock signal CK, so that the data signal DATA is written to the pixel rows when they are turned on.
[0038] Figure 2 Schematic diagram of the gate driving module 120. Figure 2As shown, the gate drive module 120 includes a cascade of gate drive circuits. The gate drive circuit can also be called a GOA (Gate Driver On Array) circuit. The input signals of each gate drive circuit include: clock signal CKa, clock signal CKb, voltage signal V SS , the scanning signal Gn-1 output by the previous gate driving circuit, and the reset signal output by the next gate driving circuit, and output the scanning signal Gn of this level. It should be noted that the scanning signal Gn output by the N-th gate driving circuit is used to drive the pixels of this row, as well as the input signal of the next gate driving circuit, or the reset signal of the previous gate driving circuit. In the gate driving module 120, the input signal of the first-level gate driving circuit is the frame start signal STV, and no reset signal is output. The last-level gate driving circuit is connected to a row of redundant GOA circuits to realize the reset of the current row. In this way, under the action of the external control signal, each level of gate driving circuit affects each other, generates a shift pulse signal, and performs row-by-row scanning in sequence.
[0039] The gate driving circuit outputs a scanning signal Gn according to the clock signal CK, and further controls the opening or closing of the pixel row according to the scanning signal Gn, so as to write data when the pixel row is opened to realize the display of the display frame.
[0040] In a traditional interlaced scanning drive display, the display screen is divided into an odd subframe including odd-numbered row data and an even subframe including even-numbered row data. The odd-numbered row pixels and the even-numbered row pixels of the display panel 110 are turned on respectively according to the scanning signal output by the gate driving module 120. When the odd-numbered row pixels are turned on, the odd-numbered row data in the odd subframe is displayed, and when the even-numbered row pixels are turned on, the even-numbered row data in the even subframe is displayed. The display of the display screen frame is realized by displaying the odd subframe and the even subframe.
[0041] However, in the traditional interlaced scanning drive display method, when the display frame is refreshed, regardless of whether the odd sub-frame or the even sub-frame is displayed first, since the pixel rows without data written still retain the data of the previous display frame, the refreshed display frame and the data of the previous display frame are interlaced and superimposed, resulting in misalignment, affecting the display effect.
[0042] The display device of the embodiment of the present application still divides the display frame displayed by the display panel 110 into adjacent first and second sub-frames, and the first and second sub-frames respectively include different pixel row data. For example, the first sub-frame includes odd-numbered row data, and the second sub-frame includes even-numbered row data; or the first sub-frame includes even-numbered row data, and the second sub-frame includes odd-numbered row data.
[0043] When the gate driver module 120 displays the refreshed first sub-frame image, the timing controller 140 controls the N-th stage gate driver circuit and the N+1-th stage gate driver circuit to simultaneously output scan signals during a portion of the time. When the gate driver module 120 displays the refreshed second sub-frame image, the timing controller 140 controls the N-th stage gate driver circuit or the N+1-th stage gate driver circuit to output scan signals.
[0044] Controlling the N-th level gate driving circuit and the N+1-th level gate driving circuit to output scanning signals simultaneously during part of the time indicates that the gate driving module 120 outputs the N-th level scanning signal through the N-th level gate driving circuit to turn on the N-th row of pixels, and also outputs the N+1-th level scanning signal through the N+1-th level gate driving circuit to turn on the N+1-th row of pixels, so that the N-th row of pixels and the N+1-th row of pixels of the display panel 110 are simultaneously turned on to write data during part of the time.
[0045] Controlling the N-th level gate driving circuit or the N+1-th level gate driving circuit to output a scanning signal indicates that the gate driving module 120 outputs the N-th level scanning signal through the N-th level gate driving circuit to turn on the N-th row of pixels, or outputs the N+1-th level scanning signal through the N+1-th level gate driving circuit to turn on the N+1-th row of pixels, so that the N-th row of pixels or the N+1-th row of pixels of the display panel 110 is turned on to write data.
[0046] When the first sub-frame includes odd-numbered rows of data, the second sub-frame includes even-numbered rows of data, and N is an odd number, the display device of the embodiment of the present application displays the refreshed first sub-frame. During the portion of time that the gate driver module 120 turns on the odd-numbered rows of pixels of the display panel 110 under the drive of the Nth-stage gate driver circuit, the gate driver module 120 also turns on the even-numbered rows of pixels of the display panel 110 under the drive of the N+1th-stage gate driver circuit. This allows the display panel 110 to not only turn on the odd-numbered rows of pixels to display the odd-numbered rows of data, but also turn on the even-numbered rows of pixels to display the odd-numbered rows of data under the control of the gate driver module 120. When displaying the refreshed second sub-frame, the gate driver module 120 turns on the even-numbered rows of pixels through the N+1th-stage gate driver circuit, so that the even-numbered rows of pixels display the even-numbered rows of data.
[0047] When the first subframe includes odd-numbered row data, the second subframe includes even-numbered row data, and N is an even number, the display device displays the refreshed first subframe. During the portion of time that the gate driver module 120, driven by the N+1-th stage gate driver circuit, turns on the odd-numbered row pixels of the display panel 110, the gate driver module 120 also turns on the even-numbered row pixels of the display panel 110, driven by the N-th stage gate driver circuit. When displaying the refreshed second subframe, the gate driver module 120 turns on the even-numbered row pixels via the N-th stage gate driver circuit.
[0048] When the first sub-frame includes even-numbered row data, the second sub-frame includes odd-numbered row data, and N is an odd number, the display device displays the refreshed first sub-frame. During the portion of time that the gate driver module 120, driven by the N+1-th stage gate driver circuit, turns on the even-numbered row pixels of the display panel 110, the gate driver module 120 also turns on the odd-numbered row pixels of the display panel 110, driven by the N-th stage gate driver circuit. This allows the display panel 110 to not only turn on the even-numbered row pixels to display the even-numbered row data, but also turn on the odd-numbered row pixels to display the even-numbered row data under the control of the gate driver module 120. When displaying the refreshed second sub-frame, the gate driver module 120 turns on the odd-numbered row pixels via the N-th stage gate driver circuit, so that the odd-numbered row pixels display the odd-numbered row data.
[0049] When the first sub-frame includes even-numbered row data, the second sub-frame includes odd-numbered row data, and N is an even number, the display device displays the refreshed first sub-frame. During the portion of time that the gate driver module 120, driven by the Nth-stage gate driver circuit, turns on the even-numbered row pixels of the display panel 110, the gate driver module 120 also turns on the odd-numbered row pixels of the display panel 110, driven by the N+1th-stage gate driver circuit. This allows the display panel 110 to not only turn on the even-numbered row pixels to display the even-numbered row data, but also turn on the odd-numbered row pixels to display the even-numbered row data under the control of the gate driver module 120. When displaying the refreshed second sub-frame, the gate driver module 120 turns on the odd-numbered row pixels via the N+1th-stage gate driver circuit, so that the odd-numbered row pixels display the odd-numbered row data.
[0050] In summary, the embodiment of the present application simultaneously displays odd-numbered row data or even-numbered row data through both odd-numbered row pixels and even-numbered row pixels when displaying the first sub-frame. This allows data to be refreshed in both odd-numbered row pixels and even-numbered row pixels in the first sub-frame after the display frame is refreshed. This avoids overlap and interleaving with the previous display frame due to the absence of data written to odd-numbered row pixels or even-numbered row pixels when the display panel 110 refreshes the display frame, thereby improving the display effect and enhancing the display quality of the display panel.
[0051] Figure 3 This is an example of a gate drive circuit. It can be understood that the embodiments of the present application have no restrictions on the architecture of the gate drive circuit. Any circuit can be selected according to needs in the application as long as it can output the scan signal Gn according to the clock signal CK.
[0052] like Figure 3 As shown, in some embodiments, the gate driving circuit includes transistors T21 to T73 and a capacitor C1. Figure 3 The gate driving circuit shown includes a pull-up module, a pull-up control module, a first pull-down maintaining module, a second pull-down maintaining module and a pull-down module.
[0053] The pull-up module includes transistors T21 and T22 and a capacitor C1. Transistor T21 has a gate connected to a first node R1, a source connected to a clock signal CK, and a drain connected to a second node R2, which is connected to a scan signal G(n). Transistor T22 has a gate connected to the first node R1, a source connected to the clock signal CK, and a drain connected to the Nth-stage cascade signal line ST(N). Capacitor C1 has a first end connected to the first node R1 and a second end connected to the second node R2.
[0054] The pull-up control module includes a transistor T11. The gate of transistor T11 is electrically connected to the NX-th stage cascade signal line ST(NX), the source is electrically connected to the NX-th stage scan signal G(NX), and the drain is electrically connected to the first node R1 and the pull-down maintenance module. Transistor T44 has a gate connected to the reset control signal STV, a source connected to the first node R1, and a drain connected to the first low-level power line VGL1.
[0055] The pull-down module includes a transistor T45 , wherein the gate of the transistor T45 is connected to the N+Y-th stage cascade signal ST(N+Y), the source is connected to the second node R2 , and the drain is connected to the first low-level power line VGL1 .
[0056] The first pull-down hold module includes transistors T51 to T72. Transistor T51 has its gate and drain connected to the first low-frequency clock signal LC1, and its source connected to the third node R3. Transistor T52 has its gate connected to the first node R1, its drain connected to the third node R3, and its source connected to the first low-level power line VGL1. Transistor T53 has its gate connected to the third node R3, its drain connected to the first low-frequency clock signal LC1, and its source connected to the fourth node R4. Transistor T54 has its gate connected to the first node R1, its drain connected to the fourth node R4, and its source connected to the first low-level power line VGL1. Transistor T55 has its gate connected to the control signal Q(N-2), its drain connected to the third node R3, and its source connected to the first low-level power line VGL1. Transistor T56 has its gate connected to the control signal Q(N-2), its drain connected to the fourth node R4, and its source connected to the first low-level power line VGL1. The gate of the transistor T32 is connected to the fourth node R4, the drain is connected to the second node R2, and the source is connected to the second low-level power supply line VGL2. The gate of the transistor T42 is connected to the fourth node R4, the drain is connected to the first node R1, and the source is connected to the first low-level power supply line VGL1. The gate of the transistor T72 is connected to the fourth node R4, the source is connected to the first low-level power supply line VGL1, and the drain is connected to the N-th stage cascade signal line ST(N).
[0057] The second pull-down hold module includes transistors T61 to T73. Transistor T61 has its gate and drain connected to the second low-frequency clock signal LC2, and its source connected to the fifth node R5. Transistor T62 has its gate connected to the first node R1, its drain connected to the fifth node R5, and its source connected to the first low-level power line VGL1. Transistor T63 has its gate connected to the fifth node R5, its drain connected to the second low-frequency clock signal LC2, and its source connected to the sixth node R6. Transistor T64 has its gate connected to the first node R1, its drain connected to the sixth node R6, and its source connected to the first low-level power line VGL1. Transistor T65 has its gate connected to the control signal Q(N-2), its drain connected to the fifth node R5, and its source connected to the first low-level power line VGL1. Transistor T66 has its gate connected to the control signal Q(N-2), its drain connected to the sixth node R6, and its source connected to the first low-level power line VGL1. The gate of the transistor T33 is connected to the sixth node R6, the drain is connected to the second node R2, and the source is connected to the second low-level power supply line VGL2. The gate of the transistor T43 is connected to the sixth node R6, the drain is connected to the first node R1, and the source is connected to the first low-level power supply line VGL1. The gate of the transistor T73 is connected to the sixth node R6, the source is connected to the first low-level power supply line VGL1, and the drain is connected to the N-th stage cascade signal line ST(N).
[0058] like Figure 3 The gate drive circuit shown in the figure precharges the first node R1 after receiving the G(NX) signal. Finally, the scan signal G(n) is output through the pull-up module's transistor T21. Upon receiving the ST(N+Y) signal from the pull-down module, the first node R1 is discharged and pulled down to the first low-level power line VGL1, while the G(n) is discharged and pulled down to the second low-level power line VGL2.
[0059] In some embodiments, the timing controller 140 is further configured to sequentially control the Nth stage gate driving circuit and the N+1th stage gate driving circuit to output scan signals when displaying the first sub-frame image after refresh.
[0060] The gate driver module 120 controls the Nth-stage gate driver circuit and the N+1th-stage gate driver circuit to simultaneously output scan signals for a portion of the time. Specifically, the gate driver module 120 sequentially outputs scan signals to each stage of the gate driver circuit to sequentially drive each row of pixels to display the image row by row. In other words, when displaying the first subframe after a refresh, the gate driver module 120 sequentially outputs the Nth-stage scan signal to the Nth-stage gate driver circuit and then outputs the N+1th-stage scan signal to the N+1th-stage gate driver circuit, based on the clock signal CK sent by the timing controller 140. For example, the first-level gate drive circuit corresponding to the first pixel row generates a scanning signal G1 for the first row of pixels according to the first clock signal (CK1), so that the first row of pixels are turned on under the drive of G1; the second-level gate drive circuit corresponding to the second pixel row generates a scanning signal G2 for the second row of pixels according to the second clock signal (CK2), so that the second row of pixels are turned on under the drive of G2; the third-level gate drive circuit corresponding to the third pixel row generates a scanning signal G3 for the third row of pixels according to the third clock signal (CK3), so that the third row of pixels are turned on under the drive of G3, ..., in this way, each row of pixels is turned on in turn, and adjacent pixel rows are turned on at the same time for part of the time to display the first subframe image.
[0061] When displaying the first sub-frame image, the embodiment of the present application opens each row of pixels in sequence through the scanning signal output by the gate driving circuit in a stage-by-stage manner, so that each row of pixels is written with the refreshed image data, thereby avoiding misalignment when the display image frame is refreshed and improving the display effect of the display panel.
[0062] In some embodiments, a first time interval exists between the N+1 level scanning signal output by the N+1 level gate driving circuit and the N level scanning signal output by the N level gate driving circuit. A second time interval exists between the N+2 level scanning signal output by the N+2 level gate driving circuit and the N+1 level scanning signal output by the N+1 level gate driving circuit. The sum of the first time interval and the second time interval is the charging time for a row of pixels.
[0063] The charging time for a row of pixels can be expressed as the unit time required for the pixel row to display data. After the pixel row of the display panel 110 is turned on, the data driving module 130 charges the pixel row so that the pixel row can stably display the image when charging is completed. Typically, the charging time for a pixel row can be expressed as 1 hour.
[0064] In this embodiment, when displaying the first subframe, each gate driver circuit sequentially outputs a scan signal to turn on pixel rows, and adjacent pixel rows are simultaneously turned on for a portion of the time, so that each pixel row is written with the refreshed image data. The N+1-level scan signal output by the N+1-level gate driver circuit is separated from the N-level scan signal output by the N-level gate driver circuit by a first time. That is, after the N-level scan signal is output for the first time, the N+1-level gate driver circuit simultaneously outputs the N+1-level scan signal to turn on the N+1-row pixels, so that the N+1-row pixels also write the N-row data of the display image frame. The N+2-level scan signal output by the N+2-level gate driver circuit is separated from the N+1-level scan signal output by the N+1-level gate driver circuit by a second time. That is, after the N+1-level scan signal is output for the second time, the N+2-level gate driver circuit simultaneously outputs the N+2-level scan signal to turn on the N+2-row pixels, so that the N+1-row pixels continue to write the N+2-row data of the display image frame, and so on. For example, after the first-level scanning signal turns on the first row of pixels for the first time, the second row of pixels is turned on at the same time under the drive of the second-level scanning signal, so that the second row of pixels also writes the data corresponding to the first row of pixels; and after the second row of pixels is turned on for the second time, the third row of pixels is turned on at the same time, so that the second row of pixels continues to write the data corresponding to the third row of pixels.
[0065] In an embodiment of the present application, when the Nth row of pixels has not yet been fully charged, the N+1th row of pixels is opened at an interval of a first time, so that after the Nth row of pixels is written into the Nth row of pixels for a first time, the Nth row of pixels is simultaneously written into the Nth row of pixels and the N+1th row of pixels; and after the N+1th row of pixels is opened for a second time, the N+2th row of pixels is opened, so that the N+2th row of pixels corresponding to the N+2th row of pixels is simultaneously written into the N+1th row of pixels and the N+2th row of pixels, thereby making the data displayed by the N+1th row of pixels have a staggered effect of the data corresponding to the upper and lower rows of pixels.
[0066] The sum of the first time and the second time is the charging time of one row of pixels, which can enable the data corresponding to the adjacent N row of pixels and the data corresponding to the N+2 row of pixels to be displayed when the N+1 row of pixels is turned on.
[0067] In some embodiments, the first time is equal to the second time.
[0068] In this embodiment, when displaying the first subframe, the pixels in row N+1 are controlled to turn on and write the data corresponding to the pixels in row N and the data corresponding to the pixels in row N+2. To facilitate calculation and control, the first time and the second time can be set to the same time. The sum of the first time and the second time is the charging time for a row of pixels, expressed as 1 hour. When the first time and the second time are equal, the first time and the second time are both equal to 0.5 hours.
[0069] Please refer to Figure 4 The driving timing diagram of the first sub-frame is shown in FIG. 1 , where STV is a frame revelation signal and CK1 to CK8 are clock signals for driving the gate driving module 120. The gate driving module 120 outputs a scanning signal Gn under the control of the clock signal CK, so that the pixel row is turned on under the drive of the scanning signal Gn. Figure 4 As shown in the figure, when displaying the first sub-frame after refresh, the first-stage gate drive circuit outputs a scan signal G1 driven by the clock signal CK1 to turn on the first row of pixels. After the first row of pixels is turned on for 0.5 hours, the second-stage gate drive circuit outputs a scan signal G2 driven by the clock signal CK2 to turn on the second row of pixels. After the second row of pixels is turned on for 0.5 hours, the third-stage gate drive circuit outputs a scan signal G3 driven by the clock signal CK3 to turn on the third row of pixels, and so on. Adjacent pixel rows are turned on simultaneously for part of the time.
[0070] In the embodiment of the present application, the first time and the second time are set to be equal, which facilitates the control of the gate driving circuits at each level and can improve the driving efficiency of the gate driving module 120.
[0071] In some embodiments, the timing controller 140 is further configured to control the Nth stage gate driving circuit or the N+1th stage gate driving circuit to output a scan signal when displaying the refreshed second sub-frame image.
[0072] The second sub-frame image corresponds to different data than the first sub-frame image. For example, when the first sub-frame image includes odd-numbered row data of the display image frame, the second sub-frame image includes even-numbered row data of the display image frame; and when the first sub-frame image includes even-numbered row data of the display image frame, the second sub-frame image includes odd-numbered row data of the display image frame. After the refreshed first sub-frame image is displayed, the pixel rows corresponding to the gate drive circuit can be turned on by the scanning signal output by the Nth-level gate drive circuit or the N+1th-level gate drive circuit to display the second sub-frame image data.
[0073] In some embodiments, the timing controller 140 is configured to: when controlling the N+1-stage gate driver circuit to output a scan signal, control the N+1-stage gate driver circuit to output the N+1-stage scan signal and the N+3-stage gate driver circuit to output the N+3-stage scan signal, with a third time interval therebetween. When controlling the N-stage gate driver circuit to output a scan signal, control the N-stage gate driver circuit to output the N-stage scan signal and the N+2-stage gate driver circuit to output the N+2-stage scan signal, with a fourth time interval therebetween. The third time or the fourth time is equal to the charging time of a row of pixels.
[0074] Please continue to refer to Figure 4 As shown in the driving timing diagram. Figure 4As shown, the second subframe screen writes screen data by turning on alternate pixel rows. For example, when the N+1-th gate drive circuit is controlled to output a scan signal, the N+1-th gate drive circuit outputs the N+1-th scan signal to turn on the N+1-th row of pixels, so that the N+1-th row of pixels writes the N+1-th row of data; after the N+1-th scan signal is output for a third time, the N+3-th gate drive circuit outputs the N+3-th scan signal to turn on the N+3-th row of pixels, so that the N+3-th row of pixels writes the N+3-th row of data, and so on. For another example, when the N-th gate drive circuit is controlled to output a scan signal, the N-th gate drive circuit is controlled to output the N-th scan signal to turn on the N-th row of pixels, so that the N-th row of pixels writes the N-th row of data; after the N-th scan signal is output for a fourth time, the N+2-th gate drive circuit outputs the N+2-th scan signal to turn on the N+2-th row of pixels, so that the N+2-th row of pixels writes the N+2-th row of data, and so on.
[0075] Since each pixel row is refreshed and written with new data when the refreshed first sub-frame is displayed, when the refreshed second sub-frame is displayed, data only needs to be written to the pixel rows corresponding to the second sub-frame. It can be understood that when the second sub-frame includes even-numbered rows of data of the display frame, if N is an odd number, the scanning signal is output in sequence through the N+1-th gate drive circuit, the N+3-th gate drive circuit, etc.; if N is an even number, the scanning signal is output in sequence through the N-th gate drive circuit, the N+2-th gate drive circuit, etc.; when the second sub-frame includes odd-numbered rows of data of the display frame, if N is an odd number, the scanning signal is output in sequence through the N-th gate drive circuit, the N+1-th gate drive circuit, etc.; if N is an even number, the scanning signal is output in sequence through the N+1-th gate drive circuit, the N+3-th gate drive circuit, etc.
[0076] When the display device of the embodiment of the present application displays the first sub-frame picture after the refresh, the cascaded N-th gate driving circuit and the N+1-th gate driving circuit simultaneously output the scanning signal at part of the time, so that each row of pixels of the display panel displays the data of the first sub-frame picture, avoiding the situation where some pixel rows overlap with the picture before the refresh due to the lack of written refreshed display picture data each time the picture to be displayed is refreshed, thereby improving the display quality of the displayed picture.
[0077] In a second aspect, an embodiment of the present application further provides a method for driving a display device, wherein the display device includes a display panel, a gate driving module, and a timing controller. The display panel includes multiple rows of pixels, and the gate driving module includes a cascaded N-level gate driving circuit and an N+1-level gate driving circuit, each gate driving circuit being connected to a row of pixels. The display screen displayed by the display panel includes adjacent first sub-frame screens and second sub-frame screens, and the timing controller is electrically connected to the gate driving module. Figure 5 As shown, the driving method includes the following steps S510 to S520.
[0078] Step S510 , when displaying the refreshed first sub-frame image, driving the Nth stage gate driving circuit and the N+1th stage gate driving circuit to simultaneously output scan signals during a portion of the time.
[0079] In step S520 , when displaying the refreshed second sub-frame image, the Nth-stage gate driving circuit or the N+1th-stage gate driving circuit is driven to output a scan signal.
[0080] The embodiment of the present application divides the display screen frame into a first sub-frame screen and a second sub-frame screen including different pixel row data. When displaying the refreshed first sub-frame screen, the N-th level gate drive circuit and the N+1-th level gate drive circuit are driven to output a scan signal simultaneously for part of the time, so that the N-th row of pixels corresponding to the N-th level gate drive circuit and the N+1-th row of pixels corresponding to the N+1-th level gate drive circuit are simultaneously turned on to write the data of the first sub-frame screen for part of the time. When displaying the refreshed second sub-frame screen, the N-th level gate drive circuit or the N+1-th level gate drive circuit is driven to output a scan signal, so that the N-th row of pixels corresponding to the N-th level gate drive circuit or the N+1-th row of pixels corresponding to the N+1-th level gate drive circuit are turned on to write the data of the second sub-frame screen.
[0081] In the embodiment of the present application, after the display frame is refreshed, the gate driver module outputs a scanning signal to each pixel row of the display panel, causing all pixel rows to refresh data. This avoids the phenomenon of overlapping and interlacing with the previous display frame caused by some pixel rows not having data written thereto when the display panel 110 refreshes the display frame in the traditional interlaced scanning method. The display device driving method of the embodiment of the present application can improve the display effect of the display image and enhance the display quality of the display panel.
[0082] In some embodiments, driving the Nth-level gate driving circuit and the N+1th-level gate driving circuit to output scanning signals simultaneously during part of the time includes: driving the Nth-level gate driving circuit and the N+1th-level gate driving circuit to output scanning signals in sequence.
[0083] Please combine Figure 4In the timing diagram shown, when displaying the refreshed first subframe, clock signals sequentially drive each gate driver circuit to output a scan signal to turn on the corresponding row of pixels. For example, clock signal CK1 sequentially drives the first-stage gate driver circuit to output a first-stage scan signal, turning on the first row of pixels. Clock signal CK2 drives the second-stage gate driver circuit to output a second-stage scan signal, turning on the second row of pixels. Clock signal CK3 drives the third-stage gate driver circuit to output a third-stage scan signal, turning on the third row of pixels. And so on, turning on each row of pixels in the display panel to write the data of the first subframe into each row of pixels, with adjacent rows of pixels turned on simultaneously for part of the time.
[0084] In some embodiments, the N-level gate driving circuit and the N+1-level gate driving circuit are driven in sequence to output scanning signals, including: after the N-level gate driving circuit outputs the N-level scanning signal, delaying the first time to output the N+1-level scanning signal through the N+1-level gate driving circuit; after the N+1-level gate driving circuit outputs the N+1-level scanning signal, delaying the second time to output the N+2-level scanning signal through the N+2-level gate driving circuit; wherein the sum of the first time and the second time is the charging time of a row of pixels.
[0085] Please continue reading Figure 4 In the timing diagram shown, there is a time delay between adjacent clock signals, which causes a time delay between the scanning signals output by the gate drive circuit. The sum of the first time and the second time is the charging time of a row of pixels, and the charging time of a row of pixels is expressed as 1H.
[0086] In some embodiments, the first time and the second time are equal.
[0087] When the first time and the second time are equal, the first time and the second time are both 0.5H. Figure 4 As shown, when driving the first sub-frame image after display refresh, the clock signals are output with a delay of 0.5H, and correspondingly, the scanning signals are also output with a delay of 0.5H.
[0088] In some embodiments, when displaying the refreshed first subframe image, the display data in the N+1th row of pixels includes the first sub-display data obtained from the Nth row of pixels in the second time and the second sub-display data obtained from the N+2th row of pixels in the first time.
[0089] For example, when the first subframe contains odd-numbered rows of data and N is 1, the pixels in the first row are turned on by the first-level scanning signal G1 and the first-row data is written. After the pixels in the first row are turned on for 0.5 hours, the pixels in the second row are turned on by the second-level scanning signal G2, and the first-row data is also written into the pixels in the second row. After the pixels in the second row are turned on for 0.5 hours, the pixels in the third row are turned on by the third-level scanning signal G3, and the third-row data is written into both the pixels in the second row and the third row.
[0090] The embodiment of the present application displays the data corresponding to the pixels in the Nth row and the data corresponding to the pixels in the N+2th row in the N+1th row of pixels, thereby avoiding the phenomenon of overlapping and interleaving with the previous display frame when the display frame is refreshed due to the fact that some pixel rows in the first sub-frame picture do not have data written, thereby improving the display quality of the picture to be displayed and enhancing the display effect of the display panel.
[0091] In some embodiments, driving the N-th level gate driving circuit or the N+1-th level gate driving circuit to output a scanning signal includes: turning off the N-th level gate driving circuit and controlling the N+1-th level gate driving circuit to output a scanning signal; or, turning off the N+1-th level gate driving circuit and controlling the N-th level gate driving circuit to output a scanning signal.
[0092] Please continue to refer to Figure 4 The driving timing diagram of the second sub-frame picture is shown. When the display of the first sub-frame picture ends and the refreshed second sub-frame picture is displayed, only the Nth level gate driving circuit or the N+1th level gate driving circuit needs to output the scanning signal, and the gate driving circuit that does not output the scanning signal is turned off.
[0093] Taking the second sub-frame picture including the even-numbered row data of the display picture as an example, when driving the display panel to display the second sub-frame picture, the gate drive circuit corresponding to the odd-numbered row pixels is turned off, and the gate drive circuit corresponding to the even-numbered row pixels is controlled to output the scanning signal, so that the even-numbered row pixels are turned on under the drive of the scanning signal and the data of the second sub-frame picture is written.
[0094] In some embodiments, controlling the N+1-level gate driving circuit to output a scanning signal includes: after the N+1-level gate driving circuit outputs the N+1-level scanning signal, delaying the third time to output the N+3-level scanning signal through the N+3-level gate driving circuit; wherein the third time is the charging time of a row of pixels.
[0095] In some embodiments, controlling the N-level gate driving circuit to output a scanning signal includes: after the N-level gate driving circuit outputs the N-level scanning signal, delaying the fourth time to output the N+2-level scanning signal through the N+2-level gate driving circuit; wherein the fourth time is the charging time of a row of pixels.
[0096] In the embodiment of the present application, when displaying the refreshed first sub-frame image, new data will be rewritten into both the odd-numbered rows of pixels and the even-numbered rows of pixels. When displaying the refreshed second sub-frame image, data only needs to be written into the pixel rows corresponding to the second sub-frame image data.
[0097] In some embodiments, the turn-on time of the gate driving circuit is greater than or equal to the charging time of a row of pixels.
[0098] The charging time of a row of pixels represents the time required for a row of pixels to display data. To ensure the display effect of the display panel, the opening time of each pixel row must be greater than the charging time to ensure complete display of the row of pixels.
[0099] Below, the display driving method provided in the embodiment of the present application is introduced and explained with an example.
[0100] In this embodiment, the display frame is a white square moving leftward on a black background. Figures 6 and 7 , Figure 6 This is a schematic diagram of the display screen split before the white box moves. Figure 7 This is a schematic diagram of the display screen split after the white box moves.
[0101] Figure 6 (a) shows the display frame before the white box moves. Figure 6 (b) and Figure 6 (c) Figure 6 (a) shows the first sub-frame and the second sub-frame after the frame is split. Figure 6 (b) include Figure 6 (a) Displays the odd-numbered rows of the image frame. Figure 6 (c) include Figure 6 (a) Displays the even-numbered lines of data in the frame.
[0102] Figure 7 (a) shows the display frame after the white box moves. Figure 7 (b) and Figure 7 (c) Figure 7 (a) shows the first sub-frame and the second sub-frame after the frame is split. Figure 7 (b) include Figure 7 (a) Displays the odd-numbered rows of the image frame. Figure 7 (c) include Figure 7 (a) Displays the even-numbered lines of data in the image frame.
[0103] Figure 8 This is a flow chart of another method for driving a display device provided by an embodiment of the present application. Figure 8As shown, the driving method may include the following steps S810 to S830.
[0104] Step S810 , obtaining a refreshed display frame of the display panel, where the refreshed display frame includes a first sub-frame and a second sub-frame.
[0105] The first sub-frame image includes odd-numbered row data of the refreshed display image frame, and the second sub-frame image includes even-numbered row data of the to-be-displayed image frame.
[0106] In step S820 , each gate driving circuit is sequentially driven to output a scan signal so that the display panel displays a first sub-frame image. Adjacent gate driving circuits output scan signals simultaneously at part of the time.
[0107] Each level of gate driving circuit is driven in sequence to output a scanning signal, that is, the first level scanning signal is output through the first level gate driving circuit, the second level scanning signal is output through the second level gate driving circuit, the third level scanning signal is output through the third level gate driving circuit..., so as to turn on the first pixel row, the second pixel row, the third pixel row and so on.
[0108] Adjacent gate drive circuits output scan signals simultaneously at some point in time, indicating that adjacent pixel rows are also turned on at some point in time. By controlling the time interval between when the Nth-stage gate drive circuit outputs the Nth-stage scan signal and when the N+1th-stage gate drive circuit outputs the N+1th-stage scan signal, display data can be written to the upper and lower pixel rows when some pixel rows are turned on.
[0109] In step S830 , the Nth gate driving circuit is turned off, the N+1th gate driving circuit is controlled to output a scan signal, and after a third time, the N+3th gate driving circuit is controlled to output a scan signal so that the display panel displays a second subframe image.
[0110] In this embodiment, the second subframe includes even-numbered rows of data, and N is an odd number. When the second subframe is displayed, the drive circuits corresponding to the odd-numbered rows of pixels are turned off, and the drive circuits corresponding to the even-numbered rows of pixels sequentially output scanning signals to display the second subframe.
[0111] Please refer to Figure 9 The data shown is a schematic diagram showing the effect, Figure 9 As shown, according to the display driving method provided in the embodiment of the present application, Figure 6 The display of (a) is refreshed to Figure 7As shown in (a), the odd-numbered row input and even-numbered row data in the refreshed first sub-frame picture are written simultaneously, avoiding the overlapping and interlacing phenomenon of the picture caused by the lack of written data in some rows of pixels in the first sub-frame picture during the traditional display picture frame switching, thereby improving the display quality of the picture to be displayed and enhancing the display effect of the display panel.
[0112] It should be understood that the driving method of the above-mentioned display device is a method embodiment corresponding to the above-mentioned display device. For a detailed description of each step in the driving method and its beneficial effects, please refer to the embodiment of the above-mentioned display device, which will not be repeated here.
[0113] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0114] The above is a detailed introduction to a display device and a driving method for a display device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A display device, characterized in that: The device comprises a display panel, a gate driving module, and a timing controller, wherein the display panel comprises multiple rows of pixels, the gate driving module comprises a cascaded N-stage gate driving circuit and an N+1-stage gate driving circuit, each gate driving circuit being connected to a row of pixels, the display frame displayed by the display panel comprising adjacent first and second sub-frame images, and the timing controller is electrically connected to the gate driving module; The timing controller is used to: control the N-th level gate drive circuit and the N+1-th level gate drive circuit to simultaneously output a scan signal during part of the time when displaying the first sub-frame image after a refresh; and control the N-th level gate drive circuit or the N+1-th level gate drive circuit to output a scan signal when displaying the second sub-frame image after a refresh.
2. The display device according to claim 1, wherein The timing controller is further configured to: When displaying the first sub-frame picture after refresh, the Nth stage gate driving circuit and the N+1th stage gate driving circuit are controlled in sequence to output scanning signals.
3. The display device according to claim 2, wherein: The N+1th level scanning signal output by the N+1th level gate driving circuit is separated from the Nth level scanning signal output by the Nth level gate driving circuit by a first time; the N+2th level scanning signal output by the N+2th level gate driving circuit is separated from the N+1th level scanning signal output by the N+1th level gate driving circuit by a second time; The sum of the first time and the second time is the charging time of a row of pixels.
4. The display device according to claim 3, wherein The first time is equal to the second time.
5. The display device according to claim 1, wherein The timing controller is further configured to: When displaying the refreshed second sub-frame image, the Nth stage gate driving circuit or the N+1th stage gate driving circuit is controlled to output a scan signal.
6. The display device according to claim 5, wherein: The timing controller is used for: In the case of controlling the N+1th stage gate driving circuit to output a scanning signal, controlling the N+1th stage gate driving circuit to output the N+1th stage scanning signal and the N+3th stage gate driving circuit to output the N+3th scanning signal to be separated by a third time; In the case of controlling the N-th stage gate driving circuit to output a scanning signal, controlling the N-th stage gate driving circuit to output the N-th stage scanning signal and the N+2-th stage gate driving circuit to output the N+2-th scanning signal to be spaced apart by a fourth time; The third time or the fourth time is equal to the charging time of a row of pixels.
7. A method for driving a display device, characterized in that: The display device includes a display panel, a gate driving module, and a timing controller. The display panel includes multiple rows of pixels. The gate driving module includes a cascaded N-stage gate driving circuit and an N+1-stage gate driving circuit, each gate driving circuit being connected to a row of pixels. The display panel displays a display image including a first sub-frame image and a second sub-frame image that are adjacent. The timing controller is electrically connected to the gate driving module. The driving method includes: When displaying the refreshed first sub-frame image, driving the Nth-stage gate driving circuit and the N+1th-stage gate driving circuit to simultaneously output scanning signals during part of the time; When displaying the refreshed second sub-frame image, the Nth-stage gate driving circuit or the N+1th-stage gate driving circuit is driven to output a scan signal.
8. The method according to claim 7, characterized in that The step of driving the Nth-stage gate driving circuit and the N+1th-stage gate driving circuit to simultaneously output scanning signals during a portion of the time includes: The Nth stage gate driving circuit and the N+1th stage gate driving circuit are driven in sequence to output scanning signals.
9. The method according to claim 8, characterized in that The step of sequentially driving the Nth-stage gate driving circuit and the N+1th-stage gate driving circuit to output scanning signals includes: After the N-th stage gate driving circuit outputs the N-th stage scanning signal, outputting the N+1-th stage scanning signal through the N+1-th stage gate driving circuit after a first delay; After the N+1-th gate driving circuit outputs the N+1-th level scanning signal, outputting the N+2-th level scanning signal through the N+2-th level gate driving circuit after a second delay; The sum of the first time and the second time is the charging time of a row of pixels.
10. The method according to claim 9, characterized in that The first time and the second time are equal.
11. The method according to claim 9, characterized in that When displaying the refreshed first subframe image, the display data in the N+1th row of pixels includes the first sub-display data acquired from the Nth row of pixels in the second time and the second sub-display data acquired from the N+2th row of pixels in the first time.
12. The method according to claim 7, characterized in that The step of driving the Nth-stage gate driving circuit or the N+1th-stage gate driving circuit to output a scanning signal includes: Turn off the Nth stage gate driving circuit and control the N+1th stage gate driving circuit to output a scan signal; or The N+1th gate driving circuit is turned off, and the Nth gate driving circuit is controlled to output a scanning signal.
13. The method according to claim 12, characterized in that The controlling the N+1th stage gate driving circuit to output a scanning signal comprises: After the N+1-level gate driving circuit outputs the N+1-level scanning signal, the N+3-level gate driving circuit outputs the N+3-level scanning signal after a delay of a third time; wherein the third time is the charging time of a row of pixels.
14. The method according to claim 12, characterized in that The controlling the N-th stage gate driving circuit to output a scanning signal comprises: After the N-th stage gate driving circuit outputs the N-th stage scanning signal, outputting the N+2-th stage scanning signal through the N+2-th stage gate driving circuit after a fourth time delay; The fourth time is the charging time of a row of pixels.