Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. According to the display panel, an invalid structure is arranged in a second sub-region, and / or a display pixel comprises a pixel driving circuit, and the width-to-length ratio of a transistor in the pixel driving circuit in the second sub-region is different from the width-to-length ratio of a corresponding transistor in the pixel driving circuit in a first sub-region; therefore, the electrical property of the transistor of the pixel driving circuit in the second sub-region is close to or even the same as that of the corresponding transistor in the pixel driving circuit in the first sub-region, the display effect of the display panel is improved, and the yield of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Micro-LED (Micro Light Emitting Diode) refers to a light-emitting diode device with a distance between pixels of micrometer level. Micro-LED display devices are widely used due to their advantages such as self-luminescence, small size, wide color gamut, high brightness, high contrast, high resolution and color saturation, long life, low operating voltage, high luminous efficiency, fast response speed, stable and reliable performance, wide operating temperature range, and low power consumption. And with the development of display devices, in order to increase the screen-to-body ratio, the frame will be reduced and the gate drive circuit will be set in the display area. However, in actual use, it is found that since the gate drive circuit is set in the display area, and the pattern of the gate drive circuit is different from the pattern of the pixel circuit, the pattern of the pixel circuit in the gate drive circuit setting area is different from the pattern of the pixel circuit in other display areas, which in turn causes the electrical properties of the transistors of the pixel circuit in the gate drive circuit setting area to be different from the electrical properties of the transistors of the pixel circuit in other display areas, resulting in poor display when displayed.

[0003] Therefore, current display devices have a technical problem in which the electrical properties of transistors in pixel circuits in an area where a gate driving circuit is provided are different from those of transistors in pixel circuits in other display areas, resulting in poor display. Summary of the Invention

[0004] The embodiments of the present application provide a display panel and a display device to alleviate the technical problem in current display devices where the electrical properties of transistors in pixel circuits in a gate drive circuit setting area are different from those of transistors in pixel circuits in other display areas, resulting in poor display.

[0005] To achieve the above objective, according to a first aspect of the present application, a display panel is provided, comprising a display area, the display area comprising a plurality of first sub-areas and at least one second sub-area, the second sub-area being arranged between adjacent first sub-areas, and both the first sub-area and the second sub-area being provided with display pixels;

[0006] Wherein, a gate driving circuit and an invalid structure are further provided in the second sub-area, and the invalid structure and the gate driving circuit are arranged in a non-overlapping manner;

[0007] And / or, the display pixel includes a pixel driving circuit, and the width-to-length ratio of transistors in the pixel driving circuit in the second sub-area is different from the width-to-length ratio of corresponding transistors in the pixel driving circuit in the first sub-area.

[0008] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0009] An embodiment of the present application provides a display panel and a display device; the display panel has an invalid structure in the second sub-area, and / or the display pixels include a pixel driving circuit, and the width-to-length ratio of the transistors in the pixel driving circuit in the second sub-area is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit in the first sub-area, so that the electrical properties of the transistors in the pixel driving circuit in the second sub-area are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit in the first sub-area, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0010] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0012] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0013] Figure 1 A schematic diagram of a comparative display device provided in an embodiment of the present application.

[0014] Figure 2 A schematic diagram of another comparative display device provided in an embodiment of the present application.

[0015] Figure 3 for Figure 2 Schematic diagram of the gate drive circuit setting area 102 of the comparative display device in FIG.

[0016] Figure 4 A schematic plan view of a display panel provided in an embodiment of the present application.

[0017] Figure 5 for Figure 4 Schematic diagram of the specific structure of each area of the display panel.

[0018] Figure 6 for Figure 4 Schematic diagram of the specific structure of the second sub-area of the display panel.

[0019] Figure 7 for Figure 6 A first schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel.

[0020] Figure 8 for Figure 6 A second schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel.

[0021] Figure 9 for Figure 8 A cross-sectional schematic diagram of at least a portion of the second sub-region of the display panel in FIG.

[0022] Figure 10 for Figure 6 A third schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel.

[0023] Figure 11 for Figure 10 A cross-sectional schematic diagram of at least a portion of the second sub-region of the display panel in FIG.

[0024] Figure 12 for Figure 6 A fourth schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel.

[0025] Figure 13 for Figure 12 A cross-sectional schematic diagram of at least a portion of the second sub-region of the display panel in FIG.

[0026] Figure 14 for Figure 6 A fifth schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel.

[0027] Reference numerals:

[0028] 101-display area; 102-gate drive circuit setting area; 111-pixel circuit; 112-gate circuit; 2-display panel; 20-display area; 201-first sub-area; 202-second sub-area; 202a-partition; 21-display pixel; 211-pixel drive circuit; 22-gate drive circuit; 221-gate drive unit; 23-invalid structure; 24-invalid pixel; 25-transistor; 32-invalid hole; 33-invalid routing; 411-substrate; 412-buffer layer; 413-active layer; 413a-active pattern; 414-gate insulating layer; 415-gate layer; 415a-gate; 416-interlayer insulating layer; 417-light-shielding layer; 417a-light-shielding pattern; 418-source and drain layer. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] In order to illustrate the principle of the technical problem of the embodiment of the present application, some comparative display devices are provided. It is understandable that these comparative display devices cannot be used as the prior art in the embodiment of the present application. Figure 1 As shown, some comparative display devices include a display area 101 and a non-display area, the non-display area includes a gate drive circuit setting area 102, a pixel circuit is set in the display area 101, and a gate circuit is set in the gate drive circuit setting area 102, so as to achieve normal operation of the comparative display device. Since the pixel circuits in the display area are equidistant and can be repeatedly set continuously, display abnormalities will not be caused by different patterns of the pixel circuits.

[0031] In order to reduce the frame, some comparative display devices may set the gate drive circuit setting area 102 within the display area 101, such as Figure 2 As shown in FIG. 1 , it can be seen that the gate drive circuit setting area 102 is located between the multiple display areas 101. In addition to the gate circuit, the gate drive circuit setting area 102 also includes pixel circuits and pixels to achieve full-screen display and increase the screen-to-body ratio. However, in actual use, Figure 3 As shown, it was found that the pattern of the gate circuit 112 was different from the pattern of the pixel circuit 111, causing the pattern of the pixel circuit 111 located in the gate driver circuit setting area 102 to be different from the pattern of the pixel circuit located in the display area 101. As a result, the electrical properties of the transistors in the pixel circuit 111 in the gate driver circuit setting area 102 were different from the electrical properties of the transistors in the pixel circuit located in the display area 101, resulting in display abnormalities during display. Therefore, current display devices have a technical problem in which the electrical properties of the transistors in the pixel circuit in the gate driver circuit setting area are different from the electrical properties of the transistors in the pixel circuit in other display areas, resulting in poor display.

[0032] In response to the above technical problems, embodiments of the present application provide a display panel and a display device to alleviate the above technical problems.

[0033] Figure 4 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 5 for Figure 4 Schematic diagram of the specific structure of each area of the display panel. Figure 6 for Figure 4Schematic diagram of the specific structure of the second sub-area of the display panel. Figure 7 for Figure 6 A first schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel. Figure 8 for Figure 6 A second schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel. Figure 9 for Figure 8 A cross-sectional schematic diagram of at least a portion of the second sub-region of the display panel in FIG. Figure 10 for Figure 6 A third schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel. Figure 11 for Figure 10 A cross-sectional schematic diagram of at least a portion of the second sub-region of the display panel in FIG. Figure 12 for Figure 6 A fourth schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel. Figure 13 for Figure 12 A cross-sectional schematic diagram of at least a portion of the second sub-region of the display panel in FIG. Figure 14 for Figure 6 A fifth schematic diagram of the specific structure of at least a portion of the second sub-region of the display panel.

[0034] like Figures 4 to 14 As shown, an embodiment of the present application provides a display panel, which includes a display area 20, multiple first sub-areas 201 and at least one second sub-area 202, wherein the second sub-area 202 is arranged between adjacent first sub-areas 201, and the first sub-area 201 and the second sub-area 202 are both provided with display pixels 21.

[0035] In some embodiments, the second sub-area 202 is provided with an invalid structure 23; and / or the display pixel 21 includes a pixel driving circuit 211, and the width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-area 202 is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201.

[0036] In some embodiments, a gate driving circuit 22 and an invalid structure 23 are further provided in the second sub-area 202, and the invalid structure 23 is arranged non-overlappingly with the gate driving circuit 22; and / or, the display pixel 21 includes a pixel driving circuit 211, and the width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-area 202 is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201; and / or, the display pixel includes a pixel driving circuit, and the width-to-length ratio of the transistors in the pixel driving circuit in the second sub-area is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit in the first sub-area.

[0037] An embodiment of the present application provides a display panel, wherein the display panel 2 is provided with an invalid structure in the second sub-region 202, and / or the display pixel 21 includes a pixel driving circuit 211, and the width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-region 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0038] Specifically, such as Figure 4 As shown, it can be seen that the display panel 2 includes multiple first sub-areas 201 and two second sub-areas 202 , but the embodiment of the present application is not limited thereto, and the display panel 2 may include only one second sub-area 202 .

[0039] Specifically, such as Figure 4 As shown, Figure 4 It is shown that the display panel 2 only includes the first sub-area 201 and the second sub-area 202, but the embodiments of the present application are not limited to this. Taking into account factors such as process limitations, the display panel 2 may have a certain non-display area. The non-display area can be set on one side edge or more sides (for example, four sides) of the display panel. The non-display area can be set on the back side of the display panel in a curved manner.

[0040] Specifically, such as Figure 4 As shown, the second sub-region 202 may include a plurality of partitions 202 a , and a gate driving circuit 22 or a display pixel 21 or other structures may be disposed in each partition 202 a . Figure 4 Each second sub-area 202 is provided with four sub-areas 202a. Figure 5 Each second sub-area 202 is provided with two sub-areas 202a. Figure 6In the description, eight partitions 202a are provided in each second sub-area 202 as an example. It can be understood that the number of partitions can be divided differently according to the number of display pixels, gate driving circuits and other structures provided.

[0041] Specifically, such as Figure 5 As shown, the second sub-area 202 is provided with a display pixel 21, so that the second sub-area 202 can also display, that is, in the embodiment of the present application, the area where the gate drive circuit 22 is provided can also display, and for the convenience of explaining the design in the embodiment of the present application, the area with the display pixel 21 and the gate drive circuit 22 is defined as the second sub-area, and the area with only the display pixel 21 but no gate drive circuit 22 is defined as the first sub-area.

[0042] Specifically, the display pixel 21 refers to a pixel unit capable of realizing a display function, which has a normal light-emitting film layer or a light-emitting unit and a corresponding driving circuit.

[0043] Specifically, an invalid structure refers to a structure that does not implement normal functions, including normal driving functions, normal connection functions, normal conduction functions, etc. For example, the display panel 2 has a source and drain layer. The source and drain layer needs to pass through the via hole of the interlayer insulating layer to connect to the active hole to realize the normal function of the transistor. If the via hole in the interlayer insulating layer does not function as a connection hole between the source and drain layer and the active layer, or if the via hole in the interlayer insulating layer is a connection hole between the source and drain layer and the active layer, but the transistor does not work, the via hole can be regarded as an invalid hole, that is, the via hole is an invalid structure.

[0044] Specifically, the aspect ratio of a transistor means that the transistor has a channel width and a channel length, and the ratio of the channel width of the transistor to the channel length of the transistor is the aspect ratio of the transistor.

[0045] Specifically, the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201 are transistors having the same function and the same connection relationship as the transistors in the pixel driving circuit 211 in the second sub-area 202. For example, the pixel driving circuit 211 includes a switching transistor. When the transistors in the pixel driving circuit 211 in the second sub-area 202 are switching transistors, the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201 are also switching transistors. Accordingly, for example, the width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-area 202 is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201 means that the width-to-length ratio of the switching transistors in the pixel driving circuit 211 in the second sub-area 202 is greater than or less than the width-to-length ratio of the switching transistors in the pixel driving circuit 211 in the first sub-area 201.

[0046] Specifically, a gate driving circuit and an invalid structure are further provided in the second sub-area, and the invalid structure is arranged non-overlappingly with the gate driving circuit; and / or the display pixel includes a pixel driving circuit, and the width-to-length ratio of the transistors in the pixel driving circuit in the second sub-area is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit in the first sub-area, which means: a gate driving circuit and an invalid structure are further provided in the second sub-area, and the invalid structure is arranged non-overlappingly with the gate driving circuit; or, the display pixel includes a pixel driving circuit, and the width-to-length ratio of the transistors in the pixel driving circuit in the second sub-area is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit in the first sub-area; or, a gate driving circuit and an invalid structure are further provided in the second sub-area, and the invalid structure is arranged non-overlappingly with the gate driving circuit, and the display pixel includes a pixel driving circuit, and the width-to-length ratio of the transistors in the pixel driving circuit in the second sub-area is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit in the first sub-area.

[0047] Specifically, such as Figure 5 As shown, multiple rows and columns of display pixels 21 are provided in the first sub-area 201, and at least one column of display pixels 21 and at least one column of gate driving circuits 22 are provided in the second sub-area 202. Then, the structure of the pixel driving circuit 211 in the display pixel 21 in the first sub-area 201 is different from the structure of the pixel driving circuit 211 in the second sub-area 202. Then, by differentiating the patterns in the second sub-area 202 and the first sub-area 201, the electrical properties of the pixel driving circuit 211 in the first sub-area 201 and the electrical properties of the pixel driving circuit 211 in the second sub-area 202 can be reduced, thereby improving the display effect of the display panel and improving the yield of the display panel. Specifically, this can be achieved by differentiating the patterns of the pixel driving circuit 211 in the second sub-area 202 and the patterns of the pixel driving circuit 211 in the first sub-area 201.

[0048] Specifically, such as Figure 6 As shown, taking the gate driving circuit 22 including four types of gate driving units 221 as an example, the various types of gate driving units 221 are interlaced with the display pixels 21, but the embodiments of the present application are not limited thereto. The gate driving circuit 22 may include fewer types of gate driving units 221 or more types of gate driving units 221. For example, the gate driving circuit 22 may include only one type of gate driving unit 221, or the gate driving circuit 22 may include five types of gate driving units 221. When the gate driving circuit 22 includes four types of gate driving units 221, the four types of gate driving units 221 may be two-level pulse amplitude modulation gate driving units and two-level pulse width modulation gate driving units.

[0049] Specifically, the gate driving circuit 22 may be an 8T2C (8 transistors, two capacitors) circuit, and the pixel driving circuit 211 may be a 13T2C circuit, but the embodiment of the present application is not limited thereto.

[0050] In some embodiments, as Figure 8 As shown, the ineffective structure 23 includes an ineffective hole 32, and a plurality of ineffective holes 32 are provided in the second sub-region 202. By providing a plurality of ineffective holes, the hole density in the second sub-region 202 is made similar to or even the same as the hole density in the first sub-region, so that the electrical properties of the transistors in the pixel driving circuit in the second sub-region 202 are similar to or even the same as those in the pixel driving circuit in the first sub-region, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0051] Specifically, when providing the ineffective hole, the ineffective hole may be provided in the pixel driving circuit, in the gate driving circuit, or between the pixel driving circuit and the gate driving circuit.

[0052] Specifically, by providing the inactive holes, the pattern area of the transistors in the pixel driving circuit in the second sub-area 202 can be similar to or even the same as the pattern area of the transistors in the pixel driving circuit.

[0053] Specifically, by setting invalid holes, the hole density in the pixel driving circuit in the second sub-area 202 can be close to or even equal to the hole density in the pixel driving circuit in the first sub-area 201; or the hole density in the second sub-area 202 can be close to or even equal to the hole density in the pixel driving circuit in the first sub-area 201 of the same area.

[0054] In some embodiments, as Figure 9 As shown, the display panel 2 includes a substrate 411, an active layer 413, a gate insulating layer 414, and an interlayer insulating layer 416. The active layer 413 is disposed on one side of the substrate 411, the gate insulating layer 414 is disposed on a side of the active layer 413 away from the substrate 411, and the interlayer insulating layer 416 is disposed on a side of the gate insulating layer 414 away from the active layer 413. The ineffective hole 32 passes through the gate insulating layer 414 and the interlayer insulating layer 416. By allowing the ineffective hole 32 to pass through the gate insulating layer 414 and the interlayer insulating layer 416, the ineffective hole 32 can affect the electrical properties of the transistors in the second sub-region 202, so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-region 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, thereby improving the display effect and the yield of the display panel.

[0055] Specifically, Figure 9 In the description, the display panel has only one active layer 413 as an example, but the embodiments of the present application are not limited to this. When the display panel has two active layers, the materials of the two active layers can be different. Accordingly, the invalid hole 32 can be a hole passing through other film layers, which can be the hole required for connecting the source and drain layers with the active layer.

[0056] In some embodiments, as Figure 10 、 Figure 11 As shown, the invalid structure 23 includes an invalid routing line 33, and a plurality of invalid routing lines 33 are provided in the second sub-area 202. By making the invalid structure 23 include the invalid routing lines 33 and providing a plurality of invalid routing lines 33 in the second sub-area 202, the line density in the second sub-area 202 is made similar to or even the same as the line density in the first sub-area, thereby making the electrical properties of the transistors in the pixel driving circuit in the second sub-area 202 similar to or even the same as those in the pixel driving circuit in the first sub-area, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0057] Specifically, when setting the invalid wiring, the invalid wiring can be set in the pixel driving circuit, or in the gate driving circuit, or between the pixel driving circuit and the gate driving circuit.

[0058] Specifically, by providing the invalid wiring, the pattern area of the transistors in the pixel driving circuit in the second sub-area 202 can be similar to or even the same as the pattern area of the transistors in the pixel driving circuit.

[0059] Specifically, by setting invalid routing lines, the line density in the pixel driving circuit in the second sub-area 202 can be made close to or even equal to the line density in the pixel driving circuit in the first sub-area 201; or the line density in the second sub-area 202 can be made close to or even equal to the line density in the pixel driving circuit in the first sub-area 201 of the same area.

[0060] In some embodiments, as Figure 11 As shown, the display panel 2 includes a gate layer 415, the gate layer 415 includes a gate 415a, and the inactive wiring 33 is disposed on the gate layer 415. By disposing the inactive wiring 33 on the gate layer 415, the inactive wiring 33 can affect the electrical properties of the transistors in the second sub-region 202, so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-region 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0061] Specifically, Figure 11The example in which the display panel has only one gate layer 415 is used for explanation, but the embodiments of the present application are not limited thereto. When the display panel has two or more gate layers 415 , the invalid wiring 33 can be set in multiple gate layers 415 accordingly.

[0062] In some embodiments, as Figure 14 As shown, the invalid structure 23 further includes an invalid pixel 24. The second sub-area 202 is provided with a gate driving unit 221, and the invalid pixel 24 is disposed between the gate driving unit 221 and the display pixel 21. By disposing the invalid pixel 24 so that the invalid pixel 24 is located between the gate driving unit 221 and the display pixel 21, the pattern of the pixel driving circuit 211 of the display pixel 21 in the second sub-area 202 can be maintained continuous, so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-area 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0063] Specifically, for the structure of invalid pixels, the invalid pixels may have a complete pixel driving circuit, but no light-emitting unit or light-emitting film layer is provided, so that the invalid pixels do not display; or the invalid pixels remove the electrodes connected to the light-emitting unit or the light-emitting film layer, and retain other structures in the pixel driving circuit, so that the invalid pixels do not display.

[0064] In some embodiments, as Figure 7 As shown, the display pixel 21 includes a pixel driving circuit 211. The active pattern of the transistors in the pixel driving circuit 211 is low-temperature polysilicon. The width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 is smaller than the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201. By making the width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 smaller than the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-region 202 are close to or even the same as those in the pixel driving circuit 211 in the first sub-region 201, thereby improving the display effect of the display panel and increasing the yield of the display panel.

[0065] Specifically, the aspect ratio of a transistor refers to the ratio of the channel width to the channel length of the transistor.

[0066] Specifically, when the active pattern of the transistor in the pixel driving circuit 211 is low-temperature polysilicon, the threshold voltage of the transistor will be positively biased. Then, by increasing the channel length of the transistor and reducing the width-to-length ratio of the transistor, the electrical properties of the transistor can be made close to or even the same as the electrical properties of the corresponding transistor in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0067] In some embodiments, as Figure 7 As shown, the display pixel 21 includes a pixel driving circuit 211. The active pattern of the transistors in the pixel driving circuit 211 is low-temperature polysilicon. The width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 is greater than the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201. By making the width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 greater than the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-region 202 are close to or even the same as those in the pixel driving circuit 211 in the first sub-region 201, thereby improving the display effect of the display panel and increasing the yield of the display panel.

[0068] Specifically, when the active pattern of the transistor in the pixel driving circuit 211 is low-temperature polysilicon, the threshold voltage of the transistor will be positively biased. Then, by increasing the channel width of the transistor and increasing the aspect ratio of the transistor, the electrical properties of the transistor can be made close to or even the same as the electrical properties of the corresponding transistor in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0069] Specifically, the electrical data of the transistors in the pixel driving circuit 211 in the second sub-area 202 of the comparison display device and the electrical data of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201 can be obtained, and the difference between the electrical data of the transistors in the pixel driving circuit 211 in the second sub-area 202 and the electrical data of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201 can be calculated. The design value can be reversed by the width-to-length ratio to perform differential compensation, so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-area 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201.

[0070] In some embodiments, as Figure 7As shown, the display pixel 21 includes a pixel driving circuit 211. The active pattern of the transistors in the pixel driving circuit 211 is a metal oxide semiconductor. The width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 is greater than the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201. By making the width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 greater than the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-region 202 are close to or even the same as those of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, thereby improving the display effect of the display panel and increasing the yield of the display panel.

[0071] Specifically, when the active pattern of the transistor in the pixel driving circuit 211 is a metal oxide, the threshold voltage of the transistor will be negatively biased. Then, by increasing the channel width of the transistor and increasing the aspect ratio of the transistor, the electrical properties of the transistor can be made close to or even the same as the electrical properties of the corresponding transistor in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0072] In some embodiments, as Figure 7 As shown, the display pixel 21 includes a pixel driving circuit 211. The active pattern of the transistors in the pixel driving circuit 211 is a metal oxide semiconductor. The width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 is smaller than the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201. By making the width-to-length ratio of the transistors in the pixel driving circuit 211 in the second sub-region 202 smaller than the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-region 202 are close to or even the same as those of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, thereby improving the display effect of the display panel and increasing the yield of the display panel.

[0073] Specifically, when the active pattern of the transistor in the pixel driving circuit 211 is a metal oxide, the threshold voltage of the transistor will be negatively biased. Then, by increasing the channel length of the transistor and reducing the width-to-length ratio of the transistor, the electrical properties of the transistor can be made close to or even the same as the electrical properties of the corresponding transistor in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0074] In some embodiments, as Figure 7As shown, the display pixel 21 includes a pixel driving circuit 211, and the active pattern of some transistors in the pixel driving circuit 211 is low-temperature polysilicon, and the active pattern of some transistors in the pixel driving circuit 211 is metal oxide semiconductor; wherein, in the second sub-area 202, the width-to-length ratio of the transistors whose active pattern is low-temperature polysilicon in the pixel driving circuit 211 is smaller than the width-to-length ratio of the corresponding transistors whose active pattern is low-temperature polysilicon in the first sub-area 201; in the second sub-area 202, the width-to-length ratio of the transistors whose active pattern is metal oxide semiconductor in the pixel driving circuit 211 is larger than the width-to-length ratio of the corresponding transistors whose active pattern is metal oxide semiconductor in the pixel driving circuit 211 in the first sub-area 201; so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-area 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0075] Specifically, for the transistors in the pixel driving circuit 211 whose active pattern is low-temperature polysilicon, the threshold voltage of the transistor is easily forward biased. Then, by increasing the channel length of the transistor and reducing the width-to-length ratio of the transistor, the electrical properties of the transistor can be made close to or even the same as the electrical properties of the corresponding transistor in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0076] Specifically, for the transistors in the pixel driving circuit 211 whose active pattern is a metal oxide, the threshold voltage of the transistor is easily negatively biased. Then, by increasing the channel width of the transistor and increasing the aspect ratio of the transistor, the electrical properties of the transistor can be made close to or even the same as the electrical properties of the corresponding transistor in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0077] In some embodiments, as Figure 7As shown, the display pixel 21 includes a pixel driving circuit 211, and the active pattern of some transistors in the pixel driving circuit 211 is low-temperature polysilicon, and the active pattern of some transistors in the pixel driving circuit 211 is metal oxide semiconductor; wherein, in the second sub-area 202, the width-to-length ratio of the transistors whose active pattern is low-temperature polysilicon in the pixel driving circuit 211 is greater than the width-to-length ratio of the corresponding transistors whose active pattern is low-temperature polysilicon in the first sub-area 201; in the second sub-area 202, the width-to-length ratio of the transistors whose active pattern is metal oxide semiconductor in the pixel driving circuit 211 is less than the width-to-length ratio of the transistors whose active pattern is metal oxide semiconductor in the pixel driving circuit 211 in the first sub-area 201; so that the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the second sub-area 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0078] Specifically, for the transistors in the pixel driving circuit 211 whose active pattern is low-temperature polysilicon, the threshold voltage of the transistor is easily forward biased. Then, by increasing the channel width of the transistor and increasing the aspect ratio of the transistor, the electrical properties of the transistor can be made close to or even the same as the electrical properties of the corresponding transistor in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0079] Specifically, for the transistors in the pixel driving circuit 211 whose active pattern is a metal oxide, the threshold voltage of the transistor is easily negatively biased. Then, by increasing the channel length of the transistor and reducing the width-to-length ratio of the transistor, the electrical properties of the transistor can be made close to or even the same as the electrical properties of the corresponding transistor in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0080] Specifically, such as Figure 7 As shown, Figure 7 In the figure, the reference numeral 311 represents a display pixel in which the width-to-length ratio of the transistors of the pixel driving circuit in the second sub-region 202 is the same as the width-to-length ratio of the transistors of the pixel driving circuit in the first sub-region 201, and the reference numeral 312 represents a display pixel in which the width-to-length ratio of the transistors of the pixel driving circuit in the second sub-region 202 is different from the width-to-length ratio of the transistors of the pixel driving circuit in the first sub-region 201.

[0081] Specifically, Figure 7In the description, an example is given in which the width-to-length ratio of the transistors of the pixel driving circuit in a column of display pixels adjacent to the gate driving unit 221 is different from the width-to-length ratio of the transistors of the pixel driving circuit in the first sub-area. However, the embodiments of the present application are not limited thereto. The width-to-length ratio of the transistors of the pixel driving circuit in multiple columns of display pixels adjacent to the gate driving unit 221 may be different from the width-to-length ratio of the transistors of the pixel driving circuit in the first sub-area.

[0082] In some embodiments, as Figure 12 、 Figure 13 As shown, the display pixel 21 includes a pixel driving circuit 211, and at least the active pattern of the transistor in the pixel driving circuit 211 is low-temperature polysilicon. The display panel 2 includes a light shielding layer 417, an active layer 413, and a gate layer 415 arranged in sequence. The light shielding layer 417 includes a light shielding pattern 417a, the active layer 413 includes an active pattern 413a, and the gate layer 415 includes a gate 415a.

[0083] In the second sub-area 202, the active pattern of at least part of the transistors in the pixel driving circuit 211 is arranged opposite to the light shielding pattern 417a and the gate 415a (see Figure 13 ), in the first sub-area 201, the active pattern 413a of the transistor in the pixel driving circuit 211 is arranged opposite to the gate 415a (see Figure 9 and Figure 11 By providing the light shielding pattern 417a so that the light shielding pattern corresponds to the active pattern of at least part of the transistors in the pixel driving circuit in the second sub-region 202, the light shielding pattern can improve the electrical properties of the transistors in the pixel driving circuit, so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-region 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-region 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0084] Specifically, the transistors in the pixel driving circuit may be only low-temperature polysilicon thin film transistors, or may include low-temperature polysilicon thin film transistors and metal oxide thin film transistors. When the transistors in the pixel driving circuit are all low-temperature polysilicon thin film transistors, the active patterns of some low-temperature polysilicon thin film transistors or all low-temperature polysilicon thin film transistors can be set corresponding to the shading pattern; when the transistors in the pixel driving circuit include low-temperature polysilicon thin film transistors and metal oxide thin film transistors, the active patterns of some low-temperature polysilicon thin film transistors or all low-temperature polysilicon thin film transistors can be set corresponding to the shading pattern.

[0085] Specifically, an electrical signal can be input into the shading pattern. Specifically, by determining the influence of the shading pattern on the electrical properties of the transistor, for example, the influence of the voltage input into the shading pattern on the electrical properties of the transistor is a linear relationship, then the voltage on the shading pattern can be reversely calculated based on the difference between the electrical properties of the transistors in the first sub-area and the electrical properties of the transistors in the pixel driving circuit of the second sub-area, so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-area 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201.

[0086] Specifically, such as Figure 12 As shown, Figure 12 Reference numeral 313 denotes a display pixel in which the transistors of the pixel driving circuit in the second sub-area 202 are not provided with a light-shielding pattern, and reference numeral 314 denotes a display pixel in which the transistors of the pixel driving circuit in the second sub-area 202 are provided with a light-shielding pattern.

[0087] Specifically, Figure 12 In the description, the transistors of the pixel driving circuit in a column of display pixels adjacent to the gate driving unit 221 are provided with a shading pattern as an example, but the embodiments of the present application are not limited to this. The transistors of the pixel driving circuit in multiple columns of display pixels adjacent to the gate driving unit 221 can be provided with a shading pattern.

[0088] In some embodiments, as Figures 4 to 14 As shown, the second sub-area 202 is provided with multiple types of gate driving units 221 , and the multiple types of gate driving units 221 are arranged alternately with multiple columns of display pixels 21 ;

[0089] The inactive structure 23 is disposed between the gate driving unit 221 and the display pixel 21;

[0090] And / or, the display pixel 21 includes a pixel driving circuit 211, and in one or more columns of the display pixels 21 arranged adjacent to the gate driving unit 221, the width-to-length ratio of the transistors in the pixel driving circuit 211 is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201.

[0091] Specifically, when setting the invalid structure 23, an invalid structure can be provided between each type of gate driving unit 221 and the display pixel 21, so that the electrical properties of the transistors of the pixel driving circuit 211 in the second sub-area 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0092] Specifically, the invalid structure may be provided in the pixel driving circuit, or in the gate driving circuit, or between the pixel driving circuit and the gate driving circuit.

[0093] Specifically, when changing the width-to-length ratio of the transistors in the pixel driving circuit of the second sub-area, the width-to-length ratio of the transistors in the pixel driving circuit of one or more columns of the display pixels 21 arranged adjacent to the gate driving unit 221 can be changed, so that the electrical properties of the transistors in the pixel driving circuit 211 in the second sub-area 202 are close to or even the same as the electrical properties of the corresponding transistors in the pixel driving circuit 211 in the first sub-area 201, thereby improving the display effect of the display panel and improving the yield of the display panel.

[0094] Specifically, such as Figure 9 As shown, the display panel 2 may include a substrate 411 , a buffer layer 412 , an active layer 413 , a gate insulating layer 414 , a gate layer 415 , an interlayer insulating layer 416 and a source / drain electrode layer 418 , which are sequentially arranged.

[0095] Specifically, such as Figure 9 As shown, the display panel 2 includes a transistor 25 , but the embodiment of the present application does not limit the structure of the transistor, and the structure of the transistor can be other structures.

[0096] Specifically, the transistor in the display panel may be one of a low-temperature polysilicon thin film transistor, a metal oxide thin film transistor, and a low-temperature polycrystalline oxide thin film transistor.

[0097] Specifically, the display panel includes one of a micro light emitting diode display panel and an organic light emitting diode display panel.

[0098] At the same time, an embodiment of the present application provides a display device, which includes the display panel as described in any of the above embodiments.

[0099] Specifically, the display device may further include a chip for driving the display panel, a control board, a power supply and other structures.

[0100] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0101] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0102] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0103] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The display area includes a plurality of first sub-areas and at least one second sub-area, wherein the second sub-area is arranged between adjacent first sub-areas, and the first sub-areas and the second sub-area are both provided with display pixels; Wherein, a gate driving circuit and an invalid structure are further provided in the second sub-area, and the invalid structure and the gate driving circuit are arranged in a non-overlapping manner; And / or, the display pixel includes a pixel driving circuit, and the width-to-length ratio of transistors in the pixel driving circuit in the second sub-area is different from the width-to-length ratio of corresponding transistors in the pixel driving circuit in the first sub-area.

2. The display panel according to claim 1, wherein: The invalid structure includes invalid holes, and a plurality of invalid holes are provided in the second sub-area.

3. The display panel according to claim 2, wherein: The display panel includes: substrate; An active layer is provided on one side of the substrate; a gate insulating layer, disposed on a side of the active layer away from the substrate; an interlayer insulating layer, disposed on a side of the gate insulating layer away from the active layer; The ineffective hole passes through the gate insulating layer and the interlayer insulating layer.

4. The display panel according to claim 1, wherein: The invalid structure includes invalid wiring, and a plurality of invalid wirings are provided in the second sub-area.

5. The display panel according to claim 4, wherein: The display panel includes a gate layer, the gate layer includes a gate, and the invalid wiring is arranged on the gate layer.

6. The display panel according to claim 1, wherein: The invalid structure further includes an invalid pixel. The second sub-area is provided with a gate driving unit. The invalid pixel is arranged between the gate driving unit and the display pixel.

7. The display panel according to claim 1, wherein: The display pixel includes a pixel driving circuit, an active pattern of a transistor in the pixel driving circuit is low-temperature polysilicon, and a width-to-length ratio of the transistor in the pixel driving circuit in the second sub-area is smaller than a width-to-length ratio of the corresponding transistor in the pixel driving circuit in the first sub-area.

8. The display panel according to claim 1, wherein: The display pixel includes a pixel driving circuit, an active pattern of a transistor in the pixel driving circuit is a metal oxide semiconductor, and a width-to-length ratio of the transistor in the pixel driving circuit in the second sub-area is greater than a width-to-length ratio of a corresponding transistor in the pixel driving circuit in the first sub-area.

9. The display panel according to claim 1, wherein: The display pixel includes a pixel driving circuit, the active pattern of some transistors in the pixel driving circuit is low-temperature polysilicon, and the active pattern of some transistors in the pixel driving circuit is metal oxide semiconductor; Among them, in the second sub-area, the width-to-length ratio of the transistor whose active pattern in the pixel driving circuit is low-temperature polysilicon is smaller than the width-to-length ratio of the corresponding transistor whose active pattern in the pixel driving circuit is low-temperature polysilicon in the first sub-area; in the second sub-area, the width-to-length ratio of the transistor whose active pattern in the pixel driving circuit is metal oxide semiconductor is greater than the width-to-length ratio of the corresponding transistor whose active pattern in the pixel driving circuit is metal oxide semiconductor in the first sub-area.

10. The display panel according to claim 1, wherein The display pixel includes a pixel driving circuit, wherein active patterns of at least some transistors in the pixel driving circuit are low-temperature polysilicon, and the display panel includes a light shielding layer, an active layer, and a gate layer arranged in sequence, wherein the light shielding layer includes a light shielding pattern, the active layer includes an active pattern, and the gate layer includes a gate; In the second sub-area, the active pattern of at least part of the transistors in the pixel driving circuit is arranged opposite to the shading pattern and the gate, and in the first sub-area, the active pattern of the transistors in the pixel driving circuit is arranged opposite to the gate.

11. The display panel according to any one of claims 1 to 10, characterized in that: The second sub-area is provided with multiple types of gate driving units, and the multiple types of gate driving units are arranged alternately with multiple columns of display pixels; Wherein, the invalid structure is arranged between the gate driving unit and the display pixel; And / or, the display pixel includes a pixel driving circuit, and in one or more columns of display pixels arranged adjacent to the gate driving unit, the width-to-length ratio of the transistors in the pixel driving circuit is different from the width-to-length ratio of the corresponding transistors in the pixel driving circuit in the first sub-area.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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