Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate body and a plurality of sub-pixels arranged on the substrate body, and the sub-pixels are distributed in an array mode. The sub-pixel comprises a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit comprises a driving sub-circuit and a light-emitting control sub-circuit which are coupled with each other; the light-emitting element comprises an anode pattern; the plurality of sub-pixels are divided into a plurality of groups of sub-pixels, each group of sub-pixels comprises two sub-pixels arranged along a first direction, and two sub-pixel driving circuits included in the two sub-pixels multiplex the same light-emitting control sub-circuit. The light-emitting control sub-circuit is used for respectively controlling the driving sub-circuits in the two sub-pixels to write driving signals into the anode pattern; the sub-pixel further includes a data line including a portion extending in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a divisional application of the Chinese patent application with the application date of July 9, 2021, application number 202180001839.5, and invention name “Display Substrate and Display Device”. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] With the continuous development of display technology, organic light-emitting diode (OLED) display products are widely used due to their advantages such as high brightness, low power consumption, fast response, high clarity, good flexibility, and high luminous efficiency. As the OLED display product market gradually opens up, the demand for OLED special-shaped display products is also growing. Summary of the Invention

[0005] An object of the present disclosure is to provide a display substrate and a display device.

[0006] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0007] A first aspect of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels being distributed in an array;

[0008] The sub-pixel includes a sub-pixel driving circuit and a light-emitting element, wherein the sub-pixel driving circuit includes a driving sub-circuit and a light-emitting control sub-circuit coupled to each other; the light-emitting element includes an anode pattern;

[0009] The plurality of sub-pixels are divided into a plurality of groups of sub-pixels, each group of sub-pixels includes two sub-pixels arranged along a first direction, the two sub-pixel driving circuits included in the two sub-pixels reuse the same light emitting control sub-circuit, and the light emitting control sub-circuit is used to respectively control the driving sub-circuits in the two sub-pixels to write driving signals to the anode pattern;

[0010] The sub-pixel further includes a data line, and the data line includes a portion extending along the first direction.

[0011] Optionally, the sub-pixel further includes:

[0012] a light-emitting control signal line, the light-emitting control signal line including a portion extending along a second direction, the second direction intersecting the first direction;

[0013] The two sub-pixel driving circuits included in the two sub-pixels reuse the same light-emitting control signal line, and the light-emitting control signal line is coupled to the light-emitting control sub-circuit for controlling the light-emitting control sub-circuit; the orthographic projection of the light-emitting control signal line on the substrate is located between the orthographic projections of the two anode patterns included in the two sub-pixels on the substrate.

[0014] Optionally, the light emitting control subcircuit includes a light emitting control transistor, a gate of the light emitting control transistor is coupled to the light emitting control signal line, and a second electrode of the light emitting control transistor is coupled to the driving subcircuit;

[0015] The light-emitting control transistor includes a light-emitting control active layer, which includes a portion extending along the second direction. The orthographic projection of the light-emitting control active layer on the substrate is located between the orthographic projections of the two anode patterns included in the two sub-pixels on the substrate.

[0016] Optionally, the sub-pixel further includes:

[0017] a power line, the power line including a portion extending along the first direction, the power lines included in the two sub-pixels being coupled;

[0018] The first electrode of the light emitting control transistor is coupled to the power line, and the light emitting control transistor is used to turn on or off the connection between the power line and the driving sub-circuits in the two sub-pixels under the control of the light emitting control signal line.

[0019] Optionally, the sub-pixel further includes:

[0020] A power connection portion, the power connection portion includes a portion extending along the second direction; the two sub-pixel driving circuits included in the two sub-pixels reuse the same power connection portion; along the second direction, the orthographic projection of the power line on the substrate is located on one side of the orthographic projection of the light-emitting control active layer on the substrate, and the first electrode of the light-emitting control transistor is coupled to the power line through the power connection portion.

[0021] Optionally, the power connection portion and the light-emitting control signal line are provided in the same layer and with the same material.

[0022] Optionally, the plurality of sub-pixels are divided into a plurality of pixel units, and the pixel unit includes at least two sub-pixels arranged along the second direction;

[0023] The at least two sub-pixels reuse a same power line, and the power connection parts included in the at least two sub-pixels are coupled in sequence.

[0024] Optionally, the driving sub-circuit includes a driving transistor, a first electrode of the driving transistor is coupled to a second electrode of the light emitting control transistor, and the second electrode of the driving transistor is coupled to an anode pattern of the light emitting element;

[0025] The driving transistor includes a driving active layer; in the two sub-pixel driving circuits, the driving active layers included in the two driving transistors are arranged in an axially symmetrical manner, the symmetry axis extends along the second direction, and the orthographic projection of the symmetry axis on the substrate is located between the orthographic projections of the two anode patterns included in the two sub-pixels on the substrate.

[0026] Optionally, the orthographic projection of the symmetry axis on the substrate overlaps with the orthographic projection of the light-emitting control active layer on the substrate.

[0027] Optionally, the sub-pixel further includes a first scan line, and the first scan line includes a portion extending along the second direction;

[0028] The sub-pixel driving circuit further includes a first transistor, wherein a gate of the first transistor is coupled to the first scan line, a first electrode of the first transistor is coupled to the data line, and a second electrode of the first transistor is coupled to the gate of the driving transistor;

[0029] The first transistor includes a first active layer, and the first active layer includes a portion extending along the second direction; in the same sub-pixel, the first active layer, the driving active layer and the light-emitting control active layer are arranged in sequence along the first direction.

[0030] Optionally, in the two sub-pixel driving circuits, the first active layers included in the two first transistors are symmetrically arranged about the symmetry axis.

[0031] Optionally, the plurality of sub-pixels are divided into a plurality of pixel units, at least some of the pixel units include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along the second direction, the first sub-pixel includes a first data line, the second sub-pixel includes a second data line, and the third sub-pixel includes a third data line;

[0032] In the first portion of pixel units, the first data line is located on a side of the first sub-pixel away from the second sub-pixel along the second direction, the second data line and the third data line are both located between the second sub-pixel and the third sub-pixel; and a first spacing region is defined between the first sub-pixel and the second sub-pixel;

[0033] In the second partial pixel unit, the first data line and the second data line are both located between the first sub-pixel and the second sub-pixel, the third data line is located on a side of the third sub-pixel away from the second sub-pixel along the second direction; and a second spacing area is provided between the second sub-pixel and the third sub-pixel.

[0034] Optionally, the multiple groups of sub-pixels are divided into multiple rows of sub-pixel groups arranged along the first direction, and each row of sub-pixel groups includes multiple groups of sub-pixels arranged along the second direction;

[0035] The display substrate further includes a plurality of gate drive circuit layout areas and a plurality of gate drive wiring layout areas;

[0036] The plurality of gate drive circuit layout areas correspond one-to-one to the plurality of rows of sub-pixel groups, each gate drive circuit layout area comprising a first layout area and a second layout area, wherein along the first direction, the first layout area is located on a first side of a corresponding row of sub-pixel groups, and the second layout area is located on a second side of a corresponding row of sub-pixel groups;

[0037] The plurality of gate drive circuit layout areas correspond one-to-one to the plurality of gate drive wiring layout areas, and the gate drive wiring layout area includes at least two third layout areas arranged along the second direction;

[0038] Among the at least two third layout areas: at least one of the third layout areas is located in the first spacing area in a corresponding row of sub-pixel groups; and at least one of the third layout areas is located in the second spacing area in a corresponding row of sub-pixel groups.

[0039] Optionally, the sub-pixel further includes a reference signal line and a second scan line, the reference signal line includes a portion extending along the first direction, and the second scan line includes a portion extending along the second direction;

[0040] The sub-pixel driving circuit further includes a second transistor, a gate of the second transistor is coupled to the second scan line, a first electrode of the second transistor is coupled to the reference signal line, and a second electrode of the second transistor is coupled to the gate of the driving transistor;

[0041] The second transistor includes a second active layer, and the second active layer includes a portion extending along the second direction; in the same sub-pixel, the second active layer, the first active layer and the light-emitting control active layer are arranged in sequence along the first direction.

[0042] Optionally, in the two sub-pixel driving circuits, the second active layers included in the two second transistors are symmetrically arranged about the symmetry axis.

[0043] Optionally, the sub-pixel further includes a reference connection portion, wherein the reference connection portion includes a portion extending along the second direction; and the first electrode of the second transistor is coupled to the reference signal line through the reference connection portion.

[0044] Optionally, the plurality of sub-pixels are divided into a plurality of pixel units, and the pixel unit includes at least two sub-pixels arranged along the second direction;

[0045] Each sub-pixel included in two adjacent pixel units arranged along the second direction reuses a reference signal line, the reference signal line is located between the two adjacent pixel units, and the reference connection portions included in each sub-pixel are coupled in sequence.

[0046] Optionally, in the same sub-pixel, the orthographic projection of the reference connection portion on the substrate, the orthographic projection of the second scanning line on the substrate, the orthographic projection of the first scanning line on the substrate, and the orthographic projection of the light-emitting control signal line on the substrate are arranged in sequence along the first direction.

[0047] Optionally, the sub-pixel further includes an initialization signal line and a third scan line, and both the initialization signal line and the third scan line include a portion extending along the second direction;

[0048] The sub-pixel driving circuit further includes a third transistor, a gate of the third transistor is coupled to the third scan line, a first electrode of the third transistor is coupled to the initialization signal line, and a second electrode of the third transistor is coupled to the anode pattern of the light-emitting element;

[0049] The third transistor includes a third active layer; in the same sub-pixel, the first active layer, the third active layer and the light-emitting control active layer are arranged in sequence along the first direction.

[0050] Optionally, in the two sub-pixel driving circuits, the third active layers included in the two third transistors are symmetrically arranged about the symmetry axis.

[0051] Optionally, at least one of the first transistor, the second transistor and the third transistor includes a dual-gate structure.

[0052] Optionally, the sub-pixel driving circuit further includes a storage capacitor, the storage capacitor including a first plate and a second plate disposed opposite to each other, the first plate being located between the substrate and the second plate; the first plate being coupled to the gate electrode of the driving transistor, and the second plate being coupled to the second electrode of the driving transistor and the anode pattern of the light-emitting element, respectively;

[0053] In the two sub-pixel driving circuits, the two first electrodes are symmetrically arranged about the symmetry axis; and / or the two second electrodes are symmetrically arranged about the symmetry axis.

[0054] Optionally, the sub-pixel further includes a first conductive connection portion and a second conductive connection portion provided in different layers, the first conductive connection portion is located between the substrate and the second conductive connection portion, and the anode pattern is located on a side of the second conductive connection portion facing away from the substrate;

[0055] The second electrode plate is coupled to the first conductive connection portion;

[0056] The orthographic projection of the second conductive connecting portion on the substrate has a first overlapping area with the orthographic projection of the first conductive connecting portion on the substrate, and the orthographic projection of the second conductive connecting portion on the substrate has a second overlapping area with the orthographic projection of the anode pattern on the substrate;

[0057] The second conductive connection portion is coupled to the first conductive connection portion through a first via, and the orthographic projection of the first via on the substrate is located in the first overlapping area; the second conductive connection portion is coupled to the anode pattern through a second via, and the orthographic projection of the second via on the substrate is located in the second overlapping area.

[0058] Optionally, at least a portion of the orthographic projection of the first conductive connection portion on the substrate is located between the orthographic projection of the third active pattern on the substrate and the orthographic projection of the driving active layer on the substrate.

[0059] Optionally, the third active layer includes a first part and a second part coupled to each other, the first part includes a part extending along the first direction, the second part includes a part extending along the second direction, and the first part and the second part form an L-shaped structure; in the same sub-pixel, the third active layer and the driving active layer are arranged along a third direction, and the third direction intersects with both the first direction and the second direction; the 90-degree angle of the L-shaped structure is toward the driving active layer.

[0060] Optionally, the display substrate further includes a data fan-out line disposed on the base, the data fan-out line is coupled to a corresponding data line, and the data fan-out line and the second conductive connection portion are disposed in the same layer and the same material.

[0061] Optionally, the display substrate further includes a pixel defining layer, wherein the pixel defining layer defines a plurality of pixel openings, and the plurality of pixel openings correspond one-to-one to the plurality of sub-pixels included in the display substrate;

[0062] The orthographic projection of the first active layer on the substrate is located inside the orthographic projection of the corresponding pixel opening on the substrate;

[0063] The orthographic projection of the second active layer on the substrate is located inside the orthographic projection of the corresponding pixel opening on the substrate;

[0064] The orthographic projection of the third active layer on the substrate is located inside the orthographic projection of the pixel defining layer on the substrate;

[0065] The orthographic projection of the light-emitting control active layer on the substrate is located inside the orthographic projection of the pixel defining layer on the substrate;

[0066] The orthographic projection of the driving active layer on the substrate partially overlaps with the orthographic projection of the pixel defining layer on the substrate and the orthographic projection of the corresponding pixel opening on the substrate.

[0067] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0069] Figure 1 A circuit diagram corresponding to the minimum repeating unit in the display substrate provided by an embodiment of the present disclosure;

[0070] Figure 2 A driving timing diagram of a sub-pixel driving circuit in a group of sub-pixels provided in an embodiment of the present disclosure;

[0071] Figure 3 for Figure 1 Layout diagram corresponding to the circuit diagram;

[0072] Figure 4 A schematic diagram of a gate drive circuit layout area and a gate drive wiring layout area provided in an embodiment of the present disclosure;

[0073] Figure 5 for Figure 3 Schematic diagram of the active layer in ;

[0074] Figure 6 for Figure 3 Schematic diagram of the layout of the first gate metal layer;

[0075] Figure 7 for Figure 3 Schematic diagram of the layout of the second gate metal layer;

[0076] Figure 8 for Figure 3 Schematic diagram of the layout of the first source and drain metal layer;

[0077] Figure 9 for Figure 3 Schematic diagram of the layout of the second source and drain metal layer;

[0078] Figure 10 for Figure 3 Schematic diagram of the layout of the middle anode layer;

[0079] Figure 11 for Figure 3 A schematic diagram of the layout of the openings formed in the pixel definition layer;

[0080] Figure 12 for Figure 3 Schematic diagram of the layout of the active layer and the first gate metal layer;

[0081] Figure 13 for Figure 3 A schematic diagram of the layout of the active layer and the first gate metal layer and the second gate metal layer;

[0082] Figure 14 for Figure 13 A schematic diagram of a layout of a first source / drain metal layer is added on the basis of FIG.

[0083] Figure 15 for Figure 14 A schematic diagram of a layout in which a second source / drain metal layer is added on the basis of FIG.

[0084] Figure 16 for Figure 15 On the basis of the above diagram, a schematic diagram of the layout of the anode layer is added;

[0085] Figure 17 for Figure 3 A schematic diagram of the layout of the active layer, the second gate metal layer and the first source and drain metal layer;

[0086] Figure 18 for Figure 3 Schematic diagram of the layout of the second gate metal layer and the first source and drain metal layer;

[0087] Figure 19 for Figure 3 Schematic diagram of the layout of the first source and drain metal layer and the second source and drain metal layer;

[0088] Figure 20 for Figure 3 Schematic diagram of the layout of the second source and drain metal layer and the anode layer;

[0089] Figure 21 A schematic cross-sectional view of a first via hole and a second via hole provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0090] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0091] In order to better meet the customization requirements of special-shaped OLED display products, it is possible to consider setting the gate drive circuit in the OLED display product within the display area, that is, using GIA (Gate Driver In AA) technology. However, the gate drive circuit will occupy part of the space within the display area, affecting the resolution of the display product.

[0092] See also Figure 1 , Figure 3 , Figure 15 and Figure 16 , an embodiment of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels 20 disposed on the substrate, wherein the plurality of sub-pixels 20 are distributed in an array;

[0093] The sub-pixel includes a sub-pixel driving circuit 201 and a light-emitting element EL. The sub-pixel driving circuit 201 includes a driving sub-circuit and a light-emitting control sub-circuit coupled to each other. The light-emitting element EL includes an anode pattern 80.

[0094] The plurality of sub-pixels are divided into a plurality of groups of sub-pixels, each group of sub-pixels A includes two sub-pixels arranged along a first direction, the two sub-pixel driving circuits 201 of the two sub-pixels reuse the same light-emitting control sub-circuit, and the light-emitting control sub-circuit is used to control the driving sub-circuits in the two sub-pixels to write driving signals to the anode pattern 80 respectively;

[0095] The sub-pixel further includes a data line, and the data line includes a portion extending along the first direction.

[0096] Exemplarily, the display substrate includes a display area and a peripheral area surrounding the display area. The display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels are distributed in the display area in an array.

[0097] Exemplarily, the sub-pixel includes a sub-pixel driving circuit 201 and a light-emitting element, wherein the sub-pixel driving circuit 201 is coupled to the light-emitting element and is used to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light. Exemplarily, the sub-pixel driving circuit 201 includes a 5T1C circuit structure, that is, it includes 5 thin-film transistors and a storage capacitor Cst. Exemplarily, the light-emitting element includes an anode pattern 80, a light-emitting functional layer and a cathode layer stacked in sequence in a direction away from the substrate; the light-emitting functional layer includes an electron injection layer, an electron transport layer, an organic light-emitting material layer, a hole transport layer and a hole injection layer stacked. Exemplarily, the cathode layer receives a negative power supply signal VSS.

[0098] Exemplarily, in the plurality of sub-pixels, the electron injection layer included in each sub-pixel is formed into an integrated structure, capable of covering the entire display area; similarly, the electron transport layer, the hole transport layer, and the hole injection layer included in each sub-pixel can also be formed into an integrated structure, capable of covering the entire display area. Exemplarily, in the plurality of sub-pixels, the cathode layer included in each sub-pixel is formed into an integrated structure, capable of covering the entire display area.

[0099] Exemplarily, the plurality of sub-pixels are divided into a plurality of groups of sub-pixels, the plurality of groups of sub-pixels being arranged in an array, and each sub-pixel can belong to only one group of sub-pixels. Exemplarily, each group of sub-pixels includes two sub-pixels arranged along a first direction, where the first direction includes a vertical direction. Exemplarily, the two sub-pixels arranged along the first direction include: layout areas of two sub-pixel driving circuits 201 included in the two sub-pixels being arranged along the first direction; and / or anode patterns 80 of two light-emitting elements included in the two sub-pixels being arranged along the first direction.

[0100] Exemplarily, each sub-pixel driving circuit 201 includes a driving sub-circuit and a light-emitting control sub-circuit, wherein the light-emitting control sub-circuit is coupled to the driving sub-circuit, and the light-emitting control sub-circuit is used to control the driving sub-circuit to write a driving signal to the anode pattern 80, thereby controlling the light-emitting condition of the light-emitting element.

[0101] Exemplarily, each group of sub-pixels includes two sub-pixels arranged along a first direction, and the two sub-pixel driving circuits 201 included in the two sub-pixels reuse the same light-emitting control sub-circuit, that is, the reused light-emitting control sub-circuit is respectively coupled to the two driving sub-circuits in the two sub-pixel driving circuits 201, and the reused light-emitting control sub-circuit respectively controls the two driving sub-circuits to write driving signals to the corresponding anode patterns 80.

[0102] According to the specific structure of the display substrate described above, the display substrate provided by the embodiment of the present disclosure divides the multiple sub-pixels into multiple groups of sub-pixels, and sets the two sub-pixel driving circuits 201 included in each group of sub-pixels to reuse the same light-emitting control sub-circuit, thereby reducing the number of light-emitting control sub-circuits and effectively reducing the layout space occupied by each group of sub-pixels. Therefore, the display substrate provided by the embodiment of the present disclosure optimizes the layout of the multiple sub-pixels, not only ensuring that the display substrate can achieve high-resolution display, but also better compatible with GOA (English: Gate On Array) logic resources, providing technical support for achieving high-resolution GIA display in special-shaped display products.

[0103] like Figure 1 , Figure 3 , Figure 6 and Figure 16 As shown, in some embodiments, the sub-pixel further includes:

[0104] a light-emitting control signal line 44 , the light-emitting control signal line 44 including a portion extending along a second direction, the second direction intersecting the first direction;

[0105] The two sub-pixel driving circuits 201 included in the two sub-pixels reuse the same light-emitting control signal line 44, and the light-emitting control signal line 44 is coupled to the light-emitting control sub-circuit for controlling the light-emitting control sub-circuit; the orthographic projection of the light-emitting control signal line 44 on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate.

[0106] Exemplarily, the first direction includes a vertical direction, and the second direction includes a horizontal direction.

[0107] Exemplarily, the two sub-pixel driving circuits 201 included in the two sub-pixels reuse the same light-emitting control signal line 44, and the light-emitting control signal line 44 is respectively coupled to the light-emitting control sub-circuit and the corresponding gate driving circuit. The light-emitting control signal line 44 is used to transmit the light-emitting control signal EM provided by the gate driving circuit to the light-emitting control sub-circuit, and the light-emitting control sub-circuit is used to control the two coupled driving sub-circuits to write driving signals to the corresponding anode pattern 80 under the control of the light-emitting control signal EM.

[0108] The two sub-pixel driving circuits 201 included in the above-mentioned two sub-pixels reuse the same light-emitting control signal line 44, thereby reducing the number of the light-emitting control signal lines 44 and effectively reducing the layout space occupied by each group of sub-pixels.

[0109] By setting the orthographic projection of the light-emitting control signal line 44 on the substrate to be located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate, the light-emitting control signal line 44 is roughly located between the two sub-pixels. In this way, the light-emitting control sub-circuit is arranged near the light-emitting control signal line 44, which not only ensures good connection performance between the light-emitting control sub-circuit and the light-emitting control signal line 44, as well as the two driving sub-circuits, but also effectively reduces the layout difficulty of the light-emitting control signal line 44 and the light-emitting control sub-circuit.

[0110] like Figure 1 , Figure 3 , Figure 5 , Figure 6 , Figure 10 and Figure 12 As shown, in some embodiments, the light emitting control sub-circuit includes a light emitting control transistor T4, a gate of the light emitting control transistor T4 is coupled to the light emitting control signal line 44, and a second electrode of the light emitting control transistor T4 is coupled to the driving sub-circuit;

[0111] The light emitting control transistor T4 includes a light emitting control active layer 34, which includes a portion extending along the second direction. The orthographic projection of the light emitting control active layer 34 on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate.

[0112] Exemplarily, when the light emitting control signal EM provided by the light emitting control signal line 44 is at a valid level, the light emitting control transistor T4 is turned on; when the light emitting control signal EM provided by the light emitting control signal line 44 is at an inactive level, the light emitting control transistor T4 is turned off.

[0113] Exemplarily, the gate of the light-emitting control transistor T4 and the light-emitting control signal line 44 coupled thereto form an integral structure. Exemplarily, the second electrode of the light-emitting control transistor T4 is coupled to the driving sub-circuit via the first conductive pattern 64. Figure 3 , Figure 8 and Figure 12 As shown, illustratively, in a group of sub-pixels, the second electrode of the emission control transistor T4 is coupled to the two driving sub-circuits in the group of sub-pixels via a first conductive pattern 64. Exemplarily, the first conductive pattern 64 includes a portion extending along the first direction. Exemplarily, the first conductive pattern 64 is provided in the same layer and material as the data lines in the display substrate. Exemplarily, the orthographic projection of the first conductive pattern 64 on the substrate partially overlaps with the orthographic projection of the emission control signal line 44 on the substrate.

[0114] Exemplarily, the light-emission control active layer 34 includes a portion extending along the second direction. Exemplarily, the width of the two ends of the light-emission control active layer 34 in the first direction is greater than the width of the middle portion of the light-emission control active layer 34 located between the two ends in the first direction. Exemplarily, the orthographic projection of the middle portion of the light-emission control active layer 34 on the substrate at least partially overlaps with the orthographic projection of the gate of the light-emission control transistor T4 on the substrate, and the middle portion of the light-emission control active layer 34 is used to form the channel region of the light-emission control transistor T4.

[0115] The above-mentioned orthographic projection of the light-emitting control active layer 34 on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate, so that the light-emitting control transistor T4 is located as a whole between two sub-pixels in a group of sub-pixels. This not only ensures good connection performance between the light-emitting control transistor T4 and the light-emitting control signal line 44, as well as the two driving sub-circuits, but also effectively reduces the layout difficulty of the light-emitting control signal line 44 and the light-emitting control transistor T4.

[0116] like Figure 3 , Figure 8 , Figure 12 As shown, in some embodiments, the sub-pixel further includes:

[0117] a power line VDD, the power line VDD including a portion extending along the first direction, the power lines VDD included in the two sub-pixels being coupled;

[0118] The first electrode of the light emitting control transistor T4 is coupled to the power line VDD. The light emitting control transistor T4 is used to turn on or off the connection between the power line VDD and the driving sub-circuits in the two sub-pixels under the control of the light emitting control signal line 44 .

[0119] Exemplarily, in the same group of sub-pixels, the power lines VDD included in the two sub-pixels are coupled to form an integrated structure.

[0120] Exemplarily, in the display substrate, the power lines VDD in all sub-pixels located in the same column along the first direction are coupled in sequence to form an integrated structure.

[0121] Exemplarily, the power line VDD includes a positive power line for providing a positive power signal Vd. The light-emission control transistor T4 is turned on or off under the control of the light-emission control signal EM provided by the light-emission control signal line 44 to control whether to transmit the power signal Vd provided by the power line VDD to the driver sub-circuit.

[0122] like Figure 3 , Figure 6 , Figure 8 , Figure 12 and Figure 15 As shown, in some embodiments, the sub-pixel further includes:

[0123] A power connection portion 45, the power connection portion 45 includes a portion extending along the second direction; the two sub-pixel driving circuits 201 included in the two sub-pixels reuse the same power connection portion 45; along the second direction, the positive projection of the power line VDD on the substrate is located on one side of the positive projection of the light-emitting control active layer 34 on the substrate, and the first electrode of the light-emitting control transistor T4 is coupled to the power line VDD through the power connection portion 45.

[0124] Exemplarily, the power connection portion 45 is arranged in a different layer from the light-emitting control active layer 34, the power connection portion 45 is arranged in a different layer from the power line VDD, the power connection portion 45 is coupled to the first electrode of the light-emitting control transistor T4 through the second conductive pattern 65, the power connection portion 45 is coupled to the power line VDD through a via, and the via passes through the insulating layer between the power connection portion 45 and the power line VDD.

[0125] Exemplarily, the power connection portion 45 and the light-emitting control signal line 44 are arranged along the first direction.

[0126] The above-mentioned arrangement of coupling the first electrode of the light-emitting control transistor T4 to the power line VDD through the power connection portion 45 not only ensures the connection performance between the light-emitting control transistor T4 and the power line VDD, but also avoids the light-emitting control transistor T4 from being short-circuited with other conductive structures in order to achieve the connection with the power line VDD, and effectively reduces the layout difficulty of the light-emitting control transistor T4.

[0127] like Figure 6 As shown, in some embodiments, the power connection portion 45 and the light-emitting control signal line 44 are provided in the same layer and made of the same material.

[0128] The above arrangement enables the power connection portion 45 and the light-emitting control signal line 44 to be formed in the same patterning process, thereby effectively simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0129] like Figure 3 , Figure 6 ,and Figure 14As shown, in some embodiments, the multiple sub-pixels are divided into multiple pixel units B, and the pixel unit B includes at least two sub-pixels arranged along the second direction; the at least two sub-pixels reuse the same power line VDD, and the power connection parts 45 included in the at least two sub-pixels are coupled in sequence.

[0130] Exemplarily, the multiple sub-pixels are divided into a plurality of pixel units B, and the plurality of pixel units B are distributed in an array.

[0131] Exemplarily, the pixel unit B includes at least two sub-pixels arranged along the second direction; the at least two sub-pixels reuse the same power line VDD, and along the second direction, the power line VDD is located on one side of the at least two sub-pixels.

[0132] Exemplarily, the power connection portions 45 included in the at least two sub-pixels are coupled in sequence to form an integrated structure. Exemplarily, in the pixel units B located in the same row along the second direction, the power connection portions 45 in each pixel unit B are coupled in sequence to form an integrated structure.

[0133] The above-mentioned setting is that the at least two sub-pixels reuse the same power line VDD, and the power connection parts 45 included in the at least two sub-pixels are coupled in sequence. This not only ensures that each sub-pixel can be coupled to the reused power line VDD through the power connection part 45, but also effectively saves the layout space occupied by each sub-pixel, which is conducive to improving the resolution of the display substrate.

[0134] Moreover, in the pixel units B located in the same row along the second direction, the power connection parts 45 in each pixel unit B are coupled in sequence, so that the power line VDD and the power connection parts 45 in the display substrate can form a mesh structure, which is beneficial to the overall uniformity of the power signal Vd.

[0135] like Figure 1 , Figure 3 , Figure 5 , Figure 8 , Figure 12 As shown, in some embodiments, the driving sub-circuit includes a driving transistor T5, a first electrode of the driving transistor T5 is coupled to the second electrode of the light emitting control transistor T4, and a second electrode of the driving transistor T5 is coupled to the anode pattern 80 of the light emitting element;

[0136] The driving transistor T5 includes a driving active layer 35; in the two sub-pixel driving circuits 201, the driving active layers 35 included in the two driving transistors T5 are arranged in an axially symmetrical manner, and the symmetry axis C extends along the second direction. The orthographic projection of the symmetry axis C on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate.

[0137] Exemplarily, the first electrode of the driving transistor T5 is coupled to the second electrode of the light-emitting control transistor T4 via the first conductive pattern 64. The second electrode of the driving transistor T5 is coupled to the second plate Cst2 of the storage capacitor Cst, and coupled to the anode pattern 80 via the second plate Cst2. Exemplarily, the second electrode of the driving transistor T5 and the second plate Cst2 of the storage capacitor Cst are disposed in different layers, and the second electrode of the driving transistor T5 is coupled to the second plate Cst2 via the third conductive pattern 66.

[0138] Exemplarily, the driving active layer 35 includes a U-shaped portion and two end portions extending from both ends of the U-shaped portion. Exemplarily, the U-shaped portion is used to form a channel region of the driving transistor T5, and the two end portions serve as a first electrode and a second electrode of the driving transistor T5.

[0139] Exemplarily, in the two sub-pixel driving circuits 201 included in the same group of sub-pixels, the gates of the two driving transistors T5 are symmetrically arranged about the symmetry axis C.

[0140] Exemplarily, the two driving active layers 35 included in the two sub-pixels adjacent along the second direction are symmetrical about the longitudinal axis, the longitudinal axis is located between the two driving active layers 35, and the longitudinal axis extends along the first direction; the gates of the two driving transistors T5 included in the two sub-pixels adjacent along the second direction are symmetrical about the longitudinal axis.

[0141] The above-mentioned symmetrical arrangement effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.

[0142] like Figure 3 and Figure 5 As shown, in some embodiments, the orthographic projection of the symmetry axis C on the substrate overlaps with the orthographic projection of the light-emitting control active layer 34 on the substrate.

[0143] The above-mentioned setting method makes the light-emitting control transistor T4 located at the center position of a group of sub-pixels along the first direction. This not only ensures the good connection performance between the light-emitting control transistor T4 and the light-emitting control signal line 44, as well as the two driving sub-circuits, but also effectively reduces the layout difficulty of the light-emitting control signal line 44 and the light-emitting control transistor T4, but also helps to reduce the layout space occupied by the sub-pixels, which is conducive to the display substrate to achieve high display resolution.

[0144] like Figure 1 , Figure 3 , Figure 5 , Figure 6 , Figure 12 As shown, in some embodiments, the sub-pixel further includes a data line 62 and a first scan line 41, the data line 62 includes a portion extending along the first direction, and the first scan line 41 includes a portion extending along the second direction;

[0145] The sub-pixel driving circuit 201 further includes a first transistor T1, wherein a gate of the first transistor T1 is coupled to the first scan line 41, a first electrode of the first transistor T1 is coupled to the data line 62, and a second electrode of the first transistor T1 is coupled to the gate of the driving transistor T5;

[0146] The first transistor T1 includes a first active layer 31, and the first active layer 31 includes a portion extending along the second direction; in the same sub-pixel, the first active layer 31, the driving active layer 35 and the light-emitting control active layer 34 are arranged in sequence along the first direction.

[0147] Exemplarily, the data lines included in the sub-pixels in the same column along the first direction are sequentially coupled to form an integrated structure. The first scan lines 41 included in the sub-pixels in the same row along the second direction are sequentially coupled to form an integrated structure.

[0148] Exemplarily, the data line receives a data signal provided by a driving chip in the display substrate.

[0149] Exemplarily, the first scan line 41 is coupled to a corresponding gate driving circuit and receives a first scan signal provided by the corresponding gate driving circuit.

[0150] Exemplarily, the first transistor T1 is turned on or off under the control of the first scan signal transmitted by the first scan line 41 to connect or disconnect the data line to the gate of the driving transistor T5.

[0151] Exemplarily, the first active layer 31 includes a portion extending along the second direction. Exemplarily, the width of the first active layer 31 at both ends in the first direction is greater than the width of the middle portion of the first active layer 31 located between the two ends in the first direction. Exemplarily, the orthographic projection of the middle portion of the first active layer 31 on the substrate at least partially overlaps with the orthographic projection of the gate of the first transistor T1 on the substrate, and the middle portion of the first active layer 31 is used to form the channel region of the first transistor T1.

[0152] Exemplarily, the first active layer 31 and the data line are disposed in a different layer, and the first active layer 31 and the gate electrode of the driving transistor T5 are disposed in a different layer. The first electrode of the first transistor T1 is coupled to the data line via a via hole, and the via hole penetrates the insulating layer between the first electrode of the first transistor T1 and the data line. The second electrode of the first transistor T1 is coupled to the gate electrode of the driving transistor T5 and the second electrode of the second transistor T2 via a sixth conductive connection portion.

[0153] Exemplarily, in one of the sub-pixels in the same group of sub-pixels, the first active layer 31, the driving active layer 35 and the light-emitting control active layer 34 are arranged in sequence from top to bottom along the first direction; in another sub-pixel in the same group of sub-pixels, the first active layer 31, the driving active layer 35 and the light-emitting control active layer 34 are arranged in sequence from bottom to top along the first direction.

[0154] like Figure 12 As shown, the above layout method enables the first transistor T1, the driving transistor T5 and the light-emitting control transistor T4 to be arranged in sequence along the second direction, which is not only conducive to reducing the layout difficulty of the sub-pixels, but also conducive to reducing the layout space occupied by the sub-pixels, and is conducive to the display substrate to achieve high display resolution.

[0155] like Figure 3 , Figure 5 and Figure 13 As shown, in some embodiments, in the two sub-pixel driving circuits 201 , the first active layers 31 included in the two first transistors T1 are symmetrically arranged about the symmetry axis C.

[0156] The above arrangement effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.

[0157] like Figure 3 and Figure 16 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of pixel units B, at least part of the pixel units B include a first sub-pixel 202, a second sub-pixel 203, and a third sub-pixel 204 arranged along the second direction, the first sub-pixel 202 includes a first data line 621, the second sub-pixel 203 includes a second data line 622, and the third sub-pixel 204 includes a third data line 623;

[0158] In the first partial pixel unit B, the first data line 621 is located on a side of the first sub-pixel 202 away from the second sub-pixel 203 along the second direction, the second data line 622 and the third data line 623 are both located between the second sub-pixel 203 and the third sub-pixel 204; and a first spacing region is defined between the first sub-pixel 202 and the second sub-pixel 203.

[0159] In the second partial pixel unit B, the first data line 621 and the second data line 622 are both located between the first sub-pixel 202 and the second sub-pixel 203, and the third data line 623 is located on the side of the third sub-pixel 204 away from the second sub-pixel 203 along the second direction; there is a second spacing area between the second sub-pixel 203 and the third sub-pixel 204.

[0160] Exemplarily, the pixel unit B includes a first sub-pixel 202 , a second sub-pixel 203 and a third sub-pixel 204 arranged along the second direction, and four pixel units B constitute a minimum repeating unit in the display substrate. Figure 3 The minimum repeating unit in the display substrate is illustrated.

[0161] Exemplarily, the colors of the first sub-pixel 202, the second sub-pixel 203 and the third sub-pixel 204 are different. Exemplarily, the first sub-pixel 202 includes a red sub-pixel, the second sub-pixel 203 includes a green sub-pixel, and the third sub-pixel 204 includes a blue sub-pixel. Figure 1 Schematic diagram of the red data signals DATAR1 and DATAR2 received by the red sub-pixel, the green data signals DATAG1 and DATAG2 received by the green sub-pixel, and the blue data signals DATAB1 and DATAB2 received by the blue sub-pixel.

[0162] Exemplarily, the first sub-pixel 202 includes a first sub-pixel driving circuit, the second sub-pixel 203 includes a second sub-pixel driving circuit, and the third sub-pixel 204 includes a third sub-pixel driving circuit.

[0163] Exemplarily, in the first partial pixel unit B, the orthographic projection of the first data line 621 on the substrate is located on the side of the orthographic projection of the first sub-pixel driving circuit on the substrate along the second direction away from the orthographic projection of the second sub-pixel driving circuit on the substrate, and the orthographic projection of the second data line 622 on the substrate and the orthographic projection of the third data line 623 on the substrate are both located between the orthographic projection of the second sub-pixel driving circuit on the substrate and the orthographic projection of the third sub-pixel driving circuit on the substrate.

[0164] Exemplarily, in the second partial pixel unit B, the orthographic projection of the first data line 621 on the substrate and the orthographic projection of the second data line 622 on the substrate are both located between the orthographic projection of the first sub-pixel driving circuit on the substrate and the orthographic projection of the second sub-pixel driving circuit on the substrate, and the orthographic projection of the third data line 623 on the substrate is located on the side of the orthographic projection of the third sub-pixel driving circuit on the substrate away from the orthographic projection of the second sub-pixel driving circuit on the substrate along the second direction.

[0165] Exemplarily, the orthographic projection of the first spacer on the substrate is located between the orthographic projection of the first sub-pixel driving circuit on the substrate and the orthographic projection of the second sub-pixel driving circuit on the substrate.

[0166] Illustratively, the orthographic projection of the first spacer on the substrate is located between the orthographic projection of the anode pattern 80 included in the first sub-pixel 202 on the substrate and the orthographic projection of the anode pattern 80 included in the second sub-pixel 203 on the substrate.

[0167] Exemplarily, the orthographic projection of the second spacer on the substrate is located between the orthographic projection of the second sub-pixel driving circuit on the substrate and the orthographic projection of the third sub-pixel driving circuit on the substrate.

[0168] Illustratively, the orthographic projection of the second spacer on the substrate is located between the orthographic projection of the anode pattern 80 included in the second sub-pixel 203 on the substrate and the orthographic projection of the anode pattern 80 included in the third sub-pixel 204 on the substrate.

[0169] The above layout method effectively reduces the layout space occupied by sub-pixels, which is conducive to achieving high display resolution for the display substrate.

[0170] like Figure 3 , Figure 4 , Figure 16 As shown, in some embodiments, the multiple groups of sub-pixels are divided into multiple rows of sub-pixel groups arranged along the first direction, and each row of sub-pixel groups includes multiple groups of sub-pixels arranged along the second direction;

[0171] The display substrate further includes a plurality of gate drive circuit layout areas 90 and a plurality of gate drive trace layout areas 91;

[0172] The plurality of gate drive circuit layout areas 90 correspond one-to-one to the plurality of rows of sub-pixel groups, and each gate drive circuit layout area 90 includes a first layout area 901 and a second layout area 902. Along the first direction, the first layout area 901 is located on a first side of a corresponding row of sub-pixel groups, and the second layout area 902 is located on a second side of a corresponding row of sub-pixel groups.

[0173] The plurality of gate drive circuit layout areas 90 correspond one-to-one to the plurality of gate drive wiring layout areas 91 , and the gate drive wiring layout area 91 includes at least two third layout areas 910 arranged along the second direction;

[0174] Among the at least two third layout areas 910: at least one of the third layout areas 910 is located in the first spacing area in a corresponding row of sub-pixel groups; at least one of the third layout areas 910 is located in the second spacing area in a corresponding row of sub-pixel groups.

[0175] Exemplarily, the gate drive circuit layout area 90 is used to layout the gate drive circuit, and the gate drive line layout area 91 is used to layout the gate drive line. The gate drive line is coupled to the corresponding gate drive circuit to provide a corresponding signal to the gate drive circuit, or to transmit the signal provided by the gate drive circuit to the sub-pixel.

[0176] Exemplarily, the first layout area 901 and the second layout area 902 both extend along the second direction, and the third layout area 910 extends along the first direction.

[0177] Illustratively, along the first direction, the first layout area 901 is located on a first side of a corresponding row of sub-pixel groups, and the second layout area 902 is located on a second side of a corresponding row of sub-pixel groups, and the first side and the second side are opposite to each other along the first direction.

[0178] Exemplarily, the multiple gate drive circuit layout areas 90 correspond one-to-one to the multiple gate drive wiring layout areas 91, and the gate drive wiring layout area 91 includes at least two third layout areas 910 arranged along the second direction, and the at least two third layout areas 910 are located between the corresponding first layout area 901 and the second layout area 902.

[0179] The above-mentioned setting method enables the gate drive circuit and the gate drive line to be arranged within the display area, optimizes the layout of the gate drive circuit and the gate drive line, is well compatible with GOA logic resources, and provides technical support for special-shaped display products to achieve high-resolution GIA display.

[0180] like Figure 1 , Figure 3 , Figure 5 , Figure 6 , Figure 12 As shown, in some embodiments, the sub-pixel further includes a reference signal line 63 and a second scan line 42, the reference signal line 63 includes a portion extending along the first direction, and the second scan line 42 includes a portion extending along the second direction;

[0181] The sub-pixel driving circuit 201 further includes a second transistor T2, a gate of the second transistor T2 is coupled to the second scan line 42, a first electrode of the second transistor T2 is coupled to the reference signal line 63, and a second electrode of the second transistor T2 is coupled to the gate of the driving transistor T5;

[0182] The second transistor T2 includes a second active layer 32 , which includes a portion extending along the second direction. In the same sub-pixel, the second active layer 32 , the first active layer 31 and the light-emitting control active layer 34 are arranged in sequence along the first direction.

[0183] Exemplarily, the reference signal lines 63 included in the sub-pixels in the same column along the first direction are sequentially coupled to form an integrated structure. The second scan lines 42 included in the sub-pixels in the same row along the second direction are sequentially coupled to form an integrated structure.

[0184] Exemplarily, the reference signal line 63 is used to provide a reference signal Vref.

[0185] Exemplarily, the second scan line 42 is coupled to a corresponding gate driving circuit and receives a second scan signal provided by the corresponding gate driving circuit.

[0186] Exemplarily, the second transistor T2 is turned on or off under the control of the second scan signal transmitted by the second scan line 42 to connect or disconnect the reference signal line 63 and the gate of the driving transistor T5.

[0187] Exemplarily, the second active layer 32 includes a portion extending along the second direction. Exemplarily, the width of the second active layer 32 at both ends in the first direction is greater than the width of the middle portion of the second active layer 32 located between the two ends in the first direction. Exemplarily, the orthographic projection of the middle portion of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the gate of the second transistor T2 on the substrate, and the middle portion of the second active layer 32 is used to form the channel region of the second transistor T2.

[0188] Exemplarily, in one of the sub-pixels in the same group of sub-pixels, the second active layer 32, the first active layer 31 and the light-emitting control active layer 34 are arranged in sequence from top to bottom along the first direction; in another sub-pixel in the same group of sub-pixels, the second active layer 32, the first active layer 31 and the light-emitting control active layer 34 are arranged in sequence from bottom to top along the first direction.

[0189] The above layout method enables the second transistor T2, the first transistor T1 and the light-emitting control transistor T4 to be arranged in sequence along the second direction, which not only helps to reduce the layout difficulty of the sub-pixels, but also helps to reduce the layout space occupied by the sub-pixels, and helps the display substrate achieve high display resolution.

[0190] like Figure 3 and Figure 5 As shown, in some embodiments, in the two sub-pixel driving circuits 201 , the second active layers 32 included in the two second transistors T2 are symmetrically arranged about the symmetry axis C.

[0191] The above arrangement effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.

[0192] like Figure 5 , Figure 12 , Figure 14 As shown, in some embodiments, the sub-pixel further includes a reference connection portion 36 , and the reference connection portion 36 includes a portion extending along the second direction; the first electrode of the second transistor T2 is coupled to the reference signal line 63 through the reference connection portion 36 .

[0193] Exemplarily, the reference connection portion 36 is provided in the same layer and the same material as the second active layer 32, the reference connection portion 36 and the reference signal line 63 are provided in different layers, the reference connection portion 36 is coupled to the first electrode of the second transistor T2 through a fourth conductive pattern 67, and the reference connection portion 36 is coupled to the reference signal line 63 through a via, and the via passes through the insulating layer between the reference connection portion 36 and the reference signal line 63.

[0194] Exemplarily, in the same group of sub-pixels, the two reference connection portions 36 included in the two sub-pixels are symmetrical about the symmetry axis C.

[0195] The above-mentioned arrangement of coupling the first electrode of the second transistor T2 to the reference signal line 63 through the reference connection portion 36 not only ensures the connection performance between the second transistor T2 and the reference signal line 63, avoids the second transistor T2 from being short-circuited with other conductive structures in order to achieve connection with the reference signal line 63, but also effectively reduces the layout difficulty of the second transistor T2.

[0196] like Figure 5 , Figure 12 , Figure 14 , Figure 17 As shown, in some embodiments, the multiple sub-pixels are divided into multiple pixel units B, and the pixel unit B includes at least two sub-pixels arranged along the second direction; each sub-pixel included in two adjacent pixel units B arranged along the second direction reuses a reference signal line 63, and the reference signal line 63 is located between the two adjacent pixel units B, and the reference connection parts 36 included in each sub-pixel are coupled in sequence.

[0197] Illustratively, the orthographic projection of the reference signal line 63 on the substrate overlaps with the orthographic projection of an anode pattern 80 included in an adjacent pixel unit B on the substrate, and does not overlap with the orthographic projection of any anode pattern 80 included in another adjacent pixel unit B on the substrate.

[0198] Exemplarily, the reference connection portions 36 included in each sub-pixel are sequentially coupled to form an integrated structure. Exemplarily, in the pixel units B located in the same row along the second direction, the power connection portions 45 in each pixel unit B are sequentially coupled to form an integrated structure.

[0199] The above-mentioned arrangement configures each sub-pixel included in two adjacent pixel units B arranged along the second direction to reuse a reference signal line 63, and the reference connection parts 36 included in each sub-pixel are coupled in sequence, which not only ensures that each sub-pixel can be coupled to the reused reference signal line 63 through the reference connection part 36, but also effectively saves the layout space occupied by each sub-pixel, which is beneficial to improving the resolution of the display substrate.

[0200] Moreover, in the pixel units B located in the same row along the second direction, the reference connection parts 36 in each pixel unit B are coupled in sequence, so that the reference signal lines 63 and the reference connection parts 36 in the display substrate can form a mesh structure, which is beneficial to the overall uniformity of the reference signal Vref.

[0201] like Figure 12As shown, in some embodiments, in the same sub-pixel, the orthographic projection of the reference connection portion 36 on the substrate, the orthographic projection of the second scanning line 42 on the substrate, the orthographic projection of the first scanning line 41 on the substrate, and the orthographic projection of the light-emitting control signal line 44 on the substrate are arranged in sequence along the first direction.

[0202] The above arrangement not only effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution, but also helps to reduce the difficulty of the layout of the sub-pixels.

[0203] like Figure 1 , Figure 3 , Figure 5 , Figure 6 , Figure 7 , Figure 10 , Figure 18 As shown, in some embodiments, the sub-pixel further includes an initialization signal line 51 and a third scan line 43, and both the initialization signal line 51 and the third scan line 43 include a portion extending along the second direction;

[0204] The sub-pixel driving circuit 201 further includes a third transistor T3, a gate of the third transistor T3 coupled to the third scan line 43, a first electrode of the third transistor T3 coupled to the initialization signal line 51, and a second electrode of the third transistor T3 coupled to the anode pattern 80 of the light-emitting element;

[0205] The third transistor T3 includes a third active layer 33 ; in the same sub-pixel, the first active layer 31 , the third active layer 33 and the light-emitting control active layer 34 are sequentially arranged along the first direction.

[0206] Exemplarily, the initialization signal line 51 includes a portion extending along the second direction, and the initialization signal lines 51 included in the sub-pixels located in the same row along the second direction are coupled in sequence to form an integrated structure.

[0207] Exemplarily, the initialization signal line 51 is used to provide an initialization signal Vinit.

[0208] Exemplarily, the third scan line 43 includes a portion extending along the second direction, and the third scan lines 43 included in the sub-pixels located in the same row along the second direction are coupled in sequence to form an integrated structure.

[0209] Exemplarily, the third scan line 43 is coupled to a corresponding gate driving circuit and receives a third scan signal provided by the corresponding gate driving circuit.

[0210] Exemplarily, the third transistor T3 is turned on or off under the control of the third scan signal transmitted by the third scan line 43 to connect or disconnect the initialization signal line 51 and the first electrode of the third transistor T3.

[0211] Exemplarily, the third active layer 33 is disposed in a different layer from the initialization signal line 51, and the third active layer 33 is disposed in a different layer from the third scan line 43. A first electrode of the third transistor T3 is coupled to the initialization signal line 51 via a fifth conductive pattern 68, and a second electrode of the third transistor T3 is coupled to the second plate Cst2 of the storage capacitor Cst via a first conductive connection portion 60.

[0212] In the above arrangement, in the same sub-pixel, the first active layer 31, the third active layer 33 and the light-emitting control active layer 34 are arranged in sequence along the first direction, which effectively reduces the layout space occupied by the sub-pixel, is beneficial for the display substrate to achieve high display resolution, and is also beneficial for reducing the layout difficulty of the sub-pixel.

[0213] like Figure 3 and Figure 5 As shown, in some embodiments, in the two sub-pixel driving circuits 201 , the third active layers 33 included in the two third transistors T3 are symmetrically arranged about the symmetry axis C.

[0214] The above arrangement effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.

[0215] like Figure 5 , Figure 6 , Figure 12 As shown, in some embodiments, at least one of the first transistor T1 , the second transistor T2 , and the third transistor T3 includes a dual-gate structure.

[0216] Exemplarily, the first transistor T1 , the second transistor T2 , the third transistor T3 , the light emitting control transistor T4 and the driving transistor T5 are all N-type low-temperature polysilicon transistors.

[0217] The above-mentioned configuration of the first transistor T1 , the second transistor T2 and the third transistor T3 including a dual-gate structure is beneficial to reducing leakage current of the transistors and ensuring functional correctness and operational stability of the sub-pixel driving circuit 201 .

[0218] like Figure 1 , Figure 3 , Figure 6 , Figure 7 , Figure 10 , Figure 16As shown, in some embodiments, the sub-pixel driving circuit 201 further includes a storage capacitor Cst, and the storage capacitor Cst includes a first electrode Cst1 and a second electrode Cst2 arranged opposite to each other, and the first electrode Cst1 is located between the substrate and the second electrode Cst2; the first electrode Cst1 is coupled to the gate of the driving transistor T5, and the second electrode Cst2 is respectively coupled to the second electrode of the driving transistor T5 and the anode pattern 80 of the light-emitting element; in the two sub-pixel driving circuits 201, the two first electrodes Cst1 are symmetrically arranged about the symmetry axis C; and / or, the two second electrodes Cst2 are symmetrically arranged about the symmetry axis C.

[0219] Exemplarily, the first electrode plate Cst1 is multiplexed as the gate of the driving transistor T5.

[0220] Exemplarily, the second electrode plate Cst2 is coupled to the second electrode of the driving transistor T5 through the third conductive pattern 66 .

[0221] Exemplarily, the orthographic projection of the second electrode plate Cst2 on the substrate at least partially overlaps with the orthographic projection of the driving active layer 35 on the substrate.

[0222] Illustratively, the orthographic projection of the second electrode plate Cst2 on the substrate is located between the orthographic projection of the first active layer 31 on the substrate and the orthographic projection of the third active layer 33 on the substrate.

[0223] Illustratively, the orthographic projection of the first electrode plate Cst1 on the substrate is located between the orthographic projection of the first active layer 31 on the substrate and the orthographic projection of the third active layer 33 on the substrate.

[0224] In the above-mentioned two sub-pixel driving circuits 201, the two first electrodes Cst1 are symmetrically arranged about the symmetry axis C; and / or, the two second electrodes Cst2 are symmetrically arranged about the symmetry axis C, which effectively reduces the layout space occupied by the sub-pixels and is conducive to achieving high display resolution for the display substrate.

[0225] like Figure 8 , Figure 9 , Figure 10 , Figure 12 , Figure 13 , Figures 18 to 21 As shown, in some embodiments, the sub-pixel further includes a first conductive connection portion 60 and a second conductive connection portion 70 provided in different layers, the first conductive connection portion 60 is located between the substrate and the second conductive connection portion 70, and the anode pattern 80 is located on a side of the second conductive connection portion 70 facing away from the substrate;

[0226] The second electrode plate Cst2 is coupled to the first conductive connection portion 60;

[0227] The orthographic projection of the second conductive connecting portion 70 on the substrate 10 and the orthographic projection of the first conductive connecting portion 60 on the substrate 10 have a first overlapping area, and the orthographic projection of the second conductive connecting portion 70 on the substrate 10 and the orthographic projection of the anode pattern 80 on the substrate 10 have a second overlapping area;

[0228] The second conductive connection part 70 is coupled to the first conductive connection part 60 through the first via Via1, and the orthographic projection of the first via Via1 on the substrate 10 is located in the first overlapping area; the second conductive connection part 70 is coupled to the anode pattern 80 through the second via Via2, and the orthographic projection of the second via Via2 on the substrate 10 is located in the second overlapping area.

[0229] Exemplarily, the first conductive connection portion 60 is coupled to the second electrode plate Cst2 , the second electrode of the third transistor T3 , and the second conductive connection portion 70 , respectively.

[0230] Exemplarily, the first via hole Via1 penetrates the insulating layer between the first conductive connection portion 60 and the second conductive connection portion 70 , and the second via hole Via2 penetrates the insulating layer between the second conductive connection portion 70 and the anode pattern 80 .

[0231] The above-mentioned arrangement of the second electrode plate Cst2 coupled to the anode pattern 80 through the first conductive connection portion 60 and the second conductive connection portion 70 makes the depths of the first via hole Via1 and the second via hole Via2 shallower, and the first via hole Via1 and the second via hole Via2 can be staggered to form a stepped hole with a gentler slope, thereby avoiding the formation of a deeper via hole between the second electrode plate Cst2 and the anode pattern 80, and effectively reducing the risk of the anode pattern 80 breaking at the second via hole Via2.

[0232] like Figure 5 and Figure 17 As shown, in some embodiments, at least a portion of the orthographic projection of the first conductive connection portion 60 on the substrate is located between the orthographic projection of the third active pattern on the substrate and the orthographic projection of the driving active layer 35 on the substrate.

[0233] The above configuration effectively reduces the layout space occupied by the sub-pixels, which helps to reduce the difficulty of sub-pixel layout and improve the resolution of the display substrate.

[0234] like Figure 5As shown, in some embodiments, the third active layer 33 includes a first portion 331 and a second portion 332 coupled to each other, the first portion 331 includes a portion extending along the first direction, the second portion 332 includes a portion extending along the second direction, and the first portion 331 and the second portion 332 form an L-shaped structure; in the same sub-pixel, the third active layer 33 and the driving active layer 35 are arranged along a third direction, and the third direction intersects with both the first direction and the second direction; the 90-degree angle of the L-shaped structure is toward the driving active layer 35.

[0235] Exemplarily, the orthographic projection of the first portion 331 on the substrate and the orthographic projection of the second portion 332 on the substrate respectively overlap with the orthographic projection of the gate of the third transistor T3 on the substrate, so that the third transistor T3 forms a dual-gate structure.

[0236] Exemplarily, the first direction is perpendicular to the second direction, and the angle between the third direction and the first direction is between 30 degrees and 45 degrees, including endpoint values.

[0237] The above configuration effectively reduces the layout space occupied by the sub-pixels, which helps to reduce the difficulty of sub-pixel layout and improve the resolution of the display substrate.

[0238] In some embodiments, the display substrate further includes a data fan-out line disposed on the base, the data fan-out line is coupled to a corresponding data line, and the data fan-out line and the second conductive connection portion 70 are disposed in the same layer and the same material.

[0239] Exemplarily, the display substrate includes multiple data fan-out lines, one end of each data fan-out line is coupled to a corresponding data line, and the other end of each data fan-out line is coupled to a corresponding pin in a driver chip, and the data fan-out line is used to transmit the data signal provided by the driver chip to the corresponding data line.

[0240] Exemplarily, the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a first passivation layer PVX1, a first planarizing layer PLN1, a second source / drain metal layer, a second passivation layer PVX2, a second planarizing layer PLN2, an anode layer, a pixel defining layer, a light-emitting functional layer, a cathode layer, and an encapsulation structure, which are sequentially stacked in a direction away from the base. Exemplarily, the display substrate may also not include the first passivation layer PVX1 and / or the second passivation layer PVX2.

[0241] Exemplarily, the second source-drain metal layer includes the data fan-out line and the second conductive connection portion 70 .

[0242] Exemplarily, the thickness of the data fan-out line is about 5500 angstroms.

[0243] Exemplarily, in a display substrate with a special design, the data fan-out lines are arranged in the display area, that is, FIA (Fanout In AA) technology is adopted.

[0244] The above-mentioned second source-drain metal layer includes the data fan-out line and the second conductive connection part 70, so that the data fan-out line is separated from the conductive structure thereunder by at least the first passivation layer PVX1 and the first flat layer PLN1, thereby effectively reducing the RC loading generated by the data fan-out line.

[0245] In more detail, the display substrate is formed by undergoing 12 patterning processes (Mask processes), specifically including: a patterning process of the active layer, a patterning process of the first gate metal layer, a patterning process of the second gate metal layer, a patterning process of the interlayer insulating layer, a patterning process of the first source-drain metal layer, a patterning process of the first flat layer PLN1, a patterning process of the first passivation layer PVX1, a patterning process of the second source-drain metal layer, a patterning process of the second flat layer PLN2, a patterning process of the second passivation layer PVX2, a patterning process of the anode layer and a patterning process of the pixel defining layer.

[0246] like Figure 5 As shown, exemplarily, the active layer includes the driving active layer 35 , the light emission control active layer 34 , the first active layer 31 , the second active layer 32 , the third active layer 33 and the reference connection portion 36 .

[0247] like Figure 6 As shown, exemplarily, the first gate metal layer includes the gate of the driving transistor T5, the gate of the light emitting control transistor T4, the gate of the first transistor T1, the gate of the second transistor T2, the gate of the third transistor T3, the first scan line 41, the second scan line 42, the third scan line 43, the light emitting control signal line 44 and the power connection part 45.

[0248] like Figure 7 As shown, illustratively, the second gate metal layer includes the second plate Cst2 of the storage capacitor Cst and the initialization signal line 51 .

[0249] like Figure 8 As shown, illustratively, the first source-drain metal layer includes a power line VDD, a data line, a reference signal line 63 , a first conductive connection portion 60 , and a first conductive pattern 64 to a sixth conductive pattern 69 .

[0250] like Figure 9As shown, illustratively, the second source-drain metal layer includes a second conductive connection portion 70 and a data fan-out line.

[0251] like Figure 10 As shown, illustratively, the anode layer includes an anode pattern 80 .

[0252] like Figure 11 As shown, the pixel defining layer exemplarily forms a pixel opening 81. Exemplarily, the pixel opening 81 is designed for constant pitch arc printing, which can increase the printing rate of the organic light-emitting material and improve the device performance of the display substrate.

[0253] Exemplarily, in the same group of sub-pixels, the two first conductive connection portions 60 are symmetrical about the symmetry axis C, the two first conductive patterns 64 are symmetrical about the symmetry axis C, the two second conductive patterns 65 are symmetrical about the symmetry axis C, the two third conductive patterns 66 are symmetrical about the symmetry axis C, the two fourth conductive patterns 67 are symmetrical about the symmetry axis C, the two fifth conductive patterns 68 are symmetrical about the symmetry axis C, the two sixth conductive patterns 69 are symmetrical about the symmetry axis C, the two second conductive connection portions are symmetrical about the symmetry axis C, the two anode patterns are symmetrical about the symmetry axis C, and the two pixel openings 81 are symmetrical about the symmetry axis C.

[0254] Exemplarily, in two adjacent sub-pixels along the second direction, the two first conductive connection portions 60 are symmetrical about the longitudinal axis, the two first conductive patterns 64 are symmetrical about the longitudinal axis, the two second conductive patterns 65 are symmetrical about the longitudinal axis, the two third conductive patterns 66 are symmetrical about the longitudinal axis, the two fourth conductive patterns 67 are symmetrical about the longitudinal axis, the two fifth conductive patterns 68 are symmetrical about the longitudinal axis, the two sixth conductive patterns 69 are symmetrical about the longitudinal axis, the two second conductive connection portions are symmetrical about the longitudinal axis, the two anode patterns are symmetrical about the longitudinal axis, the two pixel openings 81 are symmetrical about the longitudinal axis, the two first plates Cst1 are symmetrical about the longitudinal axis, the two second plates Cst2 are symmetrical about the longitudinal axis, the two first active layers 31 are symmetrical about the longitudinal axis, the two second active layers 32 are symmetrical about the longitudinal axis, the two third active layers 33 are symmetrical about the longitudinal axis, the two light-emitting control active layers 34 are symmetrical about the longitudinal axis, and the two driving active layers 35 are symmetrical about the longitudinal axis.

[0255] It should be noted that the longitudinal axis is located between two adjacent sub-pixels along the second direction, and the longitudinal axis extends along the first direction.

[0256] like Figure 1 and Figure 2 As shown, in the display substrate provided by the above embodiment, the sub-pixel driving circuit 201 includes a driving transistor T5, a light emitting control transistor T4, a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst.

[0257] The working process of the sub-pixels located in the first row and the sub-pixels located in the second row in each group of sub-pixels includes: a reset period P1, a compensation period P2, a data writing period P3 and a light emitting period P4.

[0258] The reset periods of the first row of sub-pixels and the second row of sub-pixels are staggered, the compensation periods of the first row of sub-pixels and the second row of sub-pixels are partially staggered, and the data writing periods of the first row of sub-pixels and the second row of sub-pixels are completely staggered.

[0259] It should be noted that during the data writing period of the first row of sub-pixels and the second sub-pixel 203, the light-emitting control signal EM is at an inactive level. This can prevent the first electrode of the driving transistor T5 of the first row of sub-pixels from continuously receiving the power supply signal Vd during the process of writing the data signal in the second sub-pixel 203, thereby avoiding the gate-source voltage of the driving transistor T5 of the first row of sub-pixels from dropping, affecting the compensation effect of the sub-pixel driving circuit 201 in the first sub-pixel 202.

[0260] Figure 2 Schematic diagram of the first row of sub-pixels shows a first scanning signal G11 inputted by the first scanning line 41 , a second scanning signal G21 inputted by the second scanning line 42 , and a third scanning signal G31 inputted by the third scanning line 43 . Figure 2 The figure also illustrates the first scanning signal G12 input by the first scanning line 41, the second scanning signal G22 input by the second scanning line 42, and the third scanning signal G32 input by the third scanning line 43 in the second row of sub-pixels. Figure 2 The light emitting control signal EM is also shown.

[0261] like Figure 3 , Figure 5 and Figure 11 As shown, in some embodiments, the display substrate further includes a pixel defining layer, the pixel defining layer defines a plurality of pixel openings 81, and the plurality of pixel openings 81 correspond one-to-one to the plurality of sub-pixels included in the display substrate;

[0262] The orthographic projection of the first active layer 31 on the substrate is located inside the orthographic projection of the corresponding pixel opening 81 on the substrate;

[0263] The orthographic projection of the second active layer 32 on the substrate is located inside the orthographic projection of the corresponding pixel opening 81 on the substrate;

[0264] The orthographic projection of the third active layer 33 on the substrate is located inside the orthographic projection of the pixel defining layer on the substrate;

[0265] The orthographic projection of the light-emitting control active layer 34 on the substrate is located inside the orthographic projection of the pixel definition layer on the substrate;

[0266] The orthographic projection of the driving active layer 35 on the substrate partially overlaps with the orthographic projection of the pixel defining layer on the substrate and the orthographic projection of the corresponding pixel opening on the substrate.

[0267] The above configuration effectively reduces the layout space occupied by the sub-pixels, which helps to reduce the difficulty of sub-pixel layout and improve the resolution of the display substrate.

[0268] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0269] In the display substrate provided in the above embodiment, by dividing the multiple sub-pixels into multiple groups of sub-pixels and configuring the two sub-pixel driving circuits 201 included in each group of sub-pixels to reuse the same light-emitting control sub-circuit, the layout space occupied by each group of sub-pixels is effectively reduced. Therefore, the display substrate provided in the above embodiment optimizes the layout of the multiple sub-pixels, not only ensuring that the display substrate can achieve high-resolution display, but also better compatible with GOA (English: Gate On Array) logic resources, providing technical support for achieving high-resolution GIA display in special-shaped display products.

[0270] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0271] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0272] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0273] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0274] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0275] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0276] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0277] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0278] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, characterized in that: include: A substrate and a plurality of sub-pixels disposed on the substrate, wherein the plurality of sub-pixels are distributed in an array; The sub-pixel includes a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit including a driving transistor, a second transistor, and a third transistor; a gate of the second transistor is coupled to a second scan line, a first electrode of the second transistor is coupled to a reference signal line, the reference signal line extends along a first direction, and a second electrode of the second transistor is coupled to the gate of the driving transistor; a gate of the third transistor is coupled to a third scan line, a first electrode of the third transistor is coupled to an initialization signal line via a fifth conductive pattern, and a second electrode of the third transistor is coupled to an anode pattern of the light-emitting element; the second scan line or the third scan line extends along a second direction; The multiple sub-pixels are divided into multiple groups of sub-pixels, each group of sub-pixels includes two sub-pixels arranged along the extension direction of the reference signal line, the driving active layers included in the two driving transistors in the two sub-pixels are axially symmetrically arranged about the symmetry axis, the symmetry axis extends along the second direction, and the two fifth conductive patterns in the two sub-pixels are axially symmetrically arranged about the symmetry axis.

2. The display substrate according to claim 1, wherein: The two sub-pixels further include a reference connection portion extending along the second direction, the first electrode of the second transistor is coupled to the reference signal line via the reference connection portion, and the two reference connection portions in the two sub-pixels are axially symmetrically arranged about the symmetry axis.

3. The display substrate according to claim 2, wherein: The reference connection portion and the reference signal line are arranged in different layers.

4. The display substrate according to claim 2, wherein: The reference connection portion is coupled to the first electrode of the second transistor through a fourth conductive pattern.

5. The display substrate according to claim 4, wherein: The fourth conductive pattern is symmetrical about the symmetry axis.

6. The display substrate according to claim 1, wherein: The second active layers included in the two second transistors in the two sub-pixels are arranged in an axisymmetric manner about the symmetry axis.

7. The display substrate according to claim 1, wherein: The third active layers included in the two third transistors in the two sub-pixels are arranged in an axisymmetric manner about the symmetry axis.

8. The display substrate according to claim 1, wherein: The sub-pixel driving circuit also includes a storage capacitor, which includes a first plate and a second plate arranged opposite to each other, and the first plate is coupled to the gate of the driving transistor; the two first plates in the two sub-pixels are arranged axially symmetrically about the symmetry axis; and / or the two second plates in the two sub-pixels are arranged axially symmetrically about the symmetry axis.

9. The display substrate according to claim 8, wherein: The first electrode plate includes two protrusions extending along the second direction, and the orthographic projections of the protrusions on the substrate at least partially overlap with the orthographic projection of the second electrode plate on the substrate.

10. The display substrate according to claim 8, wherein The second electrode plate is coupled to the second electrode of the driving transistor through a third conductive pattern; the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the driving active layer on the substrate.

11. The display substrate according to claim 1, wherein The third active layer in the third transistor includes a first portion and a second portion coupled to each other. The first portion includes a portion extending along the first direction, and the second portion includes a portion extending along the second direction.

12. The display substrate according to claim 11, wherein: The first portion and the second portion are formed into an L-shaped structure, and a 90-degree angle of the L-shaped structure faces the driving active layer.

13. The display substrate according to claim 1, wherein The third transistor is a dual-gate transistor.

14. The display substrate according to claim 1, wherein The gates of the two driving transistors in the two sub-pixels are arranged in an axisymmetric manner about the symmetry axis.

15. The display substrate according to claim 1, wherein The sub-pixel driving circuit further includes a light-emitting control transistor, wherein a gate of the light-emitting control transistor is coupled to a light-emitting control signal line, a first electrode of the light-emitting control transistor is coupled to a power line, and a second electrode of the light-emitting control transistor is coupled to a first electrode of the driving transistor; the light-emitting control transistor includes a light-emitting control active layer; The two light-emitting control active layers included in two sub-pixels adjacent to each other along the second direction are symmetrical about a longitudinal axis. The longitudinal axis is located between the two light-emitting control active layers, and the longitudinal axis extends along the first direction.

16. The display substrate according to claim 15, wherein: The widths of the two end portions of the light emitting control active layer in the first direction are greater than the width of a middle portion of the light emitting control active layer between the two end portions in the first direction.

17. The display substrate according to claim 1, wherein The sub-pixel further includes a data line, and the data line includes a portion extending along the first direction.

18. The display substrate according to claim 1, wherein The sub-pixel further includes a light emission control signal line, and the light emission control signal line includes a portion extending along the second direction.

19. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 18.

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