Second-order programming method of grid control signal and control circuit thereof

Abstract

The invention discloses a second-order programming method of a grid control signal, which is applied to a pre-stored field sequence pixel driving circuit, and comprises the following steps: in the initial stage of a frame, synchronously activating grid control signal lines of pixels of all rows through a global opening signal, and pre-charging pre-storage capacitors of the pixels of all rows based on data signal lines; and when gate control signal lines of the pixels are closed line by line by utilizing the shift pulse signals, writing of next frame data voltage is completed for the pre-storage capacitor of each line of pixels before the gate control signal lines are closed based on the data signal lines.

Description

Technical Field

[0001] The present invention relates to the field of pixel driving technology, and in particular to a second-order programming method of a gate control signal and a control circuit thereof. Background Art

[0002] In traditional field-sequential or color-sequential display driver technologies, the backlight can only be activated after all screen data has been written and the liquid crystal deflection has reached a stable state. Otherwise, the screen will be distorted. Therefore, the time required for data writing and liquid crystal deflection significantly compresses the backlight activation time, making it difficult to increase display brightness, refresh rate, and resolution, increasing power consumption, and increasing backlight material costs. Therefore, how to speed up the LCD drive time and increase the backlight activation time is a critical issue.

[0003] Because the pixel driver circuit of field-sequential displays lacks a filter, they offer high transmittance, high resolution, and a high PPI. This holds great potential for future high-pixel-density products. In 4K, 8K, and even 12K products, field-sequential displays, like traditional LCD displays, must maintain the pixel electrode charge rate—that is, the ratio of the maximum charge voltage to the data voltage. For the same pixel size line, the increased number of pixels doubles the number of capacitors, resulting in greater RC loading. Traditional 1T1C LCD pixel circuits often pre-charge the GOA by simultaneously turning on pixels in several adjacent rows. This requires more CK lines and is unfavorable for peripheral layout. Furthermore, the ramp-up and pull-down of the GOA turn-on waveform, including signal noise before and after, will affect the pixel charge rate. Therefore, future high-pixel-count field-sequential display products will require new gate control signal generation methods to address these issues.

[0004] In summary, the conventional method for generating gate control signals has the problems of high noise and difficulty in peripheral circuit layout. Summary of the Invention

[0005] In view of this, the present invention provides a second-stage programming method for gate control signals. By improving the programming method, the problems of high noise and difficulty in peripheral circuit layout in traditional gate control signal generation methods are solved.

[0006] To solve the above problems, the technical solution of the present invention is to adopt a two-stage programming method of gate control signals, which is applied to a pre-stored field sequential pixel driving circuit, including: at the start stage of the frame, the gate control signal lines of all rows of pixels are synchronously activated by a global turn-on signal, and the pre-storage capacitors of all rows of pixels are pre-charged based on the data signal line; while the gate control signal lines of the pixels are turned off row by row using a shift pulse signal, the pre-storage capacitors of each row of pixels are written with the next frame of data voltage based on the data signal line before the gate control signal line is turned off.

[0007] Optionally, the gate control signal lines of all rows of pixels are synchronously activated by a global turn-on signal, and the pre-storage capacitors of all rows of pixels are pre-charged based on the data signal lines, including: the global turn-on signal is coupled to a control circuit outside the display area, and the control circuit is coupled to the pixel driving circuit in the display area through the gate control signal line. When the global turn-on signal jumps to a high potential, the control circuit outputs a high-potential gate control signal and turns on the write transistor in the pixel driving circuit based on the gate control signal line, thereby pre-charging the pre-storage capacitors of all rows of pixels based on the data signal line of the pixel driving circuit, and the pre-charge potential is a fixed potential.

[0008] Optionally, a shift pulse signal is used to turn off the gate control signal line of the pixel row by row, including: the shift pulse signal is coupled to a control circuit outside the display area, and when the shift pulse signal jumps to a high potential row by row, the control circuit outputs a low potential gate control signal row by row, thereby turning off the write transistor in the pixel driving circuit row by row based on the gate control signal line.

[0009] Optionally, based on the data signal line, the pre-storage capacitor of each row of pixels completes the writing of the next frame of data voltage before the gate control signal line is turned off, including: before the write transistor of the first row is turned off, the potential of the data signal line of the pixel driving circuit jumps to the grayscale voltage required for the next frame of the first row of pixels; after the write transistor of the Nth row is turned off, the data signal line of the pixel driving circuit jumps to the grayscale voltage required for the next frame of the N+1th row of pixels, where N is a positive integer; thereby completing the writing of the next frame of data voltage to the pre-storage capacitor of each row of pixels before the gate control signal line is turned off.

[0010] Accordingly, the present invention provides a control circuit for a gate control signal, which is applied to the above-mentioned second-level programming method, comprising: a first transistor and a second transistor, wherein the first source and drain of the first transistor are coupled to a first reference signal line, the second source and drain are coupled to the second source and drain and the gate control signal line of the second transistor, and the gate is coupled to a global turn-on signal; the first source and drain of the second transistor are coupled to a second reference signal line, and the gate is coupled to a shift pulse signal.

[0011] Optionally, the control circuit may further include a third transistor. When the control circuit is provided with the third transistor: the first source and drain of the second transistor are coupled to the second source and drain of the third transistor; the gate of the third transistor is coupled to the shift pulse signal, and the first source and drain are coupled to the second reference signal line.

[0012] Accordingly, the present invention provides a control circuit for a gate control signal, which is applied to the above-mentioned second-level programming method, including: a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first source and drain of the first transistor are coupled to the third reference signal line, the second source and drain are coupled to the gate of the second transistor, the second source and drain of the third transistor and one end of the holding capacitor, and the gate is coupled to the global start signal; the first source and drain of the second transistor are coupled to the fourth reference signal line, and the second source and drain are coupled to the gate control signal line; the first source and drain of the third transistor are coupled to the second source and drain and the gate control signal line of the fourth transistor, and the gate is coupled to the shift pulse signal; the first source and drain of the fourth transistor are coupled to the second reference signal line, and the gate is coupled to the shift pulse signal.

[0013] Optionally, the other end of the holding capacitor is coupled to a common signal line.

[0014] The primary improvement of the present invention is a second-stage programming method for gate control signals. After turning on all rows of pixels using a global turn-on signal, these are then turned off row by row using a shift pulse signal. This results in fewer signal transition stages per frame, faster signal response, and less noise, resolving the high noise issue inherent in conventional gate control signal generation methods. Furthermore, the control circuit employed in the present invention utilizes fewer CK lines than the GOA pre-charge circuit employed in conventional gate control signal generation methods, resolving the difficulty in peripheral circuit layout inherent in conventional gate control signal generation methods.

[0015] At the same time, since the second-level programming method of the present invention turns on the pixels of all rows through a global turn-on signal, the pre-storage capacitor is pre-charged at the beginning of the frame, which reduces the time required for subsequent grayscale voltage writing, increases the backlight lighting time, and thus improves the light output efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a simplified flow chart of the second-stage programming method of the gate control signal of the present invention; Figure 2 is a simplified circuit diagram of a pixel driving circuit according to embodiment 1 of the present invention; Figure 3 is a simplified driving timing diagram of the pixel driving circuit according to embodiment 1 of the present invention; Figure 4 is a simplified circuit diagram of a pixel driving circuit according to embodiment 2 of the present invention; Figure 5 is a simplified circuit diagram of a pixel driving circuit according to embodiment 3 of the present invention; Figure 6 is a simplified driving timing diagram of the pixel driving circuit according to embodiment 3 of the present invention; Figure 7 is a simplified circuit diagram of a pixel driving circuit according to embodiment 4 of the present invention; Figure 8 4 is a simplified driving timing diagram of the pixel driving circuit according to embodiment 4 of the present invention. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0020] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0022] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0023] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0024] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship. Example 1

[0025] Specifically, such as Figure 1 As shown, a second-stage programming method of a gate control signal is applied to a pre-stored field sequential pixel driving circuit, comprising: S1: At the start of a frame, the gate control signal lines of all rows of pixels are synchronously activated by the global turn-on signal STV, and the pre-storage capacitors of all rows of pixels are pre-charged based on the data signal line, including: The global start signal STV is coupled to a control circuit outside the display area, and the control circuit is coupled to the pixel driving circuit in the display area through a gate control signal line. When the global start signal STV jumps to a high potential, the control circuit outputs a high potential gate control signal and turns on the write transistor in the pixel driving circuit based on the gate control signal line, thereby pre-charging the pre-storage capacitors of all rows of pixels based on the data signal line of the pixel driving circuit, and the pre-charge potential is a fixed potential.

[0026] Furthermore, the fixed potential can be set according to the polarity of the pixel column (the polarity of the pixel driving circuit usually uses column inversion). For example: when the polarity is positive, the potential of the data signal line can be 2V, 3V, etc.; when the polarity is negative, the potential of the data signal line can be -2V, -3V, etc., thereby reducing the time required for subsequent grayscale voltage writing, increasing the backlight lighting time, and thus improving the light output efficiency.

[0027] Furthermore, the fixed potential can be set to the grayscale voltage required by the first row of pixels for the next frame, thereby reducing the jump of the data signal potential once.

[0028] S2: While turning off the gate control signal line of each pixel row by row using the shift pulse signal g(n), the pre-storage capacitor of each row of pixels completes writing the next frame data voltage based on the data signal line before the gate control signal line is turned off, including: The shift pulse signal g(n) is coupled to a control circuit outside the display area. When the shift pulse signal g(n) jumps to a high potential row by row, the control circuit outputs a low potential gate control signal row by row, thereby turning off the write transistor in the pixel driving circuit row by row based on the gate control signal line.

[0029] Furthermore, based on the data signal line, the pre-storage capacitor of each row of pixels completes the writing of the next frame of data voltage before the gate control signal line is turned off, including: before the write transistor of the first row is turned off, the potential of the data signal line of the pixel driving circuit jumps to the grayscale voltage required for the next frame of the first row of pixels; after the write transistor of the Nth row is turned off, the data signal line of the pixel driving circuit jumps to the grayscale voltage required for the next frame of the N+1th row of pixels, where N is a positive integer; thereby, the pre-storage capacitor of each row of pixels completes the writing of the next frame of data voltage before the gate control signal line is turned off.

[0030] Furthermore, the shift pulse signal g(n) is a gate-on pulse signal provided by the GOA or Gate IC in the nth row.

[0031] Furthermore, Figure 2 As shown, the control circuit includes: a first transistor T1 and a second transistor T2, wherein the first source and drain of the first transistor T1 are coupled to the first reference signal line Vdd, the second source and drain are coupled to the second source and drain of the second transistor T2 and the gate control signal line G(n), and the gate is coupled to the global start signal STV; the first source and drain of the second transistor T2 are coupled to the second reference signal line Vss, and the gate is coupled to the shift pulse signal g(n).

[0032] Furthermore, the first reference signal line Vdd is a fixed high potential; the second reference signal line Vss is a fixed low potential.

[0033] To facilitate understanding of how the control circuit of this embodiment implements the above-mentioned second-order programming method, as shown in FIG. Figure 3As shown, after the global turn-on signal STV is high, the gate control signal lines G(n) of all rows are written with high signals due to T1 being turned on, turning on the write transistors in the pixel drive circuits of all rows to charge the pre-storage capacitors. When the shift pulse signal g(n) changes from low to high, T2 is turned on, and the gate control signal line G(n) is reset to a low potential to achieve a shutdown effect. Since the shift pulse signal g(n) is a pulse signal for each row, the gate control signal line G(n) is triggered to be turned off row by row.

[0034] It should be noted here that since the traditional pre-stored field sequential pixel driving circuit belongs to the conventional existing technology in this field, the specific structure of the pixel driving circuit is not limited in the present invention to avoid unnecessary limitation on the scope of application of the second-order programming method.

[0035] The present invention uses a global turn-on signal to turn on all rows of pixels, and then turns them off row by row using a shift pulse signal. This reduces the number of signal transition stages in a single frame, resulting in faster signal response and less noise, thus resolving the high noise issue associated with conventional gate control signal generation methods. Furthermore, the control circuit employed in the present invention uses fewer CK lines than the GOA precharge circuit employed in conventional gate control signal generation methods, thus resolving the difficulty in peripheral circuit layout associated with conventional gate control signal generation methods.

[0036] At the same time, since the second-level programming method of the present invention turns on the pixels of all rows through a global turn-on signal, the pre-storage capacitor is pre-charged at the beginning of the frame, which reduces the time required for subsequent grayscale voltage writing, increases the backlight lighting time, and thus improves the light output efficiency. Example 2

[0037] like Figure 4 As shown, the control circuit can further include a third transistor T3. When the control circuit is provided with the third transistor: the first source and drain of the second transistor T2 are coupled to the second source and drain of the third transistor T3; the gate of the third transistor T3 is coupled to the shift pulse signal g(n), and the first source and drain are coupled to the second reference signal line Vss.

[0038] Furthermore, this embodiment adds a TFT compared to Example 1. This primarily improves leakage. When the gate control signal line G(n) is not closed, the Vds of the TFT connected to the second reference signal line Vss is high, posing a risk of leakage. When an additional TFT is added, the leakage from T2 and T3 causes the common source and drain of T2 and T3 to be at an intermediate potential. Therefore, the Vds of both T3 and T2 can be reduced, reducing the magnitude of leakage current.

[0039] The driving timing of this embodiment is consistent with that of the first embodiment, and therefore will not be described in detail. Example 3

[0040] like Figure 5 As shown, a gate control signal control circuit is applied to the above-mentioned second-level programming method, including: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, wherein the first source and drain of the first transistor T1 are coupled to the third reference signal line Vdd1, the second source and drain are coupled to the gate of the second transistor T2, the second source and drain of the third transistor T3 and one end of the holding capacitor Cs(n), and the gate is coupled to the global start signal STV; the first source and drain of the second transistor T2 are coupled to the fourth reference signal line Vdd2, and the second source and drain are coupled to the gate control signal line G(n); the first source and drain of the third transistor T3 are coupled to the second source and drain of the fourth transistor T4 and the gate control signal line G(n), and the gate is coupled to the shift pulse signal g(n); the first source and drain of the fourth transistor T4 are coupled to the second reference signal line Vss, and the gate is coupled to the shift pulse signal g(n).

[0041] Furthermore, the other end of the holding capacitor Cs(n) is coupled to the common signal line Com.

[0042] This embodiment adds a holding capacitor Cs(n) whose main purpose is to store the high potential voltage of the global turn-on signal STV. When row m is turned off, rows m+1 to n are still kept in a charged state. Since the magnitude of the charging current when T2 is turned on is much greater than the magnitude of the leakage current of T4, the dual TFT device of embodiment 2 is not required to reduce the leakage current. The driving process is as follows: Figure 6 As shown. When the global start signal STV is given a high signal, T1 is turned on first, and the high-potential third reference signal line Vdd1 is written into the holding capacitor Cs(n). The gate signal of T2 is triggered, T2 is turned on, and the high-potential fourth reference signal line Vdd2 is written into the gate control signal line G(n), thereby realizing the pre-charging of the pre-storage capacitors of all rows of pixels. At this time, the shift pulse signal g(n) begins to produce row-by-row shift pulse signals to trigger T1 and T4. Here, the device parameters of T2 and T4 must be differentiated to ensure that the driving capability of T4 is greater than that of T2, that is, the turn-on current T4 is greater than that of T2. Because T2 is still charging the gate control signal line G(n) at this time, and T4 is discharging, T4 preferentially pulls down the gate potential of the gate control signal line G(n). When the potential of the gate control signal line G(n) drops, T3 is also in the on state, and the gate potential of T2 is gradually pulled down until it reaches the potential of the second reference signal line Vss. T2 is then turned off, and T4 completely pulls GN down to the potential of the second reference signal line Vss, achieving row-by-row shutdown. Example 4

[0043] like Figure 7 As shown, a gate control signal control circuit is applied to the above-mentioned second-level programming method, including: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, wherein the first source and drain of the first transistor T1 are coupled to the third reference signal line Vdd1, the second source and drain are coupled to the gate of the second transistor T2, the second source and drain of the third transistor T3, the second source and drain of the fourth transistor T4 and one end of the holding capacitor Cs(n), and the gate is coupled to the global start signal STV; the first source and drain of the second transistor T2 are coupled to the fourth reference signal line Vdd2, the second source and drain are coupled to the gate control signal line G(n) and the first source and drain of the fourth transistor T4; the first source and drain of the third transistor T3 are coupled to the second reference signal line Vss, and the gate is coupled to the shift pulse signal g(n); the gate of the fourth transistor T4 is coupled to the shift pulse signal g(n).

[0044] Compared with the control circuit of Example 3, this embodiment reduces the delay of the shutdown signal caused by the competition between T2, T3, and T4. The driving timing is as follows: Figure 8 As shown. When the global turn-on signal STV is turned on, T1 is turned on, and the potential of the third reference signal line Vdd1 is written into the holding capacitor Cs(n), and T2 is turned on, so that the high potential fourth reference signal line Vdd2 is written into the gate control signal line G(n), realizing the pre-charging of the pre-storage capacitors of all rows of pixels. When the shift pulse signal g(n) triggers a high potential, T3 first turns on to pull down the gate voltage of T2 to the potential of the second reference signal line Vss. At the same time, T4 turns on to pull down the potential of the gate control signal line G(n) to the potential of the second reference signal line Vss. Since there is no simultaneous charging and discharging action on the gate control signal line G(n), the pull-down signal of the gate control signal line G(n) will become steeper, which is conducive to reducing delay. At the same time, there is no need to adjust the device size, which is conducive to spatial layout.

[0045] The above is a second-order programming method for a gate control signal and a control circuit thereof provided in an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0046] Those skilled in the art will further appreciate that the elements and algorithmic steps of each example described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described above by function. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A skilled person may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the present invention. The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, software modules executed by a processor, or a combination of the two. The software modules can be stored in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Claims

1. A second-stage programming method for gate control signals, characterized in that: A field-sequential pixel driving circuit for pre-storage includes: At the start of a frame, the gate control signal lines of all rows of pixels are synchronously activated by a global turn-on signal (STV), and the pre-storage capacitors of all rows of pixels are pre-charged based on the data signal line; While the gate control signal line of the pixels is turned off row by row using the shift pulse signal (g(n)), the pre-storage capacitor of each row of pixels is written with the next frame data voltage based on the data signal line before the gate control signal line is turned off.

2. The second-level programming method according to claim 1, wherein: Synchronously activating the gate control signal lines of all rows of pixels through a global turn-on signal (STV), and pre-charging the pre-storage capacitors of all rows of pixels based on the data signal lines, including: The global turn-on signal (STV) is coupled to a control circuit outside the display area, and the control circuit is coupled to a pixel driving circuit within the display area through a gate control signal line. When the global turn-on signal (STV) jumps to a high potential, the control circuit outputs a high-potential gate control signal and turns on the write transistor in the pixel driving circuit based on the gate control signal line, thereby pre-charging the pre-storage capacitors of all rows of pixels based on the data signal line of the pixel driving circuit. The pre-charge potential is a fixed potential.

3. The second-level programming method according to claim 1, wherein: The gate control signal line that turns off the pixels row by row using a shift pulse signal (g(n)) includes: The shift pulse signal (g(n)) is coupled to a control circuit outside the display area. When the shift pulse signal (g(n)) jumps to a high potential row by row, the control circuit outputs a low potential gate control signal row by row, thereby turning off the write transistor in the pixel driving circuit row by row based on the gate control signal line.

4. The second-level programming method according to claim 3, wherein: The data voltage of the next frame is written into the pre-storage capacitor of each row of pixels based on the data signal line before the gate control signal line is turned off, including: Before the write transistors of the first row are turned off, the potential of the data signal line of the pixel driving circuit jumps to the grayscale voltage required by the pixels of the first row for the next frame; After the write transistors in the Nth row are turned off, the data signal line of the pixel driving circuit jumps to the grayscale voltage required by the pixels in the N+1th row for the next frame, where N is a positive integer; Thus, the pre-storage capacitor of each row of pixels completes writing of the next frame data voltage before the gate control signal line is closed.

5. A gate control signal control circuit, applied to the second-level programming method according to any one of claims 1 to 4, characterized in that: include: A first transistor (T1) and a second transistor (T2), wherein The first source and drain of the first transistor (T1) are coupled to a first reference signal line (Vdd), the second source and drain are coupled to a second source and drain of the second transistor (T2) and a gate control signal line (G(n)), and the gate is coupled to a global turn-on signal (STV); The first source and drain of the second transistor (T2) are coupled to the second reference signal line (Vss), and the gate is coupled to the shift pulse signal (g(n)).

6. The control circuit according to claim 5, characterized in that: The control circuit may further include a third transistor (T3). If the control circuit is provided with the third transistor: The first source and drain of the second transistor (T2) are coupled to the second source and drain of the third transistor (T3); The gate of the third transistor (T3) is coupled to the shift pulse signal (g(n)), and the first source and drain are coupled to the second reference signal line (Vss).

7. A gate control signal control circuit, applied to the second-level programming method according to any one of claims 1 to 4, characterized in that: include: a first transistor (T1), a second transistor (T2), a third transistor (T3) and a fourth transistor (T4), wherein The first source and drain of the first transistor (T1) are coupled to a third reference signal line (Vdd1), the second source and drain are coupled to the gate of the second transistor (T2), the second source and drain of the third transistor (T3) and one end of the holding capacitor (Cs(n)), and the gate is coupled to a global start signal (STV); The first source and drain of the second transistor (T2) are coupled to the fourth reference signal line (Vdd2), and the second source and drain are coupled to the gate control signal line (G(n)); The first source and drain of the third transistor (T3) are coupled to the second source and drain of the fourth transistor (T4) and the gate control signal line (G(n)), and the gate is coupled to the shift pulse signal (g(n)); The first source and drain of the fourth transistor (T4) are coupled to the second reference signal line (Vss), and the gate is coupled to the shift pulse signal (g(n)).

8. The control circuit according to claim 7, characterized in that: The other end of the holding capacitor (Cs(n)) is coupled to the common signal line (Com).

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