Data signal correction circuit and display device

Abstract

The invention discloses a data signal correction circuit and a display device, and the data signal correction circuit comprises a plurality of correction units which are arranged in a line and correspond to display units of the display device; wherein a driving chip of the display device generates a data signal, and the data signal is transmitted to a corresponding display unit through a correction unit; and the correction unit comprises a second MOS tube of which the doping type is opposite to that of the first MOS tube in the display unit, and the second MOS tube is matched with the first MOS tube, so that the voltage deviation generated by the second MOS tube due to the feed-through effect is counteracted with the voltage deviation generated by the first MOS tube due to the feed-through effect. According to the display device, the voltage deviation caused by the feed-through effect in the display device is improved, the problem of abnormal display such as picture flicker caused by the fact that the corresponding voltage cannot reach the accurate potential is avoided, and the stability and the reliability of the display device are improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly to a data signal correction circuit and a display device. Background Art

[0002] In the field of display technology, traditional liquid crystal display devices experience a feedthrough effect when the MOS transistors in pixel switches are turned off, causing a deviation in the data signal voltage. This voltage deviation can cause the actual charging voltage of the liquid crystal capacitor to be inconsistent with the source signal provided by the driver chip, leading to display quality issues such as flickering and image sticking.

[0003] In the existing technology, the feedthrough voltage is usually compensated by adjusting the common electrode voltage (Vcom). However, this method requires the addition of a common voltage regulation module and requires OTP burning and calibration on the production line, which not only increases the complexity of chip design, but also increases manufacturing costs and process difficulty.

[0004] With the gradual development of display technology, the method of using a common voltage regulator module to compensate for feedthrough voltage has become inadequate to meet development needs. Therefore, a data signal correction circuit is urgently needed to resolve display issues caused by feedthrough voltage, improve the stability and display quality of display devices, and avoid problems such as screen flicker and image sticking caused by feedthrough. Summary of the Invention

[0005] The purpose of the present invention is to provide a data signal correction circuit and a display device, aiming to improve the voltage deviation caused by the feedthrough effect in the display device, avoid the display abnormality such as screen flickering caused by the voltage corresponding to the data signal failing to charge to the accurate potential, and improve the stability and reliability of the device.

[0006] According to one aspect of the present invention, a data signal correction circuit is provided, comprising: correction units, wherein a plurality of correction units are arranged in a row and correspond to display units of a display device; wherein a driver chip of the display device generates a data signal, and the data signal is transmitted to the corresponding display unit through the correction unit; the correction unit includes a second MOS transistor having a doping type opposite to that of a first MOS transistor in the display unit, the second MOS transistor being matched with the first MOS transistor so that a voltage deviation generated by a feedthrough effect in the second MOS transistor offsets a voltage deviation generated by the feedthrough effect in the first MOS transistor.

[0007] Optionally, the correction unit includes: a second MOS transistor, a first end of the second MOS transistor is connected to a driver chip to receive a data signal, a second end of the second MOS transistor is connected to a data line of a display unit to provide a source drive signal to the display unit, and a control end of the second MOS transistor is connected to a driver chip to receive a clock signal; a second liquid crystal capacitor, corresponding to a first liquid crystal capacitor in the display unit, a first end of the second liquid crystal capacitor is connected to a second end of the second MOS transistor, and a second end of the second liquid crystal capacitor is connected to a common electrode; a second storage capacitor, connected in parallel with the second liquid crystal capacitor, corresponding to the first storage capacitor in the display unit, a first end of the second storage capacitor is connected to the second end of the second MOS transistor, and a second end of the second storage capacitor is connected to a common electrode; wherein the control ends of the second MOS transistors of multiple correction units are connected to each other and to the driver chip to receive the clock signal.

[0008] Optionally, parameters of the second liquid crystal capacitor match those of the first liquid crystal capacitor, and parameters of the second storage capacitor match those of the first storage capacitor.

[0009] Optionally, the first MOS transistor and the second MOS transistor are located on the same substrate, and parasitic capacitances between gates and drains of the first MOS transistor and the second MOS transistor are the same.

[0010] Optionally, the frequency of the clock signal matches the refresh rate of the corresponding display device.

[0011] According to another aspect of the present invention, a display device is provided, comprising: a driver chip connected to a display circuit for providing a data signal; a display circuit having a plurality of display units, each of the display units performing corresponding grayscale control according to the data signal; and a correction circuit, the correction circuit being located between the driver chip and the display circuit; wherein the data signal is generated by the driver unit and transmitted to the display circuit after passing through the correction circuit to compensate for a feedthrough effect of the display circuit.

[0012] Optionally, the display device further includes a display area, the display circuit is located in the display area, and each row of the display units is controlled by a corresponding gate drive signal; the correction circuit is located outside the display area, and a single-row correction unit provides corresponding data signals to multiple rows of display units through timing control.

[0013] Optionally, the correction circuit is located in a frame area around the display area.

[0014] Optionally, the first MOS tube of the display unit is an N-type MOS tube, and the second MOS tube of the correction unit is a P-type MOS tube.

[0015] Optionally, the P-type MOS transistor of the correction unit and the N-type MOS transistor of the display unit have the same conductivity and are manufactured through the same process.

[0016] This invention integrates MOS transistors with opposite doping types corresponding to the display area on the same substrate to form a correction circuit. The parasitic capacitance, liquid crystal capacitance, and storage capacitance of the correction circuit and display circuit are strictly matched. This ensures that the voltage deviations caused by the feedthrough effect in the display unit and the correction unit are equal in magnitude and opposite in polarity, thereby canceling each other out. This design enables the data signal (source signal) to be accurately charged to the target potential, eliminating screen flicker caused by voltage deviation. It also eliminates the traditional common voltage regulation module, simplifying the driver chip design and the corresponding common voltage regulation module data programming steps.

[0017] The display device provided by the present invention has a correction unit and a display unit integrated using the same process, ensuring the consistency of capacitance parameters. It also has a timing design for driving multiple rows of display units through a single row of correction units, significantly reducing circuit area occupancy and improving system integration. At the same time, it avoids frequent adjustments to the common voltage, thereby improving the stability and reliability of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0019] Figure 1 A schematic diagram showing a data signal correction circuit according to an embodiment of the present invention;

[0020] Figure 2 A schematic diagram showing a display device according to an embodiment of the present invention;

[0021] Figure 3 A driving timing diagram of the MOS transistor in the display unit and the MOS transistor in the correction circuit in the display device according to an embodiment of the present invention is shown;

[0022] Figure 4a and Figure 4b Schematic diagrams showing the MOS tube of the display unit in the display device according to the embodiment of the present invention when it is turned on and off respectively;

[0023] Figure 5a and Figure 5b Waveform diagrams showing the voltages at each end of an N-type MOS transistor and a P-type MOS transistor in a display device according to an embodiment of the present invention;

[0024] Figure 6a and Figure 6b Schematic diagrams respectively show waveforms of feed-through voltages of a display unit and a correction unit in a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be described in more detail below with reference to the accompanying drawings. To facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to facilitate a more thorough and comprehensive understanding of the disclosure of the present application.

[0026] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0027] In the description of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being preferred or advantageous over other embodiments. "And / or" in this document describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exists simultaneously, or B exists alone. "Connected" describes the connection relationship between associated objects. For example, "A is connected to B" can mean a direct connection between A and B, or an indirect connection between A and B through other devices / units / modules. "Multiple" refers to two or more than two. In addition, to facilitate the clear description of the technical solutions of the embodiments of this application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity or execution order, and words such as "first" and "second" do not necessarily indicate differences.

[0028] In addition, the same reference numerals in the figures represent the same or similar structures, and their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manner, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other. The words expressing position and direction described in this application are all explained with the drawings as examples, but they can be changed as needed, and the changes made are included in the scope of protection of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0029] Many specific details of the present invention are described in this application, such as the specific structure, size, connection relationship and technology of the modules, to facilitate a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without following these specific details.

[0030] The present invention may be embodied in various forms, some examples of which are described below.

[0031] Figure 1 A schematic diagram of a data signal correction circuit according to an embodiment of the present invention is shown; the data signal correction circuit includes a plurality of correction units, the number of which corresponds to the number of display units included in each row of the display device. Specifically, taking a single display unit and a single correction unit as an example, each display unit includes, for example, a MOS tube M1, a capacitor C LC1 and capacitor C st1 MOS tube M1 is used as a pixel switch to control the liquid crystal capacitor C LC1 The charging and discharging process of the MOS tube M1 is, for example, an N-type MOS tube, and the capacitor C LC1 is the liquid crystal capacitor, capacitor C st1 is the storage capacitor, capacitor C st1 Used to store charge to maintain pixel voltage. The source S1 of MOS tube M1 receives source signal Source through source line Data Line, the gate G1 of MOS tube M1 receives gate signal Gate through gate line Gate Line, the drain D1 of MOS tube M1 and capacitor C LC1 One end and capacitor C st1 One end of the capacitor C LC1 The other end of the capacitor C st1 The other end is connected to the common electrode Common, and the capacitor C LC1 With capacitor C st1 Each correction unit includes, for example, a MOS tube M2, a capacitor C LC2 and capacitor C st2 MOS tube M2 is a P-type MOS tube corresponding to MOS tube M1, and capacitor C LC2 and capacitor Cst2 Respectively with capacitor C LC1 and capacitor C st1 Correspondingly, the source S2 of the MOS tube M2 is connected to the driver chip to receive the source signal Source, the gate G2 of the MOS tube M2 is connected to the driver chip to receive the clock signal Clk, and the drain D2 of the MOS tube M2 is connected to the capacitor C LC2 One end of the capacitor C st2 One end of the capacitor is connected to the source line Data Line, and is connected to the source S1 of the MOS tube M1 through the source line Data Line. LC2 The other end of the capacitor C st2 The other end is connected to the common electrode Common, and the capacitor C LC2 With capacitor C st2 Parallel connection. The MOS transistor M2 and the MOS transistor M1 have different doping types. For example, they are both located on the same substrate, and their specifications and sizes correspond to each other. Their conductivity is the same, so that the parasitic capacitance Cgd between the gate and drain of the MOS transistor M1 is the same as the parasitic capacitance Cgd between the gate and drain of the MOS transistor M2. The source signal Source provided by the driver chip needs to pass through the correction unit before being connected to the display unit. The source signal Source passes through the MOS transistor M2, the parallel capacitor C in sequence. LC2 With capacitor C st2 Then it is connected to the MOS tube M1. When the MOS tube M1 is turned on, it will supply the capacitor C LC1 With capacitor C st1 Charge.

[0032] Since the doping types of MOS tubes M1 and M2 are different, and their specifications and sizes correspond to each other, and their conductivity is the same, the voltage deviation caused by the feed-through effect of MOS tube M1 during operation and the voltage deviation caused by the feed-through effect of MOS tube M2 during operation can offset each other, and the liquid crystal capacitor C LC1 The actual charging voltage is consistent with the source signal Source provided by the driver chip, which can effectively avoid problems such as screen flickering caused by voltage deviation, improve display stability and significantly enhance display quality.

[0033] Figure 2A schematic diagram illustrates a display device according to an embodiment of the present invention. Taking a 1080P display device as an example, the display circuit of the display device includes 1080 rows of display cells. Each row of display cells is driven and controlled by gate drive signals Gate1, Gate2, ..., Gate1080, respectively. Each row includes, for example, 1920 display cells. Accordingly, the correction circuit of the display device also includes 1920 correction cells, each corresponding to a column of display cells. Timing control enables the correction circuit of a single row to correct all 1080 rows of display cells. Specifically, a data signal (source signal Source) is provided by a driver chip and passed through the corresponding correction cell before entering the Data Line of the corresponding column, providing the corresponding data signal to the display cells in that column. The gates of the MOS transistors in the correction cells are controlled by a clock signal Clk provided by the driver chip. The driver chip is located at the bottom of the display device, for example. The correction circuit is located between the driver chip and the display circuit. The display circuit is located within the display area indicated by the red frame. The correction circuit is located outside the display area. Specifically, the correction circuit is located within the display frame to prevent it from affecting the display area. The doping type of the MOS tube in the display circuit is opposite to that of the MOS tube in the correction circuit. For example, the MOS tubes in the display circuit are all N-type MOS tubes, and the MOS tubes in the correction circuit are all P-type MOS tubes. The correction circuit has the same parasitic capacitance Cgd and liquid crystal capacitance C as the display circuit. LC And the storage capacitor C st , the clock signal Clk is used to control the correction circuit, see Figure 3 As shown, G1, G2, G3, and G4 respectively show the waveforms of the gate drive signals in the first to fourth rows of display units. The clock signal Clk is, for example, a drive signal of a MOS tube in a correction circuit. Specifically, the frequency of the clock signal Clk = Vtotal * refresh rate, where Vtotal refers to the drive voltage Vdata (the liquid crystal capacitor C LC1 voltage) and the storage capacitor C st1 The refresh rate refers to the refresh rate of the display device. Through this timing design, the correction circuit of a single row can correct the display circuits of multiple rows.

[0034] The correction circuit provided by the present invention is used to improve the voltage deviation problem of the data signal of the display unit caused by the feedthrough effect. Taking a single display unit as an example, the factors affecting the voltage value Vft of the voltage deviation caused by the feedthrough effect are explained. Figure 4a and Figure 4b ,in, Figure 4a A schematic diagram showing a display unit when the gate is open and the MOS tube is turned on; Figure 4bA schematic diagram showing a display unit when the gate is closed and the MOS tube is turned off;

[0035] According to the law of conservation of charge:

[0036] (Vd1-Vg1)*Cgd+(Vd1-Vcom)*(Clc+Cs)=(Vd2-Vg2)*Cgd+(Vd2-Vcom)*(Clc+Cs)

[0037] Therefore, Vft=Vd2-Vd1=(Vg2-Vg1)*Cgd / (Cgd+Clc+Cs)

[0038] Among them, Vd1 is the display voltage when the MOS tube is turned on, Vg1 is the gate voltage when the MOS tube is turned on, Cgd is the capacitance generated by the overlapping area of the gate and the drain, Vcom is the common voltage, Clc is the liquid crystal capacitance, and Cs is the capacitance generated by the overlapping area of the pixel electrode and the common electrode.

[0039] Figure 5a and Figure 5b Waveforms of voltages at each end of an N-type MOS transistor and a P-type MOS transistor in a display device according to an embodiment of the present invention are shown respectively, thereby illustrating the influence of the feedthrough effect on the N-type MOS transistor and the P-type MOS transistor.

[0040] Specifically, see Figure 5a As shown in FIG, for example, it is a waveform diagram of the voltage at each end of an N-type MOS tube, wherein the green solid line is the source voltage, the orange solid line is the gate voltage, the dark blue solid line is the drain voltage, the black solid line is the common voltage, and the dark blue dotted line is the common voltage corrected to eliminate the influence of the feedthrough effect. Figure 5a As can be seen from the figure, when the gate voltage of the N-type MOS tube is high, the source and drain are connected and start to charge the liquid crystal capacitor. When the gate voltage is low, the charging stops and enters the voltage maintenance stage. Due to the existence of the feedthrough effect, the drain voltage in the maintenance stage will deviate downward compared to the corresponding source voltage.

[0041] See also Figure 5b As shown, it is a waveform diagram of the voltage at each end of a P-type MOS tube, where the green solid line is the source voltage, the light blue solid line is the gate voltage, the red solid line is the drain voltage, the black solid line is the common voltage, and the red dotted line is the common voltage corrected to eliminate the influence of the feedthrough effect. Figure 5b As can be seen from the figure, when the gate voltage of the P-type MOS tube is at a low level, the source and drain are connected and start to charge the liquid crystal capacitor. When the gate voltage is at a high level, the charging stops and enters the voltage maintenance stage. Due to the existence of the feedthrough effect, the drain voltage in the maintenance stage will deviate upward compared to the corresponding source voltage.

[0042] Take the MOS tube of the display unit as an N-type tube and the MOS tube of the correction unit as a P-type tube as an example, see Figure 6a and Figure 6b The actual transmission path of the data signal (source signal Source) in the display device is generated by the driving unit, passed through the correction circuit, and then transmitted to the display circuit of the display area. Specifically, the display circuit of the display area includes multiple display units, M1 in each display unit is, for example, an N-type MOS transistor, and M2 in each correction unit in the correction circuit is, for example, a P-type MOS transistor. The source signal Source is, for example, ±5V, and the voltage deviation value Vft caused by the feedthrough effect is, for example, 1V. Figure 6a The blue square wave is for example the gate drive signal G1 of M1, and the red square wave is for example the corresponding liquid crystal capacitor C LC1 voltage; Figure 6b The blue square wave in the figure is, for example, the clock signal Clk, which serves as the gate drive signal of M2, and the red square wave is, for example, the corresponding liquid crystal capacitor C LC2 The black dotted line is, for example, the data signal sent by the driver chip.

[0043] Vft1 of M1=-(VGH-VGL)*Cgd / (Cgd+Clc+Cs)

[0044] Vft2 of M2=(VGH-VGL)*Cgd / (Cgd+Clc+Cs)

[0045] The correction unit uses a MOS tube with a doping type opposite to that of the MOS tube in the display unit and adopts a corresponding design to ensure that the Cgd and Cs of the correction unit are consistent with those of the display unit. The same process is used to ensure C LC with C st The voltage deviations caused by the feedthrough effect in the display unit and the correction unit are consistent, so that the voltage values are the same and opposite, thereby canceling each other out. Specifically, regarding the production of MOS transistors, the method for producing an N-type MOS transistor and its corresponding P-type MOS transistor on the same substrate can be referred to patent application publication number CN105489522A. The remaining process steps can be adjusted according to specific circumstances and will not be detailed here.

[0046] This invention integrates MOS transistors with opposite doping types corresponding to the display area on the same substrate to form a correction circuit. The parasitic capacitance, liquid crystal capacitance, and storage capacitance of the correction circuit and display circuit are strictly matched. This ensures that the voltage deviations caused by the feedthrough effect in the display unit and the correction unit are equal in magnitude and opposite in polarity, thereby canceling each other out. This design enables the data signal (source signal) to be accurately charged to the target potential, eliminating screen flicker caused by voltage deviation. It also eliminates the traditional common voltage regulation module, simplifying the driver chip design and the corresponding common voltage regulation module data programming steps.

[0047] The display device provided by the present invention, wherein the correction unit and the display unit are integrated using the same process, ensuring the consistency of the capacitance parameters, and having a timing design of driving multiple rows of display units by a single row of correction units, significantly reducing the circuit area occupied, improving the integration of the system, while avoiding frequent adjustments to the common voltage, and improving the stability and reliability of the display device. According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, based on the above description, many modifications and changes can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention.

Claims

1. A data signal correction circuit, characterized in that: include: a correction unit, wherein a plurality of correction units are arranged in a row and correspond to the display units of the display device; In which, a driver chip of the display device generates a data signal, and the data signal is transmitted to the corresponding display unit through a correction unit; the correction unit includes a second MOS transistor with a doping type opposite to that of the first MOS transistor in the display unit, and the second MOS transistor is matched with the first MOS transistor so that a voltage deviation generated by a feedthrough effect in the second MOS transistor is offset by a voltage deviation generated by the feedthrough effect in the first MOS transistor.

2. The data signal correction circuit according to claim 1, wherein: The correction unit includes: a second MOS transistor, wherein a first end of the second MOS transistor is connected to the driver chip to receive a data signal, a second end of the second MOS transistor is connected to a data line of the display unit to provide a source drive signal to the display unit, and a control end of the second MOS transistor is connected to the driver chip to receive a clock signal; a second liquid crystal capacitor, corresponding to the first liquid crystal capacitor in the display unit, wherein a first end of the second liquid crystal capacitor is connected to the second end of the second MOS transistor, and a second end of the second liquid crystal capacitor is connected to the common electrode; a second storage capacitor connected in parallel with the second liquid crystal capacitor, the second storage capacitor corresponding to the first storage capacitor in the display unit, a first end of the second storage capacitor connected to the second end of the second MOS transistor, and a second end of the second storage capacitor connected to the common electrode; The control ends of the second MOS transistors of the plurality of correction units are connected to each other and to the driving chip to receive the clock signal.

3. The data signal correction circuit according to claim 2, wherein: The parameters of the second liquid crystal capacitor match those of the first liquid crystal capacitor, and the parameters of the second storage capacitor match those of the first storage capacitor.

4. The data signal correction circuit according to claim 3, wherein: The first MOS transistor and the second MOS transistor are located on the same substrate, and the parasitic capacitance between the gate and the drain of the first MOS transistor and the second MOS transistor is the same.

5. The data signal correction circuit according to claim 4, wherein: The frequency of the clock signal matches the refresh rate of the corresponding display device.

6. A display device, characterized in that: include: A driver chip is connected to the display circuit and is used to provide data signals; A display circuit, wherein the display circuit has a plurality of display units, and each of the display units performs corresponding grayscale control according to the data signal; A correction circuit, wherein the correction circuit is as described in any one of claims 1 to 3, and the correction circuit is located between the driver chip and the display circuit; The data signal is generated by the driving unit, and is transmitted to the display circuit after passing through the correction circuit, so as to compensate for the feedthrough effect of the display circuit.

7. The display device according to claim 6, wherein: The display device also includes a display area, the display circuit is located in the display area, and each row of display units is controlled by a corresponding gate drive signal; the correction circuit is located outside the display area, and a single row of correction units provides corresponding data signals to multiple rows of display units through timing control.

8. The display device according to claim 7, wherein: The correction circuit is located in the frame area around the display area.

9. The display device according to claim 8, wherein: The first MOS tube of the display unit is an N-type MOS tube, and the second MOS tube of the correction unit is a P-type MOS tube.

10. The display device according to claim 9, wherein The P-type MOS tube of the correction unit and the N-type MOS tube of the display unit have the same conductivity and are manufactured through the same process.

Images