Anti-irradiation circuit of magnetic memory chip
By designing radiation-proof reading circuits in MRAM chips, using cross-coupled inverters and redundant storage node structures, the problem of CMOS logic circuits being susceptible to single-particle flip and double-node flip in a radiation environment is solved, and efficient radiation resistance and low-cost circuit design are achieved.
Patent Information
- Application Number
- CN202510604777.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-12
- Publication Date
- 2025-08-12
AI Technical Summary
The CMOS logic circuit of MRAM chip is susceptible to single-particle flip and double-node flip in the radiating environment, resulting in errors in reading information. The existing reinforcement methods have problems such as complex circuits, large area overhead and high power consumption.
An radiation-proof reading circuit is designed, including a cross-coupled inverter, a magnetic tunnel junction MTJ storage unit, a reference resistor and a specific connection MOS tube structure. By introducing redundant storage nodes and feedback circuits, the storage node state is restored within hundreds of picoseconds to prevent flip-diffusion.
Improves the performance of MRAM chips in resisting single-particle flip and dual-node flip, simplifies the circuit structure, reduces the number and power consumption of MOS tubes, and reduces costs.
Smart Images
Figure CN120472957A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a radiation protection circuit of a magnetic memory chip MRAM reading circuit. Background Art
[0002] With the increasing miniaturization driven by Moore's Law, the proportion of standby power consumed by traditional MOSFET-based DRAM and SRAM has increased, becoming a serious problem for computer memory chips. Magnetic random access memory (MRAM) utilizes electron spin to store information, eliminating the need for standby power consumption. It is currently the most promising candidate to replace SRAM and DRAM for large-scale applications. The memory cell of MRAM is a magnetic tunnel junction (MTJ), consisting of two ferromagnetic thin-film structures (typically multilayer films) sandwiched between an insulating oxide film (typically magnesium oxide). The spin orientations of the two ferromagnetic layers of the MTJ exhibit low resistance (Rp) and high resistance (Rap) when parallel and antiparallel, respectively, allowing them to store information "0" and "1." Typically, the resistance state is changed, i.e., information is written, by fixing the spin orientation of one ferromagnetic layer (the fixed layer) and changing the spin orientation of the other ferromagnetic layer (the free layer). Reading information is accomplished by reading the resistance of the MTJ. As the fundamental unit of information storage in MRAM memory chips, the MTJ utilizes magnetic effects rather than electrical charge to store data. Compared to systems that rely on charge storage, this provides inherent radiation immunity, meaning it is resistant to radiation exposure. MTJs exhibit excellent anti-interference properties, particularly in radiation environments, and are therefore widely used in high-radiation applications such as aerospace and military applications.
[0003] However, the MRAM chip as a whole still requires CMOS logic circuits to perform operations such as reading and writing information, so there is still a risk of being affected by radiation. Generally, STT-MRAM requires a larger pulse current (information writing energy or current) and a wider pulse wavelength (information writing time) to complete information writing. Therefore, the information writing circuit is relatively insensitive to radiation, that is, it has strong radiation resistance. The information reading circuit, on the other hand, only requires a smaller pulse current (information writing energy or current) and a shorter pulse wavelength (information writing time). Therefore, when irradiated particles hit certain regions of the sense amplifier in the information reading circuit (usually the drain region of the cut-off NMOS or cut-off PMOS), they can cause single event upset (SEU) effects, single event transient (SET) effects, and double node upset (DNU) effects. This is because electron-hole pairs are generated in the semiconductor material. After being captured by the electric field, charge accumulates, which in turn generates an abnormal voltage pulse, causing the cut-off NMOS or PMOS to briefly turn on. This can corrupt the interlocked values in the cross-coupled inverters in the sense amplifier, causing an erroneous flip, resulting in read errors. This further causes errors in reading information from the MRAM chip storage array.
[0004] In order to improve the circuit's ability to resist radiation, traditional technologies mainly use reinforcement methods such as triple-mode redundancy (TMR) and DICE circuits. However, these methods have disadvantages such as more complex circuit structure, large area overhead, high power consumption, and high cost. Summary of the Invention
[0005] In view of the above background, the present invention proposes a radiation protection circuit for a magnetic memory chip MRAM to improve the performance against single event upset (SEU) and double node upset (DNU). The structural characteristics of the read circuit are as follows:
[0006] The read circuit of the radiation protection circuit includes an radiation protection unit, a first inverter consisting of a first NMOS transistor NM1 and a first PMOS transistor PM1, and a cross-coupling structure consisting of a second NMOS transistor NM2 and a second PMOS transistor PM2, a magnetic tunnel junction MTJ storage unit, a reference resistor Rref, and a fifth NMOS transistor NM5 having a gate connected to an external clock signal CLK, a source grounded, and a drain connected to an end of the magnetic tunnel junction MTJ storage unit that is different from the connection end of the reference resistor Rref and the radiation protection unit; a third PMOS transistor PM3 connected in parallel with the first PMOS transistor PM1 of the first inverter; and a fourth PMOS transistor PM4 connected in parallel with the second PMOS transistor PM2 of the second inverter; and the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 have a common source connected to a power supply VDD, and the gates of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are commonly connected to the external clock signal CLK.
[0007] Based on the above-mentioned radiation protection read circuit of the magnetic memory chip MRAM, the characteristics of the radiation protection unit are further defined as follows:
[0008] The radiation protection unit includes a third NMOS transistor NM3 whose drain is connected to the source of the first NMOS transistor NM1 of the first inverter and whose source is connected to the end of the magnetic tunnel junction MTJ storage unit not connected to the fifth NMOS transistor NM5, a fourth NMOS transistor NM4 whose drain is connected to the source of the second NMOS transistor NM2 of the second inverter and whose source is connected to the end of the reference resistor Rref not connected to the fifth NMOS transistor NM5, a fifth PMOS transistor PM5 whose source is connected to the drain of the first PMOS transistor PM1 of the first inverter and whose drain is grounded, a sixth PMOS transistor PM6 whose source is connected to the drain of the second PMOS transistor PM2 of the second inverter and whose drain is grounded, and a fourth NMOS transistor NM5 whose drain is connected to the source of the second NMOS transistor NM2 of the second inverter and whose source is connected to the end of the reference resistor Rref not connected to the fifth NMOS transistor NM5. The first inverter comprises a seventh PMOS transistor PM7 having a gate connected to the common power supply VDD and a drain connected to the gate of the fifth PMOS transistor PM5, the gate of the third NMOS transistor NM3, and the source of the second NMOS transistor NM2; and an eighth PMOS transistor PM8 having a source connected to the common power supply VDD and a drain connected to the gate of the sixth PMOS transistor PM6, the gate of the fourth NMOS transistor NM4, and the source of the first NMOS transistor NM1. The gate of the seventh PMOS transistor PM7 is connected to the drain of the first NMOS transistor NM1 of the first inverter, and the gate of the eighth PMOS transistor PM8 is connected to the drain of the second NMOS transistor NM2 of the second inverter.
[0009] Based on the aforementioned radiation protection read circuit of the magnetic memory chip MRAM, the structural features of the radiation protection unit are further defined as follows:
[0010] The radiation protection unit includes a third NMOS transistor NM3 whose drain is connected to the source of the first NMOS transistor NM1 of the first inverter and whose source is connected to the end of the magnetic tunnel junction MTJ storage unit that is not connected to the fifth NMOS transistor NM5, a fourth NMOS transistor NM4 whose drain is connected to the source of the second NMOS transistor NM2 of the second inverter and whose source is connected to the end of the reference resistor Rref that is not connected to the fifth NMOS transistor NM5, and a fourth NMOS transistor NM5 whose source is connected to the common power supply VDD and whose drain is connected to the third NMOS transistor NM6. The inverter comprises a seventh PMOS transistor PM7 having a gate connected to the fourth NMOS transistor NM4 and a source connected to the first NMOS transistor NM1, and an eighth PMOS transistor PM8 having a source connected to the common power supply VDD and a drain connected to the gate of the fourth NMOS transistor NM4 and the source of the first NMOS transistor NM1. The gate of the seventh PMOS transistor PM7 is connected to the drain of the first NMOS transistor NM1 of the first inverter, and the gate of the eighth PMOS transistor PM8 is connected to the drain of the second NMOS transistor NM2 of the second inverter.
[0011] The following supplementary explanations are provided for the above content:
[0012] In the above circuit, the cross-coupling nodes of the inverters are the first storage node Q and the second storage node Qb, respectively. The first storage node Q and the second storage node Qb are interlocked nodes. The drain region of the first NMOS transistor NM1 of the first inverter is the first storage node Q, and the drain region of the second NMOS transistor NM2 connected to the second inverter is the second storage node Qb. Both Q and Qb are regions that are susceptible to radiation and flip. In addition, the gate of the fourth NMOS transistor NM4 is connected to the drain of the third NMOS transistor NM3, and the connection region is the S node. The gate of the third NMOS transistor NM3 is connected to the drain of the fourth NMOS transistor NM4, and the connection region is the Sb node. The above-mentioned S and Sb are also sensitive regions of the circuit that are easily affected by radiation.
[0013] During the rising clock edge of a "1" read operation, the sensitive nodes Q(S) and Qb(Sb) store "1" and "0," respectively. For DNU, we consider the case where a pair of nodes, QS, Q-Sb, Qb-S, Qb-Sb, or S-Sb, flip simultaneously. Node Sb is at a stable low voltage because it is connected to an NMOS transistor. Therefore, the recovery mechanisms for flipped Q-Sb, Qb-Sb, and S-Sb are similar to those for SEU (i.e., sensitive nodes Q, Qb, and S).
[0014] During the rising clock edge of a "0" read operation, the sensitive nodes Q(S) and Qb(Sb) store "0" and "1," respectively. For DNU, we consider the case where a pair of nodes, QS, Q-Sb, Qb-S, Qb-Sb, or S-Sb, flip simultaneously. Node S is at a stable low voltage because it is connected to an NMOS transistor. Therefore, the recovery mechanism for flipped QS, Qb-S, and S-Sb is similar to that for SEU (i.e., sensitive nodes Q, Qb, and S).
[0015] The radiation hardening method used in the above circuit is to introduce redundant storage nodes. After a single particle is incident, there are still nodes in the storage unit that have not been flipped. The state of the storage node can be restored through the feedback circuit. That is, the hardened structure can prevent SEU and DNU from further spreading to other sensitive nodes, and use feedback to charge / discharge the impacted nodes, quickly restoring the initial state within hundreds of picoseconds.
[0016] For the sensitive nodes Q, Qb, S, and Sb mentioned above, the mechanism of protecting against radiation is described as follows:
[0017] When a particle strikes sensitive node Qb, it changes from "0" to "1." Node Qb is connected to the gates of the first and eighth PMOS transistors PM1 and PM8, which are now turned off. Because the MTJ storage cell is in a high-resistance state and difficult to discharge instantly, nodes Q and S remain in their initial "1" state. Because Q and S remain "1," the second and fourth NMOS transistors NM2 and NM4 remain on, so node Qb is discharged back to "0" by the second and fourth NMOS transistors NM2 and NM4.
[0018] In addition, the resistance value of the reference resistor Rref is the average of the low resistance state resistance (RP) and the high resistance state resistance (RAP) of the magnetic tunnel junction MTJ, that is, the reference resistor Rref is usually fixed at (RAP+RP) / 2, so that the sensing margin when the sense amplifier reads "0" and reads "1" is as similar as possible to improve the accuracy of reading and writing. However, depending on the actual situation, the resistance value of the reference resistor Rref here can deviate from (RAP+RP) / 2. In addition, in order to reduce the impact of the process, the reference resistor here can also be implemented by connecting the two states of the MTJ in parallel or in other ways.
[0019] The advancement of the present invention lies in: the above-mentioned circuit can simultaneously improve the circuit's performance against single-particle upsets and double-node upsets. Compared with traditional reinforcement methods such as triple-mode redundancy and DICE circuits, the structure is relatively simple, the space occupied is further reduced, the power consumption generated by the smaller number of MOS tubes is relatively low, and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a schematic diagram of the structure of a radiation-proof read circuit for a magnetic memory chip MRAM provided by the present invention, one of the embodiments of the present invention. 1 is a schematic diagram of the overall structure of the radiation-proof read circuit, and 2 (in the dotted box) is the radiation-proof unit.
[0021] Figure 2 This is one embodiment of the present invention, that is, a structural diagram of another magnetic memory chip MRAM radiation protection read circuit provided by the present invention, that is, changing Figure 1 1a is a schematic diagram of the overall structure of the radiation protection read circuit, and 2b (in the dotted box) is the radiation protection unit.
[0022] Figure 3 This is a circuit structure diagram of one embodiment of the present invention, namely a traditional pre-charged sense amplifier.
[0023] Figure 4 This is a waveform diagram of the radiation-proof reading circuit provided by the present invention reading "1" in the absence of external radiation.
[0024] Figure 5 This is a waveform diagram of the radiation-proof reading circuit provided by the present invention reading "0" in the absence of external radiation.
[0025] Figure 6 This is a schematic diagram of the waveform of the "1" reading operation of the pre-charged sense amplifier circuit provided by the present invention.
[0026] Figure 7 This is a schematic diagram of the waveform of the "0" reading operation of the pre-charged sense amplifier circuit provided by the present invention.
[0027] Figure 8 This is a waveform diagram of the radiation-proof reading circuit provided by the present invention reading "1" under external radiation.
[0028] Figure 9 This is a waveform diagram of the radiation-proof reading circuit provided by the present invention when reading "0" under external radiation.
[0029] Figure 10 This is a schematic diagram of the structure of the radiation-proof reading circuit provided by the present invention in a chip. DETAILED DESCRIPTION
[0030] The present invention will be described below with reference to the accompanying drawings and by way of examples of embodiments.
[0031] The read circuit of the memory chip MRAM is vulnerable to SEU and DNU attacks. The present invention proposes a radiation-proof read circuit for the magnetic memory chip MRAM, which improves the performance against single event upset (SEU) and double node upset (DNU). The number of MOS tubes is relatively small, the circuit structure is relatively simple, and the read reliability is high. The following is a description of the embodiment:
[0032] Example 1:
[0033] like Figure 1 The read circuit of the illustrated radiation protection circuit primarily adds a radiation protection unit (see dashed box 2) to a conventional pre-charge sense amplifier. The conventional pre-charge sense amplifier structure comprises the following components: a cross-coupling structure comprising a first inverter formed by a first NMOS transistor NM1 and a first PMOS transistor PM1, a second inverter formed by a second NMOS transistor NM2 and a second PMOS transistor PM2, a magnetic tunnel junction (MTJ) memory cell, a reference resistor Rref, a fifth NMOS transistor NM5 having a gate connected to an external clock signal CLK, a source grounded, and a drain connected to a terminal of the magnetic tunnel junction (MTJ) memory cell connected to the reference resistor Rref that is different from the terminal connected to the radiation protection unit, a third PMOS transistor PM3 connected in parallel with the first PMOS transistor PM1 of the first inverter, and a fourth PMOS transistor PM4 connected in parallel with the second PMOS transistor PM2 of the second inverter. Moreover, in the above part, the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 have their common sources connected to the power supply VDD, and the gates of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are commonly connected to the external clock signal CLK.
[0034] Figure 1The radiation protection unit in the dotted box is composed of four PMOS tubes and two NMOS tubes, specifically: a third NMOS tube NM3 whose drain is connected to the source of the first NMOS tube NM1 of the first inverter and whose source is connected to the end of the magnetic tunnel junction MTJ not connected to the fifth NMOS tube NM5, and a fourth NMOS tube NM4 whose drain is connected to the source of the second NMOS tube NM2 of the second inverter and whose source is connected to the end of the reference resistor Rref not connected to the fifth NMOS tube NM5, and a fifth NMOS tube NM5 whose source is connected to the drain of the first PMOS tube PM1 of the first inverter and whose drain is grounded. a PMOS transistor PM5, a sixth PMOS transistor PM6 having a source connected to the drain of the second PMOS transistor PM2 of the second inverter and a drain grounded, a seventh PMOS transistor PM7 having a source connected to the common power supply VDD and a drain connected to the gate of the fifth PMOS transistor PM5, the gate of the third NMOS transistor NM3, and the source of the second NMOS transistor NM2, and an eighth PMOS transistor PM8 having a source connected to the common power supply VDD and a drain connected to the gate of the sixth PMOS transistor PM6, the gate of the fourth NMOS transistor NM4, and the source of the first NMOS transistor NM1. The gate of the seventh PMOS transistor PM7 is connected to the drain of the first NMOS transistor NM1 of the first inverter, and the gate of the eighth PMOS transistor PM8 is connected to the drain of the second NMOS transistor NM2 of the second inverter.
[0035] The resistance value of the reference resistor Rref is the average of the low resistance state resistance (RP) and the high resistance state resistance (RAP) of the magnetic tunnel junction MTJ. That is, the reference resistor Rref is often fixed at (RAP+RP) / 2, so that the sensing margin when the sense amplifier reads "0" and reads "1" is as similar as possible to improve the accuracy of reading and writing. Usually, in order to avoid the influence of process fluctuations, the reference resistor can also be formed by connecting the MTJ in the low resistance state and the high resistance state in parallel. It is also possible to select a resistance between the low resistance state resistance (RP) and the high resistance state resistance (RAP) as the reference resistor Rref according to the actual process.
[0036] In addition, the MTJ can be used to read information from an MRAM in an STT write mode, that is, the present invention is applicable to STT-MRAM. In an actual chip, a large number of MTJ storage cells share the radiation protection circuit proposed by the present invention.
[0037] The specific principle of the above circuit's radiation protection is as follows: This circuit utilizes a pair of cross-coupled inverters to store data. The sensitive nodes can be Q, Qb, S, and Sb. During the rising clock edge of a "1" read operation, nodes Q(S) and Qb(Sb) store "1" and "0," respectively. For DNU, we consider the case where a pair of nodes, QS, Q-Sb, Qb-S, and Qb-Sb, flip simultaneously. Node Sb is at a stable low voltage because it is connected to a conducting NMOS transistor. Therefore, the recovery mechanism for flipped Q and Qb-Sb is similar to that of SEU (i.e., sensitive nodes Q, Qb, and S).
[0038] During the rising edge of the clock during a read "1" operation, nodes Q and S store "1," while nodes Qb and Sb store "0." Output Sb is a stable low voltage, unaffected by SEUs, because the NMOS transistor (NM4) it connects to is on. In this case, the sensitive nodes are Q, Qb, and S. When a particle strikes sensitive node Qb, it changes from "0" to "1." Node Qb is connected to the gates of the first and eighth PMOS transistors PM1 and PM8, which are now off. Because the MTJ memory cell is in a high-resistance state and difficult to discharge instantly, nodes Q and S remain in their initial "1" state. Because Q and S remain "1," the second and fourth NMOS transistors NM2 and NM4 remain on, allowing node Qb to discharge through them.
[0039] Similarly, when a particle strikes sensitive node Q, it changes from "1" to "0." Node Q is connected to the gates of the second PMOS transistor PM2 and the second NMOS transistor NM2, turning off the second NMOS transistor NM2. Nodes Qb and S, however, remain in their initial states, and the first PMOS transistor PM1 remains on, quickly charging node Q to "1."
[0040] When a particle strikes sensitive node S, it changes from "1" to "0." Node S0 is connected to the gate of the fourth NMOS transistor NM4 and the drain of the eighth PMOS transistor PM8, turning off the fourth NMOS transistor NM4. Nodes Q, Qb, and Sb remain in their initial states. The eighth PMOS transistor PM8 remains on, charging node S. Node S returns to "1," leaving no impact on the states of nodes Q and Qb.
[0041] If nodes Q and S are hit by DNU, they become "0" and "0" respectively. Since node Q is connected to the gates of the second PMOS transistor PM2 and the second NMOS transistor NM2, nodes Qb and Sb remain in their initial states and the first PMOS transistor PM1 is in the turned-on state, causing node Q to quickly charge to "1".
[0042] If nodes Qb and S are hit by DNU, they become "1" and "0" respectively. At this time, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off, and the fourth NMOS transistor NM4 is turned off. Nodes Q and Sb remain in their initial states. At this time, the sixth PMOS transistor PM6 is turned on to discharge node Qb, and node Qb returns to "0". Node S has no effect on the states of Q and Qb.
[0043] If nodes S and S0 are hit by DNU, they become "0" and "1" respectively. At this time, the sixth PMOS transistor PM6 is in the on state, and nodes Q and Qb remain in the initial state, so there is no impact on the states of nodes Q and Qb.
[0044] Since the circuit has a symmetrical structure, the protection of the sensitive nodes Q, Qb, and Sb during the rising edge of the clock in the read "0" operation is similar to the above, so it will not be described in detail.
[0045] Example 2:
[0046] like Figure 2 The read circuit of the radiation protection circuit shown is mainly based on the traditional pre-charge sense amplifier with the radiation protection unit in the dotted box 3. Figure 1 The specific structure of the radiation protection unit is that the radiation protection unit is composed of four MOS tubes, namely, a third NMOS tube NM3, a fourth NMOS tube NM4, a seventh PMOS tube PM7, and an eighth PMOS tube PM8, and other structures remain unchanged.
[0047] Example 3:
[0048] Figure 3 It is the structure of precharge sense amplifier, and its specific structure is similar to Figure 1 and Figure 2 Similarly, the principle is as follows: this circuit requires two steps to complete the read operation. Initially, the clock level CLK is set to "0", the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are turned on, and the fifth NMOS transistor NM5 is turned off. Nodes Q and Qb are charged to "1" during the precharge phase. Then, the clock level CLK is set to "1", the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are turned off, and the fifth NMOS transistor NM5 is turned on, and nodes Q and Qb begin to discharge. During the discharge state, due to the different resistances of the MTJ and the reference resistor Rref (for example, MTJ > Rref), the discharge rates of the two paths are different. When Qb first discharges to "0", the first PMOS transistor PM1 is turned on, at which point the potential Q is pulled to "1". The values of Q and Qb can be read by peripheral circuitry to retrieve the information stored in the cell.
[0049] Example 4:
[0050] Figure 4 This is a waveform diagram of the radiation-resistant read circuit provided by the present invention during a normal "1" read operation in the absence of external radiation. CLK is the clock signal, and State1 and State2 represent the states of the magnetic tunnel junction (MTJ) memory cell and reference resistor Rref, respectively, during the rising edge of the read "1" clock. Before the rising clock edge arrives, the circuit completes precharge, at which point nodes Q, Qb, S, and Sb are all "1." After the rising clock edge arrives, nodes Q and S are all "1," while nodes Qb and Sb are all "0," allowing the circuit to achieve a normal "1" read operation.
[0051] Figure 5 This is a waveform diagram of the radiation-resistant read circuit provided by the present invention during a normal "0" read operation in the absence of external radiation. CLK is the clock signal, and State1 and State2 represent the states of the magnetic tunnel junction (MTJ) memory cell and reference resistor Rref, respectively, during the rising edge of the read "0" clock. Before the rising clock edge arrives, the circuit completes precharge, at which point nodes Q, Qb, S, and Sb are all "1." After the rising clock edge arrives, nodes Q and S are "0," and nodes Qb and Sb are "1," allowing the circuit to achieve a normal "0" read operation.
[0052] Figure 6 This is a schematic diagram of the waveforms for the precharged sense amplifier circuit of the present invention during a "1" read operation. CLK represents the clock signal, and State1 and State2 represent the states of the magnetic tunnel junction (MTJ) memory cell and reference resistor Rref, respectively, during the rising edge of the read "1" clock. Before the rising clock edge arrives, the circuit completes precharging, and nodes Q, Qb, S, and Sb are all "1." After the rising clock edge arrives, node Q is "1," and nodes Qb, S, and Sb are all "0," allowing the circuit to perform a normal "1" read operation.
[0053] Figure 7 This is a schematic diagram of the waveforms for the precharged sense amplifier circuit described in the present invention during a read "0" operation. CLK represents the clock signal, and State1 and State2 represent the states of the magnetic tunnel junction (MTJ) memory cell and reference resistor Rref, respectively, during the rising edge of the read "0" clock. Before the rising clock edge arrives, the circuit completes precharging, with nodes Q, Qb, S, and Sb at "1." After the rising clock edge arrives, node Qb is "1," while nodes Q, S, and Sb are "0," allowing the circuit to perform a normal read "0" operation.
[0054] Therefore, the radiation-proof reading circuit provided by the present invention can realize normal reading "1" and reading "0" operations without external radiation.
[0055] Figure 8This is a schematic diagram of the waveforms for the radiation-resistant read circuit of the present invention during a "1" read operation. CLK is the clock signal, and State1 and State2 represent the states of the magnetic tunnel junction (MTJ) memory cell and reference resistor Rref during the rising edge of the read "1" clock. Before the rising edge of the clock, the circuit completes precharging, and nodes Q, Qb, S, and Sb are all "1." After the rising edge of the clock, according to simulation results, pulse currents introduced to nodes Q, Qb, and S cause switching, but they quickly return to their original states, with nodes Q and S at "1" and nodes Qb and Sb at "0." Therefore, the circuit can achieve a normal "1" read operation.
[0056] Figure 9 This is a schematic diagram of the waveforms for the radiation-resistant read circuit of the present invention during a "0" read operation. CLK is the clock signal, and State1 and State2 represent the states of the magnetic tunnel junction (MTJ) and reference resistor (Rref) during the rising edge of the read "0" clock. Before the rising edge of the clock, the circuit completes precharge, and nodes Q, Qb, S, and Sb are all "1." After the rising edge of the clock, simulation results show that pulsed currents introduced to Q, Qb, and Sb cause switching, but they quickly return to their original states, allowing the circuit to achieve a normal "0" read operation.
[0057] Figure 10 This is a schematic diagram of the structure of an MRAM radiation protection reading circuit in a chip provided by the present invention. Figure 10 As shown, the circuit structure mainly includes three parts: MTJ storage unit, radiation-resistant read circuit unit, and read driver unit. In actual chip applications, a large number of MTJ storage units can share the radiation-resistant circuit proposed by the present invention.
[0058] The MRAM radiation protection circuit provided in the embodiment of the present invention has a simple circuit structure, uses a small number of MOS tubes, further reduces the chip space occupied, and has low cost. It can solve the particle radiation problem in the circuit and improve the radiation resistance of the chip.
[0059] The above-described embodiments (including circuit layouts, etc.) merely represent certain implementations of the present invention. While the descriptions are relatively specific, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention's patent shall be determined by the appended claims.
Claims
1. A radiation protection circuit for a magnetic memory chip, wherein the read circuit thereof has the following structural features: The read circuit of the radiation protection circuit includes an radiation protection unit, a first inverter consisting of a first NMOS transistor NM1 and a first PMOS transistor PM1, and a cross-coupling structure consisting of a second NMOS transistor NM2 and a second PMOS transistor PM2, a magnetic tunnel junction MTJ storage unit, a reference resistor Rref, and a fifth NMOS transistor NM5 having a gate connected to an external clock signal CLK, a source grounded, and a drain connected to an end of the magnetic tunnel junction MTJ storage unit that is different from the connection end of the reference resistor Rref and the radiation protection unit; a third PMOS transistor PM3 connected in parallel with the first PMOS transistor PM1 of the first inverter; and a fourth PMOS transistor PM4 connected in parallel with the second PMOS transistor PM2 of the second inverter; and the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 have a common source connected to a power supply VDD, and the gates of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are commonly connected to the external clock signal CLK.
2. The radiation protection circuit for a magnetic memory chip according to claim 1, wherein: The radiation protection unit includes a third NMOS transistor NM3 whose drain is connected to the source of the first NMOS transistor NM1 of the first inverter and whose source is connected to the end of the magnetic tunnel junction MTJ storage unit not connected to the fifth NMOS transistor NM5, a fourth NMOS transistor NM4 whose drain is connected to the source of the second NMOS transistor NM2 of the second inverter and whose source is connected to the end of the reference resistor Rref not connected to the fifth NMOS transistor NM5, a fifth PMOS transistor PM5 whose source is connected to the drain of the first PMOS transistor PM1 of the first inverter and whose drain is grounded, a sixth PMOS transistor PM6 whose source is connected to the drain of the second PMOS transistor PM2 of the second inverter and whose drain is grounded, and a fourth NMOS transistor NM5 whose drain is connected to the source of the second NMOS transistor NM2 of the second inverter and whose source is connected to the end of the reference resistor Rref not connected to the fifth NMOS transistor NM5. The first inverter comprises a seventh PMOS transistor PM7 having a gate connected to the common power supply VDD and a drain connected to the gate of the fifth PMOS transistor PM5, the gate of the third NMOS transistor NM3, and the source of the second NMOS transistor NM2; and an eighth PMOS transistor PM8 having a source connected to the common power supply VDD and a drain connected to the gate of the sixth PMOS transistor PM6, the gate of the fourth NMOS transistor NM4, and the source of the first NMOS transistor NM1. The gate of the seventh PMOS transistor PM7 is connected to the drain of the first NMOS transistor NM1 of the first inverter, and the gate of the eighth PMOS transistor PM8 is connected to the drain of the second NMOS transistor NM2 of the second inverter.
3. The radiation protection circuit for a magnetic memory chip according to claim 1, wherein: The radiation protection unit includes a third NMOS transistor NM3 whose drain is connected to the source of the first NMOS transistor NM1 of the first inverter and whose source is connected to the end of the magnetic tunnel junction MTJ storage unit that is not connected to the fifth NMOS transistor NM5, a fourth NMOS transistor NM4 whose drain is connected to the source of the second NMOS transistor NM2 of the second inverter and whose source is connected to the end of the reference resistor Rref that is not connected to the fifth NMOS transistor NM5, and a fourth NMOS transistor NM5 whose source is connected to the common power supply VDD and whose drain is connected to the third NMOS transistor NM6. The inverter comprises a seventh PMOS transistor PM7 having a gate connected to the fourth NMOS transistor NM4 and a source connected to the first NMOS transistor NM1, and an eighth PMOS transistor PM8 having a source connected to the common power supply VDD and a drain connected to the gate of the fourth NMOS transistor NM4 and the source of the first NMOS transistor NM1. The gate of the seventh PMOS transistor PM7 is connected to the drain of the first NMOS transistor NM1 of the first inverter, and the gate of the eighth PMOS transistor PM8 is connected to the drain of the second NMOS transistor NM2 of the second inverter.