A chip testing method
By screening out faulty memory cells during chip testing and prohibiting their erasure operations, the problem of writing '00' to an entire row of memory cells due to leakage current is prevented, thus solving the quality problem of an entire row of memory cells in chip production and improving the quality and reliability of the chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2025-04-29
- Publication Date
- 2026-07-10
AI Technical Summary
In the chip manufacturing process, failed gate flash memory cannot be effectively screened, leading to quality problems of the entire array of memory cells during subsequent erase operations. Existing technology cannot effectively prevent the entire array of memory cells from being written with '00'.
During chip testing, after identifying memory cells that have failed to be erased, erasure operations on them are prohibited, and '00' is written to all memory cells in the abnormal sector to prevent the entire column of memory cells from being written with '00' due to leakage.
By preventing write interference caused by leakage current in faulty memory cells due to abnormal sectors, the quality and reliability of the chip are improved, and the risk to end users is reduced.
Smart Images
Figure CN120472967B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a chip testing method. Background Technology
[0002] During chip manufacturing, a small number of defective chips may occur due to process or design issues. If these defective chips cannot be effectively identified and reach the customer, it will increase the difficulty and cost of resolving the problem later. Gate-separated flash memory (DSRAM) is a component within a chip, and its failure can directly cause the failure of the entire chip. Multiple DRAMs may exist simultaneously on a single wafer, arranged in multiple rows and columns. Please refer to [reference needed]. Figure 1 The gate-divided flash memory includes: a substrate 101; a gate oxide layer 102 and a source line polysilicon 103, the gate oxide layer 102 and the source line polysilicon 103 being located on the substrate 101, the gate oxide layer 102 being located on both sides of the source line polysilicon 103; a floating gate 104, the floating gate 104 being located on a portion of the surface of the gate oxide layer 102; a first sidewall 105 and a second sidewall 106, the first sidewall 105 being located on the surface of the floating gate 104, the second sidewall 106 being located between the source line polysilicon 103 and the first sidewall 105, the floating gate 104 and the gate oxide layer 102; a word line polysilicon 107, the word line polysilicon 107 being separated from the floating gate 104, the first sidewall 105 and the surface of the substrate 101 by a tunneling oxide layer 108; and a word line sidewall 109, the word line sidewall 109 being located on the surface of the substrate 201 and covering the sidewalls of the word line polysilicon 107 and the tunneling oxide layer 108. Adjacent memory cells are separated by a channel 200. Various anomalies may occur during the fabrication of gate-based flash memory, such as... Figure 2 The floating gate 104 on the right side of the word line polysilicon 107 has an abnormal morphology. The floating gate 104 on the right side of the word line polysilicon 107 was less etched during the formation process, so the polysilicon that should have been etched was not etched. As a result, the floating gate 104 is too close to the channel 200, which may cause channel leakage.
[0003] The existing method for screening gate flash memories with abnormal floating gate morphology involves determining that the memory cell is faulty during the first erase test and adding it to the repair area. Then, the gate flash memory in the repair area is repaired.
[0004] However, during subsequent chip testing, the erase operation still erases the sector containing the failed memory cell, potentially causing the failed memory cell to be gradually and completely erased. This leads to the opening of the channel next to the failed memory cell. The opening of the channel causes the suppression voltage of the entire row of memory cells to be pulled low, resulting in the entire row of memory cells being written with "00", thus causing a serious quality problem. Summary of the Invention
[0005] The purpose of this invention is to provide a chip testing method that, after identifying memory cells that have failed erasure, prohibits erasure operations on these failed memory cells during chip testing. This prevents the opening of channels adjacent to the failed memory cells, prevents the suppression voltage of the entire array of memory cells from being pulled low, and prevents the entire array of memory cells from being written with "00", thereby improving chip quality.
[0006] To achieve the above objectives, the present invention provides a chip testing method, comprising:
[0007] A chip to be tested is provided, the chip including multiple memory cells in multiple rows and columns, the word lines of each row of memory cells are connected, the bit lines of each column of memory cells are connected, and 2N adjacent rows of memory cells form a sector, where N is a positive integer greater than or equal to 1, and multiple rows of memory cells form multiple sectors.
[0008] The erase test is performed sequentially on multiple sectors, and it is determined whether there are any sectors with abnormal erase test results.
[0009] If there are sectors that fail the erase test, they are considered abnormal sectors.
[0010] Write "00" to all memory cells contained in the abnormal sector;
[0011] Erase non-abnormal sectors; at this time, erase abnormal sectors are prohibited from being erased.
[0012] Optionally, in the chip testing method, the multiple sectors are sequentially erased according to the address of the storage unit.
[0013] Optionally, in the chip testing method, the method for sequentially performing erase tests on multiple sectors and determining whether there are any sectors with erase test anomalies includes:
[0014] S11: Perform an erase test on the sector;
[0015] S12: Read the value of the storage cell after the erase test;
[0016] S13: Determine the value read from the storage unit. If the read value is 0, the erase test of the storage unit is considered abnormal.
[0017] S14: Repeat steps S11 to S13 to obtain the values after reading all storage units. If the erase test of at least one of the storage units is abnormal, the erase test of the sector where the storage unit is located is considered to be abnormal.
[0018] Optionally, in the chip testing method, if there is no storage unit with an abnormal erasure test, the chip passes the test.
[0019] Optionally, in the chip testing method, the sector includes two rows of storage units.
[0020] Optionally, in the chip testing method, the storage unit includes:
[0021] A substrate;
[0022] A gate oxide layer and a source line polysilicon, the gate oxide layer and the source line polysilicon are respectively located on the substrate, and the gate oxide layer is located on both sides of the source line polysilicon;
[0023] A floating gate, the floating gate is located on the surface of part of the gate oxide layer;
[0024] A first sidewall and a second sidewall, the first sidewall is located on the surface of the floating gate, and the second sidewall is located between the source line polysilicon and the first sidewall, the floating gate, and the gate oxide layer;
[0025] A word line polysilicon, the word line polysilicon is located on the side of the first sidewall opposite to the source line polysilicon, and the word line polysilicon is separated from the floating gate and the first sidewall by a tunneling oxide layer;
[0026] A word line sidewall, the word line sidewall is located on the substrate surface and covers the sidewalls of the word line polysilicon and the tunneling oxide layer.
[0027] Optionally, in the chip testing method, there is a channel between adjacent storage units.
[0028] Optionally, in the chip testing method, the storage unit with an abnormal erasure test includes a storage unit with an abnormal floating gate morphology, and the storage unit with an abnormal floating gate morphology includes:
[0029] The area where the floating gate is located between the second sidewall and the word line sidewall exceeds a set value.
[0030] Optionally, in the chip testing method, the distance between the floating gate of the storage unit with an abnormal floating gate morphology and the channel is less than a set value.
[0031] The chip testing method provided by this invention includes: providing a chip to be tested, the chip comprising multiple memory cells arranged in multiple rows and columns, wherein the word lines of each row of memory cells are connected, the bit lines of each column of memory cells are connected, and adjacent 2N rows of memory cells form a sector, where N is a positive integer greater than or equal to 1, and multiple rows of memory cells form multiple sectors; performing erase tests on multiple sectors sequentially, and determining whether there are any sectors with erase test anomalies; if there are any sectors with erase test anomalies, they are designated as abnormal sectors; writing "00" to all memory cells contained in the abnormal sectors; and performing erase operations on non-abnormal sectors, while prohibiting erase operations on the abnormal sectors. This invention, by prohibiting erase operations on sectors containing failed memory cells during chip testing, prevents some memory cells in an entire column of memory cells from being written with "00" due to write interference caused by leakage current in the failed memory cells of abnormal sectors, thus improving chip quality. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the gate-separated memory structure;
[0033] Figure 2 This is a schematic diagram of a multi-gate memory with an unusual floating gate morphology;
[0034] Figure 3 This is a flowchart of a chip testing method according to an embodiment of the present invention;
[0035] Figure 4 This is a schematic diagram showing the distribution of multi-row, multi-column storage units according to an embodiment of the present invention;
[0036] In the figure: 101-substrate, 102-gate oxide layer, 103-source line polysilicon, 104-floating gate, 105-first sidewall, 106-second sidewall, 107-word line polysilicon, 108-tunneling oxide layer, 109-channel. Detailed Implementation
[0037] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0038] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0039] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0040] Please refer to Figure 3 This invention provides a chip testing method, comprising:
[0041] S1: Provide the chip to be tested. The chip includes multiple memory cells in multiple rows and columns. The word lines of each row of memory cells are connected, and the bit lines of each column of memory cells are connected. Adjacent 2N rows of memory cells form a sector, where N is a positive integer greater than or equal to 1. Multiple rows of memory cells form multiple sectors.
[0042] S2: Perform erase tests on multiple sectors sequentially and determine if there are any sectors with abnormal erase test results;
[0043] S3: If there are sectors that fail the erase test, they are considered abnormal sectors;
[0044] S4: Write "00" to all memory cells contained in the abnormal sector;
[0045] S5: Perform an erase operation on non-abnormal sectors. At this time, erase operations on abnormal sectors are prohibited.
[0046] In the embodiments of the present invention, please refer to Figure 1The memory cell includes: a substrate 101; a gate oxide layer 102 and a source line polysilicon 103, the gate oxide layer 102 and the source line polysilicon 103 being located on the substrate 101, the gate oxide layer 102 being located on both sides of the source line polysilicon 103; a floating gate 104, the floating gate 104 being located on a portion of the surface of the gate oxide layer 102; a first sidewall 105 and a second sidewall 106, the first sidewall 105 being located on the surface of the floating gate 104, and the second sidewall 106 being located between the source line polysilicon 103 and the first sidewall 106. Between one sidewall 105, the floating gate 104, and the gate oxide layer 102; word line polysilicon 107, located on the side of the first sidewall 105 opposite to the source line polysilicon 103, the word line polysilicon 107 is separated from the floating gate 104, the first sidewall 105, and the surface of the substrate 101 by a tunnel oxide layer 108; word line sidewall 109, located on the surface of the substrate 201 and covering the sidewalls of the word line polysilicon 107 and the tunnel oxide layer 108. A channel 200 is provided between adjacent memory cells. Please refer to... Figure 4 The chip comprises multiple memory cells arranged in multiple rows and columns. The source lines (polysilicon 103) of each row of memory cells are all connected, and the word lines (polysilicon 107) are all connected, for example, word line 0 and word line 1. Word line 0 and word line 1 share a single source line. The drain areas of each column of memory cells are all connected, for example, bit line 0 and bit line 1. Because it consists of multiple rows and columns, multiple row and column addresses are set, allowing the corresponding memory cell to be located based on the row and column addresses. Each memory cell has a unique address. Adjacent 2N rows of memory cells form a sector, where N is a positive integer greater than or equal to 1. Multiple rows of memory cells form multiple sectors.
[0047] Memory cells exhibiting abnormal erase test results may include those with abnormal floating gate topography. Abnormal floating gate topography includes instances where the area of the floating gate located on the second sidewall and word line sidewall exceeds a set value. This set value can be a predefined value, similar to that of a normal memory cell. If the floating gate area on the second sidewall and word line sidewall is excessively large, it may cause the word line polysilicon to connect to the floating gate. Furthermore, an excessively large floating gate area on the second sidewall and word line sidewall may cause the distance between the floating gate and the channel to be less than a set value. During the erase process, erase electrons may enter the channel, causing the channel to open.
[0048] In this embodiment of the invention, multiple sectors are sequentially erased according to the address of the storage unit. For example... Figure 4A sector can include two rows of memory cells. Word lines 0 and 1 can be used as the first sector, and word lines 2 and 3 can be used as the second sector. If the erase test fails for a memory cell on word line 0 or word line 1, the first sector is considered an abnormal sector. In step S4, all memory cells within the first sector (i.e., those on word lines 0 and 1) must be written with "00", not just the memory cells that failed the erase test. In the subsequent step S5, no further erase operations are performed on any memory cells in the first sector. This prevents the opening of channels next to failed memory cells during subsequent erase operations. Furthermore, writing "00" in advance further mitigates the risk of end-user write failures due to word line channel leakage, reducing the reliability risk for end-users.
[0049] In this embodiment of the invention, if the read value is 0, the erase test of the memory cell is considered normal. The memory cell undergoing the erase test does not need to be extracted. After all memory cells have undergone the erase test, if there are no memory cells with abnormal erase test results, the chip is considered to have passed this test and can proceed to the next functional test.
[0050] In this embodiment of the invention, the method for sequentially performing erase tests on multiple sectors and determining whether there are sectors with erase test anomalies includes: S11: performing an erase test on the sectors; S12: reading the value of the storage cell after the erase test; S13: determining the value of the read storage cell; if the read value is 0, the erase test of the storage cell is considered abnormal; if the read value is 1, the erase test of the storage cell is considered normal; S14: repeating steps S11 to S13 to obtain the values after reading all storage cells; if the erase test of at least one storage cell is abnormal, the sector containing that storage cell is considered to have an abnormal erase test. When the number of sectors with abnormal erase tests is greater than or equal to 1, it is considered that there are sectors with abnormal erase tests.
[0051] In summary, the chip testing method provided in this embodiment of the invention includes: providing a chip to be tested, the chip comprising multiple memory cells arranged in multiple rows and columns, wherein the word lines of each row of memory cells are connected, the bit lines of each column of memory cells are connected, and adjacent 2N rows of memory cells form a sector, where N is a positive integer greater than or equal to 1, and multiple rows of memory cells form multiple sectors; performing an erase test on the multiple sectors sequentially, and determining whether there are any sectors with erase test anomalies; if there are any sectors with erase test anomalies, they are designated as abnormal sectors; writing "00" to all memory cells contained in the abnormal sectors; and performing an erase operation on non-abnormal sectors, while prohibiting the erase operation on the abnormal sectors. This invention, by prohibiting the erase operation on the sectors containing the failed memory cells during chip testing, prevents some memory cells in an entire column of memory cells from being written with "00" due to write interference caused by leakage current in the failed memory cells of the abnormal sectors, thus improving chip quality.
[0052] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A chip testing method, characterized in that, Including: Providing a chip to be tested, the chip includes a plurality of memory cells arranged in multiple rows and columns. The word lines of the memory cells in each row are connected, and the bit lines of the memory cells in each column are connected. Adjacent 2N rows of memory cells form a sector, where N is a positive integer greater than or equal to 1, and multiple rows of memory cells form multiple sectors; Performing an erase test on multiple sectors in sequence and determining whether there is a sector with an abnormal erase test; If there is a sector with an abnormal erase test, it is regarded as an abnormal sector; Writing "00" to all memory cells included in the abnormal sector; Performing an erase operation on non-abnormal sectors. At this time, the erase operation on the abnormal sector is prohibited.
2. The chip testing method as described in claim 1, characterized in that, Performing an erase test on multiple sectors in sequence according to the addresses of the memory cells.
3. The chip testing method as described in claim 1, characterized in that, A method for performing an erase test on multiple sectors in sequence and determining whether there is a sector with an abnormal erase test includes: S11: Performing an erase test on the sector; S12: Reading the value of the memory cell after the erase test; S13: Determining whether to read the value of the memory cell. If the read value is 0, it is considered that the erase test of the memory cell is abnormal; S14: Looping steps S11 to S13 to obtain the values after reading all memory cells. If the erase test of at least one memory cell is abnormal, it is considered that the erase test of the sector where the memory cell is located is abnormal.
4. The chip testing method as described in claim 1, characterized in that, If there is no memory cell with an abnormal erase test, the chip test is qualified.
5. The chip testing method as described in claim 1, characterized in that, The sector includes 2 rows of memory cells.
6. The chip testing method as described in claim 1, characterized in that, The memory cell includes: A substrate; A gate oxide layer and source line polysilicon, the gate oxide layer and source line polysilicon are respectively located on the substrate, and the gate oxide layer is located on both sides of the source line polysilicon; A floating gate, the floating gate is located on the surface of part of the gate oxide layer; A first sidewall and a second sidewall, the first sidewall is located on the surface of the floating gate, and the second sidewall is located between the source line polysilicon and the first sidewall, floating gate, and gate oxide layer; Word line polysilicon, the word line polysilicon is located on the side of the first sidewall opposite to the source line polysilicon, and the word line polysilicon is separated from the floating gate and the first sidewall by a tunneling oxide layer; A word line sidewall, the word line sidewall is located on the substrate surface and covers the sidewalls of the word line polysilicon and the tunneling oxide layer.
7. The chip testing method as described in claim 6, characterized in that, There is a channel between adjacent memory cells.
8. The chip testing method as described in claim 7, characterized in that, Memory cells with abnormal erase tests include memory cells with abnormal floating gate morphology. The memory cells with abnormal floating gate morphology include: The area where the floating gate is located between the second sidewall and the word line sidewall exceeds a set value.
9. The chip testing method as described in claim 8, characterized in that, The distance between the floating gate of the memory cell with abnormal floating gate morphology and the channel is less than a set value.