Front-end circuits for data receivers and related systems, methods, and apparatus

Abstract

The invention discloses a front-end circuit for a data receiver and related systems, methods, and apparatus. The front-end circuit includes a passive equalizer including a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits a behavior substantially opposite the behavior of the first frequency response. The amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.

Description

[0001] This application is a divisional application of the patent application with an international application date of December 1, 2020, an international application number of PCT / US2020 / 070836, a Chinese national application date of December 1, 2020, an application number of 202080101133.1, and an invention name of "Front-end circuits for data receivers and related systems, methods and devices".

[0002] Priority Declaration

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 027,152, filed on May 19, 2020, and entitled “PROGRAMMABLE DATA RECEIVER FRONT ENDS HAVING PASSIVE EQUALIZERS AND RELATED SYSTEMS, METHODS, AND DEVICES,” under 35 U.S. Sc §119(e), the entire disclosure of which is hereby incorporated by reference into this document. Technical Field

[0004] The present disclosure relates generally to programmable data receiver front ends, and more particularly to a programmable data receiver having a passive equalizer and a programmable amplifier circuit. Background Art

[0005] As data rates increase, backplane channels in SerDes systems experience increased attenuation compared to systems using lower data rates. This results in the need for more equalization of the received data signal to prevent intersymbol interference and eye closure. A typical data channel can have losses exceeding 20 to 35 decibels (20dB-35dB) at the Nyquist frequency (half the baud rate). The result is "eye closure" at the receiver input. As a result, "zeros" and "ones" may not be distinguishable in the received signal.

[0006] One approach to channel equalization involves a programmable attenuator followed by one or more stages of continuous-time linear equalizers (CTLEs) based on differential pair amplifiers with configurable resistor-capacitor (Rc) degeneration, or analog finite impulse response (aFIR) equalizers. However, the inventors of the present disclosure recognized that active equalizers such as CTLEs require a pre-programmable attenuator with switches, which compromises signal integrity. For example, short channels require pre-attenuation to prevent overloading the CTLE. Additionally, active equalizers exhibit different properties at various equalizer settings, complicating design and system modeling. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] While the disclosure concludes with claims that particularly point out and distinctly claim specific embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is the circuit diagram of the Zobel network;

[0009] Figure 2 This is the circuit diagram of the second-order Zobel network;

[0010] Figure 3 is shown in response to the input signal, Figure 2 A frequency response graph of the top voltage potential VTOP and the bottom voltage potential VBOT of the second-order Zobel network;

[0011] Figure 4 is a block diagram of a data receiver according to some embodiments;

[0012] Figure 5 According to some embodiments, Figure 4 A circuit diagram of a passive equalizer for a data receiver;

[0013] Figure 6 According to some embodiments, Figure 4 A circuit diagram of an alternative passive equalizer for a data receiver;

[0014] Figure 7 According to some embodiments, Figure 4 A circuit diagram of a programmable amplifier circuit of a data receiver;

[0015] Figure 8 is shown plotted against frequency from Figure 4 A graph 800 illustrating an example of an equalized signal of a front-end circuit, wherein a signal input of the front-end circuit is electrically connected to a relatively short physical channel;

[0016] Figure 9 is shown plotted against frequency from Figure 4 a graph of an example of an equalized signal of a front-end circuit, wherein a signal input of the front-end circuit is electrically connected to a physical channel of medium length;

[0017] Figure 10 is a graph showing examples of a channel input signal curve, a channel output signal curve, and an equalized signal curve;

[0018] Figure 11 Shown with Figure 10 The eye diagram curves corresponding to the channel input signal curve, the channel output signal curve and the equalized signal curve; and

[0019] Figure 12 is a diagram illustrating the use of Figure 4 Flowchart of a method for equalizing an input signal in a front-end circuit. DETAILED DESCRIPTION

[0020] In the following detailed description, reference is made to the accompanying drawings which form a part of this disclosure and in which are shown, by way of example, specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the present disclosure. However, other embodiments disclosed herein may be utilized, and structural, material, and process changes may be made without departing from the scope of this disclosure.

[0021] The illustrations presented herein are not intended to be actual views of any particular method, system, apparatus, or structure, but are merely idealized representations for describing embodiments of the present disclosure. In some cases, similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, construction, or any other attribute.

[0022] The following description may include examples to help those skilled in the art practice the embodiments disclosed herein. The use of the terms "exemplary," "such as," and "for example" means that the relevant description is illustrative, and while the scope of this disclosure is intended to encompass examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to the specified components, steps, features, functions, etc.

[0023] It should be readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in many different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of the present disclosure, but rather is merely representative of various embodiments. Although various aspects of these embodiments may be shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0024] In addition, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure with unnecessary detail. On the contrary, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise indicated herein. In addition, the block definitions and the partitioning of logic between the various blocks are examples of specific embodiments. It will be apparent to one of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details regarding timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of one of ordinary skill in the relevant art.

[0025] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some figures may illustrate signals as a single signal. Those skilled in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0026] The various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed with a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor (also referred to herein as a "host processor" or simply "host") may be a microprocessor, but in an alternative embodiment, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer when it is configured to execute computing instructions (e.g., software code, but not limited thereto) associated with the embodiments of the present disclosure.

[0027] The embodiment can be described according to the process that is depicted as a flow chart, a flow diagram, a structure diagram or a block diagram. Although the flow chart can describe the operation action as a continuous process, many of these actions can be performed in accordance with another sequence, in parallel or substantially simultaneously. In addition, the order of the actions can be rearranged. The process herein can correspond to a method, a thread, a function, a process (procedure), a subroutine, a subprogram, other structures or a combination thereof. In addition, the method disclosed herein can be implemented by hardware, software or both. If implemented in software, these functions can be stored or transferred to a computer-readable medium as one or more instructions or codes. Computer-readable media includes both computer storage media and communication media, and the communication media includes any medium that is conducive to transferring a computer program from one location to another.

[0028] Any reference to an element herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is explicitly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not mean that only two elements may be employed therein or that the first element must precede the second element in some manner. Furthermore, unless otherwise specified, a group of elements may include one or more elements.

[0029] As used herein, the term "substantially" when referring to a given parameter, property, or condition means and includes to the extent that one of ordinary skill in the art would understand that the given parameter, property, or condition is achieved with minor variations (such as, for example, within acceptable manufacturing tolerances). By way of example, depending on the specific parameter, property, or condition that is substantially met, the parameter, property, or condition may be met by at least 90%, by at least 95%, or even by at least 99%.

[0030] Receiver front-ends are designed to handle high transmission amplitudes, potentially exceeding one volt differential peak-to-peak (1 Vppd). Given that transmitted signals exceed one volt (1 Vppd), active equalizers implemented in low-voltage technologies operating below these amplitudes struggle to handle the dynamic peak-to-peak voltage range when determining the outer envelope of the received data eye. Receiver front-ends, which may include passive attenuators or equalizers, are designed to attenuate the data eye envelope. While it is desirable to accommodate multiple channels, making such passive attenuators or equalizers programmable to accommodate multiple channels at frequencies exceeding ten gigahertz (10 GHz) is challenging. If passive front-end circuitry is reconfigurable, signal integrity can be easily compromised above 10 GHz. For example, channel loss (e.g., attenuation in the conductive traces carrying the signal to the receiver front-end, but not limited to this) is low at low frequencies (e.g., typically below 100 MHz in serial communications, but not limited to this) but increases with frequency (e.g., is substantially proportional to frequency). The SerDes receiver front end should preferably compensate for channel losses that increase with frequency, which may be greater than twenty to thirty-five decibels (20dB-35dB) at the Nyquist rate, so that the receiver front end (e.g., a passive attenuator or equalizer) combined with the channel has an overall frequency response that is largely consistent with frequency. For typical SerDes receivers known to the inventors of this disclosure, the data eye envelope provided by the receiver front end may not be greater than approximately 400mVppd. Larger envelopes may cause the receiver circuit to enter a nonlinear region (e.g., saturation, clipping, but not limited thereto), which may cause distortion.

[0031] Disclosed herein is a front-end circuit having a passive equalizer and a programmable amplifier circuit. The front-end circuit disclosed herein can be particularly useful for high-speed (e.g., substantially 10 GHz or greater channel frequencies) data receivers (e.g., SerDes, but not limited thereto). The passive equalizer may include a fixed Zobel constant resistance bridge (sometimes referred to herein as a "Zobel network"). The impedance compensation arm of the fixed Zobel constant resistance bridge, which is typically not used in most applications, serves as a secondary signal path in addition to the primary signal path of the fixed Zobel constant resistance bridge. The secondary signal path exhibits a complementary frequency response relative to the primary signal path. By combining the signal from the primary signal path and the signal from the secondary signal path in a programmable amplifier circuit (which may include a programmable dual-input summing amplifier), a flat and fully balanced frequency response can be obtained. Both inputs of the programmable dual-input summing amplifier receive a signal having a data envelope attenuated by a fixed amount of low-frequency de-emphasis of the fixed Zobel constant resistance bridge, and are therefore protected from the effects of excessive input voltage potential levels. At the same time, since the two signal paths of the fixed Zobel constant resistance bridge are properly terminated by the programmable dual-input summing amplifier, and since the fixed Zobel constant resistance bridge itself is fixed, the input return loss and signal integrity of the receiving path are ensured.

[0032] In some embodiments, the passive equalizer includes a fixed dual-path passive equalizer based on a fixed Zobel constant resistance bridge, and the programmable amplifier circuit includes a programmable gain summing amplifier that linearly combines the two outputs from the fixed Zobel constant resistance bridge. The fixed Zobel constant resistance bridge includes two signal paths. The first signal path of the fixed Zobel constant resistance bridge represents a balanced response. The second signal path of the fixed Zobel constant resistance bridge represents the complement of the balanced response of the first signal path. The input impedances of the first and second signal paths are complementary. In other words, the first and second signal paths together represent a substantially constant resistance regardless of the frequency of the input signal applied thereto because the reactive components of the impedances of the first and second signal paths cancel each other. This ensures proper high-speed termination of the high-speed data receiver.

[0033] Typically, the first signal path and the second signal path are implemented by creating two parallel impedances. The first signal path may be formed by a series combination of a first terminal resistor having an impedance Zo (e.g., 50 ohms, but not limited thereto) and a frequency-dependent impedance Z. The second signal path may be formed by a series combination of a second terminal resistor having an impedance Zo and an impedance Z′ set to Z′=(Zo^2) / Z. When a fixed Zobel constant resistance bridge is implemented as a balanced bridge, because the output impedance is equal to the input impedance, the sensitivity to the downstream terminal is reduced, and thus secondary reflections are greatly reduced.

[0034] Compared to using a programmable attenuator in front of an active equalizer (e.g., a CTLE, but not limited thereto) to keep the data envelope within the equalizer's linear input range, the embodiments disclosed herein include a passive equalizer with an amount of de-emphasis (peaking) based on the longest channel used in the system (e.g., the longest length of conductive trace carrying the input signal to the passive equalizer, but not limited thereto). The sum of de-emphasis and equivalent decision feedback equalizer (DFE) equalization equalizes to the Nyquist channel loss, i.e., the absorption loss experienced by a signal transmitted along the communication channel at the Nyquist frequency. As a result, the data envelope entering the programmable amplifier circuit (the active portion of the receiver front end) is reduced to below its linearity limit while attenuation at the Nyquist frequency is kept to a minimum. No switches are required within the passive equalizer. Instead, the effective amount of de-emphasis is determined by the programmable amplifier circuit. Implementing a programmable amplifier circuit is much easier than implementing a programmable passive attenuator or equalizer.

[0035] In some embodiments, several (eg, approximately 10) fixed Zobel constant resistance bridges may be constructed for each path. 2 or 10 3 , such as, but not limited to, forty amplifier slices (e.g., each slice comprising a differential pair amplifier, but not limited thereto). Gain adjustment is achieved by selectively turning the slices on or off. Since the input capacitance of the amplifier slices is largely constant, broadband matching is achieved regardless of the equalizer settings.

[0036] The front-end circuit disclosed herein counteracts frequency-dependent losses in physical channels between computer servers, network cards, and / or chips that carry serial data at high speeds (e.g., ten gigabits per second, but not limited thereto). The losses that increase with increasing channel frequency are compensated by increasing the gain of a programmable amplifier with frequency, thereby achieving a "flat" response and an "open eye." Furthermore, the front-end circuit system disclosed herein overcomes the often conflicting requirements of linearity, signal integrity, and programmability by using a dual-path passive equalizer (linearity) with complementary responses in front and a programmable amplifier circuit that combines the two responses, preferably in a linear manner.

[0037] The embodiments disclosed herein reduce the large transmit signal envelope entering the active device by using a passive equalizer front end to alleviate linearity requirements. The embodiments disclosed herein decouple the programmability requirements of the passive equalizer and / or attenuator from the terminal requirements by using a fixed, constant resistance equalizer with dual outputs. The embodiments disclosed herein also separate the equalizer function from the gain function. Each (equalizer and gain) can be optimized and modeled without compromising each other. The summing circuit, preferably implemented with a linear summing amplifier, has a flat, broadband response, which is suitable for modeling by design tools.

[0038] Figure 1 is a circuit schematic diagram of a Zobel network 100. Zobel network 100 includes an impedance Z, an impedance Z′, a bridging impedance ZB, and a pair of reference impedances Z0. Impedance Z′ is substantially equal to the dual impedance of impedance Z relative to reference impedance Z0: Z′=Z0^2 / Z. In addition, the reactive portion of the dual impedance Z′ cancels the reactive portion of impedance Z. The reference impedances are substantially equal to each other (Z0=Z0). Zobel network 100 also includes an input 102 across a first node 106 and a fourth node 112, and an output 104 across a third node 110 and a fourth node 112. A first reference impedance and a dual impedance Z′ in reference impedance Z0 are electrically connected in series across input 102. In other words, the first reference impedance Z0 is electrically connected from first node 106 to second node 108, and the dual impedance Z′ is electrically connected from second node 108 to fourth node 112. A second reference impedance in reference impedance Z0 is electrically connected across output 104. In other words, the second reference impedance in reference impedance Z0 is electrically connected from third node 110 to fourth node 112. Impedance Z is electrically connected from first node 106 to third node 110, and thus impedance Z and the second reference impedance in reference impedance Z0 are electrically connected in series across input 102. Bridging impedance ZB is electrically connected between the first reference impedance in reference impedance Z0 and the dual impedance Z′, i.e., between impedance Z and the second reference impedance in reference impedance Z0 from second node 108. In other words, bridging impedance ZB is electrically connected from second node 108 to third node 110.

[0039] The input impedance looking toward the input 102 of the Zobel network 100 is represented by ZIN. The output impedance looking toward the output 104 of the Zobel network 100 is represented by ZOUT. The values of Z, Z', and Z0 may be selected such that the Zobel network 100 is balanced (a "balanced Zobel network"). As used herein, the term "balanced" when referring to an impedance network refers to a situation where the input impedance looking toward the input of the impedance network is substantially equal to the output impedance looking toward the output of the impedance network. Figure 1In the case of the Zobel network 100, when the input impedance ZIN is substantially equal to the output impedance ZOUT, the Zobel network 100 is balanced. In particular, the Zobel network 100 is balanced if the following relationship is substantially satisfied:

[0040]

[0041] The inverse of the input impedance ZIN of the Zobel network 100 (i.e., the input admittance) is given by the following formula:

[0042]

[0043] The dual impedance Z′ can be given by the following formula:

[0044]

[0045] When the Zobel network 100 is balanced, the input impedance ZIN of the Zobel network 100 may be substantially equal to the reference impedance Z0. If the reference impedance Z0 is selected to include substantially only active components (and substantially no reactive components), the input impedance ZIN is substantially resistive.

[0046] The dual impedance Z' may be selected to be dual to the impedance Z. As used herein, the term "dual" when referring to a first impedance and a second impedance indicates that the second impedance is substantially the square of a reference impedance divided by the first impedance (e.g., a balanced condition, or In the case of impedance Z and dual impedance Z′, if Z′ is substantially equal to Z0 2 / Z, then Z and Z' can be selected to be dual. If Z and Z' are dual, then Zobel network 100 is balanced, and the input impedance ZIN of Zobel network 100 is substantially equal to the reference impedance Z0. Impedance Z and the dual impedance Z can be first-order, second-order, or any other order impedance network. The bridging impedance ZB can optionally be selected to be substantially equal to the reference impedance Z0. In such cases, Zobel network 100 can be symmetrical.

[0047] As used herein, the term "complementary," when referring to a first frequency response and a second frequency response, indicates that the second frequency response exhibits substantially opposite behavior to the first frequency response over a frequency range of interest (e.g., 100 MHz to 100 GHz, but not limited thereto). For example, where the first frequency response is characteristic of a bandpass filter having a specific passband, the second frequency response would be characteristic of a bandstop filter having a specific stopband that is substantially the same as the specific passband of the first frequency response. Additionally, at frequencies where the first frequency response has a peak, the second frequency response has a valley. "Complementary" does not necessarily imply that the second frequency response exhibits behavior that is completely opposite to that of the first frequency response. Rather, "complementary" indicates that adding the second frequency response to the first frequency response results in an overall frequency response that is flatter than the first frequency response alone.

[0048] Figure 2 is a circuit diagram of a second-order Zobel network 200. The second-order Zobel network 200 is Figure 1 For example, the second-order Zobel network 200 includes an impedance Z, a dual impedance Z′, a reference impedance Z0, and a bridge impedance ZB. In the second-order Zobel network 200, the impedance Z and the dual impedance Z′ are second-order impedance networks. For example, in Figure 2 In the second-order Zobel network 200, the impedance Z includes a first resistor R1 connected in parallel with a series combination of a capacitor C1 and an inductor L1, and the dual impedance Z′ includes a parallel combination of a capacitor C2 and an inductor L2 connected in series with a second resistor R2. The reference impedance and the bridge impedance of the second-order Zobel network 200 are each a reference resistor R0. Since the bridge impedance ZB is equal to the reference impedance Z0, Figure 2 The second-order Zobel network 200 is symmetrical.

[0049] Figure 2 The dual impedance Z′ is dual to the impedance Z with respect to the reference impedance Z0. In other words, therefore, Figure 2 The second-order Zobel network 200 is balanced. To achieve this, the value of the first resistor may be R1=N*R0 (where "*" is a multiplication operator), and the value of the second resistor may be R2=R0 / N (satisfying the balance condition), where N is a positive real number. In this example, the balance condition requires substantially achieving the following formula:

[0050] L2=Z0 2 *C1 and

[0051]

[0052] The transfer function of the second-order Zobel network 200 following these conditions is given by the following formula:

[0053]

[0054] Where ω0 is 2πf0, f0 is the resonant frequency of the second-order Zobel network 200 (given by Given), ω is 2πf, f is the frequency of the input voltage potential VIN, s is jω, Q = ω0R0C2, and N is a positive real number. The input voltage potential VIN and the output voltage potential VO are each defined with respect to the reference voltage potential VREF. As long as the condition is satisfied The constant input resistance and balance of the second-order Zobel network 200 can be designed.

[0055] Relative to a reference voltage potential VREF (e.g., ground or another specified voltage, but not limited thereto), the top voltage potential VTOP and the bottom voltage potential VBOT can be positioned above the parallel combination of L2 and c2 and below the parallel combination of L2 and c2, respectively. Note that, due to the aforementioned equilibrium condition, the VTOP voltage potential is substantially equal to the output voltage potential VO. The frequency response of the bottom voltage potential VBOT can be substantially complementary to the frequency response of the top voltage potential VTOP. One way to ensure that the frequency response of the bottom voltage potential VBOT is substantially complementary to, or opposite to, the frequency response of the top voltage potential VTOP is to set Z and Z′ to be dual. In other words, the transfer function HTOP=VTOP / VIN of the top voltage potential VTOP with respect to the input voltage potential VIN can have a peak at substantially the same frequency at which the transfer function HBOT=VBOT / VIN of the bottom voltage potential VBOT with respect to the input voltage potential VIN has a valley. Furthermore, HTOP can have a valley at a frequency at which HBOT has a peak. It can be shown that the transfer functions HTOP and HBOT as functions of the complex frequency s are complementary when HBOT is weighted by N: HTOP(s)+N*HBOT(s)=1. Figure 2 For the second-order Zobel network 200, the transfer functions HTOP and HBOT are given by the following formulas:

[0056] and

[0057]

[0058] Figure 3 is a graph showing the input voltage signal VIN ( Figure 2 )of Figure 2 A graph 300 is provided showing the frequency response of the top voltage potential VTOP and the bottom voltage potential VBOT of the second-order Zobel network 200. The graph 300 includes the frequency response of the top voltage potential VTOP and the bottom voltage potential VBOT plotted against the frequency (in Hertz). Figure 2 300 . A top voltage potential VTOP curve 302 and a bottom voltage potential VBOT curve 304 are plotted in units of voltage potential magnitude, or in other words, in units of volts (V). As can be seen in curve 300 , the bottom voltage potential VBOT curve 304 exhibits a frequency response that is substantially opposite to the frequency response of the top voltage potential VTOP curve 302 . Note that while the weighted vector sum of HTOP and N*HBOT equals one, this is not necessarily true for the magnitudes |HTOP| and |HBOT|. Therefore, the two curves |HTOP| and |HBOT| corresponding to the top voltage potential VTOP curve 302 and the bottom voltage potential VBOT curve 304 , respectively, do not add up to one, but |HTOP+HBOT| does.

[0059] Since the bottom voltage potential VBOT curve 304 has a frequency response that is substantially opposite to the frequency response of the top voltage potential VTOP curve 302, a linear combination of the top voltage potential VTOP curve 302 and the bottom voltage potential VBOT curve 304 will correspond to a substantially flat frequency response of the passive equalizer. Thus, embodiments of the present disclosure utilize a passive equalizer including complementary signal paths and a programmable amplifier circuit programmed to cancel the frequency dependence of the channel, thereby providing a substantially flat frequency response for the combination of the channel and the receiver front end.

[0060] Figure 4 4 is a block diagram of a data receiver 400 according to some embodiments. The data receiver 400 includes a front-end circuit 406 configured to utilize a passive equalizer 402 including complementary signal paths (a first signal path 410 and a second signal path 412) and an amplifier circuit 404 configured to add, preferably linearly, signals (a first equalizer output signal VAO and a second equalizer output signal VBO) from the first signal path 410 and the second signal path 412 to provide a substantially flat frequency response of the equalized output signal VEQZ in response to the input signal VIN.

[0061] As previously mentioned, the first signal path 410 and the second signal path 412 are complementary. Therefore, the impedance of the second signal path 412 is dual to the impedance of the first signal path 410. Therefore, in response to the input signal VIN, the frequency response of the second equalizer output signal VBO is substantially opposite to the frequency response of the first equalizer output signal VAO. As a non-limiting example, the frequency response of the first signal path 410 may have a peak at the Nyquist frequency, and the frequency response of the second signal path 412 may have a notch at the Nyquist frequency. The passive equalizer 402 can compensate for the large signal envelope of the input signal VIN by reducing the signal envelopes of the first equalizer output signal VAO and the second equalizer output signal VBO to within the linear input range of the amplifier circuit 404 using passive circuitry, without the need for programmability of the passive equalizer 402. Figure 5 and Figure 6 A more detailed example discusses passive equalizers.

[0062] Amplifier circuit 404 includes a first amplifier 414, a second amplifier 416, and a summing circuit 418. First amplifier 414 and second amplifier 416 are configured to receive a first equalizer output signal VAO and a second equalizer output signal VAO, respectively. First amplifier 414 is configured to amplify first equalizer output signal VAO by a gain A to generate a first amplified signal VAA. Second amplifier 416 is configured to amplify second equalizer output signal VBO by a gain of 1-A (one minus the gain of first amplifier 414) to generate a second amplified signal VAB. It should be noted that the gain of second amplifier 416 can be selected to be different from 1-A and can even be independent of A. However, by using the gain of second amplifier 416, which is a function of the gain A of first amplifier 414, only a single variable, A, is introduced to determine the gains of both first amplifier 414 and second amplifier 416. Summing circuit 418 is configured to sum first amplified signal VAA and second amplified signal VAB to generate equalized signal VEQZ. Thus, the amplifier circuit 404 is configured to combine the responses of the first signal path 410 and the second signal path 412. Figure 7 Further details regarding examples of amplifier circuit 404 are discussed.

[0063] The amplifier circuit 404 is a programmable amplifier circuit. The data receiver 400 also includes a control circuit 408 that is configured to provide a control signal 420 to control the gain of the first amplifier 414 and the second amplifier 416, which may be programmable gain amplifiers. As a non-limiting example, the control signal 420 may be configured to control the value of A of the first amplifier 414 and the second amplifier 416.

[0064] The configuration of the front-end circuit 406 separates the equalization function (performed by the passive equalizer 402) from the gain function (performed by the amplifier circuit 404). Therefore, the passive equalizer 402 and the amplifier circuit 404 can be optimized separately without compromising each other.

[0065] Figure 5 is a circuit diagram of a passive equalizer 500 according to some embodiments, which can be used as Figure 4 4. The passive equalizer 402 of the data receiver 400 is shown. The passive equalizer 500 includes a signal input 512 (e.g., a conductive pin, connector, trace, or wire, but not limited thereto) and an equalizer output 510. The equalizer output 510 includes a first equalizer output 506 and a second equalizer output 508 (e.g., a conductive pin, connector, trace, or wire, but not limited thereto). The passive equalizer 500 also includes a first signal path 502 between the signal input 512 and the first equalizer output 506. The passive equalizer 500 also includes a second signal path 504 between the signal input 512 and the second equalizer output 508.

[0066] Passive Equalizer 500 with Figure 2 The second-order Zobel network 200 has some similarities. For example, the impedance Z of the first signal path 502 is dual to the impedance ZA' of the second signal path 504. Also by way of example, the passive equalizer 500 includes a circuit similar to Figure 2 The impedance Z and the dual impedance Z′ of the impedance Z and the dual impedance ZA'. Similar to Figure 2 The impedance Z and the dual impedance Z′, the impedance Z and the dual impedance ZA′ are second-order impedance networks. However, it should be noted that the impedance Z and the dual impedance ZA′ can alternatively be implemented as first-order, third-order, fourth-order, or any other order impedance networks without exceeding the scope of the present disclosure. In addition, Figure 5 The impedance Z comprises a first resistor R1 in parallel with a series combination of capacitor c1 and inductor L1, and the dual impedance ZA' comprises a parallel combination of capacitor c2 and inductor L2 in series with a second resistor R2A. Figure 2 The first resistor R1, Figure 5 The value of the first resistor R1 may be the reference resistance R0 multiplied by N (R1=R0*N). However, Figure 5 The value of the second resistor R2A is the reference resistance R0 divided by N-1 In contrast, Figure 2 The value of the second resistor R2 is R2 = R0 / N. The passive equalizer 500 and Figure 2 Another difference between the second-order Zobel network 200 and the passive equalizer 500 is that the passive equalizer 500 does not include a reference resistor R0 between the first equalizer output 506 and the reference voltage potential VREF, but an amplifier circuit (eg, Figure 4 The input impedance of the amplifier circuit 404 (but not limited thereto) can be set to be substantially equal to R0 so that the passive equalizer 500 is similar to Figure 2 The selection of the value of N, and by extension the values of R1 and R2A, may be based at least in part on the length of the physical channel (e.g., but not limited to, the conductive trace in the integrated circuit chip including the passive equalizer 500) that carries the input signal VIN to the signal input 512, as will be seen in reference to FIG. Figure 8 and Figure 9 discussed.

[0067] Passive Equalizer 500 with Figure 2 These differences between the second-order Zobel network 200 can compensate for input impedances equal to the reference resistance R0 looking into the first amplifier electrically connected to the first equalizer output 506 and the second amplifier electrically connected to the second equalizer output 508 (e.g., Figure 4 Assuming that an amplifier having R0 as its input impedance is electrically connected to the first equalizer output 506 and the second equalizer output 508, the passive equalizer 500 is equivalent to Figure 2 The second-order Zobel network 200 of FIG. In such a case, the passive equalizer 500 is balanced.

[0068] The passive equalizer 500 includes a signal input 512 with a signal similar to Figure 2 The passive equalizer 500 further includes a bridging impedance 514 that bridges the first signal path 502 to the second signal path 504. The bridging impedance 514 is set to have an impedance equal to the reference resistor R0, similar to Figure 2 The bridging impedance ZB of the second-order Zobel network 200 is .

[0069] In operation, an input signal VIN is provided to the passive equalizer 500 and applied to a first signal path 502 and a second signal path 504. In response, the first signal path 502 provides a first equalizer output signal VBO to a first equalizer output 506, and the second signal path 504 provides a second equalizer output signal VAB to a second equalizer output 508. The second equalizer output signal VBO exhibits a frequency response that is substantially the opposite of the frequency response of the first equalizer input signal VAO.

[0070] The passive equalizer 500 attenuates the envelopes of the first and second equalizer output signals VAO and VBO compared to the envelope of the input signal VIN. The passive equalizer 500 also provides termination (e.g., appropriate frequency response, but not limited thereto) to the input signal VIN to reduce return loss.

[0071] Note that the values of the first resistor R1 and the second resistor R2A are fixed. Therefore, the passive equalizer 500 is implemented without variable resistors, which can simplify the design, implementation, and operation of the passive equalizer 500 compared to equalizer circuits using variable resistors (e.g., electrically controlled potentiometers, which may include switching elements in integrated circuit implementations, but are not limited thereto).

[0072] Figure 6 is a circuit diagram of an alternative passive equalizer 600 according to some embodiments, which may be used as Figure 4 The passive equalizer 402 of the data receiver 400 is shown in FIG. 6 . The alternative passive equalizer 600 includes a signal input 612 and an equalizer output 610, the equalizer output including a first equalizer output 606 and a second equalizer output 608. The signal input 612, the equalizer output 610, the first equalizer output 606 and the second equalizer output 608 are similar to Figure 5 The passive equalizer 500 includes a signal input 512 , an equalizer output 510 , a first equalizer output 506 , and a second equalizer output 508 .

[0073] The alternative passive equalizer 600 also includes a first signal path 602 and a second signal path 604. Although the first signal path 602 and the second signal path 604 are complementary, the alternative passive equalizer 600 does not include a bridging impedance that bridges the first signal path 602 to the second signal path 604, in contrast to the passive equalizer 500 that includes a bridging impedance 514 that bridges the first signal path 502 to the second signal path 504. Figure 5 ). The first signal path 602 includes an impedance Z, and the second signal path 604 includes a dual impedance ZB', similar to Figure 5 The impedance Z and the dual impedance ZA'. Similar to Figure 5 The impedance Z and the dual impedance ZA', Figure 6 The impedance Z and the dual impedance ZB' are second-order impedance networks. However, it should be noted that the impedance Z and the dual impedance ZB' may alternatively be implemented as first-order, third-order, fourth-order or any other order impedance networks. In addition, Figure 6 The impedance Z comprises a first resistor R1 in parallel with a series combination of capacitor c1 and inductor L1, and the dual impedance ZB' comprises a parallel combination of capacitor c2 and inductor L2 in series with a second resistor R2B. Figure 2and Figure 5 The first resistor R1, Figure 6 The value of the first resistor R1 may be the reference resistance R0 multiplied by N (R1=R0*N). However, Figure 6 The value of the second resistor R2B is N+1 multiplied by the reference resistance R0, divided by N-1 In contrast, Figure 5 The value of the second resistor R2A is The alternative passive equalizer 600 further includes a resistor R1 (value R1 =N*R0) electrically connected from between the parallel combination of the second inductor L2 and the second capacitor c2 and the second resistor R2B to the second equalizer output 608 .

[0074] In operation, an input signal VIN is provided to the signal input 612 and, thus, to the first signal path 602 and the second signal path 604. The first signal path 602 provides a first equalizer output signal VAO to the first equalizer output 606 in response to the input signal VIN. The second signal path 604 provides a second equalizer output signal VBO to the second equalizer output 608 in response to the input signal VIN. The second equalizer output signal VBO exhibits a frequency-dependent behavior that is opposite to the frequency-dependent behavior of the first equalizer output signal VAO.

[0075] In the case of the alternative passive equalizer 600 configured as discussed above, the resistance value of the second resistor R2B may be selected to be generally relatively higher than Figure 5 The resistance value of the second resistor R2A ( compared to ). This is because the resistance value of the second resistor R2B is in the same order of magnitude as the reference resistance value R0 regardless of the value of N (assuming N is not equal to 1), even if the value of N is selected to be relatively high (for example, N>3, but not limited thereto). As a non-limiting example, if N=4, then R2B=(5 / 3)*R0. Also as a non-limiting example, if N=10, then R2B=(11 / 9)*R0. In contrast, if N is relatively large, then Figure 5 The resistance value of the second resistor R2A may be much smaller than the resistance value of the reference resistor R0. As a non-limiting example, if N=4, then R2A=(1 / 3)*R0. Also as a non-limiting example, if N=10, then R2A=(1 / 9)*R0. It may be relatively difficult to implement very small resistors on an integrated circuit chip because implementing very small resistors may involve placing several larger resistors in parallel, which consumes a relatively large chip area to implement. Therefore, Figure 5Compared to the passive equalizer 500 , the alternative passive equalizer 600 has the advantage that, since the resistance value of the second resistor R2B is in the same order of magnitude as the reference resistor R0 , its chip area can be reduced compared to the chip area of the passive equalizer 500 .

[0076] However, Figure 5 The passive equalizer 500 also has its advantages. As a non-limiting example, since the passive equalizer 500 includes a bridge impedance 514 ( Figure 5 ), so the passive equalizer 500 can be balanced (i.e., the output impedance of the passive equalizer 500 can be substantially equal to the input impedance of the passive equalizer 500). When the signals (i.e., the first equalizer output signal VAO and the second equalizer output signal VBO) are provided to the amplifier circuit (e.g., Figure 4 When the passive equalizer 500 is used with the amplifier circuit 404 (e.g., but not limited to), the passive equalizer 500 may experience fewer reflections than the alternative passive equalizer 600.

[0077] Figure 7 According to some embodiments, Figure 4 The programmable amplifier circuit 700 of the amplifier circuit 404 of the data receiver 400 is a circuit diagram. The programmable amplifier circuit 700 may be Figure 4 Detailed description of the programmable amplifier circuit 404. The programmable amplifier circuit 700 includes a first amplifier input 712, a second amplifier input 714, a first impedance matching network 708, a second impedance matching network 710, a first programmable gain amplifier 702, a second programmable gain amplifier 704, a summing circuit 706, and an amplifier output 716. The first amplifier input 712 and the second amplifier input 714 are configured to receive a signal from a passive equalizer (e.g., Figure 4 Passive equalizer 402, Figure 5 Passive equalizer 500, Figure 6 The first equalizer output signal VAO and the second equalizer output signal VBO are received by the alternative passive equalizer 600, but not limited thereto. Therefore, the first amplifier input 712 and the second amplifier input 714 can be electrically connected to the passive equalizer (for example, electrically connected to Figure 5 The first equalizer output 506 and the second equalizer output 508 are electrically connected to Figure 6 The first equalizer output 606 and the second equalizer output 608 are, but not limited to, those of the embodiment of the present invention.

[0078] The first programmable gain amplifier 702 and the second programmable gain amplifier 704 are programmable amplifiers having gains (a gain of A for the first programmable gain amplifier 702 and a gain of 1-A for the second programmable gain amplifier 704). As a non-limiting example, the gains of the first programmable gain amplifier 702 and the second programmable gain amplifier 704 (i.e., the value of A) are responsive to a control signal from a control circuit (e.g., from Figure 4 The control signal 420 of the control circuit 408 (including, but not limited to, the control signal 420) can be electrically programmable. The control circuit 408 is used to change the gain in response to the frequency of VIN and information about the channel length to provide compensation for the channel.

[0079] In some embodiments, the first programmable gain amplifier 702 and the second programmable gain amplifier 704 can each be implemented using a plurality of amplifiers (e.g., complementary metal oxide semiconductor (cMOS) differential pair amplifiers, but not limited thereto), which can be individually controlled to enable or disable. Thus, the gain of the first programmable gain amplifier 702 and the second programmable gain amplifier 704 can be increased by enabling a greater number of their amplifiers. Similarly, the gain of the first programmable gain amplifier 702 and the second programmable gain amplifier 704 can be decreased by disabling a greater number of their amplifiers. In other embodiments, the first programmable gain amplifier 702 and the second programmable gain amplifier 704 can be implemented using an operational amplifier circuit including an electrically controlled resistor to adjust the gain of the first programmable gain amplifier 702 and the second programmable gain amplifier 704.

[0080] It may be assumed that an ideal amplifier has infinite input impedance and zero output impedance. However, in practice, all amplifiers have finite input impedance and non-zero output impedance. As a result, then, in practice, the first programmable gain amplifier 702 and the second programmable gain amplifier 704 have finite input impedance and non-zero output impedance. Therefore, the first impedance matching network 708 and the second impedance matching network 710 are configured to provide appropriate impedance termination to the passive equalizer electrically connected to the first impedance matching network 708 and the second impedance matching network 710. As a non-limiting example, Figure 5 The passive equalizer 500 and Figure 6 The alternative passive equalizer 600 is designed for termination substantially equal to the reference resistor R0. Thus, the first impedance matching network 708 and the second impedance matching network 710 can be configured such that the input impedance looking into the first amplifier input 712 and the second amplifier input 714 is substantially equal to the reference resistor R0.

[0081] In embodiments where the first programmable gain amplifier 702 and the second programmable gain amplifier 704 are implemented using a plurality of CMOS differential pair amplifiers that can be controllably enabled or disabled to adjust the gain of the first programmable gain amplifier 702 and the second programmable gain amplifier 704, the input impedances of the first programmable gain amplifier 702 and the second programmable gain amplifier 704 may have relatively large capacitive components. In such embodiments, the first impedance matching network 708 and the second impedance matching network 710 are configured to compensate for these large capacitive components. As a non-limiting example, the first impedance matching network 708 and the second impedance matching network 710 may include a bridged t-coil network to compensate for the large capacitive components.

[0082] The first programmable gain amplifier 702 and the second programmable gain amplifier 704 are configured to amplify the first equalizer output signal VAO and the second equalizer output signal VBO to generate a first amplified signal VAA and a second amplified signal VAB, respectively. More specifically, the first programmable gain amplifier 702 is configured to amplify the first equalizer output signal VAO by a gain A to generate a first amplified signal VAA. In addition, the second programmable gain amplifier 704 is configured to amplify the second equalizer output signal VBO by a gain 1-A to generate a second amplified signal VAB. Figure 5 Passive equalizer 500 or Figure 6 In some embodiments of the alternative passive equalizer 600, the value of A may be 1 / (N+1), where N is the value of Figure 5 and Figure 6 The first programmable gain amplifier 702 and the second programmable gain amplifier 704 are electrically connected to the summing circuit 706. Therefore, the first programmable gain amplifier 702 and the second programmable gain amplifier 704 are configured to provide the first amplified signal VAA and the second amplified signal VAB to the summing circuit 706.

[0083] The summing circuit 706 is configured to receive the first amplified signal VAA and the second amplified signal VAB, and generate an equalized signal VEQZ based on the sum of the first amplified signal VAA and the second amplified signal VAB, which is preferably linear. In some embodiments, the summing circuit 706 may include a linear summing amplifier (for example, implemented using an operational amplifier, but not limited thereto). Assume that the programmable amplifier circuit 700 is connected to the programmable amplifier circuit described above. Figure 4 If the passive equalizer 402 of FIG. 1 is used together with the passive equalizer having the properties discussed above, and assuming that the first impedance matching network 708 and the second impedance matching network 710 provide impedance matching, the equalized signal VEQZ provided at the amplifier output 716 is VEQZ with respect to the source signal (i.e., the signal injected into the channel, the output of which is Figure 4 、 Figure 5 and Figure 6 VIN in the output has a flat frequency response.

[0084] Figure 8 is shown plotted against frequency from Figure 4 800 is a graph illustrating an example of an equalized signal VEQZ of a front-end circuit 406, wherein the signal input of the front-end circuit 406 is electrically connected to a relatively short physical channel (e.g., a relatively short conductive trace of an integrated circuit device that transmits an input signal VIN from a source signal to the front-end circuit 406, but is not limited thereto). The equalized signal VEQZ of the graph 800 is shown in decibel volts (dB V). Specifically, the graph 800 includes an A=0.1 curve 802, an A=0.2 curve 804, an A=0.3 curve 806, an A=0.4 curve 808, an A=0.5 curve 810, an A=0.6 curve 812, an A=0.7 curve 814, an A=0.8 curve 816, an A=0.9 curve 818, and an A=1.0 curve 820, where A is the value of the ... Figure 4 and Figure 7 The A in question (i.e. Figure 4 The first amplifier 414 or Figure 7 The value of N=4 for the passive equalizer 402 (see above) Figure 5 and Figure 6 The discussed N) is used to generate the graph 800.

[0085] When examining the graph 800, the A=0.2 curve 804 may show a flatter frequency response than the A=0.1 curve 802, the A=0.3 curve 806, the A=0.4 curve 808, the A=0.5 curve 810, the A=0.6 curve 812, the A=0.7 curve 814, the A=0.8 curve 816, the A=0.9 curve 818, or the A=1.0 curve 820. Thus, in a relatively short physical channel electrically connected to the front-end circuit 406 ( Figure 4 ), N=4 and A=0.2 may be appropriate design choices for implementing the front-end circuit 406. Note that for short physical channels, an appropriate relationship between A and N may be given by A=1 / (N+1).

[0086] Figure 9 is shown plotted against frequency from Figure 4Graph 900 shows an example of an equalized signal VEQZ of a front-end circuit 406, wherein the signal input of the front-end circuit 406 is electrically connected to a medium-length physical channel (e.g., a medium-length conductive trace of an integrated circuit device that transmits an input signal VIN from a source signal to the front-end circuit 406, but is not limited thereto). The equalized signal VEQZ of graph 900 is shown in dB V. Specifically, graph 900 includes an A=0.1 curve 902, an A=0.2 curve 904, an A=0.3 curve 906, an A=0.4 curve 908, an A=0.5 curve 910, an A=0.6 curve 912, an A=0.7 curve 914, an A=0.8 curve 916, an A=0.9 curve 918, and an A=1.0 curve 920, where A is the value of the A=0.1 curve 902, which is referred to above. Figure 4 and Figure 7 The A in question (i.e. Figure 4 The first amplifier 414 or Figure 7 The gain of the first programmable gain amplifier 702 is similar to Figure 8 800, the value of N=4 for the passive equalizer 402 (see above for reference Figure 5 and Figure 6 The discussed N) is used to generate the graph 900.

[0087] When examining graph 900, A=0.8 curve 916 may exhibit a flatter frequency response than A=0.1 curve 902, A=0.2 curve 904, A=0.3 curve 906, A=0.4 curve 908, A=0.5 curve 910, A=0.6 curve 912, A=0.7 curve 914, A=0.9 curve 918, or A=1.0 curve 920. Thus, in the case of a medium-length physical channel electrically connected to front-end circuitry 406 ( Figure 4 ), N=4 and A=0.8 may be appropriate design choices for implementing the front-end circuit 406. Note that in some embodiments, the values of N, A, or both may be selected based at least in part on the length of the channel electrically connected to the signal input of the front-end circuit 406.

[0088] Figure 10 1 is a graph 1000 showing an example of a channel input signal curve 1002, a channel output signal curve 1004, and an equalized signal VEQZ curve 1006. The channel input signal curve 1002 is a signal at the input to a physical channel (e.g., a conductive trace, but not limited thereto), the output of which is electrically connected to a Figure 4 The channel output signal curve 1004 is the signal at the output of the physical channel in response to the channel input signal curve 1002 applied to the physical channel, or in other words, the channel output signal curve 1004 is the input signal VIN ( Figure 4 The equalized signal VEQZ curve 1006 is the equalized signal VEQZ obtained from the output of the front end circuit 406 in response to the channel output signal curve 1004 applied to the signal input of the front end circuit 406 .

[0089] The physical channel attenuates the signal applied to its input, and this attenuation generally increases with frequency, as evident from the channel input signal curve 1002 and the channel output signal curve 1004. While the channel output signal curve 1004 decreases steadily with frequency, the equalized signal VEQZ curve 1006 exhibits a substantially flat response through a passband 1010 ending at a cutoff frequency 1008 (at -3 dB attenuation) of substantially 12.8 GHz.

[0090] Figure 11 Shown with Figure 10 100 . Specifically, the eye diagram graph 1100 includes the channel input signal eye diagram 1102, the channel output signal eye diagram 1104, and the equalized signal VEQZ eye diagram 1106. As can be seen in the eye diagram graph 1100 , any opening in the channel input signal eye diagram 1102 is closed in the channel output signal eye diagram 1104. As can also be seen in the eye diagram graph 1100 , the eye is open in the equalized signal VEQZ eye diagram 1106. Therefore, even if the signal is fed to the front-end circuit 406 ( Figure 4 ) input signal VIN( Figure 4 ) Due to the physical channel, the eyes are closed, and the front-end circuit 406 still provides the equalized signal VEQZ with an open eye ( Figure 4 ).

[0091] Figure 12 is a diagram illustrating the use of Figure 4 Flowchart of method 1200 for equalizing an input signal using front-end circuit 406 of a first embodiment. In operation 1202, method 1200 generates a first equalizer output signal in response to an input signal applied to a first signal path. The first signal path has a first frequency response. In operation 1204, method 1200 generates a second equalizer output signal in response to an input signal applied to a second signal path. The second signal path has a second frequency response. The second frequency response is substantially opposite to the first frequency response. In operation 1206, method 1200 amplifies the first equalizer output signal with a first gain to generate a first amplified signal. In operation 1208, method 1200 amplifies the second equalizer output signal with a second gain to generate a second amplified signal. In operation 1210, method 1200 adds the first amplified signal to the second amplified signal to generate an equalized output signal.

[0092] Example

[0093] The following is a non-exhaustive, non-limiting list of exemplary embodiments. Not every exemplary embodiment listed below is explicitly and individually indicated as combinable with all other exemplary embodiments listed below and the above-described embodiments. However, it is intended that these exemplary embodiments can be combined with all other exemplary embodiments and the above-described embodiments unless it is obvious to one of ordinary skill in the art that these embodiments are not combinable.

[0094] Embodiment 1: A passive equalizer, comprising: a signal input; an equalizer output, the equalizer output comprising a first equalizer output and a second equalizer output; a first signal path, the first signal path being between the signal input and the first equalizer output, the first signal path having a first frequency response in response to an input signal provided to the signal input; and a second signal path, the second signal path being between the signal input and the second equalizer output, the second signal path having a second frequency response in response to the input signal provided to the signal input, the second frequency response exhibiting behavior substantially opposite to that of the first frequency response.

[0095] Embodiment 2: The passive equalizer according to embodiment 1, wherein the first signal path and the second signal path form respective parts of a Zobel network.

[0096] Embodiment 3: The passive equalizer according to embodiment 2, wherein the Zobel network is implemented as a balanced Zobel network.

[0097] Embodiment 4: The passive equalizer according to any one of embodiments 1 to 3, wherein the first signal path and the second signal path include second-order impedance networks.

[0098] Embodiment 5: The passive equalizer according to any one of Embodiments 1 to 4, further comprising a bridging impedance that bridges the first signal path and the second signal path.

[0099] Embodiment 6: The passive equalizer according to any one of Embodiments 1 to 4, wherein the first signal path and the second signal path are substantially free of a bridging element bridging the first signal path and the second signal path.

[0100] Embodiment 7: A passive equalizer according to any one of embodiments 1 to 6, wherein: the first signal path includes a first impedance network, which includes a first resistor in parallel with a series combination of a first capacitor and a first inductor; and the second signal path includes a parallel combination of a second capacitor and a second inductor, and the parallel combination of the second capacitor and the second inductor is connected in series with a second resistor.

[0101] Embodiment 8: A passive equalizer according to any one of embodiments 1 to 7, wherein: the first equalizer output is configured to provide a first equalizer output signal to a programmable amplifier circuit; the second equalizer output is configured to provide a second equalizer output signal to the programmable amplifier circuit; and the programmable amplifier circuit is configured to amplify and add the first equalizer output signal and the second equalizer output signal to provide a balanced output signal.

[0102] Embodiment 9: A front-end circuit for a data receiver, the front-end circuit comprising: a passive equalizer, the passive equalizer being configured to receive an input signal, the passive equalizer comprising a first signal path and a second signal path, the impedance of the first signal path and the impedance of the second signal path being dual to each other, the first signal path being configured to provide a first equalizer output signal in response to the received input signal, the second signal path being configured to provide a second equalizer output signal in response to the received input signal; and a programmable amplifier circuit, the programmable amplifier circuit being configured to receive the first equalizer output signal and the second equalizer output signal from the passive equalizer, the programmable amplifier circuit comprising: a first programmable gain amplifier, the first programmable gain amplifier being configured to amplify the first equalizer output signal with a first gain to provide a first amplified signal; a second programmable gain amplifier being configured to amplify the second equalizer output signal with a second gain to provide a second amplified signal; and an adding circuit, the adding circuit being configured to add the first amplified signal and the second amplified signal to provide an equalized output signal.

[0103] Embodiment 10: The front-end circuit according to embodiment 9, wherein the second gain is equal to the difference between one and the first gain.

[0104] Example 11: A front-end circuit according to any one of Examples 9 and 10, wherein the programmable amplifier circuit further includes: a first impedance matching network, which is configured to terminate the first signal path; and a second impedance matching network, which is configured to terminate the second signal path.

[0105] Embodiment 12: The front-end circuit according to any one of Embodiments 9 to 11 further includes a control circuit configured to provide a control signal to the programmable amplifier circuit to control the first gain and the second gain.

[0106] Embodiment 13: The front-end circuit according to any one of embodiments 9 to 12, wherein the programmable amplifier circuit comprises a programmable gain summing amplifier.

[0107] Embodiment 14: The front-end circuit according to any one of embodiments 9 to 13, wherein the adding circuit comprises a linear adding amplifier.

[0108] Example 15: A front-end circuit according to any one of Examples 9 to 14, wherein at least one of the first programmable gain amplifier and the second programmable gain amplifier includes an amplifier slice, each amplifier slice includes a differential pair amplifier, and gain adjustment of the at least one of the first programmable gain amplifier and the second programmable gain amplifier is achieved by selectively turning on or off the amplifier slice.

[0109] Embodiment 16: A data receiver includes a front-end circuit, the front-end circuit comprising: a passive equalizer, the passive equalizer being configured to receive an input signal, the passive equalizer comprising a first signal path and a second signal path, the impedance of the first signal path and the impedance of the second signal path being dual to each other, the first signal path being configured to provide a first equalizer output signal in response to the received input signal, the second signal path being configured to provide a second equalizer output signal in response to the received input signal; and a programmable amplifier circuit, the programmable amplifier circuit being configured to receive the first equalizer output signal and the second equalizer output signal from the passive equalizer, the programmable amplifier circuit comprising: a first programmable gain amplifier, the first programmable gain amplifier being configured to amplify the first equalizer output signal with a first gain to provide a first amplified signal; a second programmable gain amplifier being configured to amplify the second equalizer output signal with a second gain to provide a second amplified signal; and an adding circuit, the adding circuit being configured to add the first amplified signal and the second amplified signal to provide a balanced output signal.

[0110] Embodiment 17: The data receiver of embodiment 16, wherein the data receiver is implemented as a serializer / deserializer.

[0111] Embodiment 18: The data receiver according to any one of Embodiments 16 and 17 further includes a control circuit configured to control the first gain of the first programmable gain amplifier and the second gain of the second programmable gain amplifier.

[0112] Example 19: A method for equalizing an input signal, the method comprising: generating a first equalizer output signal in response to the input signal applied to a first signal path, the first signal path having a first frequency response; generating a second equalizer output signal in response to the input signal applied to a second signal path, the second signal path having a second frequency response, the second frequency response being substantially opposite to the first frequency response; amplifying the first equalizer output signal with a first gain to generate a first amplified signal; amplifying the second equalizer output signal with a second gain to generate a second amplified signal; and adding the first amplified signal to the second amplified signal to generate a balanced output signal.

[0113] Example 20: A method according to Example 19, wherein generating the first equalizer output signal in response to the input signal applied to the first signal path and generating the second equalizer output signal in response to the input signal applied to the second signal path includes applying the input signal to a second-order impedance network.

[0114] Example 21: A method according to any one of Examples 19 and 20, wherein generating the second equalizer output signal in response to the input signal applied to the second signal path includes generating the second equalizer output signal in response to the input signal applied to a second impedance, which is dual to the first impedance of the first signal path.

[0115] Embodiment 22: The method according to any one of embodiments 19 to 21, wherein amplifying the second equalizer output signal with the second gain includes amplifying the second equalizer output signal with the second gain minus the first gain.

[0116] Example 23: A method according to any one of Examples 19 to 22, wherein: amplifying the first equalizer output signal includes applying the first equalizer output signal to a first programmable gain amplifier; and amplifying the second equalizer output signal includes applying the second equalizer output signal to a second programmable gain amplifier.

[0117] Conclusion

[0118] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In some embodiments, the various components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads, etc., but not limited thereto). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are possible and contemplated.

[0119] As used in this disclosure, the term "combination" referring to multiple elements may include all of the elements in combination or any of various subcombinations of certain elements. For example, the phrase "A, B, C, D or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0120] The terms used in this disclosure, especially in the appended claims (e.g., the bodies of the appended claims, but not limited thereto) are generally intended to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” and the term “comprising” should be interpreted as “including but not limited to,” but not limited thereto).

[0121] In addition, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more," but are not limited thereto); the same is true when a claim recitation is introduced using a definite article.

[0122] Furthermore, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the unmodified recitation "two recitations" without other modifiers means at least two recitations, or two or more recitations, but is not limited thereto). Furthermore, in those instances where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three of A, B, and C, etc.

[0123] Furthermore, any discrete word or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to include the possibility of one, either, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B."

[0124] Although the present invention is described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrated embodiments and the described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. A front-end circuit for a data receiver, the front-end circuit comprising: a passive equalizer configured to receive an input signal, the passive equalizer comprising a first signal path and a second signal path, wherein an impedance of the first signal path and an impedance of the second signal path are dual to each other, the first signal path being configured to provide a first equalizer output signal in response to the received input signal, and the second signal path being configured to provide a second equalizer output signal in response to the received input signal; and a programmable amplifier circuit configured to receive the first equalizer output signal and the second equalizer output signal from the passive equalizer, the programmable amplifier circuit comprising: a first programmable gain amplifier configured to amplify the first equalizer output signal with a first gain to provide a first amplified signal; a second programmable gain amplifier configured to amplify the second equalizer output signal with a second gain to provide a second amplified signal; and A summing circuit is configured to sum the first amplified signal and the second amplified signal to provide a balanced output signal. 2 . The front-end circuit of claim 1 , wherein the second gain is equal to a difference between one and the first gain.

3. The front-end circuit according to claim 1 , wherein the programmable amplifier circuit further comprises: a first impedance matching network configured to terminate the first signal path; and A second impedance matching network is configured to terminate the second signal path. 4 . The front-end circuit of claim 1 , further comprising a control circuit configured to provide a control signal to the programmable amplifier circuit to control the first gain and the second gain.

5. The front-end circuit of claim 1, wherein the programmable amplifier circuit comprises a programmable gain summing amplifier. The front-end circuit of claim 1 , wherein the summing circuit comprises a linear summing amplifier.

7. The front-end circuit of claim 1 , wherein at least one of the first programmable gain amplifier and the second programmable gain amplifier comprises amplifier slices, each amplifier slice comprising a differential pair amplifier, and gain adjustment of the at least one of the first programmable gain amplifier and the second programmable gain amplifier is achieved by selectively turning the amplifier slices on or off.

8. A data receiver, comprising a front-end circuit, the front-end circuit comprising: a passive equalizer configured to receive an input signal, the passive equalizer comprising a first signal path and a second signal path, wherein an impedance of the first signal path and an impedance of the second signal path are dual to each other, the first signal path being configured to provide a first equalizer output signal in response to the received input signal, and the second signal path being configured to provide a second equalizer output signal in response to the received input signal; and a programmable amplifier circuit configured to receive the first equalizer output signal and the second equalizer output signal from the passive equalizer, the programmable amplifier circuit comprising: a first programmable gain amplifier configured to amplify the first equalizer output signal with a first gain to provide a first amplified signal; a second programmable gain amplifier configured to amplify the second equalizer output signal with a second gain to provide a second amplified signal; and A summing circuit is configured to sum the first amplified signal and the second amplified signal to provide a balanced output signal.

9. The data receiver of claim 8, wherein the data receiver is implemented as a serializer / deserializer. 10 . The data receiver of claim 8 , further comprising a control circuit configured to control the first gain of the first programmable gain amplifier and the second gain of the second programmable gain amplifier.

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