LVDS type daisy chain communication method based on effective signal detection

Abstract

The invention discloses an LVDS (Low Voltage Differential Signaling) type daisy chain communication method based on effective signal detection, which relates to the technical field of communication, and comprises the following steps: S1, setting acquisition nodes, and connecting all the acquisition nodes in series by using a differential LVDS link to form a daisy chain topological structure in a grading manner; s2, keeping the transceivers in the daisy chain topological structure in a sleep mode and keeping real-time detection; s3, when a high pulse signal is detected, waking up the LVDS module to receive data; and S4, after confirming that the parameters take effect, generating a response packet, returning the response packet to the computer end, returning to a dormant state, and forming a communication transmission energy-saving closed loop. According to the invention, through a mechanism of event triggering and local node participation, the system is awakened when a high-pulse effective signal is detected, so that the power consumption overhead caused by that all nodes are always active in a traditional communication architecture is avoided; the method has the advantages of greatly reducing the average power consumption of daisy chain data communication, improving the overall response rate of the system and reducing the confirmation time delay.

Description

[0001] A LVDS daisy chain communication method based on effective signal detection Technical Field

[0002] The present invention relates to the technical field of communications, and in particular to an LVDS type daisy chain communication method based on effective signal detection. Background Art

[0003] In distributed data acquisition systems, daisy-chain communication is widely used due to its simple wiring and strong scalability. It is especially suitable for multi-node, low-speed sensor networks, such as industrial monitoring and environmental sensing. Traditional daisy-chain designs are mainly aimed at high-speed data transmission, such as SerDes architecture, Gbps-level rates, and rely on complex clock recovery and equalization technologies, resulting in significant resource waste and excessive power consumption in low-speed scenarios (such as ≤100Mbps). High-channel interconnection bottleneck: Traditional buses, such as CAN and Ethernet, cannot meet the high-speed data aggregation needs of 80+ nodes or more, and the complexity of star topology wiring increases exponentially. The technical bottleneck of traditional low-speed buses is that in traditional multi-node systems, single-ended signal transmission methods such as SPI or UART have significant defects. Bandwidth limitation: The theoretical rate of SPI at a 20MHz clock is only 20Mbps (full-duplex), and the actual throughput of UART at a baud rate of 115200 is less than 1Mbps; Poor scalability: The CS line of SPI increases linearly with the number of nodes. 80 nodes require 80 chip select lines, and the wiring complexity increases exponentially; Insufficient anti-interference: Single-ended signals are susceptible to common-mode noise (CMRR < 30dB) during long-distance transmission, and the bit error rate can be as high as 1e-5.

[0004] Existing low-speed daisy-chain solutions, such as those based on JTAG or UART cascades, can reduce power consumption but suffer from low protocol efficiency and poor synchronization. Master-slave polling mechanisms are often used, resulting in link latency that increases linearly with the number of nodes. With an 80-level cascade, latency exceeds 10ms, failing to meet real-time requirements. Furthermore, traditional solutions lack hardware-level fault tolerance, and single-point failures can easily lead to system paralysis. In recent years, event-driven transmission and low-power LVDS interfaces have become research and development trends, but existing technologies have yet to resolve the critical contradiction between efficient synchronization and reliable bypass in low-speed scenarios. Summary of the Invention

[0005] The present invention provides an LVDS type daisy chain communication method based on effective signal detection, which solves the problem that it is difficult to maintain efficient data synchronization and control low latency while reducing power consumption in the low-speed data acquisition process of the existing low-speed daisy chain data communication.

[0006] The present invention is achieved through the following technical solutions: An LVDS daisy chain communication method based on effective signal detection, the method comprising: Step S1: setting a number of acquisition nodes connected to the computer end, using differential LVDS links to connect all the acquisition nodes in series to form a hierarchical daisy chain topology, and initializing a global clock tree for the daisy chain topology; Step S2: Using a computer terminal to load node parameters to the daisy chain topology using downlink commands, keeping the transceivers in the daisy chain topology in sleep mode, and simultaneously maintaining real-time detection of the loaded node parameters; Step S3: when it is detected that the valid signal of the node parameter is a high pulse signal, the transceiver is awakened to start the LVDS module in the differential LVDS link to receive data, and no operation is performed when a low pulse signal is detected; Step S4: After the last node of the daisy chain topology confirms that the parameters are effective, a response packet is generated and transmitted back to the computer. After confirming that each node has completed the transmission, it is forced to return to the sleep state, forming a communication transmission energy-saving closed loop.

[0007] Existing low-speed daisy chain solutions, such as the cascade method based on JTAG or UART, can reduce power consumption, but have the defects of low protocol efficiency and poor synchronization. Usually, the master-slave polling mechanism is more widely used, which causes the link delay to increase linearly with the number of nodes. The delay exceeds 10ms when the 80-level cascade is used, which cannot meet the real-time requirements. In addition, the traditional solution lacks hardware-level fault-tolerant design, and a single point failure can easily cause the system to crash. In recent years, event-driven transmission and low-power LVDS interfaces have become research and development trends, but the existing technology has not yet solved the key contradiction between efficient synchronization and reliable bypass in low-speed scenarios. Based on this, the present invention provides an LVDS daisy chain communication method based on effective signal detection to solve the problem that it is difficult to maintain efficient data synchronization and difficult to control low latency while reducing power consumption in the low-speed data acquisition process of the existing low-speed daisy chain data communication.

[0008] Furthermore, a detection processing process is also provided for the daisy chain topology structure, and the detection processing process is provided after the global clock tree is initialized; the detection processing process includes link quality detection and link fault detection: when the result of the detection processing process determines that the current link is an abnormal link, the instruction returns to the computer end to use the downlink instruction to load the node parameters to enter the valid signal detection; when the result of the detection processing process determines that the current link is a valid link, the data collection of all the acquisition nodes is packaged and transmitted back to the computer end.

[0009] Furthermore, a Trig trigger node is used to perform link quality detection on the daisy-chain topology after the global clock tree is initialized. The process includes: A BER threshold is set for the bit error rate of the daisy chain topology. When the bit error rate does not exceed the BER threshold, the current link is judged to be a valid link; when the bit error rate exceeds the BER threshold, the current link is judged to be an abnormal link.

[0010] Furthermore, the BYPASS fault node is used to perform link fault detection on the daisy-chain topology after the global clock tree is initialized. The process includes: A switching time threshold is set for the total switching time from fault detection to data path switching completion; valid signals of unloaded node parameters are collected. When the total switching time of the system is less than the switching time threshold, the current link is judged to be a valid link; when the total switching time of the system is greater than the switching time threshold, the current link is judged to be an abnormal link.

[0011] Furthermore, when the result of link fault detection determines that the current link is a valid link, the LVDS module in the daisy chain topology is used to receive data, and the data collected from all acquisition nodes is packaged and transmitted back to the computer through the BYPASS digital bypass.

[0012] Furthermore, the daisy chain topology structure includes: using multiple X-ray acquisition cards connected in series through a differential LVDS link, each X-ray acquisition card represents an acquisition node; the signal transmission interface of the X-ray acquisition card includes an uplink and a downlink; the uplink and downlink each include two sets of data input interfaces and data output interfaces.

[0013] Furthermore, the data input interface and data output interface of the uplink are configured as follows: the X-ray acquisition card is provided with a first uplink transmission terminal RX and a second uplink transmission terminal RX2, the first uplink transmission terminal RX and the second uplink transmission terminal RX2 respectively including an uplink input interface and an uplink output interface; The uplink form in the daisy chain topology is set as follows: the uplink output interface of the first uplink transmission end RX is connected to the uplink input interface of the first uplink transmission end RX, and the uplink output interface of the second uplink transmission end RX2 is connected to the uplink input interface of the second uplink transmission end RX2, so that multiple X-ray acquisition cards are connected in series end to end to form a closed loop.

[0014] Furthermore, the data input interface and data output interface of the downlink are configured as follows: the X-ray acquisition card is provided with a first downlink transmission terminal TX and a second downlink transmission terminal TX2, the first downlink transmission terminal TX and the second downlink transmission terminal TX2 respectively including a downlink input interface and a downlink output interface; The downlink form in the daisy chain topology is set as follows: multiple X-ray acquisition cards are connected in series end to end to form a closed loop by connecting the uplink output interface of the first downlink transmission end TX to the uplink input interface of the first uplink transmission end RX, and the uplink output interface of the second uplink transmission end RX2 to the uplink input interface of the second uplink transmission end RX2.

[0015] Furthermore, the uplink also includes an LVDS clock signal for initializing the global clock tree. The initial frequency of the LVDS clock signal is set to a 200MHz global synchronous clock, which is gradually transmitted to all nodes from an external input frequency of 10MHz and generated by MMCM inside the FPGA of each node.

[0016] Furthermore, the transmission contents of the uplink and downlink both include data signals and data valid signals; the data signals are used to transmit data and parameter configurations, and the data valid signals are used to complete data upload at the current acquisition node when the signal is in a high level state.

[0017] Compared with the existing technology, the present invention responds only to necessary nodes through the mechanism of event triggering and local node participation, greatly compressing the communication path and response time. At the same time, it is awakened when a high-pulse valid signal is detected, avoiding the power consumption overhead caused by all nodes being always active in the traditional communication architecture, and constructing a dynamic power consumption management cycle of "wake up-work-confirmation-sleep", which has the advantages of greatly reducing the average power consumption of daisy-chain data communication and improving the overall response rate of the system and reducing the confirmation delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Figure 1 It is a flowchart of the present invention; Figure 2 This is a complete structural diagram of the present invention; Figure 3 This is a block diagram of the daisy chain topology structure principle of the present invention; Figure 4 This is a timing diagram of the present invention. DETAILED DESCRIPTION

[0019] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0020] Example 1 like Figure 1As shown, this embodiment is an LVDS type daisy chain communication method based on effective signal detection, the method comprising: Step S1: setting a number of acquisition nodes connected to the computer end, using differential LVDS links to connect all the acquisition nodes in series to form a hierarchical daisy chain topology, and initializing a global clock tree for the daisy chain topology; Step S2: Using a computer terminal to load node parameters to the daisy chain topology using downlink commands, keeping the transceivers in the daisy chain topology in sleep mode, and simultaneously maintaining real-time detection of the loaded node parameters; Step S3: when it is detected that the valid signal of the node parameter is a high pulse signal, the transceiver is awakened to start the LVDS module in the differential LVDS link to receive data, and no operation is performed when a low pulse signal is detected; Step S4: After the last-level acquisition node of the daisy-chain topology confirms that the parameters are effective, a response packet is generated and transmitted back to the computer. After confirming that each node has completed the transmission, it is forced to return to the sleep state, forming a communication transmission energy-saving closed loop.

[0021] Using LVDS differential links to connect multiple nodes in series offers the inherent advantages of low power consumption, high noise immunity, and high speed. A "global clock tree" is initialized within the daisy-chain topology to ensure synchronized clock distribution across all nodes. This global clock tree eliminates synchronization errors caused by hop-by-hop jitter accumulation in traditional serial links, ensuring sub-nanosecond synchronization even in low-speed scenarios. Differential LVDS links offer excellent common-mode noise immunity, ensuring reliable communication in industrial environments. They also retain the advantages of daisy-chain wiring and are independent of star or ring topologies, allowing for manageability even when the number of nodes scales to hundreds. After loading downlink commands, the transceiver enters sleep mode by default, performing only real-time valid signal detection for the loaded node parameters. In sleep mode, the LVDS driver and receiver circuits disable most internal modules, saving over 50% static power compared to continuously awakening. Real-time monitoring of the loaded command signal avoids the unnecessary power consumption and potential delays associated with traditional polling to wake up all nodes. Nodes respond only when a high-frequency pulse arrives, eliminating the linear delay associated with the polling cycle and the number of nodes. The final node generates a "parameter validation response packet" and transmits it back. After confirming the completion of the response, all nodes enter a sleep state, forming a "communication-wake-up-transmission-sleep" cycle. The link automatically sleeps after each command cycle, eliminating the need for additional downlink commands to shut down the circuit, simplifying closed-loop control. The response packet mechanism also detects packet loss and link interruptions. If no response is received, a retry or bypass mechanism is triggered, enhancing hardware-level fault tolerance.

[0022] Example 2 In this embodiment, if Figure 2As shown, a detection processing process is also provided for the daisy chain topology structure, and the detection processing process is provided after the global clock tree is initialized; the detection processing process includes link quality detection and link fault detection: when the result of the detection processing process determines that the current link is an abnormal link, the instruction returns to the computer end to use the downlink instruction to load the node parameters to enter the valid signal detection; when the result of the detection processing process determines that the current link is a valid link, the data collected by all the acquisition nodes are packaged and transmitted back to the computer end.

[0023] Before the link actually begins parameter loading and data transmission, the link health is assessed to avoid wasted wake-up, transmission, and sleep cycles due to invalid or damaged links. Link quality testing evaluates LVDS differential link signal integrity metrics, such as bit error rate (BER), eye opening, and jitter, to determine whether communication performance meets thresholds. Link fault detection rapidly detects hardware faults such as physical link interruptions and signal anomalies, achieved through digital bypass or dedicated diagnostic frames. If a link is identified as poor quality or faulty, the system immediately returns to the "downlink command loading" phase, re-executes parameter loading, and re-awakens the corresponding node through "valid signal detection," enabling rapid isolation and repair of the link fault. If the link is identified as valid, the system skips the wake-up / loading process and directly enters the data collection, packaging, and backhaul phases. This allows for efficient data transmission, reduces wake-up and sleep transitions, saves power, and shortens response latency. This dual link quality and fault detection allows for rapid troubleshooting at the physical level, preventing data loss caused by interruptions and bit errors. At the same time, the wake-up / loading process is only entered when necessary, effectively reducing the number of wake-up-transmission-sleep switching times; direct transmission can be performed on stable links, saving switching overhead; and the use of automated detection and recovery processes reduces manual inspection and maintenance costs.

[0024] Furthermore, as a feasible implementation method, a Trig trigger node is used to perform link quality detection on the daisy chain topology structure after the global clock tree is initialized. The process includes: setting a BER threshold for the bit error rate of the daisy chain topology structure; when the bit error rate does not exceed the BER threshold, the current link is judged to be a valid link; when the bit error rate exceeds the BER threshold, the current link is judged to be an abnormal link.

[0025] After the global clock tree is distributed, the Trig trigger node generates a detection start signal, which can be a timed or event-triggered implementation. This trigger signal is sent to the link quality detection module, initiating the subsequent BER measurement process. A BER statistics unit is integrated into the transceiver of the differential LVDS link to continuously or periodically collect the number of error bits and the total number of bits in the received data stream. The BER threshold can be pre-configured in the host computer or trigger node based on the actual system tolerance and environmental noise conditions. If a valid link is identified, the wake-up and load process is skipped, and data collection and transmission proceed directly. If an abnormal link is identified, a downlink instruction is immediately triggered to reload parameters or bypass switching, and valid signal detection is re-executed. In specific implementations, the Trig trigger node can be designed using a small FPGA or dedicated microcontroller to monitor the global clock completion signal and output a detection start pulse. By synchronizing the Trig with the global clock and using standardized BER thresholds, fast BER measurement can be achieved in parallel with data transmission.

[0026] Furthermore, as a feasible implementation method, a BYPASS fault node is used to perform link fault detection on the daisy chain topology after the global clock tree is initialized. The process includes: A switching time threshold is set for the total switching time from fault detection to data path switching completion; valid signals of unloaded node parameters are collected. When the total switching time of the system is less than the switching time threshold, the current link is judged to be a valid link; when the total switching time of the system is greater than the switching time threshold, the current link is judged to be an abnormal link.

[0027] When the main link fails, the BYPASS fault node immediately triggers bypass switching and automatically redirects the communication path to the backup link or the backup port of the next-level node. The BYPASS fault node starts a high-precision timer internally, and the period from "fault detection to handshake completion" is the "total switching time"; at the same time, the "valid signal of unloaded node parameters" status is collected in parallel to ensure that the node is in standby rather than transmission state during the measurement, eliminating the delay interference of the transmission itself. Including the bypass switching time in the link health judgment index enables the system to not only perceive the fault, but also measure the recovery speed. When the switching time is within the threshold, communication can continue immediately without interrupting the process; if it times out, it will automatically enter the deep recovery or alarm process. In a specific implementation, the switching time threshold can be set to 100ns.

[0028] Furthermore, as a feasible implementation method, when the result of the link fault detection determines that the current link is a valid link, the LVDS module in the daisy chain topology is used to receive data, and the data collected from all acquisition nodes is packaged and transmitted back to the computer through the BYPASS digital bypass.

[0029] The LVDS transceivers on all cascaded nodes exit the sleep state and only keep the receiving channel open. The LVDS module receives the acquisition command and timing forwarded by the upper level or trigger node, and synchronously picks up the data frames of the sensors or acquisition units of each node. The BYPASS fault node performs "digital bypass" in parallel when receiving link data, that is, there is no need to interrupt the main link, and the data collected by each node is directly aggregated to the bypass buffer. After the data is aggregated, the bypass module packages the data of all nodes in the entire link according to the predefined protocol. After the packaging is completed, the data frame is directly passed back to the computer host through the differential LVDS link. Digital bypass packaging avoids multiple handshakes at each node, and data return only requires one link transmission; at the same time, only the minimum LVDS module is started in the receiving and packaging links, and the overall power consumption is further reduced.

[0030] Example 3 In this embodiment, if Figure 3-Figure 4 As shown, the daisy chain topology includes: using multiple X-ray acquisition cards connected in series through a differential LVDS link, each X-ray acquisition card represents an acquisition node; the signal transmission interface of the X-ray acquisition card includes an uplink and a downlink; the uplink and downlink each include two sets of data input interfaces and data output interfaces.

[0031] Furthermore, the data input interface and data output interface of the uplink are configured as follows: the X-ray acquisition card is provided with a first uplink transmission terminal RX and a second uplink transmission terminal RX2, the first uplink transmission terminal RX and the second uplink transmission terminal RX2 respectively including an uplink input interface and an uplink output interface; The uplink form in the daisy chain topology is set as follows: the uplink output interface of the first uplink transmission end RX is connected to the uplink input interface of the first uplink transmission end RX, and the uplink output interface of the second uplink transmission end RX2 is connected to the uplink input interface of the second uplink transmission end RX2, so that multiple X-ray acquisition cards are connected in series end to end to form a closed loop.

[0032] Furthermore, the data input interface and data output interface of the downlink are configured as follows: the X-ray acquisition card is provided with a first downlink transmission terminal TX and a second downlink transmission terminal TX2, the first downlink transmission terminal TX and the second downlink transmission terminal TX2 respectively including a downlink input interface and a downlink output interface; The downlink form in the daisy chain topology is set as follows: multiple X-ray acquisition cards are connected in series end to end to form a closed loop by connecting the uplink output interface of the first downlink transmission end TX to the uplink input interface of the first uplink transmission end RX, and the uplink output interface of the second uplink transmission end RX2 to the uplink input interface of the second uplink transmission end RX2.

[0033] In the uplink, the uplink input interface of the first uplink transmission terminal RX of the previous collection node is connected to the uplink output interface of the first uplink transmission terminal RX of the next collection node; the uplink output interface of the first uplink transmission terminal RX of the last collection node is then connected to the uplink output interface of the first uplink transmission terminal RX of the first collection node; the second uplink transmission terminal RX2 is similar to the first uplink transmission terminal RX. The connection form of the downlink is the same as that of the uplink. The downlink input interface of the first downlink transmission terminal TX of the previous collection node is connected to the downlink output interface of the first downlink transmission terminal TX of the next collection node, and then the end is looped back to the head end, forming a dual-channel closed loop; the second downlink transmission terminal TX2 is similar to the first downlink transmission terminal TX. The end loops back to the head end, naturally forming a ring network. If a single point of link breakage occurs, it can be bypassed in another direction. Unlike traditional star or tree structures, the series structure facilitates scalability, the number of nodes can be freely increased, and the wiring cost increases linearly. Globally synchronized clocks and differential LVDS links ensure low latency, allowing for free addition and removal of serial nodes. This supports deployments exceeding 100 nodes and is suitable for multi-card, low-speed, long-loop, and industrial-grade X-ray acquisition scenarios, playing an important role in improving overall system performance.

[0034] There are two physical links in each direction. As a feasible specific implementation method, the transmission content of the uplink and downlink includes data signals and data valid signals; the data signal is used to transmit data and parameter configuration, and the data valid signal is used to complete data upload at the current acquisition node when the signal is in a high-level state. When the node is ready to complete its own data upload, the data valid signal is set to a high level and the corresponding data frame is sent at the same time; the data valid signal is a "transmission synchronization trigger" to notify subsequent nodes or hosts that the frame is uploaded by this node and cannot be ignored. Using an independent valid signal as a frame trigger can effectively avoid common low-speed link problems such as data packet misjudgment, packet sticking or miscoding. At the same time, all nodes are bypassed by default during non-high-level periods, and unloaded nodes can be skipped to reduce invalid transmission and link congestion; when the node spacing is large and the time extension is extended, it relies on the valid signal trigger to improve the control accuracy of the upload timing.

[0035] As a specific application, the uplink is also provided with a protocol signal port, such as Figure 4As shown, the protocol signal ports include the RX_DATA port in the uplink and the TX_DATA port in the downlink. The RX_DATA and TX_DATA ports are used to convert serial SPI protocol data into 32-bit AXI stream protocol bytes via Xilinx ISERDES and a 1:4 FIFO, facilitating data parsing. The data valid signal is configured as one of the data input and output interfaces in the uplink and downlink, labeled as the RX_EN port and the TX_EN port in the downlink. During a high-level period, the current node responds to instructions or uploads data; when the level is low, the bus is ignored. IDELAYE2 adjustment and TX_D / RX_D delay ensure phase ambiguity. The data signal is configured as another data input and output interface in the uplink and downlink, labeled as the RX_D port and the TX_D port in the downlink. Functioning similarly to SPI_SDI, it is used to transmit data or parameter configuration.

[0036] This embodiment proposes a hardware-level valid signal detection mechanism, replacing the traditional continuously active communication mode. The LVDS transceiver wakes up only when a valid signal rising edge is detected; during inactive periods, it is forced into a sleep state, resulting in over 90% energy savings compared to traditional solutions. Valid and data signals are transmitted separately via dedicated LVDS pairs. Low-power detection circuitry is integrated within the FPGA, achieving a response latency of <100ns. By physically isolating the data forwarding path from the business logic processing path, daisy-chain communication and board functions can operate completely independently.

[0037] In normal mode, the data transparent transmission channel: LVDS data streams are directly forwarded after being buffered at the FPGA hardware level, with a fixed latency of <10ns, ensuring real-time communication. Parallel business logic: Data parsing, protocol packaging, and other functions are asynchronously processed in independent logic threads, without timing coupling with the communication link. In fault mode, when a business logic failure is detected, such as a checksum timeout or state machine deadlock, a purely combinatorial logic bypass path is automatically activated, completely bypassing the processing module and maintaining a smooth link.

[0038] In specific implementations, the independent clock domain division of the Xilinx Artix-7 FPGA can be used. The communication link (200MHz synchronous clock) and the business logic (100MHz asynchronous clock) interact through a dual-port RAM; the data forwarding path only includes shift registers and FIFO hard cores (no software programmable logic).

[0039] This embodiment uses a valid signal as the accompanying clock reference, simplifying the data recovery process. This eliminates the need for traditional embedded clock recovery circuitry, reducing power consumption by 70%. Data bytes are captured and reassembled within a fixed window of eight CLK cycles, mitigating bit slippage. Within the valid data window, the rising edge of the CLK is sampled eight times continuously to form a complete data word. The FPGA's internal IDELAYE2 dynamically calibrates delays (accuracy: ±78ps) to match multi-node timing skew.

[0040] In terms of beneficial effects, this embodiment utilizes a differential LVDS low-voltage differential signaling architecture to achieve ultra-high transmission rates: a single LVDS pair supports 100Mbps at a 200MHz clock (DDR mode), and four LVDS pairs in parallel provide 400Mbps effective bandwidth; this represents a 20-fold improvement compared to SPI and a 400-fold improvement compared to UART. It also simplifies topology design: a daisy-chain connection requires only five LVDS pairs across all nodes, reducing wiring requirements for an 80-node system by 98% (compared to SPI). Parallel data aggregation is also possible, with each node transmitting data clocks via five TX / RX LVDS pairs. A hard-core serializer integrated within the FPGA converts 8-bit data into a serial LVDS stream. A clock synchronization solution: a dedicated LVDS pair transmits a 10MHz global clock, and each node regenerates a low-jitter clock via a multi-processor module (MMCM). 8-bit data is reassembled within the data valid window, avoiding the power consumption issues of traditional embedded clock recovery.

[0041] Furthermore, as a feasible implementation method, the uplink also includes an LVDS clock signal for initializing the global clock tree. The initial frequency of the LVDS clock signal is set to a 200MHz global synchronous clock, which is gradually transmitted to all nodes by an external input frequency of 10MHz, and is generated by MMCM inside the FPGA of each node; the transmission content of the uplink and downlink both include data signals and data valid signals; the data signal is used to transmit data and parameter configuration, and the data valid signal is used to complete data upload at the current acquisition node when the signal is in a high-level state.

[0042] Each X-ray acquisition card's FPGA integrates an integrated MMCM to multiply the 10MHz input clock to a 200MHz LVDS synchronous clock. The initial clock signal is input to the first node by an external master controller. Subsequent nodes receive it and regenerate the clock using their own MMCMs, maintaining consistent frequency and adjustable phase, thus achieving global synchronization at the link level. Data signals, which typically include raw sensor data, status information, command feedback, and parameter configurations, are transmitted using LVDS encoding. The data valid signal is typically a single bit. A high state indicates that the data for the current node is ready and the system should immediately accept and upload it. In the control state machine, the data signal content is considered valid only when the data valid signal is high. Global 200MHz clock synchronization is achieved using LVDS and MMCM, ensuring consistent timing and low jitter across all acquisition nodes. The data signal and data valid signal are separated, ensuring that data is transmitted only when the valid flag is set, avoiding "dirty writes" or empty transmissions. Only a 10MHz reference clock input is required externally, while the internal MMCM output can be dynamically adjusted to accommodate acquisition and transmission requirements of varying frequencies. When there is no valid data signal, some modules of the node can enter the IDLE or low-power state, and combined with the wake-up mechanism, it can form an energy-saving closed-loop control logic. The global clock tree works together with the data signal and the valid signal to ensure the alignment of the node time axis when data is packaged, simplifying the back-end timestamp synchronization and sorting logic.

[0043] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An LVDS type daisy chain communication method based on effective signal detection, characterized in that: The method includes: Step S1: setting a number of acquisition nodes connected to the computer end, using differential LVDS links to connect all the acquisition nodes in series to form a hierarchical daisy chain topology, and initializing a global clock tree for the daisy chain topology; Step S2: Using a computer terminal to load node parameters to the daisy chain topology using downlink commands, keeping the transceivers in the daisy chain topology in sleep mode, and simultaneously maintaining real-time detection of the loaded node parameters; Step S3: when it is detected that the valid signal of the node parameter is a high pulse signal, the transceiver is awakened to start the LVDS module in the differential LVDS link to receive data, and no operation is performed when a low pulse signal is detected; Step S4: After the last node of the daisy chain topology confirms that the parameters are effective, a response packet is generated and transmitted back to the computer. After confirming that each node has completed the transmission, it is forced to return to the sleep state, forming a communication transmission energy-saving closed loop.

2. The LVDS daisy chain communication method based on effective signal detection according to claim 1, characterized in that: A detection processing process is also provided for the daisy chain topology structure, and the detection processing process is provided after the global clock tree is initialized; the detection processing process includes link quality detection and link fault detection: when the result of the detection processing process determines that the current link is an abnormal link, the instruction returns to the computer end to use the downlink instruction to load the node parameters to enter the valid signal detection; when the result of the detection processing process determines that the current link is a valid link, the data collected by all the acquisition nodes is packaged and transmitted back to the computer end.

3. The LVDS daisy chain communication method based on effective signal detection according to claim 2, characterized in that: Use the Trig trigger node to perform link quality testing on the daisy-chain topology after the global clock tree is initialized. The process includes: A BER threshold is set for the bit error rate of the daisy chain topology. When the bit error rate does not exceed the BER threshold, the current link is judged to be a valid link; when the bit error rate exceeds the BER threshold, the current link is judged to be an abnormal link.

4. The LVDS daisy chain communication method based on effective signal detection according to claim 2, characterized in that: Use the BYPASS fault node to detect link faults in the daisy-chain topology after the global clock tree is initialized. The process includes: A switching time threshold is set for the total switching time from fault detection to data path switching completion; valid signals of unloaded node parameters are collected. When the total switching time of the system is less than the switching time threshold, the current link is judged to be a valid link; when the total switching time of the system is greater than the switching time threshold, the current link is judged to be an abnormal link.

5. The LVDS daisy chain communication method based on effective signal detection according to claim 4, characterized in that: When the link fault detection result determines that the current link is a valid link, the LVDS module in the daisy chain topology is used to receive data, and the data collected from all acquisition nodes is packaged and transmitted back to the computer through the BYPASS digital bypass.

6. The LVDS daisy chain communication method based on effective signal detection according to claim 1, characterized in that: The daisy chain topology structure includes: using multiple X-ray acquisition cards connected in series through a differential LVDS link, each X-ray acquisition card represents an acquisition node; the signal transmission interface of the X-ray acquisition card includes an uplink and a downlink; the uplink and downlink each include two sets of data input interfaces and data output interfaces.

7. The LVDS daisy chain communication method based on effective signal detection according to claim 6, characterized in that: The data input interface and data output interface of the uplink are configured as follows: the X-ray acquisition card is provided with a first uplink transmission terminal RX and a second uplink transmission terminal RX2, wherein the first uplink transmission terminal RX and the second uplink transmission terminal RX2 respectively include an uplink input interface and an uplink output interface; The uplink form in the daisy chain topology is set as follows: the uplink output interface of the first uplink transmission end RX is connected to the uplink input interface of the first uplink transmission end RX, and the uplink output interface of the second uplink transmission end RX2 is connected to the uplink input interface of the second uplink transmission end RX2, so that multiple X-ray acquisition cards are connected in series end to end to form a closed loop.

8. The LVDS daisy chain communication method based on effective signal detection according to claim 6, characterized in that: The data input interface and data output interface of the downlink are configured as follows: the X-ray acquisition card is provided with a first downlink transmission terminal TX and a second downlink transmission terminal TX2, the first downlink transmission terminal TX and the second downlink transmission terminal TX2 respectively including a downlink input interface and a downlink output interface; The downlink form in the daisy chain topology is set as follows: multiple X-ray acquisition cards are connected in series end to end to form a closed loop by connecting the uplink output interface of the first downlink transmission end TX to the uplink input interface of the first uplink transmission end RX, and the uplink output interface of the second uplink transmission end RX2 to the uplink input interface of the second uplink transmission end RX2.

9. The LVDS daisy chain communication method based on effective signal detection according to claim 6, characterized in that: The uplink also includes an LVDS clock signal for initializing the global clock tree. The initial frequency of the LVDS clock signal is set to a 200MHz global synchronous clock, which is gradually transmitted to all nodes from an external input frequency of 10MHz and generated by MMCM inside the FPGA of each node.

10. The LVDS daisy chain communication method based on effective signal detection according to claim 6, characterized in that: The transmission contents of the uplink and downlink both include data signals and data valid signals; the data signals are used to transmit data and parameter configurations, and the data valid signals are used to complete data upload at the current acquisition node when the signal is in a high-level state.

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