TOPCon battery and preparation method thereof

Abstract

The invention relates to the technical field of TOPCon batteries, in particular to a TOPCon battery and a preparation method thereof. The preparation method of the TOPCon battery comprises the following steps: texturing a silicon wafer; performing boron diffusion doping on the front surface of the silicon wafer; carrying out acid washing and alkali washing polishing on the back surface of the silicon wafer; a first tunneling layer, a first doped polycrystalline silicon layer, a second tunneling layer and a second doped polycrystalline silicon layer are sequentially deposited on the back face of the silicon wafer, high-temperature annealing is conducted on the silicon wafer, and temporary protection layers are formed in an emitting electrode grid line area and a non-emitting electrode grid line area on the back face of the silicon wafer; performing film opening treatment on the temporary protection layer in a non-emitter grid line area; forming a textured structure on the second doped polycrystalline silicon layer; pickling the silicon wafer; depositing a passivation layer on the front surface of the silicon wafer; and depositing protective layers on the front surface and the back surface of the silicon wafer and then performing metallization sintering. According to the technical scheme, the absorption of sunlight by the TOPCon cell can be improved, and the conversion efficiency of the TOPCon cell can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of TOPCon batteries, and in particular to a TOPCon battery and a preparation method thereof. Background Art

[0002] TOPCon cell is a high-efficiency solar cell with tunneling oxide passivation contact based on the principle of selective carriers.

[0003] The current process flow for TOPCon cells is as follows: texturing – boron diffusion – alkaline polishing – N+ polysilicon layer – RCA cleaning – ALD aluminum oxide – positive nitride film – back silicon nitride film – screen-printed emitter – sintering – light injection. TOPCon cells are alkaline-polished on the backside to create a planar structure. An ultrathin silicon oxide layer is then deposited, followed by a thin doped silicon layer, which remains planar. Together, these two layers form a passivated contact structure, effectively reducing surface and metal-contact recombination, increasing the open-circuit voltage and, consequently, the conversion efficiency of the solar cell.

[0004] To achieve better tunneling passivation and improve the front-side efficiency of solar cells, the backside of solar cells is typically a planar structure with high reflectivity, resulting in very poor light trapping on the backside and, in turn, low backside efficiency. The bifaciality of Topcon cells is affected by both front-side and backside efficiencies, with bifaciality being the ratio of backside efficiency to frontside efficiency. Therefore, the planar structure of the cell's backside surface reduces backside efficiency, leading to a low bifaciality. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a TOPCon battery and a preparation method thereof.

[0006] In a first aspect, the present invention provides a method for preparing a TOPCon battery, comprising:

[0007] Step 1, texturing the silicon wafer;

[0008] Step 2: performing boron diffusion doping on the front surface of the silicon wafer;

[0009] Step 3, acid washing and alkaline polishing are performed on the back side of the silicon wafer;

[0010] Step 4: forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer in sequence on the back side of the silicon wafer, and performing high-temperature annealing on the silicon wafer, and forming a temporary protective layer on the emitter gate line region and the non-emitter gate line region on the back side of the silicon wafer;

[0011] Step 5, performing a film opening process on the temporary protection layer in the non-emitter gate line area;

[0012] Step 6: Texturing the non-emitter gate line region to form a textured structure on the second doped polysilicon layer in the non-emitter gate line region;

[0013] Step 7, pickling the silicon wafer;

[0014] Step 8: depositing a passivation layer on the front side of the silicon wafer;

[0015] Step 9: depositing a protective layer on the front and back sides of the silicon wafer;

[0016] Step 10: metallizing and sintering the silicon wafer.

[0017] In some embodiments, in step 4, forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer in sequence on the back side of the silicon wafer includes:

[0018] Depositing a first tunneling layer, a first polysilicon layer, a second tunneling layer, and a second polysilicon layer in sequence on the back side of the silicon wafer using an LPCVD process;

[0019] Phosphorus diffusion doping is performed on the back side of the silicon wafer to form the first doped polysilicon layer and the second doped polysilicon layer, and a temporary protective layer formed on the surface of the second doped polysilicon layer is a phosphorus silicon glass layer.

[0020] In some embodiments, in step 4, forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer in sequence on the back side of the silicon wafer includes:

[0021] A first tunneling layer, a first doped polysilicon layer, a second tunneling layer and a second doped polysilicon layer are sequentially deposited on the back of the silicon wafer using a PECVD process, and a temporary protective layer formed on the surface of the second doped polysilicon layer is a silicon oxide layer.

[0022] In some embodiments, in step 4, the sheet resistance of the first doped polysilicon layer and the second doped polysilicon layer is 30-60Ω.

[0023] In some embodiments, in step 4, the high temperature annealing temperature is 850-950°C.

[0024] In some embodiments, in step 5, performing a film opening process on the temporary protective layer in the non-emitter gate line region includes:

[0025] Laser is used to perform a film-opening process on the temporary protection layer in the non-emitter gate line area.

[0026] In some embodiments, the laser spot size is 100-300 μm, and the laser power is 50-300 W.

[0027] In some embodiments, in step 5, the film opening depth is 30%-50% of the thickness of the temporary protective layer.

[0028] In some embodiments, in step 9, the protective layer is Si x N y Thin film or SiON y film.

[0029] In a second aspect, the present invention further provides a TOPCon battery, which is prepared according to the preparation method described in the first aspect, and the TOPCon battery comprises:

[0030] A silicon wafer, wherein a first textured structure is formed on the front side of the silicon wafer, and a boron-doped layer, a passivation layer, a protective layer, and a first electrode burned through the passivation layer are sequentially formed on the textured structure;

[0031] A first tunneling layer, a first doped polysilicon layer, a second tunneling layer, a second doped polysilicon layer, a protective layer and a second electrode burned through to the first doped polysilicon layer are formed in sequence on the back side of the silicon wafer, and a second velvet structure is formed on the side of the second doped polysilicon layer away from the silicon wafer.

[0032] The technical solution provided by the embodiment of the present invention has the following advantages compared with the existing technology:

[0033] The TOPCon cell prepared by the TOPCon cell preparation method provided in an embodiment of the present invention adopts a planar polishing structure in the emitter grid line area on the back side of the TOPCon cell to maintain contact performance, and forms a velvet structure in the non-emitter grid line area on the back side of the TOPCon cell to enhance light capture capability. This can maintain electrical contact to improve the optical utilization rate of the back side of the TOPCon cell, which is beneficial to improving the back side efficiency, thereby improving the bifaciality of the TOPCon cell, improving the absorption of sunlight by the TOPCon cell, and improving the conversion efficiency of the TOPCon cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0036] Figure 1 A schematic flow chart of a method for preparing a TOPCon battery according to an embodiment of the present invention;

[0037] Figure 2 A schematic structural diagram of a TOPCon battery provided in an embodiment of the present invention;

[0038] Figure 3 This is a structural diagram of a TOPCon battery provided in the related art.

[0039] Among them, 10, silicon wafer; 11, boron-doped layer; 12, passivation layer; 13, protective layer; 14, first tunneling layer; 15, first doped polysilicon layer; 16, second tunneling layer; 17, second doped polysilicon layer; 01, first electrode; 02, second electrode. DETAILED DESCRIPTION

[0040] In order to more clearly understand the above-mentioned objectives, features and advantages of the present invention, the scheme of the present invention will be further described below. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features therein can be combined with each other.

[0041] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present invention, rather than all the embodiments.

[0042] The TOPCon cell prepared by the TOPCon cell preparation method provided in an embodiment of the present invention adopts a planar polishing structure in the emitter grid line area on the back side of the TOPCon cell to maintain contact performance, and forms a velvet structure in the non-emitter grid line area on the back side of the TOPCon cell to enhance light capture capability. This can maintain electrical contact to improve the optical utilization rate of the back side of the TOPCon cell, which is beneficial to improving the back side efficiency, thereby improving the bifaciality of the TOPCon cell, improving the absorption of sunlight by the TOPCon cell, and improving the conversion efficiency of the TOPCon cell.

[0043] Figure 1 A schematic diagram of a process for preparing a TOPCon battery according to an embodiment of the present invention. Figure 1 As shown, the preparation method of TOPCon battery includes the following steps:

[0044] S1, texturing the silicon wafer;

[0045] S2, performing boron diffusion doping on the front side of the silicon wafer;

[0046] S3, pickling and alkali-washing and polishing the back side of the silicon wafer;

[0047] S4. Forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer in sequence on the back side of the silicon wafer, and performing high-temperature annealing on the silicon wafer, forming a temporary protective layer on the emitter gate line region and the non-emitter gate line region on the back side of the silicon wafer;

[0048] S5, performing a film opening process on the temporary protection layer in the non-emitter gate line area;

[0049] S6, performing texturing on the non-emitter gate line region to form a texturing structure on the second doped polysilicon layer in the non-emitter gate line region;

[0050] S7, pickling the silicon wafer;

[0051] S8, depositing a passivation layer on the front side of the silicon wafer;

[0052] S9, depositing a protective layer on the front and back sides of the silicon wafer;

[0053] S10, metallizing and sintering the silicon wafer.

[0054] Figure 2 A schematic structural diagram of a TOPCon battery provided in an embodiment of the present invention is shown. Figure 2 The TOPCon battery shown uses Figure 1 Prepared by the preparation method shown in FIG. Figure 2 As shown, the TOPCon cell includes: a silicon wafer 10, a first velvet structure is formed on the front side of the silicon wafer 10, a boron-doped layer 11, a passivation layer 12 and a protective layer 13 are sequentially formed on the velvet structure, and a first electrode 01 is formed on the front side of the silicon wafer 10 and burned through to the passivation layer 12; a first tunneling layer 14, a first doped polysilicon layer 15, a second tunneling layer 16, a second doped polysilicon layer 17 and a protective layer 13 are sequentially formed on the back side of the silicon wafer 10, a second electrode 02 is formed on the back side of the silicon wafer 10 and burned through to the first doped polysilicon layer 15, and a second velvet structure is formed on the side of the second doped polysilicon layer 17 away from the silicon wafer 10.

[0055] It should be noted that Figure 2 The boron-doped layer 11 in the figure can be understood as a film layer located between the passivation layer 12 and the front surface of the silicon wafer 10. Figure 3 The boron-doped layer 11 shown is also understood to be a film layer located between the passivation layer 12 and the front side of the silicon wafer 10 .

[0056] In this embodiment of the present invention, the silicon wafer provided in S1 is an N-type silicon wafer. A texturing additive is required when texturing the surface of the N-type silicon wafer. The core mechanism of the texturing additive is to form a uniform light-trapping pyramid structure on the silicon wafer surface by regulating the anisotropic corrosion dynamics of the alkaline solution (crystal plane selectivity, hydrogen bubble release) and optimizing interface conditions (surface tension, corrosion rate), thereby improving the light absorption efficiency of the solar cell.

[0057] Among them, the front and back of the N-type silicon wafer include Figure 2 The emitter gate line region AA' is used to set the electrode and the non-emitter gate line region BB' is located outside the emitter gate line region.

[0058] In the embodiment of the present invention, boron diffusion doping is performed on the front side of the silicon wafer in S2 to form a boron doped layer on the front side of the silicon wafer, and simultaneously borosilicate glass layers are formed on the front side and the back side of the silicon wafer.

[0059] In the embodiment of the present invention, the acid cleaning in S3 is to remove the borosilicate glass layer formed on the back side of the silicon wafer, followed by alkaline cleaning and polishing.

[0060] In an embodiment of the present invention, after the alkaline washing and polishing in S3, a tower base is formed on the back of the silicon wafer. The width of the tower base is 7-15um and the depth is 1-5um. Thus, a tower base with uniform consistency is obtained, and the flatness of the back of the silicon wafer is maintained, which is conducive to the next step of the deposition process on the back of the silicon wafer.

[0061] Specifically, in S1, when the silicon wafer is textured, a velvet structure is formed on the front side of the silicon wafer, and a velvet structure is formed on the back side of the silicon wafer. The velvet structure can be a pyramid structure. In S3, the alkali cleaning and polishing is performed to remove the top of the pyramid structure formed on the back side of the silicon wafer, thereby obtaining a consistent tower base with a reflectivity of 40-50%. For example, the entire back side of the silicon wafer is placed in a wet tank, and the top of the pyramid structure is etched away.

[0062] Among them, the width of the tower base can be 7um, 8um, 9um, 10um, 11um, 12um, 13um, 14um, and 15um; the depth of the tower base can be 1um, 2um, 3um, 4um, and 5um.

[0063] In an embodiment of the present invention, in S4, the thickness of the first tunneling layer is 1-2 nm, the thickness of the first doped polysilicon layer is 20-50 nm, the thickness of the second tunneling layer is 2-5 nm, and the thickness of the second doped polysilicon layer is 90-150 nm.

[0064] Exemplarily, the thickness of the first tunneling layer is 1nm, 1.5nm, and 2nm; the thickness of the first polysilicon layer is 20nm, 30nm, 40nm, and 50nm; the thickness of the second tunneling layer is 2nm, 3nm, 4nm, and 5nm; and the thickness of the second doped polysilicon layer is 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, and 150nm.

[0065] In an embodiment of the present invention, the step of sequentially forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer on the back side of the silicon wafer in S4 includes:

[0066] Depositing a first tunneling layer, a first polysilicon layer, a second tunneling layer, and a second polysilicon layer in sequence on the back side of the silicon wafer using an LPCVD process;

[0067] Phosphorus diffusion doping is performed on the back side of the silicon wafer to form the first doped polysilicon layer and the second doped polysilicon layer, and a temporary protective layer formed on the surface of the second doped polysilicon layer is a phosphorus silicon glass layer.

[0068] The LPCVD process is a low-pressure chemical vapor deposition process. Specifically, a phosphosilicate glass layer is formed on the surface of the second doped polysilicon layer using the LPCVD process as a temporary protective layer for the emitter gate line region in step 6. The thickness of the phosphosilicate glass layer is 20-35 nm. For example, the thickness of the phosphosilicate glass layer can be 20 nm, 25 nm, 30 nm, or 35 nm.

[0069] In an embodiment of the present invention, in S4, forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer in sequence on the back side of the silicon wafer includes:

[0070] A first tunneling layer, a first doped polysilicon layer, a second tunneling layer and a second doped polysilicon layer are sequentially deposited on the back of the silicon wafer using a PECVD process, and a temporary protective layer formed on the surface of the second doped polysilicon layer is a silicon oxide layer.

[0071] The PECVD process is a plasma-enhanced chemical vapor deposition process. Specifically, a silicon oxide layer is formed on the surface of the second doped polysilicon layer using the PECVD process as a temporary protective layer for the emitter gate line region in step 6. The thickness of the silicon oxide layer is 5-30 nm. For example, the thickness of the silicon oxide layer can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm.

[0072] In an embodiment of the present invention, in S4, the sheet resistance of the first doped polysilicon layer and the second doped polysilicon layer is 30-60Ω. For example, the sheet resistance may be 30Ω, 40Ω, 50Ω, or 60Ω. Within this sheet resistance range, the first doped polysilicon layer and the second doped polysilicon layer can have relatively good conductivity.

[0073] In an embodiment of the present invention, in S4, the temperature of the high-temperature annealing is 850-950° C. Exemplarily, the temperature of the high-temperature annealing is 850° C., 870° C., 890° C., 910° C., 930° C., or 950° C. Specifically, setting the temperature of the high-temperature annealing to 850-950° C. is conducive to crystallizing the first doped polysilicon layer and the second doped polysilicon layer.

[0074] In an embodiment of the present invention, in S5, performing a film opening process on the temporary protective layer in the non-emitter gate line region includes:

[0075] Laser is used to perform a film-opening process on the temporary protection layer in the non-emitter gate line area.

[0076] Specifically, the laser beam has a small spot size and concentrated energy. Using the laser to perform the film-opening process on the temporary protective layer in the non-emitter grid line area can achieve high processing precision and efficiency. Furthermore, the laser film-opening process eliminates the need for large amounts of cutting fluids and lubricants, reducing environmental pollution.

[0077] In some embodiments, the temporary protection layer in the non-emitter gate line region may be opened by other processes well known in the art, which is not specifically limited in the embodiment of the present invention.

[0078] In an embodiment of the present invention, in S5, laser film opening is performed, with a laser spot size of 100-300 μm and a laser power of 50-300 W. The laser spot size can be 100 μm, 150 μm, 250 μm, or 300 μm; the laser power can be 50 W, 100 W, 150 W, 200 W, 250 W, or 300 W. The laser wavelength is 400-700 nm, for example, 400 nm, 500 nm, 600 nm, or 700 nm.

[0079] Specifically, laser ablation is performed on the temporary protective layer in the non-emitter gridline area on the back of the silicon wafer. The mechanism of laser ablation is primarily based on the thermal and photochemical effects generated by the interaction between the high-energy laser beam and the material. The laser beam spot size enables submicron processing accuracy, avoiding material damage caused by mechanical contact. It is suitable for non-destructive ablation of ultra-thin layers (thickness <100µm). Combined with a galvanometer scanning system, it can process thin film patterns of arbitrary shapes (such as circles, grids, and irregular holes) to meet the requirements of photovoltaic cell selectivity.

[0080] In an embodiment of the present invention, in S5, the laser film opening depth is set to 30%-50% of the thickness of the protective layer. Specifically, by setting the film opening depth to 30%-50% of the thickness of the temporary protective layer, in S6, it is advantageous to form a velvet structure on the second doped polysilicon layer in the non-emitter gate line region while preserving the integrity of the second doped polysilicon layer in the emitter gate line region.

[0081] In the embodiment of the present invention, in step S6, a slow etching rate is achieved by regulating the concentration of the alkaline and additives in the presence of alkalinity and the texturing additive, thereby forming a textured structure, such as a pyramid, on the corresponding second doped polysilicon layer. Furthermore, due to the protection of the second tunneling layer, the textured structure is formed on the second doped polysilicon layer.

[0082] In an embodiment of the present invention, in S7, after pickling the silicon wafer, the temporary protective layer in the emitter gate line area and the borosilicate glass layer on the front of the silicon wafer can be removed, and a complete first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer is obtained in the emitter gate line area on the back of the silicon wafer; and the non-emitter gate line area is the first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer with a velvet structure, which can reduce the reflectivity of the non-emitter gate line area.

[0083] The reflectivity of the emitter grid line area is 40-50%, and the reflectivity of the non-emitter grid line area is 10-30%.

[0084] In the embodiment of the present invention, the passivation layer is deposited in S8 by using an ALD process, which is an atomic layer deposition process. The passivation layer may be an Al2O3 thin film.

[0085] In the embodiment of the present invention, the protective layer in S9 is Si x N y Thin film or SiON y The protective layer may be deposited by a PECVD process in S9.

[0086] Example 1:

[0087] like Figure 2As shown, a TOPCon cell includes: a silicon wafer 10, a first velvet structure is formed on the front side of the silicon wafer 10, a boron-doped layer 11, a passivation layer 12 and a protective layer 13 are sequentially formed on the first velvet structure, and a first electrode 01 is formed on the front side of the silicon wafer 10 and is burned through to the passivation layer 12; a first tunneling layer 14, a first doped polysilicon layer 15, a second tunneling layer 16, a second doped polysilicon layer 17 and a protective layer 13 are sequentially formed on the back side of the silicon wafer 10, a second electrode 02 is formed on the back side of the silicon wafer 10 and is burned through to the first doped polysilicon layer, and a second velvet structure is formed on the side of the second doped polysilicon layer 17 away from the silicon wafer 10.

[0088] The preparation method of the TOPCon battery in this embodiment specifically includes the following steps:

[0089] S1, texturing the silicon wafer to form a velvet structure on the surface of the silicon wafer;

[0090] S2. Boron diffusion doping is performed on the front side of the silicon wafer to form a boron-doped layer with a thickness of 0.6 μm. Borosilicate glass layers are formed on the front side and the back side of the silicon wafer.

[0091] S3. The back side of the silicon wafer is pickled to remove the borosilicate glass layer, and then the back side is alkali-washed and polished. The top of the pyramid is etched off on the entire back side of the silicon wafer in a wet-process trough to obtain a consistent pyramid base with a width of 7 μm and a depth of 1 μm.

[0092] S4. Depositing a first tunneling layer with a thickness of 1 nm, a first polysilicon layer with a thickness of 20 nm, a second tunneling layer with a thickness of 2 nm, and a second polysilicon layer with a thickness of 90 nm on the back side of the silicon wafer using an LPCVD process. Performing phosphorus diffusion doping on the back side of the silicon wafer to form a first doped polysilicon layer with a thickness of 20 nm and a second doped polysilicon layer with a thickness of 90 nm. The silicon wafer is subjected to high-temperature annealing to form a phosphosilicate glass layer with a thickness of 20 nm on the surface of the second doped polysilicon layer. The sheet resistance of the first doped polysilicon layer and the second doped polysilicon layer is 30 Ω, and the high-temperature annealing temperature is 850° C.

[0093] S5. Laser-open the phosphosilicate glass layer in the non-emitter gridline area on the back of the silicon wafer. The opening depth is 30% of the thickness of the phosphosilicate glass layer. The laser spot size is 100 μm and the laser power is 50 W. The emitter gridline area on the back of the silicon wafer is still fully protected by the phosphosilicate glass layer.

[0094] S6. Texturing the non-emitter gate line region on the back side of the silicon wafer in an alkaline environment and with a texturing additive, to form a textured structure on the second doped polysilicon layer in the non-emitter gate line region;

[0095] S7. Pickle the back side of the silicon wafer to remove the phosphosilicate glass layer in the emitter gate line area on the back side of the silicon wafer and the borosilicate glass layer on the front side of the silicon wafer. In the emitter gate line area on the back side of the silicon wafer, a complete first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer is obtained, with a reflectivity of 40%. In the non-emitter gate line area, the first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer with a velvet structure is obtained, with a reflectivity of 10%.

[0096] S8, depositing an Al2O3 film with a thickness of 3.0 nm on the front side of the silicon wafer;

[0097] S9, depositing Si with a thickness of 70nm on the front and back of the silicon wafer x N y film;

[0098] S10. Metallization sintering is performed on the front and back sides of the silicon wafer to form a first electrode and a second electrode on the front and back sides of the silicon wafer, respectively. The first electrode formed on the front side of the silicon wafer is burned through to the passivation layer, and the second electrode formed on the back side of the silicon wafer is burned through to the first doped polysilicon layer.

[0099] Example 2:

[0100] like Figure 2 As shown, a TOPCon cell includes: a silicon wafer 10, a first velvet structure is formed on the front side of the silicon wafer 10, a boron-doped layer 11, a passivation layer 12 and a protective layer 13 are sequentially formed on the first velvet structure, and a first electrode 01 is formed on the front side of the silicon wafer 10 and is burned through to the passivation layer 12; a first tunneling layer 14, a first doped polysilicon layer 15, a second tunneling layer 16, a second doped polysilicon layer 17 and a protective layer 13 are sequentially formed on the back side of the silicon wafer 10, a second electrode 02 is formed on the back side of the silicon wafer 10 and is burned through to the first doped polysilicon layer, and a second velvet structure is formed on the side of the second doped polysilicon layer 17 away from the silicon wafer 10.

[0101] The preparation method of the TOPCon battery in this embodiment specifically includes the following steps:

[0102] S1, texturing the silicon wafer to form a velvet structure on the surface of the silicon wafer;

[0103] S2. Boron diffusion doping is performed on the front side of the silicon wafer to form a boron-doped layer with a thickness of 0.7 μm. Borosilicate glass layers are formed on the front side and the back side of the silicon wafer.

[0104] S3. The back side of the silicon wafer is pickled to remove the borosilicate glass layer, and then the back side is alkali-washed and polished. The top of the pyramid is etched off on the entire back side of the silicon wafer in a wet-process trough to obtain a consistent pyramid base with a width of 10 μm and a depth of 3 μm.

[0105] S4. Depositing a first tunneling layer with a thickness of 1.5 nm, a first polysilicon layer with a thickness of 35 nm, a second tunneling layer with a thickness of 4 nm, and a second polysilicon layer with a thickness of 120 nm on the back side of the silicon wafer using an LPCVD process. Performing phosphorus diffusion doping on the back side of the silicon wafer to form a first doped polysilicon layer with a thickness of 35 nm and a second doped polysilicon layer with a thickness of 120 nm. The silicon wafer is subjected to high-temperature annealing to form a 30 nm thick phosphorus-silicate glass layer on the surface of the second doped polysilicon layer. The sheet resistance of the first doped polysilicon layer and the second doped polysilicon layer is 40 Ω, and the high-temperature annealing temperature is 900° C.

[0106] S5. Laser-open the phosphosilicate glass layer in the non-emitter gridline area on the back of the silicon wafer. The opening depth is 40% of the thickness of the phosphosilicate glass layer. The laser spot size is 200 μm and the laser power is 150 W. The emitter gridline area on the back of the silicon wafer is still fully protected by the phosphosilicate glass layer.

[0107] S6. Texturing the non-emitter gate line region on the back side of the silicon wafer in an alkaline environment and with a texturing additive, to form a textured structure on the second doped polysilicon layer in the non-emitter gate line region;

[0108] S7. Pickle the back side of the silicon wafer to remove the phosphorus-silicate glass layer in the emitter gate line area on the back side of the silicon wafer and the borosilicate glass layer on the front side of the silicon wafer. The emitter gate line area on the back side of the silicon wafer is formed into a complete first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer with a reflectivity of 45%. The non-emitter gate line area is formed into the first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer with a velvet structure with a reflectivity of 15%.

[0109] S8, depositing an Al2O3 film with a thickness of 3.5 nm on the front side of the silicon wafer;

[0110] S9, depositing Si with a thickness of 75nm on the front and back of the silicon wafer x N y film;

[0111] S10. Metallization sintering is performed on the front and back sides of the silicon wafer to form a first electrode and a second electrode on the front and back sides of the silicon wafer, respectively. The first electrode formed on the front side of the silicon wafer is burned through to the passivation layer, and the second electrode formed on the back side of the silicon wafer is burned through to the first doped polysilicon layer.

[0112] Example 3:

[0113] like Figure 2As shown, a TOPCon cell includes: a silicon wafer 10, a first velvet structure is formed on the front side of the silicon wafer 10, a boron-doped layer 11, a passivation layer 12 and a protective layer 13 are sequentially formed on the first velvet structure, and a first electrode 01 is formed on the front side of the silicon wafer 10 and is burned through to the passivation layer 12; a first tunneling layer 14, a first doped polysilicon layer 15, a second tunneling layer 16, a second doped polysilicon layer 17 and a protective layer 13 are sequentially formed on the back side of the silicon wafer 10, a second electrode 02 is formed on the back side of the silicon wafer 10 and is burned through to the first doped polysilicon layer, and a second velvet structure is formed on the side of the second doped polysilicon layer 17 away from the silicon wafer 10.

[0114] The preparation method of the TOPCon battery in this embodiment specifically includes the following steps:

[0115] S1. Texturing the front side of the silicon wafer to form a velvet structure on the surface of the silicon wafer;

[0116] S2. Boron diffusion doping is performed on the front side of the silicon wafer to form a boron-doped layer with a thickness of 0.8 μm. Borosilicate glass layers are formed on the front side and the back side of the silicon wafer.

[0117] S3. The back side of the silicon wafer is pickled to remove the borosilicate glass layer, and then the back side is alkali-washed and polished. The top of the pyramid is etched off on the entire back side of the silicon wafer in a wet-process trough to obtain a consistent pyramid base with a width of 15 μm and a depth of 5 μm.

[0118] S4. Depositing a first tunneling layer with a thickness of 2 nm, a first polysilicon layer with a thickness of 50 nm, a second tunneling layer with a thickness of 5 nm, and a second polysilicon layer with a thickness of 150 nm on the back side of the silicon wafer using an LPCVD process. Performing phosphorus diffusion doping on the back side of the silicon wafer to form a first doped polysilicon layer with a thickness of 50 nm and a second doped polysilicon layer with a thickness of 150 nm. The silicon wafer is subjected to high-temperature annealing to form a 35 nm thick phosphorus-silicate glass layer on the surface of the second doped polysilicon layer. The sheet resistance of the first doped polysilicon layer and the second doped polysilicon layer is 60 Ω, and the high-temperature annealing temperature is 950° C.

[0119] S5. Laser-open the phosphosilicate glass layer in the non-emitter gridline area on the back of the silicon wafer. The opening depth is 50% of the thickness of the phosphosilicate glass layer. The laser spot size is 300 μm and the laser power is 300 W. The emitter gridline area on the back of the silicon wafer is still fully protected by the phosphosilicate glass layer.

[0120] S6. Texturing the non-emitter gate line region on the back side of the silicon wafer in an alkaline environment and with a texturing additive, to form a textured structure on the second doped polysilicon layer in the non-emitter gate line region;

[0121] S7. Pickle the back side of the silicon wafer to remove the phosphorus-silicate glass layer in the emitter gate line area on the back side of the silicon wafer and the borosilicate glass layer on the front side of the silicon wafer. In the emitter gate line area on the back side of the silicon wafer, a complete first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer is obtained, with a reflectivity of 50%. In the non-emitter gate line area, the first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer with a velvet structure is obtained, with a reflectivity of 30%.

[0122] S8, depositing a 4.0 nm thick Al2O3 film on the front side of the silicon wafer;

[0123] S9, depositing Si with a thickness of 80nm on the front and back of the silicon wafer x N y film;

[0124] S10. Metallization sintering is performed on the front and back sides of the silicon wafer to form a first electrode and a second electrode on the front and back sides of the silicon wafer, respectively. The first electrode formed on the front side of the silicon wafer is burned through to the passivation layer, and the second electrode formed on the back side of the silicon wafer is burned through to the first doped polysilicon layer.

[0125] Example 4:

[0126] like Figure 2 As shown, a TOPCon cell includes: a silicon wafer 10, a first velvet structure is formed on the front side of the silicon wafer 10, a boron-doped layer 11, a passivation layer 12 and a protective layer 13 are sequentially formed on the first velvet structure, and a first electrode 01 is formed on the front side of the silicon wafer 10 and is burned through to the passivation layer 12; a first tunneling layer 14, a first doped polysilicon layer 15, a second tunneling layer 16, a second doped polysilicon layer 17 and a protective layer 13 are sequentially formed on the back side of the silicon wafer 10, a second electrode 02 is formed on the back side of the silicon wafer 10 and is burned through to the first doped polysilicon layer, and a second velvet structure is formed on the side of the second doped polysilicon layer 17 away from the silicon wafer 10.

[0127] The preparation method of the TOPCon battery in this embodiment specifically includes the following steps:

[0128] S1, texturing the silicon wafer to form a velvet structure on the surface of the silicon wafer;

[0129] S2. Boron diffusion doping is performed on the front side of the silicon wafer to form a boron-doped layer with a thickness of 0.7 μm. Borosilicate glass layers are formed on the front side and the back side of the silicon wafer.

[0130] S3, pickling the back of the silicon wafer to remove the borosilicate glass layer, then alkali cleaning and polishing the back, etching the top of the pyramid on the back of the wet trough to obtain a consistent pyramid base;

[0131] S4. Depositing a first tunneling layer with a thickness of 2 nm, a first doped polysilicon layer with a thickness of 40 nm, a second tunneling layer with a thickness of 4 nm, and a second doped polysilicon layer with a thickness of 100 nm on the back side of the silicon wafer using a PECVD process, and performing high-temperature annealing on the silicon wafer. A silicon oxide layer with a thickness of 20 nm is formed on the surface of the second doped polysilicon layer; wherein the sheet resistance of the first doped polysilicon layer and the second doped polysilicon layer is 30 Ω, and the high-temperature annealing temperature is 850° C.

[0132] S5. Laser-open the silicon oxide layer in the non-emitter gate line area on the back of the silicon wafer. The opening depth is 30% of the silicon oxide layer thickness. The laser spot size is 100 μm and the laser power is 50 W. The emitter gate line area on the back of the silicon wafer is still protected by the complete silicon oxide layer.

[0133] S6. Texturing the non-emitter gate line region on the back side of the silicon wafer in an alkaline environment and with a texturing additive, to form a textured structure on the second doped polysilicon layer in the non-emitter gate line region;

[0134] S7. Pickle the back side of the silicon wafer to remove the silicon oxide layer in the emitter gate line area on the back side of the silicon wafer and the borosilicate glass layer on the front side of the silicon wafer. In the emitter gate line area on the back side of the silicon wafer, a complete first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer is obtained, with a reflectivity of 40%. In the non-emitter gate line area, the first tunneling layer + first doped polysilicon layer + second tunneling layer + second doped polysilicon layer with a velvet structure is obtained, with a reflectivity of 30%.

[0135] S8, depositing an Al2O3 film with a thickness of 3.5 nm on the front side of the silicon wafer;

[0136] S9, depositing Si with a thickness of 75nm on the front and back of the silicon wafer x N y film;

[0137] S10. Metallization sintering is performed on the front and back sides of the silicon wafer to form a first electrode and a second electrode on the front and back sides of the silicon wafer, respectively. The first electrode formed on the front side of the silicon wafer is burned through to the passivation layer, and the second electrode formed on the back side of the silicon wafer is burned through to the first doped polysilicon layer.

[0138] Example 5:

[0139] The difference between Example 5 and Example 1 is S9, and the rest of the steps are the same. In Example 5, S9 deposits SiON on the front and back of the silicon wafer. y film.

[0140] Example 6:

[0141] The difference between Example 6 and Example 1 is S4, and the remaining steps are the same. The temperature of the high-temperature annealing in Example 6 is 800°C.

[0142] Example 7:

[0143] The difference between Example 7 and Example 1 is S4, and the remaining steps are the same. The temperature of the high-temperature annealing in Example 7 is 1000°C.

[0144] Example 8:

[0145] The difference between Example 8 and Example 1 is S5, and the remaining steps are the same. In Example 8, the film opening depth is 20% of the thickness of the phosphosilicate glass layer.

[0146] Example 9:

[0147] The difference between Example 9 and Example 1 is S5, and the remaining steps are the same. In Example 9, the film opening depth is 60% of the thickness of the phosphosilicate glass layer.

[0148] Comparative Example 1:

[0149] like Figure 3 As shown, the TOPCon cell includes: a silicon wafer 10, a velvet structure is formed on the front side of the silicon wafer 10, and a boron-doped layer 11, a passivation layer 12, a protective layer 13 and a first electrode 01 burned through to the passivation layer 12 are formed in sequence on the velvet structure; a silicon oxide layer 18, a doped polysilicon layer 19, a protective layer 13 and a second electrode 02 burned through to the doped polysilicon layer 19 are formed on the back side of the silicon wafer 10.

[0150] The preparation method of the TOPCon battery in this comparative example specifically includes the following steps:

[0151] S1. Texturing the front side of the silicon wafer to form a velvet structure on the surface of the silicon wafer;

[0152] S2. performing boron diffusion doping on the front surface of the silicon wafer to form a boron-doped layer, and forming a borosilicate glass layer on the front and back surfaces of the silicon wafer;

[0153] S3, the back side of the silicon wafer is acid-washed to remove the borosilicate glass layer, and then the back side is alkaline-washed and polished. The top of the pyramid is etched off the entire back side of the silicon wafer in a wet-process trough to obtain a consistent pyramid base;

[0154] S4: A silicon oxide layer is first formed on the back of the silicon wafer at a high temperature, and then a doped polysilicon layer is grown. A phosphorus silicon glass layer is formed on the surface of the doped polysilicon layer.

[0155] S5, acid washing to remove the borosilicate glass layer on the front side of the silicon wafer, and alkali washing to remove the phosphosilicate glass layer on the back side of the silicon wafer;

[0156] S6, depositing an Al2O3 thin film on the front surface of the silicon wafer;

[0157] S7, depositing Si on the front and back sides of the silicon wafer x N y film;

[0158] S8. Metallize and sinter the front and back sides of the silicon wafer to form a first electrode and a second electrode on the front and back sides of the silicon wafer, respectively, wherein the first electrode is burned through to the passivation layer, and the second electrode is burned through to the second electrode on the doped polysilicon layer.

[0159] TOPCon batteries were prepared using the preparation methods provided in Examples 1 to 9 and Comparative Example 1, and the performance of the TOPCon batteries was measured. The results are shown in Table 1.

[0160] Table 1

[0161]

[0162] As can be seen from Table 1, the TOPCon batteries prepared using the methods provided in Examples 1 to 9 have higher conversion efficiencies than those in Comparative Example 1. The open circuit voltage and short circuit current of the TOPCon batteries prepared using the methods provided in Examples 1 to 5 are higher than those in Comparative Example 1. The fill factors of the TOPCon batteries prepared using the methods provided in Examples 1 to 5 are close to those in Comparative Example 1, with little difference.

[0163] The TOPCon cells prepared in Examples 1 to 5 form a velvet structure on the second doped polysilicon layer in the non-emitter gridline region on the back side of the N-type silicon wafer. This reduces the backside reflectivity of the N-type silicon wafer and significantly increases the backside current. Furthermore, a portion of the second doped polysilicon layer in the non-emitter gridline region is removed, significantly reducing metal recombination and significantly improving the backside voltage. Because the tunneling effect in the non-emitter gridline region on the back side of the N-type silicon wafer remains unchanged and lateral transmission is achieved by the first doped polysilicon layer, the overall contact and lateral resistance are unaffected, the fill factor (ff) remains unchanged, and the overall backside efficiency of the cell is significantly increased, with the bifaciality improvement consistent with the mechanism.

[0164] The open circuit voltage and short circuit current of the TOPCon batteries prepared by the methods provided in Examples 6 and 7 are lower than those in Example 1, and the fill factors of the TOPCon batteries prepared by the methods provided in Examples 6 and 7 are lower than those in Example 1, indicating that setting the high temperature annealing temperature too high or too low will affect the performance of the TOPCon battery.

[0165] The open circuit voltage and short circuit current of the TOPCon batteries prepared by the methods provided in Examples 8 and 9 are lower than those in Example 1, and the fill factors of the TOPCon batteries prepared by the methods provided in Examples 8 and 9 are lower than those in Example 1, indicating that the depth of the membrane opening affects the performance of the TOPCon battery.

[0166] The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0167] The above description is merely an illustration of the preferred embodiments of the present invention and the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this invention is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the aforementioned inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions invented in this invention.

Claims

1. A method for preparing a TOPCon battery, characterized in that: include: Step 1, texturing the silicon wafer; Step 2: performing boron diffusion doping on the front surface of the silicon wafer; Step 3, acid washing and alkaline polishing are performed on the back side of the silicon wafer; Step 4: forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer in sequence on the back side of the silicon wafer, and performing high-temperature annealing on the silicon wafer, and forming a temporary protective layer on the emitter gate line region and the non-emitter gate line region on the back side of the silicon wafer; Step 5, performing a film opening process on the temporary protection layer in the non-emitter gate line area; Step 6: Texturing the non-emitter gate line region to form a textured structure on the second doped polysilicon layer in the non-emitter gate line region; Step 7, pickling the silicon wafer; Step 8: depositing a passivation layer on the front side of the silicon wafer; Step 9: depositing a protective layer on the front and back sides of the silicon wafer; Step 10: metallizing and sintering the silicon wafer.

2. The method for preparing a TOPCon battery according to claim 1, wherein: In step 4, a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer are sequentially formed on the back side of the silicon wafer, including: Depositing a first tunneling layer, a first polysilicon layer, a second tunneling layer, and a second polysilicon layer in sequence on the back side of the silicon wafer using an LPCVD process; Phosphorus diffusion doping is performed on the back side of the silicon wafer to form the first doped polysilicon layer and the second doped polysilicon layer, and a temporary protective layer formed on the surface of the second doped polysilicon layer is a phosphorus silicon glass layer.

3. The method for preparing a TOPCon battery according to claim 1, wherein: In step 4, a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer are sequentially formed on the back side of the silicon wafer, including: A first tunneling layer, a first doped polysilicon layer, a second tunneling layer and a second doped polysilicon layer are sequentially deposited on the back of the silicon wafer using a PECVD process, and a temporary protective layer formed on the surface of the second doped polysilicon layer is a silicon oxide layer.

4. The method for preparing a TOPCon battery according to claim 1, wherein: In step 4, the sheet resistance of the first doped polysilicon layer and the second doped polysilicon layer is 30-60Ω.

5. The method for preparing a TOPCon battery according to claim 1, wherein: In step 4, the temperature of the high temperature annealing is 850-950°C.

6. The method for preparing a TOPCon battery according to claim 1, characterized in that: In step 5, the temporary protective layer in the non-emitter gate line region is subjected to a film opening process, including: Laser is used to perform a film-opening process on the temporary protection layer in the non-emitter gate line area.

7. The method for preparing a TOPCon battery according to claim 6, characterized in that: The laser spot size is 100-300um and the laser power is 50-300w.

8. The method for preparing a TOPCon battery according to claim 6, wherein: In step 5, the film opening depth is 30%-50% of the thickness of the temporary protective layer.

9. The method for preparing a TOPCon battery according to claim 1, wherein: In step 9, the protective layer is Si x N y Thin film or SiON y film.

10. A TOPCon battery prepared by the preparation method according to any one of claims 1 to 9, characterized in that: The TOPCon battery includes: A silicon wafer (10), wherein a first velvet structure is formed on the front surface of the silicon wafer (10), and a boron-doped layer (11), a passivation layer (12), a protective layer (13), and a first electrode (01) burned through the passivation layer (12) are sequentially formed on the velvet structure; A first tunneling layer (14), a first doped polysilicon layer (15), a second tunneling layer (16), a second doped polysilicon layer (17), a protective layer (13), and a second electrode (02) burned through to the first doped polysilicon layer (15) are sequentially formed on the back side of the silicon wafer (10), and a second velvet structure is formed on a side of the second doped polysilicon layer (17) away from the silicon wafer (10).

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