Back contact battery and photovoltaic module

Abstract

The invention relates to a back contact battery and a photovoltaic module. Comprising a substrate, the substrate is provided with a first surface and a second surface which are oppositely arranged, the first surface comprises a first area and a second area, the first area comprises an overlapping area, and the overlapping area is adjacent to the second area; the first doped semiconductor layer is arranged in the first region; the second doped semiconductor layer is arranged in the second region and the overlapping region, and the conduction type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer; the conductive layer is arranged on one side, deviating from the substrate, of the first doped semiconductor layer and the second doped semiconductor layer; the conductive layer is provided with a first isolation groove, the first isolation groove is arranged in the first region and comprises a first groove part and a second groove part along the arrangement direction of the first region and the second region, the first groove part penetrates to the surface of the side, away from the substrate, of the first doped semiconductor layer, and the second groove part is located in the overlapping region; and the second groove part penetrates to the surface of one side, deviating from the first doped semiconductor layer, of the second doped semiconductor layer.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a photovoltaic module. Background Art

[0002] A back-contact cell refers to a solar cell in which the light-facing side of the cell has no electrode, and the positive and negative electrodes are arranged on the side of the cell that is not facing the light. This can reduce the obstruction of the electrodes on the cell, increase the short-circuit current of the cell, and improve the energy conversion efficiency of the cell.

[0003] In the related art, in order to avoid the hot spot effect caused by the obstruction of the battery cell, an overlapping area is set between the first area and the second area of the battery cell, the doping layers of the first area and the second area overlap in the overlapping area, and an isolation groove is set in the conductive layer of the overlapping area, and the electrodes of the first area and the second area are physically isolated by the isolation groove.

[0004] However, in the related art, the isolation trench is set in the overlapping area, and the conductive layers on both sides of the isolation trench are prone to short circuit, causing the battery cell to fail. Summary of the Invention

[0005] Based on this, the embodiments of the present application provide a back-contact cell and photovoltaic module, which can reduce the risk of short circuit between the first region and the second region and ensure the normal operation of the cell.

[0006] In one aspect, an embodiment of the present application provides a back-contact battery, comprising:

[0007] A substrate having a first surface and a second surface opposite to each other, the first surface including a first region and a second region, the first region including an overlapping region, and the overlapping region being adjacent to the second region;

[0008] A first doped semiconductor layer is provided in the first region;

[0009] A second doped semiconductor layer is provided in the second region and the overlapping region, wherein the second doped semiconductor layer in the overlapping region is provided on a side of the first doped semiconductor layer facing away from the substrate, and the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types;

[0010] A conductive layer, the conductive layer is arranged on the side of the first doped semiconductor layer and the second doped semiconductor layer facing away from the substrate; the conductive layer is provided with a first isolation trench, the first isolation trench is arranged in the first region, and along the arrangement direction of the first region and the second region, the first isolation trench includes a first trench portion and a second trench portion, the first trench portion penetrates to the surface of the first doped semiconductor layer facing away from the substrate, the second trench portion is located in the overlapping region, and the second trench portion penetrates to the surface of the second doped semiconductor layer facing away from the first doped semiconductor layer.

[0011] In one embodiment, along the arrangement direction of the first region and the second region, the opening size of the first isolation trench is 10-200 μm;

[0012] The first groove portion has a first size, the second groove portion has a second size, and a ratio of the second size to the first size is 0.8-2.

[0013] In one embodiment, a first distance is defined between the surface of the second region and the second surface, a second distance is defined between the first region and the second surface, and the first distance is less than the second distance; the second doped semiconductor layer includes a first doped sub-section, a second doped sub-section, and a third doped sub-section connected in sequence; the first doped sub-section is located in the second region, the second doped sub-section and the third doped sub-section are located in an overlapping region, the second doped sub-section is located on a sidewall of the first doped semiconductor layer facing an end of the second region, and the third doped sub-section is located on a surface of the first doped semiconductor layer facing away from the substrate;

[0014] Alternatively, one end of the second groove facing the second region is flush with an edge of the first doped semiconductor layer facing the second region.

[0015] In one embodiment, the conductive layer further has a second isolation trench, the second isolation trench is provided in the second region, and the second isolation trench is located at one end of the second region close to the first region.

[0016] In one embodiment, the distance between the second isolation trench and the surface of the conductive layer on the second doped sub-portion facing the second region is 0-100 μm; along the arrangement direction of the first region and the second region, the opening size of the second isolation trench is 10-200 μm.

[0017] In one embodiment, the second isolation trench penetrates two surfaces of the conductive layer along a first direction, and the first direction intersects with an arrangement direction of the first region and the second region.

[0018] In one embodiment, a plurality of second isolation trenches are provided along the first direction, and the plurality of second isolation trenches are arranged at intervals along the first direction; the first direction intersects with the arrangement direction of the first region and the second region.

[0019] In one embodiment, the first doped semiconductor layer includes:

[0020] a first passivation layer, the first passivation layer covering the first region;

[0021] The first doping layer covers a side of the first passivation layer facing away from the substrate.

[0022] In one embodiment, the first passivation layer includes a tunneling oxide layer, and the thickness of the first passivation layer is 1-2 nm;

[0023] The first doping layer includes an N-type doped polysilicon layer, the thickness of the first doping layer is 50-200 nm, and the doping concentration of the first doping layer is 1e19 cm -3 -1e21 cm -3 .

[0024] In one embodiment, the second doped semiconductor layer includes:

[0025] a second passivation layer, the second passivation layer covering the second region and a side of the first doped layer facing away from the substrate;

[0026] The second doping layer covers a side of the second passivation layer facing away from the substrate.

[0027] In one embodiment, the second passivation layer includes an intrinsic amorphous silicon layer, an intrinsic amorphous silicon oxide layer or an intrinsic amorphous silicon carbide layer, and the thickness of the second passivation layer is 3-8nm; the second doped layer includes a P-type doped amorphous silicon layer, a P-type doped microcrystalline silicon layer, a P-type doped nano-silicon layer or a P-type doped silicon carbide layer.

[0028] In another aspect, an embodiment of the present application provides a photovoltaic assembly, comprising:

[0029] The back contact battery provided in the aforementioned embodiment of the present application,

[0030] The main grid is electrically connected to the electrode of the back contact battery, and the main grid is electrically connected to the conductive layer of the overlapping area.

[0031] In one embodiment, the back contact cell includes a first electrode and a second electrode, the first electrode being connected to the conductive layer of the first region, and the second electrode being connected to the conductive layer of the second region;

[0032] The main grid includes a first main grid and a second main grid. In the same back-contact battery, the first main grid is electrically connected to one of the first electrode and the second electrode, and the first main grid is insulated from the other of the first electrode and the second electrode; the electrode electrically connected to the second conductive layer is opposite to the electrode electrically connected to the first main grid; the first main grid and the second main grid are both electrically connected to the conductive layer in the overlapping area.

[0033] The back-contact cell and photovoltaic module provided in the embodiments of the present application are configured by disposing a first doped semiconductor layer in a first region of a first surface of a substrate, wherein the first region includes an overlapping region, the overlapping region being adjacent to a second region, and disposing a second doped semiconductor layer in the second region and the overlapping region, wherein the second doped semiconductor layer in the overlapping region covers the side of the first doped semiconductor layer in the overlapping region facing away from the substrate. In this way, different electrodes of the back-contact cell can be formed by the different conductivity types of the first doped semiconductor layer and the second doped semiconductor layer, thereby facilitating the collection of carriers. A conductive layer is disposed on the side of the first doped semiconductor layer and the second doped semiconductor layer facing away from the substrate, and a first isolation trench is disposed in the conductive layer, wherein the first isolation trench is disposed in the first region. In this way, the conductive layer in the first region and the conductive layer in the second region can be physically insulated and separated by the first isolation trench. After the conductive layer is connected to the main grid, the conductive layer has a high conductivity, and can promptly conduct the carriers collected by the first doped semiconductor layer and the second doped semiconductor layer, thereby reducing the carrier coincidence rate.

[0034] In addition, the first isolation trench is configured to include a first trench portion and a second trench portion along the arrangement direction of the first region and the second region, wherein the first trench portion extends through the surface of the first doped semiconductor layer facing away from the substrate, and the second trench portion is located in the overlapping region and extends through the side of the second doped semiconductor layer facing away from the first doped semiconductor layer. In this way, a portion of the second doped semiconductor layer can be present within the first isolation trench, and the second doped semiconductor layer can raise the height of the conductive layer in the overlapping region, thereby increasing the distance between the conductive layer in the overlapping region and the conductive layer above the first doped semiconductor layer, thereby reducing the risk of short circuiting of the conductive layers on both sides of the first isolation trench and ensuring the normal operation of the battery cell. The portion of the second doped semiconductor layer located in the overlapping region can be within the first isolation trench, and the second doped semiconductor layer can isolate the conductive layer in the overlapping region, thereby improving the physical insulation effect of the conductive layers on both sides of the first isolation trench, reducing the risk of short circuiting of the conductive layers on both sides of the first isolation trench, and ensuring the normal operation of the battery cell.

[0035] When the back contact cell is blocked, the blocked back contact cell does not work. At this time, the current of the photovoltaic module can break down in the conductive layer, the second doped semiconductor layer and the first doped semiconductor layer in the overlapping area, forming reverse leakage, which can bypass the blocked back contact cell, reduce or eliminate the hot spot effect, and extend the service life of the back contact cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a cross-sectional view of a back-contact battery provided in some embodiments of the present application.

[0037] Figure 2 is another cross-sectional view of a back-contact battery provided in some embodiments of the present application.

[0038] Figure 3 This is a front view of a back-contact battery provided in some embodiments of the present application.

[0039] Figure 4 This is another front view of the back-contact battery provided in some embodiments of the present application.

[0040] Figure 5 This is another cross-sectional view of a back-contact battery provided in some embodiments of the present application.

[0041] Figure 6 This is another front view of the back-contact battery provided in some embodiments of the present application.

[0042] Description of reference numerals:

[0043] 10-back contact battery; 20-main grid; 30-first insulating layer; 40-second insulating layer;

[0044] 11-substrate; 12-first doped semiconductor layer; 13-second doped semiconductor layer; 14-conductive layer; 15-antireflection layer; 21-first main grid; 22-second main grid;

[0045] 111 - first surface; 112 - second surface; 121 - first passivation layer; 122 - first doped layer; 131 - first doped sub-section; 132 - second doped sub-section; 133 - third doped sub-section; 134 - second passivation layer; 135 - second doped layer; 141 - first isolation trench; 142 - second isolation trench; 143 - first electrode; 144 - second electrode;

[0046] 1111-first region; 1112-second region; 1411-first groove portion; 1412-second groove portion;

[0047] 1111a-Overlapping area. DETAILED DESCRIPTION

[0048] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0049] In the description of this application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0050] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0051] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connected," "fixed," etc., should be interpreted broadly. For example, these terms may refer to fixed connections, removable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; and internal communication between two components or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0052] In this application, unless otherwise expressly specified or limited, if a first feature is described as being "above" or "below" a second feature, or similar descriptions, this may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is described as being "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is described as being "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0053] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only embodiment.

[0054] Figure 1 This is a cross-sectional view of a back-contact battery provided in some embodiments of the present application.

[0055] On the one hand, referring to Figure 1 As shown, an embodiment of the present application provides a back-contact cell 10. The back-contact cell 10 may include a substrate 11. The substrate 11 may be a semiconductor silicon substrate 11.

[0056] In some examples, the doping type of the semiconductor silicon substrate 11 may be N-type. It is understood that in the embodiments of the present application, the doping type of the semiconductor silicon substrate 11 is only shown as a specific example and does not limit the doping type of the semiconductor silicon substrate 11.

[0057] In some examples, the substrate 11 may have a first surface 111 and a second surface 112 disposed opposite to each other. Figure 1 As shown, the first surface 111 and the second surface 112 can be along Figure 1 The directions shown on the y-axis are relatively set.

[0058] In some examples, the first surface 111 may include a first region 1111 and a second region 1112 . The first region 1111 may include an overlapping region 1111 a . The overlapping region 1111 a is adjacent to the second region 1112 .

[0059] In some examples, the first surface 111 may be a backlight-removing surface of the back-contact cell 10 , and the second surface 112 may be a light-facing surface of the back-contact cell 10 .

[0060] For some examples, refer to Figure 1 As shown, the back contact cell 10 may include a first doped semiconductor layer 12. The first doped semiconductor layer 12 may be provided in a first region 1111. An orthographic projection of the first doped semiconductor layer 12 on the substrate 11 may be located in the first region 1111.

[0061] For some examples, refer to Figure 1As shown, the back contact cell 10 may include a second doped semiconductor layer 13. The second doped semiconductor layer 13 may be provided in the second region 1112 and the overlapping region 1111a. The conductivity type of the second doped semiconductor layer 13 may be opposite to that of the first doped semiconductor layer 12.

[0062] For some examples, refer to Figure 1 As shown, the second doped semiconductor layer 13 in the overlapping region 1111a may be disposed on a side of the first doped semiconductor layer 12 facing away from the substrate 11. That is, in the overlapping region 1111a, the second doped semiconductor layer 13 overlaps the first doped semiconductor layer 12.

[0063] For some examples, refer to Figure 1 As shown, the back contact cell 10 may include a conductive layer 14. The conductive layer 14 may be provided on a side of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 facing away from the substrate 11.

[0064] In some examples, the conductive layer 14 may have a first isolation trench 141 . The first isolation trench 141 may be provided in the first region 1111 .

[0065] In some examples, along the arrangement direction of the first area 1111 and the second area 1112 (for example Figure 1 In the direction shown by the x-axis, the first isolation trench 141 may include a first trench portion 1411 and a second trench portion 1412.

[0066] In some examples, the first groove 1411 penetrates to the surface of the first doped semiconductor layer 12 facing away from the substrate 11 .

[0067] In some examples, the second groove 1412 may be located in the overlapping region 1111 a and may penetrate to a surface of the second doped semiconductor layer 13 facing away from the first doped semiconductor layer 12 .

[0068] In some examples of the embodiments of the present application, by setting the first isolation trench 141 in the first area 1111, the first trench portion 1411 of the first isolation trench 141 penetrates to the side of the first doped semiconductor layer 12 away from the substrate 11, and the second trench portion 1412 penetrates to the side of the second doped semiconductor layer 13 away from the first doped semiconductor layer 12. In this way, part of the second doped semiconductor layer 13 can be located in the first isolation trench 141, and the second doped semiconductor layer 13 can isolate the conductive layer 14 from the first doped semiconductor layer 12, which can increase the distance between the conductive layers 14 on both sides of the first isolation trench 141, thereby improving the physical insulation effect of the conductive layers 14 on both sides of the first isolation trench 141, reducing the risk of short circuit of the conductive layers 14 on both sides of the first isolation trench 141, and ensuring the normal operation of the battery cell.

[0069] The back-contact battery 10 provided in the embodiment of the present application is configured by disposing a first doped semiconductor layer 12 in a first region 1111 of a first surface 111 of a substrate 11, wherein the first region 1111 includes an overlapping region 1111a, the overlapping region 1111a is adjacent to the second region 1112, and a second doped semiconductor layer 13 is disposed in the second region 1112 and the overlapping region 1111a, wherein the second doped semiconductor layer 13 located in the overlapping region 1111a covers the side of the first doped semiconductor layer 12 in the overlapping region 1111a away from the substrate 11; in this way, different electrodes of the back-contact battery 10 can be formed by the different conductive types of the first doped semiconductor layer 12 and the second doped semiconductor layer 13, thereby facilitating the collection of carriers. A conductive layer 14 is provided on the side of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 facing away from the substrate 11, and a first isolation groove 141 is provided in the conductive layer 14, and the first isolation groove 141 is provided in the first region 1111; in this way, the conductive layer 14 in the first region 1111 and the conductive layer 14 in the second region 1112 can be physically insulated and separated by the first isolation groove 141. After the conductive layer 14 is connected to the main gate 20, the conductive layer 14 has a high conductivity, can timely conduct the carriers collected by the first doped semiconductor layer 12 and the second doped semiconductor layer 13, and can reduce the carrier coincidence rate.

[0070] In addition, the first isolation trench 141 is set to include a first trench portion 1411 and a second trench portion 1412 along the arrangement direction of the first region 1111 and the second region 1112, the first trench portion 1411 penetrates to the surface of the first doped semiconductor layer 12 away from the substrate 11, the second trench portion 1412 is located in the overlapping area 1111a, and the second trench portion 1412 penetrates to the side of the second doped semiconductor layer 13 away from the first doped semiconductor layer 12; in this way, part of the second doped semiconductor layer 13 can exist in the first isolation trench 141, and the second doped semiconductor layer 13 can raise the height of the conductive layer 14 in the overlapping area 1111a, thereby increasing the distance between the conductive layer 14 in the overlapping area 1111a and the conductive layer 14 on the first doped semiconductor layer 12, thereby reducing the risk of short circuit of the conductive layers 14 on both sides of the first isolation trench 141, thereby ensuring the normal operation of the battery cell. Among them, the portion of the second doped semiconductor layer 13 located in the overlapping area 1111a can be within the first isolation trench 141. The second doped semiconductor layer 13 can isolate the conductive layer 14 in the overlapping area 1111a, thereby improving the physical insulation effect of the conductive layer 14 on both sides of the first isolation trench 141, reducing the risk of short circuit of the conductive layer 14 on both sides of the first isolation trench 141, and ensuring the normal operation of the battery cell.

[0071] When the back contact cell 10 is blocked, the blocked back contact cell 10 does not work. At this time, the current of the photovoltaic module can break down in the conductive layer 14, the second doped semiconductor layer 13 and the first doped semiconductor layer 12 in the overlapping area 1111a, forming reverse leakage, which can bypass the blocked back contact cell 10, reduce or eliminate the hot spot effect, and extend the service life of the back contact cell 10.

[0072] For some examples, refer to Figure 1 As shown, along the arrangement direction of the first area 1111 and the second area 1112 (for example Figure 1 In the direction shown by the x-axis), the opening size of the first isolation trench 141 can be 10-200 μm.

[0073] In some examples, the opening size of the first isolation trench 141 may be 50-200 μm.

[0074] In some examples, the opening size of the first isolation trench 141 may be 80-200 μm.

[0075] In some examples, the opening size of the first isolation trench 141 may be 120-200 μm.

[0076] In some examples, the opening size of the first isolation trench 141 may be 10-150 μm.

[0077] In some examples, the opening size of the first isolation trench 141 may be 10-120 μm.

[0078] In some examples, the opening size of the first isolation trench 141 may be 10-80 μm.

[0079] In some examples, the opening size of the first isolation trench 141 may be 50-150 μm.

[0080] In some examples, the opening size of the first isolation trench 141 may be 80-120 μm.

[0081] In some examples, the opening size of the first isolation trench 141 may be 80-150 μm.

[0082] It can be understood that the numerical values and numerical ranges involved in some examples of the embodiments of the present application are approximate values. Due to the influence of the manufacturing process, there may be a certain range of errors. Those skilled in the art can consider this part of the error to be negligible.

[0083] In some examples, along the arrangement direction of the first region 1111 and the second region 1112 , the first groove portion 1411 may have a first size, and the second groove portion 1412 may have a second size.

[0084] In some examples, the ratio of the second size to the first size may be 0.8-2.

[0085] In some examples, the ratio of the second size to the first size may be 0.8-1.5.

[0086] In some examples, the ratio of the second size to the first size may be 0.8-1.2.

[0087] In some examples, the ratio of the second size to the first size may be 1-2.

[0088] In some examples, the ratio of the second size to the first size may be 1.2-2.

[0089] In some examples, the ratio of the second size to the first size may be 1.5-2.

[0090] In some examples of the embodiments of the present application, the opening size of the first isolation trench 141 is set to 10-200 μm along the arrangement direction of the first region 1111 and the second region 1112. The first trench portion 1411 has a first size, the second trench portion 1412 has a second size, and the ratio of the second size to the first size is set to 0.8-2. In this way, it is possible to ensure that the conductive layers 14 on both sides of the first isolation trench 141 have a sufficient distance, and to ensure the effectiveness of the first isolation trench 141 in physically insulating the conductive layers 14 on both sides, thereby improving the physical insulation effect of the conductive layers 14 on both sides of the isolation trench, reducing the risk of short circuits in the conductive layers 14 on both sides of the first isolation trench 141, and ensuring the normal operation of the battery cell.

[0091] For some examples, refer to Figure 1 As shown, a first distance L1 exists between the surface of the second region 1112 and the second surface 112. A second distance L2 exists between the surface of the first region 1111 and the second surface 112.

[0092] In some examples, the first distance L1 is smaller than the second distance L2.

[0093] For some examples, refer to Figure 1 As shown, the second doped semiconductor layer 13 may include a first doped sub-section 131, a second doped sub-section 132 and a third doped sub-section 133 connected once; the first doped sub-section 131 is located in the second region 1112, the second doped sub-section 132 and the third doped sub-section 133 are located in the overlapping region 1111a, the second doped sub-section 132 is located on the side wall of the first doped semiconductor layer 12 facing the second region 1112, and the third doped sub-section 133 is located on the side surface of the first doped semiconductor layer 12 facing away from the substrate 11.

[0094] In some examples of the embodiments of the present application, by setting the first distance L1 to be smaller than the second distance L2, the second doped sub-portion 132 can be disposed on the sidewall of the first doped semiconductor layer 12 facing the second region 1112, and the third doped sub-portion 133 can be disposed on the surface of the first doped semiconductor layer 12 facing away from the substrate 11. In this way, a reverse leakage path can be formed between the first doped semiconductor layer 12 and the conductive layer 14 in the overlapping region 1111a and the sidewall of the first doped semiconductor layer 12 facing the second region 1112. When the back-contact cell 10 is blocked, the current generated by other back-contact cells 10 connected in series in the photovoltaic module can break down in the overlapping region 1111a and the end of the first doped semiconductor layer 12 facing the second region 1112, thereby forming reverse leakage current. This can bypass the blocked back-contact cell 10, thereby protecting the blocked cell and avoiding the hot spot effect. In addition, the sidewall of the overlapping region 1111a and the first doped semiconductor layer 12 at one end toward the second region 1112 is broken down to form reverse leakage, which can reduce the power consumption of other back contact cells 10 and improve energy conversion efficiency.

[0095] In some examples, one end of the second groove portion 1412 facing the second region 1112 can be flush with the edge of the first doped semiconductor layer 12 facing the second region 1112. That is to say, when setting the second groove portion 1412, the conductive layer 14 of the overlapping region 1111a can be completely removed. In this way, a reverse leakage channel can be formed on the side wall of one end of the first doped semiconductor layer 12 facing the second region 1112, which can reduce or eliminate the hot spot effect. In addition, the distance between the conductive layers 14 on both sides of the first isolation groove 141 can be increased, thereby improving the physical insulation effect of the conductive layers 14 on both sides of the first isolation groove 141. The risk of short circuit of the conductive layers 14 on both sides of the first isolation groove 141 is reduced, thereby ensuring the normal operation of the battery cell.

[0096] Figure 2 is another cross-sectional view of a back-contact battery provided in some embodiments of the present application.

[0097] For some examples, refer to Figure 2 As shown, the conductive layer 14 may be provided with a second isolation trench 142. The second isolation trench 142 may be provided in the second region 1112. The second isolation trench 142 may be located at one end of the second region 1112 close to the first region 1111.

[0098] In some examples, the second isolation trench 142 may penetrate from a side of the conductive layer 14 facing away from the second doped semiconductor layer 13 to a surface of the second doped semiconductor layer 13 facing away from the substrate 11 .

[0099] In some examples of the embodiments of the present application, a second isolation trench 142 is provided in the conductive layer 14, and the second isolation trench 142 is provided in the second region 1112. In this way, the conductive layer 14 in the second region 1112 can be physically insulated and isolated from the conductive layer 14 in the overlapping region 1111a by the second isolation trench 142. When the back-contact cell 10 is operating normally, the leakage current of the conductive layer 14 in the overlapping region 1111a can be reduced, and the energy consumption of the photovoltaic module in the overlapping region 1111a is reduced, thereby improving the energy conversion efficiency of the photovoltaic module.

[0100] For some examples, refer to Figure 2 As shown, the distance between the second isolation trench 142 and the surface of the conductive layer 14 on the second doped sub-portion 132 facing the second region 1112 may be 0-100 μm.

[0101] In some examples, the distance between the second isolation trench 142 and the surface of the conductive layer 14 on the second doped sub-portion 132 facing the second region 1112 may be 20-100 μm.

[0102] In some examples, the distance between the second isolation trench 142 and the surface of the conductive layer 14 on the second doped sub-portion 132 facing the second region 1112 may be 50-100 μm.

[0103] In some examples, the distance between the second isolation trench 142 and the surface of the conductive layer 14 on the second doped sub-portion 132 facing the second region 1112 may be 80-100 μm.

[0104] In some examples, the distance between the second isolation trench 142 and the surface of the conductive layer 14 on the second doped sub-portion 132 facing the second region 1112 may be 20-80 μm.

[0105] In some examples, the distance between the second isolation trench 142 and the surface of the conductive layer 14 on the second doped sub-portion 132 facing the second region 1112 may be 50-80 μm.

[0106] In some examples, along the arrangement direction of the first area 1111 and the second area 1112 (for example Figure 2 In the direction shown by the x-axis), the opening size of the second isolation trench 142 can be 10-200 μm.

[0107] In some examples, the opening size of the second isolation trench 142 can be the same, close or similar to the opening size of the first isolation trench 141. For details, please refer to the detailed description of the first isolation trench 141 in the aforementioned embodiments of the present application, and the embodiments of the present application will not repeat them.

[0108] In some examples of the embodiments of the present application, the distance between the second isolation trench 142 and the surface of the conductive layer 14 on the second doped sub-section 132 facing the second region 1112 is set to 0-100 μm. In this way, when the second isolation trench 142 is formed in the conductive layer 14, damage to the conductive layer 14 in the overlapping region 1111a can be avoided, and the integrity of the conductive layer 14 in the overlapping region 1111a can be ensured. This facilitates the breakdown between the conductive layer 14 in the overlapping region 1111a and the first doped semiconductor layer 12 to form a reverse leakage path, thereby eliminating the hot spot effect and extending the service life and energy conversion efficiency of the back-contact battery 10.

[0109] Figure 3 This is a front view of a back-contact battery provided in some embodiments of the present application.

[0110] For some examples, refer to Figure 3 As shown, along the first direction (eg Figure 3 The second isolation trench 142 penetrates the two surfaces of the conductive layer 14. The first direction may be aligned with the arrangement direction of the first region 1111 and the second region 1112 (eg, Figure 3 intersects the direction shown by the y-axis).

[0111] In some examples, the first direction may be perpendicular or approximately perpendicular to the arrangement direction of the first region 1111 and the second region 1112 .

[0112] In some examples of the embodiments of the present application, the second isolation trench 142 extends through both surfaces of the conductive layer 14 along the first direction. In other words, the second isolation trench 142 physically separates the conductive layer 14 located in the second region 1112 from the conductive layer 14 located in the overlapping region 1111a. This improves the insulation performance between the conductive layer 14 located in the second region 1112 and the conductive layer 14 located in the overlapping region 1111a. When the back-contact cell 10 is operating normally, the leakage current of the conductive layer 14 located in the overlapping region 1111a is reduced, reducing the energy consumption of the photovoltaic module in the overlapping region 1111a and improving the energy conversion efficiency of the photovoltaic module.

[0113] Figure 4 This is another front view of the back-contact battery provided in some embodiments of the present application.

[0114] For some examples, refer to Figure 4 As shown, along the first direction (eg Figure 4In some embodiments of the present invention, the second isolation trenches 142 may not completely isolate the conductive layer 14 in the second region 1112 from the conductive layer 14 in the overlapping region 1111a. The plurality of second isolation trenches 142 spaced apart along the first direction may reduce the conductive cross-sectional area between the conductive layer 14 in the second region 1112 and the conductive layer 14 in the overlapping region 1111a. In this way, when the back contact cell 10 is operating normally, the leakage current of the conductive layer 14 located in the overlapping region 1111a can be reduced, the energy consumption of the photovoltaic module by the overlapping region 1111a is reduced, and the energy conversion efficiency of the photovoltaic module is improved. In addition, when the back contact cell 10 is blocked, the current of other normally operating cells can break down in the overlapping region 1111a and the first doped semiconductor layer 12, thereby forming a reverse leakage channel, which can bypass the blocked cell, thereby reducing or eliminating the hot spot effect and extending the service life of the photovoltaic module. In some examples, the shape and size of the second isolation groove 142 can be adjusted to adjust the area and leakage current of the reverse leakage channel, so as to facilitate adjusting the area and leakage current of the reverse leakage channel according to the actual application scenario, and facilitate eliminating or reducing the hot plate effect of the photovoltaic module in different scenarios, thereby improving the applicable scenarios of the back contact cell 10.

[0115] Figure 5 This is another cross-sectional view of a back-contact battery provided in some embodiments of the present application.

[0116] For some examples, refer to Figure 5 As shown, the first doped semiconductor layer 12 may include a first passivation layer 121. The first passivation layer 121 may cover the first region 1111.

[0117] In some examples, when preparing the back contact cell 10, a semiconductor silicon substrate 11 may be provided first. The thickness of the semiconductor silicon substrate 11 may be 80-200 μm.

[0118] In some examples, the silicon substrate 11 may be double-sided polished. For example, the first surface 111 and the second surface 112 of the substrate 11 may be polished.

[0119] In some examples, after the substrate 11 is polished, a first passivation layer 121 may be deposited on the first surface 111 .

[0120] In some examples, the first passivation layer 121 may include a tunneling oxide layer. The material selected for the first passivation layer 121 may be silicon dioxide (SiO2) and may have a thickness of 1-2 nm.

[0121] In some examples, the first doped semiconductor layer 12 may include a first doping layer 122 , and the first doping layer 122 may cover a side of the first passivation layer 121 facing away from the substrate 11 .

[0122] In some examples, the material of the first doping layer 122 can be N-type polysilicon. The thickness of the first doping layer 122 can be 50-200 nm. The doping concentration of the first doping layer 122 is 1e19 cm -3 -1e21 cm -3 .

[0123] In some examples, after the first passivation layer 121 is deposited, the first doping layer 122 may be deposited on a side of the first passivation layer 121 facing away from the substrate 11 .

[0124] In some examples, after the first doping layer 122 is deposited, a mask layer may be deposited on the side of the first doping layer 122 facing away from the substrate 11. The mask layer may protect the first passivation layer 121 and the first doping layer 122 to facilitate the deposition of subsequent film layers.

[0125] In some examples, the second doped semiconductor layer 13 may include a second passivation layer 134. The second passivation layer 134 may cover the second region 1112 and a side of the first doped semiconductor layer 12 facing away from the substrate 11.

[0126] In some examples, the mask layer, the first doping layer 122 and the first passivation layer 121 in the second region 1112 may be laser etched to remove the mask layer, the first doping layer 122 and the first passivation layer 121 in the second region 1112 .

[0127] In some examples, after removing the mask layer, the first doping layer 122 and the first passivation layer 121 in the second region 1112 , wet cleaning can be used to clean the damage caused by the laser irradiation area and remove the mask layer in the first region 1111 .

[0128] In some examples, after wet cleaning, the second passivation layer 134 may be deposited on the first region 1111 and the second region 1112 , so that the second passivation layer 134 covers the second region 1112 and the side of the first doping layer 122 facing away from the substrate 11 .

[0129] In some examples, the second passivation layer 134 may include an intrinsic amorphous silicon layer, an intrinsic amorphous silicon oxide layer, or an intrinsic amorphous silicon carbide layer. In other words, the material of the second passivation layer 134 may be any one of intrinsic amorphous silicon, intrinsic amorphous silicon oxide, or intrinsic amorphous silicon carbide. The thickness of the second passivation layer 134 may be 3-8 nm.

[0130] In some examples, the second doped semiconductor layer 13 may include a second doping layer 135 . The second doping layer 135 may cover a side of the second passivation layer 134 facing away from the substrate 11 .

[0131] In some examples, after the second passivation layer 134 is deposited, the second doping layer 135 may be deposited on a side of the second passivation layer 134 facing away from the substrate 11 .

[0132] In some examples, the second doped layer 135 may include a P-type doped amorphous silicon layer, a P-type doped microcrystalline silicon layer, a P-type doped nano-silicon layer, or a P-type doped silicon carbide layer. In other words, the material of the second doped layer 135 may be any one of P-type doped amorphous silicon, P-type doped microcrystalline silicon, P-type residual nano-silicon, or P-type doped silicon carbide.

[0133] It should be noted that, in some examples of the embodiments of the present application, the types of the first passivation layer 121, the first doping layer 122, the second passivation layer 134 and the second doping layer 135 are only shown as some specific examples, and do not limit the specific types of the first passivation layer 121, the first doping layer 122, the second passivation layer 134 and the second doping layer 135.

[0134] In some examples, after the deposition of the second doping layer 135 is completed, the second doping layer 135 and the second passivation layer 134 in the first region 1111 can be removed by laser etching. When removing the second doping layer 135 and the second passivation layer 134 in the first region 1111, a portion of the first doping layer 122 and the second passivation layer 134 can be reserved on the side of the first region 1111 facing the second region 1112. In this way, the second doped semiconductor layer 13 and the first doped semiconductor layer 12 can form an overlapping region 1111a in the first region 1111. At the same time, the second doping layer 135 and the second passivation layer 134 in the second region 1112 can be protected, maintaining the integrity of the second doping layer 135 and the second passivation layer 134 in the second region 1112, and facilitating the second doping layer 135 to collect carriers.

[0135] In some examples, after the second doping layer 135 and the second passivation layer 134 in the first region 1111 are removed by laser etching, the laser oxidation layer in the etched region may be removed by chain etching.

[0136] In some examples, after the second doping layer 135 and the second passivation layer 134 are removed, a conductive layer 14 may be deposited on the front sides of the first region 1111 and the second region 1112 .

[0137] In some examples, the thickness of the conductive layer 14 may be 20-100 nm.

[0138] In some examples, the material of the conductive layer 14 may be a combination of one or more of transparent conductive oxides (TCO), indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), zinc oxide (SnO 2 ), or manganese oxide (MnO 2 ).

[0139] It can be understood that in some examples of the embodiments of the present application, the material of the conductive layer 14 is only shown as some specific examples, and does not limit the specific material of the conductive layer 14.

[0140] In some examples, after the conductive layer 14 is deposited, portions of the conductive layer 14 in the first region 1111 and the second region 1112 can be removed by etching, thereby forming a first isolation trench 141 and a second isolation trench 142. The first trench portion 1411 of the first isolation trench 141 can extend through the surface of the first doped layer 122 facing away from the substrate 11, and the second trench portion 1412 of the first isolation trench 141 can extend through the surface of the second doped layer 135 facing away from the substrate 11.

[0141] Figure 6 This is another front view of the back-contact battery provided in some embodiments of the present application.

[0142] For some examples, refer to Figure 6 As shown, the back contact cell 10 may include electrodes arranged in a first region 1111 and a second region 1112 along a first direction.

[0143] In some examples, the electrode may include a first electrode 143. The first electrode 143 may be provided in the first region 1111. The first electrode 143 may be electrically connected to the conductive layer 14 in the first region 1111.

[0144] In some examples, the electrode may include a second electrode 144. The second electrode 144 may be provided in the second region 1112. The second electrode 144 may be electrically connected to the conductive layer 14 in the second region 1112.

[0145] In some examples, after the conductive layer 14 is deposited, a first electrode 143 may be formed in the first region 1111 and a second electrode 144 may be formed in the second region 1112 by screen printing.

[0146] For some examples, refer to Figure 1 、 Figure 2 and Figure 5 As shown, a second passivation layer 134 may be provided on the second surface 112 of the substrate 11 .

[0147] In some examples, an anti-reflection layer 15 may be provided on the surface of the second passivation layer 134 facing away from the substrate 11 . This can reduce the reflection of sunlight from the second surface 112 and improve the energy conversion efficiency of the back-contact cell 10 .

[0148] For some examples, refer to Figure 1 、 Figure 2 and Figure 5 As shown, the second surface 112 may have a suede structure, which can reduce the reflection of sunlight by the second surface 112 and improve the energy conversion efficiency of the back contact solar cell 10 .

[0149] On the other hand, an embodiment of the present application provides a photovoltaic module, which may include the back-contact cell 10 provided in the aforementioned embodiment of the present application.

[0150] In some examples, a photovoltaic module may include a plurality of back-contact cells 10 provided in the aforementioned embodiments of the present application. The plurality of back-contact cells 10 may be connected in series.

[0151] For some examples, refer to Figure 3 、 Figure 4 and Figure 6 As shown, the photovoltaic module may include a busbar 20. The busbar 20 may be electrically connected to the electrodes of the back contact cell 10. The busbar 20 may be electrically connected to the conductive layer 14 of the overlap region 1111a.

[0152] In some examples, the bus gate 20 may include a first bus gate 21 . The first bus gate 21 may be electrically connected to the first electrode 143 and the conductive layer 14 in the overlapping region 1111 a . The first bus gate 21 may be insulated from the second electrode 144 .

[0153] In some examples, the photovoltaic module may include a first insulating layer 30 . The first insulating layer 30 may be attached between the first busbar 21 and the second electrode 144 .

[0154] That is, in the same back-contact cell 10 , the first busbar 21 is electrically connected to one of the first electrode 143 and the second electrode 144 , and the first busbar 21 is insulated from the other of the first electrode 143 and the second electrode 144 .

[0155] In some examples, the bus gate 20 may include a second bus gate 22 . The second bus gate 22 may be electrically connected to the second electrode 144 and the conductive layer 14 in the overlapping region 1111 a . The second bus gate 22 may be insulated from the first electrode 143 .

[0156] In some examples, the photovoltaic module may include a second insulating layer 40 . The second insulating layer 40 may be attached between the second busbar 22 and the first electrode 143 .

[0157] That is, in the same back-contact battery 10 , the electrode electrically connected to the second conductive layer 14 is opposite to the electrode electrically connected to the first main grid 21 ; the first main grid 21 and the second main grid 22 are both electrically connected to the conductive layer 14 in the overlapping region 1111 a .

[0158] It is understood that when multiple back-contact cells 10 are connected in series, the electrodes connected to the first busbar 21 can be opposite in adjacent back-contact cells 10. For example, in adjacent back-contact cells 10, the first busbar 21 can be electrically connected to the first electrode 143 in one cell and to the second electrode 144 in the other cell.

[0159] It can be understood that when multiple back-contact batteries 10 are connected in series, the connection method of the second main grid 22 can be the same, close or similar to that of the first main grid 21. For details, please refer to the detailed description of the first main grid 21 in the aforementioned embodiment of this application, and the embodiment of this application will not go into details.

[0160] It should be noted that the photovoltaic module provided in the embodiment of the present application has the same or corresponding technical features as the back contact cell 10 provided in the aforementioned embodiment of the present application, and therefore has the same or similar technical effects. For details, please refer to the detailed description of the aforementioned embodiment of the present application, and the embodiment of the present application will not go into details about this.

[0161] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0162] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A back contact battery, characterized in that: include: A substrate (11), the substrate (11) having a first surface (111) and a second surface (112) arranged opposite to each other, the first surface (111) including a first region (1111) and a second region (1112), the first region (1111) including an overlapping region (1111a), and the overlapping region (1111a) being adjacent to the second region (1112); A first doped semiconductor layer (12) is provided in the first region (1111); a second doped semiconductor layer (13) disposed in the second region (1112) and the overlapping region (1111a); the second doped semiconductor layer (13) located in the overlapping region (1111a) is disposed on a side of the first doped semiconductor layer (12) facing away from the substrate (11); and the second doped semiconductor layer (13) and the first doped semiconductor layer (12) have opposite conductivity types; A conductive layer (14), the conductive layer (14) being arranged on a side of the first doped semiconductor layer (12) and the second doped semiconductor layer (13) facing away from the substrate (11); the conductive layer (14) being provided with a first isolation groove (141), the first isolation groove (141) being arranged in the first region (1111), and along the arrangement direction of the first region (1111) and the second region (1112), the first isolation groove (141) comprising a first groove portion (1411) and a second groove portion (1412), the first groove portion (1411) penetrating to the surface of the first doped semiconductor layer (12) facing away from the substrate (11), the second groove portion (1412) being located in the overlapping region (1111a), and the second groove portion (1412) penetrating to the surface of the second doped semiconductor layer (13) facing away from the first doped semiconductor layer (12).

2. The back contact battery according to claim 1, characterized in that Along the arrangement direction of the first region (1111) and the second region (1112), the opening size of the first isolation groove (141) is 10-200 μm; The first groove portion (1411) has a first size, the second groove portion (1412) has a second size, and a ratio of the second size to the first size is 0.8-2.

3. The back contact battery according to claim 1, characterized in that There is a first distance between the surface of the second region (1112) and the second surface (112), and there is a second distance between the surface of the first region (1111) and the second surface (112), and the first distance is smaller than the second distance; the second doped semiconductor layer (13) comprises a first doped sub-section (131), a second doped sub-section (132), and a third doped sub-section (133) connected in sequence; the first doped sub-section (131) is located in the second region (1112), the second doped sub-section (132) and the third doped sub-section (133) are located in the overlapping region (1111a), the second doped sub-section (132) is provided on a side wall of the first doped semiconductor layer (12) facing one end of the second region (1112), and the third doped sub-section (133) is provided on a side surface of the first doped semiconductor layer (12) facing away from the substrate (11); Alternatively, one end of the second groove portion (1412) facing the second region (1112) is flush with an edge of the first doped semiconductor layer (12) facing the second region (1112).

4. The back contact battery according to claim 3, characterized in that The conductive layer (14) is further provided with a second isolation trench (142), the second isolation trench (142) being provided in the second region (1112), and the second isolation trench (142) being located at one end of the second region (1112) close to the first region (1111).

5. The back contact battery according to claim 4, characterized in that The distance between the second isolation groove (142) and the surface of the conductive layer (14) on the second doping sub-section (132) facing the second region (1112) is 0-100 μm; along the arrangement direction of the first region (1111) and the second region (1112), the opening size of the second isolation groove (142) is 10-200 μm.

6. The back contact battery according to claim 4, characterized in that The second isolation trench (142) penetrates the two surfaces of the conductive layer (14) along a first direction, and the first direction intersects with the arrangement direction of the first region (1111) and the second region (1112).

7. The back contact battery according to claim 4, characterized in that Along a first direction, a plurality of second isolation grooves (142) are provided, and the plurality of second isolation grooves (142) are arranged at intervals along the first direction; the first direction intersects with the arrangement direction of the first region (1111) and the second region (1112).

8. The back contact battery according to any one of claims 1 to 3, characterized in that: The first doped semiconductor layer (12) comprises: a first passivation layer (121), the first passivation layer (121) covering the first region (1111); A first doping layer (122), the first doping layer (122) covers a side of the first passivation layer (121) facing away from the substrate (11).

9. The back contact battery according to claim 8, characterized in that The first passivation layer (121) comprises a tunneling oxide layer, and the thickness of the first passivation layer (121) is 1-2 nm; The first doping layer (122) comprises an N-type doped polysilicon layer, the thickness of the first doping layer (122) is 50-200 nm, and the doping concentration of the first doping layer (122) is 1e19 cm -3 -1e21 cm -3 .

10. The back contact battery according to claim 8, characterized in that The second doped semiconductor layer (13) comprises: a second passivation layer (134), the second passivation layer (134) covering the second region (1112) and a side of the first doped layer (122) facing away from the substrate (11); A second doping layer (135), the second doping layer (135) covers a side of the second passivation layer (134) facing away from the substrate (11).

11. The back contact battery according to claim 10, characterized in that The second passivation layer (134) comprises an intrinsic amorphous silicon layer, an intrinsic amorphous silicon oxide layer or an intrinsic amorphous silicon carbide layer, and the thickness of the second passivation layer (134) is 3-8 nm; the second doping layer (135) comprises a P-type doped amorphous silicon layer, a P-type doped microcrystalline silicon layer, a P-type doped nano-silicon layer or a P-type doped silicon carbide layer.

12. A photovoltaic module, characterized in that: include: The back contact battery (10) according to any one of claims 1 to 11; A main grid (20), the main grid (20) is electrically connected to the electrode of the back contact battery, and the main grid (20) is electrically connected to the conductive layer (14) of the overlapping area (1111a).

13. The photovoltaic module according to claim 12, characterized in that: The back contact battery (10) comprises a first electrode (143) and a second electrode (144), wherein the first electrode (143) is connected to the conductive layer (14) of the first region (1111), and the second electrode (144) is connected to the conductive layer (14) of the second region (1112); The main grid (20) includes a first main grid (21) and a second main grid (22). In the same back-contact battery (10), the first main grid (21) is electrically connected to one of the first electrode (143) and the second electrode (144), and the first main grid (21) is insulated from the other of the first electrode (143) and the second electrode (144); the electrode electrically connected to the second main grid (22) is opposite to the electrode electrically connected to the first main grid (21); and the first main grid (21) and the second main grid (22) are both electrically connected to the conductive layer (14) of the overlapping area (1111a).

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