Display panel and display equipment

Abstract

The embodiment of the invention discloses a display panel and display equipment, the display panel comprises a data line, a pixel circuit and a signal shielding wire, the pixel circuit comprises a storage capacitor, and the storage capacitor and the data line are arranged on different layers; in the thickness direction of the display panel, the signal shielding wire is arranged between the storage capacitor and the data line; in the display panel in an overlooking view angle, the storage capacitor and the data line are partially overlapped to form an overlapped part, and at least part of the signal shielding wire is overlapped with the overlapped part. According to the display panel provided by the embodiment of the invention, the signal shielding wire is arranged in the overlapping area between the storage capacitor and the data line, so that the coupling effect of the data line on the storage capacitor is reduced, and the risk of flicker or signal crosstalk is further reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Ultra-high-resolution OLED displays typically use a 3T1C pixel circuit to save layout space. However, due to the high resolution requirement, the space for the pixel circuit is limited, resulting in overlapping signal lines and parasitic capacitance. The data line generates significant parasitic capacitance with the two plates of the storage capacitor, which in turn significantly affects pixel brightness due to coupling with the data line, causing flicker or signal crosstalk. Summary of the Invention

[0003] Embodiments of the present application provide a display panel and a display device, which can reduce the risk of coupling of data lines to storage capacitors, thereby reducing the risk of flickering or signal crosstalk.

[0004] An embodiment of the present application provides a display panel, comprising:

[0005] substrate;

[0006] a plurality of data lines, arranged on the substrate;

[0007] A plurality of pixel circuits are provided on the substrate, each pixel circuit being connected to one of the data lines; the pixel circuits include a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate and the gate of the driving transistor being connected to a first node, the second plate, the first end of the driving transistor, and the anode of the light-emitting device being respectively connected to a second node, and the storage capacitor and the data line being provided in different layers in the thickness direction of the display panel;

[0008] a plurality of signal shielding lines, wherein the signal shielding lines are arranged between the storage capacitor and the data line in a thickness direction of the display panel;

[0009] Wherein, in the display panel viewed from a top perspective, the storage capacitor and the data line partially overlap to form an overlapping portion, and at least a portion of the signal shielding wiring is arranged to overlap with the overlapping portion.

[0010] Optionally, in some embodiments of the present application, the display panel further includes a signal control line provided in a different layer from the data line, the signal control line being connected to the pixel circuit, and in a top-down view of the display panel, the data line and the signal control line are arranged to cross and overlap;

[0011] In the thickness direction of the display panel, the signal shielding line is arranged at an intersection between the signal control line and the data line.

[0012] Optionally, in some embodiments of the present application, the pixel circuit further includes a first transistor and a second transistor, the first end of the first transistor is connected to the data line, the second end of the second transistor is connected to the first node, the first end of the second transistor is connected to the reference voltage line, the second end of the second transistor is connected to the second node, and part of the signal control line is multiplexed as the gate of the first transistor and the gate of the second transistor.

[0013] Optionally, in some embodiments of the present application, in the display area of the display panel, one of the signal shielding traces corresponds to one of the data lines, and the signal shielding trace is extended along the extension direction of the data line. In the display area of the display panel from a top-down perspective, one of the data lines is correspondingly arranged within the area of one of the signal shielding traces.

[0014] Optionally, in some embodiments of the present application, the width of the signal shielding trace is greater than the width of the data line.

[0015] Optionally, in some embodiments of the present application, the signal shielding trace is configured to access a constant voltage signal.

[0016] Optionally, in some embodiments of the present application, the display panel further includes a positive power supply voltage line, a cathode power supply line and a reference voltage line, and the signal shielding line connects one of the positive power supply voltage line, the cathode power supply line and the reference voltage line.

[0017] Optionally, in some embodiments of the present application, the display panel includes a positive power supply voltage line, the positive power supply voltage line is connected to the second end of the driving transistor, and the signal shielding line extends to the non-display area of the display panel and is connected to the positive power supply voltage line in the non-display area.

[0018] Optionally, in some embodiments of the present application, the display panel includes a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the positive power supply voltage line is arranged on the substrate, the first insulating layer covers at least part of the positive power supply voltage line, the first electrode is arranged on the first insulating layer, the second insulating layer covers the first electrode, the second electrode is arranged on the second insulating layer, the third insulating layer covers the second electrode, the signal shielding line is arranged on the third insulating layer, the fourth insulating layer covers the signal shielding line, the data line is arranged on the fourth insulating layer, the signal shielding line is connected to the positive power supply voltage line through a first via, and the first via passes through the first insulating layer to the third insulating layer.

[0019] Optionally, in some embodiments of the present application, the display panel includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a line-transfer portion; the positive power supply voltage line is provided on the substrate; the first insulating layer covers at least a portion of the positive power supply voltage line; the data line and the line-transfer portion are provided on the first insulating layer; the second insulating layer covers the data line and the line-transfer portion; the signal shielding trace is provided on the second insulating layer; the third insulating layer covers the signal shielding trace; the first electrode plate is provided on the third insulating layer; the fourth insulating layer covers the first electrode plate; and the second electrode plate is provided on the fourth insulating layer;

[0020] The signal shielding trace is connected to the line-turning portion through a first via hole, the first via hole passes through the second insulating layer, the line-turning portion is connected to the positive power supply voltage line through a second via hole, and the second via hole passes through the first insulating layer.

[0021] Optionally, in some embodiments of the present application, the display panel includes a reference voltage line, the pixel circuit also includes a second transistor, the first end of the second transistor is connected to the reference voltage line, the second end of the second transistor is connected to the second node, and the signal shielding line extends to the non-display area of the display panel and is connected to the reference voltage line in the non-display area.

[0022] Optionally, in some embodiments of the present application, the display panel includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer, the first insulating layer is arranged on the substrate, the first electrode is arranged on the first insulating layer, the second insulating layer covers the first electrode, the second electrode is arranged on the second insulating layer, the third insulating layer covers the second electrode, the signal shielding line is arranged on the third insulating layer, the fourth insulating layer covers the signal shielding line, the data line is arranged on the fourth insulating layer, the fifth insulating layer covers the data line, and the reference voltage line is arranged on the fifth insulating layer; the reference voltage line is connected to the signal shielding line through a third via, and the third via passes through the fifth insulating layer and the fourth insulating layer.

[0023] Optionally, in some embodiments of the present application, the display panel includes a cathode power line, which is connected to the cathode of the light-emitting device, and the signal shielding line extends to the non-display area of the display panel and is connected to the cathode power line in the non-display area.

[0024] Correspondingly, an embodiment of the present application further provides a display device, which includes the display panel as described in any one of the above embodiments.

[0025] The display panel of the embodiment of the present application includes a data line, a pixel circuit, and a signal shielding line. The pixel circuit includes a storage capacitor, and the storage capacitor and the data line are arranged in different layers; in the thickness direction of the display panel, the signal shielding line is arranged between the storage capacitor and the data line; in the display panel viewed from a top-down perspective, the storage capacitor and the data line partially overlap to form an overlapping portion, and at least a portion of the signal shielding line is arranged to overlap with the overlapping portion.

[0026] It is understandable that the display panel of the embodiment of the present application sets a signal shielding line in the overlapping area between the storage capacitor and the data line to reduce the coupling effect of the data line on the storage capacitor, thereby reducing the risk of flickering or signal crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a top plan structure of a display panel provided in an embodiment of the present application;

[0028] Figure 2 yes Figure 1 Schematic diagram of removing signal shielding routing;

[0029] Figure 3 is an equivalent circuit diagram of a pixel circuit of a display panel provided in an embodiment of the present application;

[0030] Figure 4 is a schematic cross-sectional structural diagram of a display panel provided in an embodiment of the present application;

[0031] Figure 5 is a planar schematic diagram of the active layer of the display panel provided in an embodiment of the present application;

[0032] Figure 6 is another schematic cross-sectional view of a display panel provided in an embodiment of the present application;

[0033] Figure 7 This is another schematic cross-sectional view of a display panel provided in an embodiment of the present application;

[0034] Figure 8 It is a structural schematic diagram of the display device provided in an embodiment of the present application.

[0035] Description of reference numerals:

[0036] 1000 - display device; 100 - display panel; 11 - substrate; 12 - data line; 13 - signal shielding line; p1 - pixel circuit; T1 - driving transistor; T2 - first transistor; T3 - second transistor; C1 - storage capacitor; c11 - first plate; c12 - second plate; Q1 - first node; Q2 - second node; EL - light-emitting device; cv1 - overlapping portion; Fv - thickness direction; F1 - first direction; F2 - second direction; v1 - first contact hole; Vdd - positive power supply voltage line; Sense - reference voltage line; Vss - cathode power supply line; 14 -Signal control line; 141-first sub-control line; 142-second sub-control line; 151-first insulating layer; 152-second insulating layer; 153-third insulating layer; 154-fourth insulating layer; 155-fifth insulating layer; 16-turning part; 17-active layer; 171-first part; 172-second part; 173-third part; 17a-first end sub-segment; 17b-first inclined sub-segment; 17c-middle sub-segment; 17d-second inclined sub-segment; 17e-second end sub-segment; 17f-avoidance space; k1-first via hole; k2-second via hole; k3-third via hole. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described here are only used to illustrate and explain the present application and are not used to limit the present application. In this application, the various embodiments can be combined with each other but will not be repeated one by one. In addition, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inner" and "outer" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as labels and do not impose numerical requirements or establish an order.

[0038] The embodiments of the present application provide a display panel and a display device, which are described in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0039] Please refer to Figures 1 to 4 An embodiment of the present application provides a display panel 100 , which includes a substrate 11 , a plurality of data lines 12 , a plurality of signal shielding traces 13 , and a plurality of pixel circuits p1 .

[0040] A plurality of data lines 12 are disposed on a substrate 11. A plurality of pixel circuits p1 are disposed on the substrate 11. One pixel circuit p1 is connected to one data line 12.

[0041] Pixel circuit p1 includes a driving transistor T1 and a storage capacitor C1. The storage capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 and the gate electrode of the driving transistor T1 are connected to a first node Q1. The second plate C12, the first terminal of the driving transistor T1, and the anode electrode of the light-emitting device EL are respectively connected to a second node Q2. In the thickness direction Fv of the display panel 100, the storage capacitor C1 and the data line 12 are arranged in different layers.

[0042] In the thickness direction Fv of the display panel 100 , the signal shielding trace 13 is disposed between the storage capacitor C1 and the data line 12 .

[0043] In the display panel 100 viewed from a top perspective, the storage capacitor C1 and the data line 12 partially overlap to form an overlapping portion cv1 , and at least a portion of the signal shielding trace 13 overlaps with the overlapping portion cv1 .

[0044] It should be noted that, in order to achieve high resolution in the display panel 100, the data line 12 and the storage capacitor C1 need to be stacked. However, the stacking of the data line 12 and the storage capacitor C1 results in a significant coupling effect from the data voltage connected to the data line 12 before the signal shielding trace 13 is provided. This results in unstable voltage on the storage capacitor C1, which in turn changes the gate voltage of the drive transistor T1 and causes current variations in the light-emitting device EL, resulting in flickering or uneven brightness.

[0045] It is understandable that the display panel 100 of the embodiment of the present application sets a signal shielding line 13 in the overlapping area between the storage capacitor C1 and the data line 12 to reduce the coupling effect of the data line 12 on the storage capacitor C1, thereby reducing the risk of flickering or signal crosstalk.

[0046] Optionally, the light emitting device EL may be an OLED light emitting device, a QLED light emitting device or a micro light emitting diode device.

[0047] Optionally, the pixel circuit p1 is configured to drive the light emitting device EL to emit light. The pixel circuit p1 can be a pixel circuit p1 of various architectures, such as 3T1C, 4T1C, or 8T2C.

[0048] In some embodiments of the present application, the pixel circuit p1 adopts a 3T1C architecture to reduce the layout space of the pixel circuit p1 and thereby achieve higher resolution.

[0049] Optionally, one pixel circuit p1 is correspondingly connected to one light-emitting device EL.

[0050] Optional, in Figure 1 and Figure 2 In the embodiment, a plurality of pixel circuits p1 are arranged along a first direction F1, and a plurality of pixel circuits p1 are arranged along a second direction F2. Optionally, the first direction F1 is perpendicular to the second direction F2.

[0051] Optionally, in some embodiments of the present application, the first plate c11 and the second plate c12 of the storage capacitor C1 are arranged in different layers. The storage capacitor C1 is arranged on a side of the gate g1 of the driving transistor T1 away from the substrate 11 .

[0052] In some embodiments, the second electrode plate c12 is disposed between the gate g1 of the driving transistor T1 and the first electrode plate c11 in the thickness direction Fv of the display panel 100. However, the present invention is not limited thereto. For example, the first electrode plate c11 may be disposed between the gate g1 of the driving transistor T1 and the second electrode plate c12.

[0053] Optionally, the second electrode plate c12 is disposed between the gate g1 of the driving transistor T1 and the first electrode plate c11. In a top-down view of the display panel 100, a portion of the first electrode plate c11 overlaps with the gate g1 of the driving transistor T1 and is located outside the second electrode plate c12, so that the first electrode plate c11 is connected to the gate g1 of the driving transistor T1 through the first contact hole v1, and the first contact hole v1 avoids the second electrode plate c12.

[0054] Optionally, in the display panel 100 viewed from above, the overlapping area between the first electrode plate c11 and the data line 12 includes the overlapping area between the second electrode plate c12 and the data line 12. Figure 4 As shown), the second electrode plate c12 is not affected by the coupling of the data line 12, thereby improving the display effect.

[0055] Optionally, in some other embodiments of the present application, in the display panel 100 viewed from a top perspective, the area of the overlapping region between the first electrode plate c11 and the data line 12 may be greater than the area of the overlapping region between the second electrode plate c12 and the data line 12. In addition, since the second electrode plate c12 is closer to the data line 12 than the first electrode plate c11, the first electrode plate c11, which is farther away from the data line 12, is less affected by the coupling of the data line 12, while the overlapping area between the first electrode plate c11 and the data line 12 is larger, thereby reducing the overall influence of the data line 12 on the storage capacitor C1.

[0056] exist Figure 3Pixel circuit p1 further includes a first transistor T2 and a second transistor T3. The second terminal of the driving transistor T1 is connected to a positive power supply voltage line Vdd. A first terminal of the first transistor T2 is connected to a data line I2, a second terminal of the second transistor T3 is connected to a first node Q1, and a gate of the first transistor T2 is configured to receive a first scan signal Scan1. A first terminal of the second transistor T3 is connected to a reference voltage line Sense, a second terminal of the second transistor T3 is connected to a second node Q2, and a gate of the second transistor T3 is configured to receive a second scan signal Scan2. The cathode of the light-emitting device EL is connected to a cathode power supply line Vss.

[0057] The reference voltage line Sense is configured to pull down the voltage level of the second node Q2 to reset it. Furthermore, the reference voltage line Sense is configured to transmit the real-time voltage of the second node Q2 to the compensation circuit, allowing the compensation circuit to obtain the real-time threshold voltage of the driving transistor T1. The compensation circuit is configured to compensate the second node Q2 when the real-time threshold voltage is less than a set voltage.

[0058] Optionally, the driving transistor T1 , the first transistor T2 , and the second transistor T3 may each be a P-type or N-type thin film transistor.

[0059] The first end of the transistor is one of the source and the drain, and the second end of the transistor is the other of the source and the drain.

[0060] Optionally, in some embodiments of the present application, the display panel 100 further includes a signal control line 14 disposed in a different layer from the data line 12, and the signal control line 14 is connected to the pixel circuit p1. In the top view of the display panel 100, the data line 12 and the signal control line 14 are arranged to cross and overlap.

[0061] In the thickness direction Fv of the display panel 100 , the signal shielding trace 13 is further disposed at the intersection between the signal control line 14 and the data line 12 .

[0062] It should be noted that the signal control line 14 is configured to provide a control signal to the pixel circuit p1 .

[0063] Among them, based on the cross-overlapping setting of the data line 12 and the signal control line 14, when the signal shielding line 13 is not set, the data line 12 has a coupling effect on the signal control line 14. When the data line 12 jumps, it will affect the voltage signal of the signal control line 14, and then affect the switching state of the transistor connected to the signal control line 14 in the pixel circuit p1, thereby affecting the display effect.

[0064] Therefore, in the embodiment of the present application, the signal shielding line 13 is arranged at the intersection between the signal control line 14 and the data line 12 to reduce the coupling effect of the data line 12 on the signal control line 14 and improve the display effect.

[0065] Optionally, in some embodiments of the present application, a signal control line 14 is connected to the first transistor T2, and the signal control line 14 is connected to the first scan signal Scan1; another signal control line 14 is connected to the second transistor T3, and the signal control line 14 is connected to the second scan signal Scan2.

[0066] Optionally, in other embodiments of the present application, the gates of the first transistor T2 and the second transistor T3 are both connected to the same scanning signal, that is, the first scanning signal Scan1 and the second scanning signal Scan2 are the same scanning signal, so that the gates of the first transistor T2 and the second transistor T3 of the same pixel circuit p1 are connected to the same signal control line 14, and the signal control line 14 is configured to be connected to the scanning signal to further save space and achieve better resolution.

[0067] Optionally, in some embodiments of the present application, part of the signal control line 14 is multiplexed as the gate of the first transistor T2 and the gate of the second transistor T3.

[0068] It is understandable that by multiplexing part of the signal control line 14 as the gates of the first transistor T2 and the second transistor T3 , the layout space of the gates can be saved to achieve higher resolution.

[0069] Optionally, in some embodiments of the present application, the first transistor T2 and the second transistor T3 are both dual-gate transistors to reduce the risk of leakage current. The signal control line 14 includes a first sub-control line 141 and a second sub-control line 142. Part of the first sub-control line 141 is multiplexed as the first gate of the first transistor T2 and the first gate of the second transistor T3, and part of the second sub-control line 142 is multiplexed as the second gate of the first transistor T2 and the second gate of the second transistor T3 to achieve higher resolution.

[0070] Optionally, the first sub-control line 141 and the second sub-control line 142 are configured to receive the same scan signal, but not limited thereto. For example, the first sub-control line 141 and the second sub-control line 142 are configured to receive different scan signals.

[0071] Optionally, the first sub-control line 141 and the second sub-control line 142 are both extended along the first direction F1 . In the second direction F2 , the first sub-control line 141 and the second sub-control line 142 are adjacent to each other.

[0072] Optionally, in some embodiments of the present application, in the display area of the display panel 100, a signal shielding trace 13 corresponds to a data line 12, and the signal shielding trace 13 is extended along the extension direction of the data line 12. In the display area of the display panel 100 from a top-down perspective, a data line 12 is correspondingly arranged within the area of a signal shielding trace 13.

[0073] It can be understood that a data line 12 is correspondingly arranged in the area of a signal shielding line 13, so that the signal shielding line 13 can completely shield the data line 12 in the display area, reducing the coupling effect of the data line 12 on the entire pixel circuit p1 and improving the display effect.

[0074] In some embodiments, the signal shielding trace 13 further extends between the gate g1 of the driving transistor T1 and the data line 12. The signal shielding trace 13 can shield the data line 12 from coupling effects on the gate g1 of the driving transistor T1, thereby improving the stability of the driving transistor T1. Furthermore, since the gate g1 of the driving transistor T1 is connected to the first electrode plate c11, the gate g1 of the driving transistor T1 can serve as an extension of the first electrode plate c11. Therefore, the signal shielding trace 13 extends between the gate g1 and the data line 12, thereby reducing the coupling effects of the data line 12 on the storage capacitor C1.

[0075] Optionally, in some embodiments of the present application, the width of the signal shielding trace 13 is greater than the width of the data line 12, so that the outline range of the data line 12 in the display area is completely overlapped within the outline range of the signal shielding trace 13, so as to minimize the coupling effect of the data line 12 on the pixel circuit p1.

[0076] Optionally, in some embodiments of the present application, the signal shielding trace 13 is configured to access a constant voltage signal.

[0077] It is understandable that the signal shielding trace 13 is connected to a constant voltage signal to prevent the signal shielding trace 13 from floating, thereby improving the shielding effect of the signal shielding trace 13 on interference signals.

[0078] Optionally, the display panel 100 further includes a positive power supply voltage line Vdd, a cathode power supply line Vss, and a reference voltage line Sense. The signal shielding trace 13 is connected to one of the positive power supply voltage line Vdd, the cathode power supply line Vss, and the reference voltage line Sense.

[0079] It can be understood that the signal shielding trace 13 connects one of the positive power supply voltage line Vdd, the cathode power supply line Vss and the reference voltage line Sense, so that no additional constant voltage signal line is required, thus saving wiring space and achieving higher resolution.

[0080] Optionally, the positive power supply voltage line Vdd is configured to be connected to a high level, and the cathode power supply line Vss and the reference voltage line Sense are both configured to be connected to a low level.

[0081] Optionally, in some embodiments of the present application, the cathode power line Vss is connected to the cathode of the light emitting device EL. The signal shielding trace 13 extends to the non-display area of the display panel 100 and is connected to the cathode power line Vss in the non-display area.

[0082] It is understandable that the connection point between the signal shielding line 13 and the cathode power line Vss is set in the non-display area of the display panel 100 to save wiring space in the display area of the display panel 100 and achieve higher resolution.

[0083] Optionally, in some embodiments of the present application, the positive power supply voltage line Vdd is connected to the second end of the driving transistor T1, and the signal shielding line 13 extends to the non-display area of the display panel 100 and is connected to the positive power supply voltage line Vdd in the non-display area.

[0084] It is understandable that the connection point between the signal shielding line 13 and the positive power supply voltage line Vdd is set in the non-display area of the display panel 100 to save wiring space in the display area of the display panel 100 and achieve higher resolution.

[0085] Optionally, the plurality of signal shielding lines 13 are connected to a branch of the positive power voltage line Vdd, the branch is extended along the first direction F1, and the plurality of signal shielding lines 13 are extended along the second direction F2.

[0086] Optional, please refer to Figure 4 In some embodiments of the present application, the display panel 100 includes a first insulating layer 151, a second insulating layer 152, a third insulating layer 153, and a fourth insulating layer 154. A positive power supply voltage line Vdd is provided on the substrate 11. The first insulating layer 151 covers at least a portion of the positive power supply voltage line Vdd. A first electrode c11 is provided on the first insulating layer 151. The second insulating layer 152 covers the first electrode c11. The second electrode c12 is provided on the second insulating layer 152. The third insulating layer 153 covers the second electrode c12. A signal shielding trace 13 is provided on the third insulating layer 153. The fourth insulating layer 154 covers the signal shielding trace 13. The data line 12 is provided on the fourth insulating layer 154. The signal shielding trace 13 is connected to the positive power supply voltage line Vdd through a first via k1. The first via k1 passes through the first insulating layer 151 to the third insulating layer 153.

[0087] It can be understood that, since the gate g1 of the driving transistor T1 is stacked below the storage capacitor C1 and connected to the first plate c11, the gate g1 of the driving transistor T1 serves as an extension of the first plate c11. Therefore, the data line 12 is set above the storage capacitor C1, which reduces the coupling effect of the data line 12 on the gate g1 and reduces the coupling effect on the storage capacitor C1.

[0088] Optionally, in some embodiments of the present application, the driving transistor T1, the first transistor T2, the second transistor T3 and the signal control line 14 are formed in the first metal layer. The display panel 100 further includes an active layer 17, which is disposed on a side of the first metal layer close to the substrate 11.

[0089] Please refer to Figure 5 The active layer 17 includes a first portion 171 and a second portion 172 disposed in the display area of the display panel 100. The first portion 171 extends along the second direction F2, and the second portion 172 also extends substantially along the second direction F2. In the first direction F1, the first portion 171 and the second portion 172 are alternately arranged.

[0090] In the second direction F2, the second portion 172 includes a first end subsegment 17a, a first inclined subsegment 17b, a middle subsegment 17c, a second inclined subsegment 17d, and a second end subsegment 17e connected in sequence.

[0091] The first inclined sub-segment 17b, the middle sub-segment 17c, and the second inclined sub-segment 17d are connected to form a clearance space 17f. In the first direction F1, the first portion 171 is positioned adjacent to the clearance space 17f and avoids the first end sub-segment 17a and the second end sub-segment 17e. In the second direction F2, the first portion 171 at least partially overlaps with the first end sub-segment 17a and the second end sub-segment 17e.

[0092] Such an arrangement allows a larger space around the first end sub-segment 17 a and the second end sub-segment 17 e for layout of other traces or vias, thereby achieving higher resolution.

[0093] Optional, combined Figure 1 and Figure 2 In some embodiments of the present application, in the second direction F2, two adjacent pixel circuits p1 share a first portion 171 and a second portion 172. A portion of the first portion 171 is configured as the channel of the first transistor T2. A portion of the middle subsegment 17c is configured as the channel of the second transistor T3. In the first direction F1, the channel of the first transistor T2 and the channel of the second transistor T3 are aligned.

[0094] At least a portion of the first end sub-segment 17a is configured as the channel of a driving transistor T1, and at least a portion of the second end sub-segment 17e is configured as the channel of another driving transistor T1. Both the first end sub-segment 17a and the second end sub-segment 17e have a meandering structure formed by at least three segments of sub-wires, resulting in the channel of the driving transistor T1 having such a meandering structure. This increases the channel length of the driving transistor T1 and reduces the risk of leakage current and breakdown of the driving transistor T1.

[0095] Optionally, in some embodiments of the present application, the active layer 17 further includes a third portion 173 , which extends along the first direction F1 , and the first end sub-segments 17a of the plurality of second portions 172 are all connected to a third portion 173 , and the second end sub-segments 17e of the plurality of second portions 172 are all connected to another third portion 173 .

[0096] The third portion 173 is configured as a connection line connected to the positive power voltage line Vdd. That is, a high-level signal can be provided to the plurality of driving transistors T1 through the third portion 173 , saving layout space and achieving higher resolution.

[0097] Please refer to Figure 6 , Figure 6 FIG. 1 shows another cross-sectional structural diagram of the display panel 100 according to an embodiment of the present application. Figure 6 In the embodiment, the parts different from those in the above embodiment will be described to avoid redundancy, that is, Figure 6 The corresponding embodiments will not be repeated. Figures 1 to 3 and Figure 5 Related content.

[0098] In some embodiments of the present application, the display panel 100 includes a first insulating layer 151, a second insulating layer 152, a third insulating layer 153, a fourth insulating layer 154, and a transition portion 16. A positive power supply voltage line Vdd is provided on the substrate 11. The first insulating layer 151 covers at least a portion of the positive power supply voltage line Vdd. The data line 12 and the transition portion 16 are provided on the first insulating layer 151. The second insulating layer 152 covers the data line 12 and the transition portion 16. The signal shielding trace 13 is provided on the second insulating layer 152. The third insulating layer 153 covers the signal shielding trace 13. The first electrode plate c11 is provided on the third insulating layer 153. The fourth insulating layer 154 covers the first electrode plate c11. The second electrode plate c12 is provided on the fourth insulating layer 154.

[0099] The signal shielding trace 13 is connected to the line-turning portion 16 through a first via k1 that passes through the second insulating layer 152 . The line-turning portion 16 is connected to the positive power supply voltage line Vdd through a second via k2 that passes through the first insulating layer 151 .

[0100] Please refer to Figure 7 , Figure 7 FIG. 1 shows another cross-sectional structural diagram of the display panel 100 according to an embodiment of the present application. Figure 7 In the embodiment, the parts different from those in the above embodiment will be described to avoid redundancy, that is, Figure 7 The corresponding embodiments will not be repeated. Figures 1 to 3 and Figure 5 Related content.

[0101] Optionally, in some embodiments of the present application, a first terminal of the second transistor T3 is connected to a reference voltage line Sense, and a second terminal of the second transistor T3 is connected to a second node Q2. The signal shielding trace 13 extends to a non-display area of the display panel 100 and is connected to the reference voltage line Sense in the non-display area.

[0102] It is understandable that the connection point between the signal shielding line 13 and the reference voltage line Sense is set in the non-display area of the display panel 100 to save wiring space in the display area of the display panel 100 and achieve higher resolution.

[0103] Optionally, in some embodiments of the present application, the display panel 100 includes a first insulating layer 151, a second insulating layer 152, a third insulating layer 153, a fourth insulating layer 154, and a fifth insulating layer 155. The first insulating layer 151 is disposed on the substrate 11. The first electrode plate c11 is disposed on the first insulating layer 151. The second insulating layer 152 covers the first electrode plate c11. The second electrode plate c12 is disposed on the second insulating layer 152. The third insulating layer 153 covers the second electrode plate c12. The signal shielding trace 13 is disposed on the third insulating layer 153. The fourth insulating layer 154 covers the signal shielding trace 13. The data line 12 is disposed on the fourth insulating layer 154.

[0104] The fifth insulating layer 155 covers the data line 12. The reference voltage line Sense is disposed on the fifth insulating layer 155. The reference voltage line Sense is connected to the signal shielding line 13 through a third via k3. The third via k3 passes through the fifth insulating layer 155 and the fourth insulating layer 154.

[0105] Please refer to Figure 8 Accordingly, an embodiment of the present application further provides a display device 1000 , which includes the display panel 100 as described in any one of the above embodiments.

[0106] It should be noted that the structure of the display panel 100 of the display device 1000 of the embodiment of the present application is similar to or the same as the structure of the display panel 100 of any of the above embodiments. Figures 1 to 7 , so I will not repeat it here.

[0107] The display panel 100 of the display device 1000 according to an embodiment of the present application includes a data line 12, a pixel circuit p1, and a signal shielding trace 13. The pixel circuit p1 includes a storage capacitor C1, which is disposed in a different layer from the data line 12. In the thickness direction Fv of the display panel 100, the signal shielding trace 13 is disposed between the storage capacitor C1 and the data line 12. In a top-down view of the display panel 100, the storage capacitor C1 and the data line 12 partially overlap to form an overlapping portion cv1, and at least a portion of the signal shielding trace 13 overlaps with the overlapping portion cv1.

[0108] It can be understood that the display panel 100 of the display device 1000 of the embodiment of the present application adopts a signal shielding line 13 set in the overlapping area between the storage capacitor C1 and the data line 12 to reduce the coupling effect of the data line 12 on the storage capacitor C1, thereby reducing the risk of flickering or signal crosstalk.

[0109] Optionally, the display device 1000 can be applied to a cellular phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a television, a game console, a watch-type electronic device, a head-mounted display, a display of a personal computer, a notebook computer, a vehicle navigation system, a vehicle dashboard, a digital camera, a video camera, an outdoor billboard, an electronic display board, a medical device, an inspection device, various household appliances such as a refrigerator and a washing machine, or an Internet of Things device.

[0110] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: substrate; a plurality of data lines, arranged on the substrate; A plurality of pixel circuits are provided on the substrate, each pixel circuit being connected to one of the data lines; the pixel circuits include a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate and the gate of the driving transistor being connected to a first node, the second plate, the first end of the driving transistor, and the anode of the light-emitting device being respectively connected to a second node, and the storage capacitor and the data line being provided in different layers in the thickness direction of the display panel; a plurality of signal shielding lines, wherein the signal shielding lines are arranged between the storage capacitor and the data line in a thickness direction of the display panel; Wherein, in the display panel viewed from a top perspective, the storage capacitor and the data line partially overlap to form an overlapping portion, and at least a portion of the signal shielding wiring is arranged to overlap with the overlapping portion.

2. The display panel according to claim 1, wherein: The display panel further includes a signal control line provided in a different layer from the data line, the signal control line being connected to the pixel circuit, and in a top view of the display panel, the data line and the signal control line are arranged to cross and overlap; In the thickness direction of the display panel, the signal shielding line is arranged at an intersection between the signal control line and the data line.

3. The display panel according to claim 2, wherein: The pixel circuit also includes a first transistor and a second transistor, the first end of the first transistor is connected to the data line, the second end of the second transistor is connected to the first node, the first end of the second transistor is connected to the reference voltage line, the second end of the second transistor is connected to the second node, and part of the signal control line is multiplexed as the gate of the first transistor and the gate of the second transistor.

4. The display panel according to claim 3, wherein: In the display area of the display panel, one of the signal shielding traces corresponds to one of the data lines, and the signal shielding traces are extended along the extension direction of the data line. In the display area of the display panel from a top-down perspective, one of the data lines is correspondingly arranged within the area of one of the signal shielding traces.

5. The display panel according to claim 4, wherein: The width of the signal shielding line is greater than the width of the data line.

6. The display panel according to any one of claims 1 to 5, characterized in that: The signal shielding trace is configured to receive a constant voltage signal.

7. The display panel according to claim 6, wherein: The display panel further includes a positive power supply voltage line, a cathode power supply line, and a reference voltage line, and the signal shielding line is connected to one of the positive power supply voltage line, the cathode power supply line, and the reference voltage line.

8. The display panel according to claim 6, wherein: The display panel includes a positive power supply voltage line connected to the second end of the driving transistor. The signal shielding line extends to a non-display area of the display panel and is connected to the positive power supply voltage line in the non-display area.

9. The display panel according to claim 8, wherein: The display panel includes a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer. The positive power supply voltage line is arranged on the substrate, the first insulating layer covers at least a portion of the positive power supply voltage line, the first electrode is arranged on the first insulating layer, the second insulating layer covers the first electrode, the second electrode is arranged on the second insulating layer, the third insulating layer covers the second electrode, the signal shielding line is arranged on the third insulating layer, the fourth insulating layer covers the signal shielding line, the data line is arranged on the fourth insulating layer, the signal shielding line is connected to the positive power supply voltage line through a first via, and the first via passes through the first insulating layer to the third insulating layer.

10. The display panel according to claim 8, wherein The display panel includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a line-transfer portion, wherein the positive power supply voltage line is arranged on the substrate, the first insulating layer covers at least a portion of the positive power supply voltage line, the data line and the line-transfer portion are arranged on the first insulating layer, the second insulating layer covers the data line and the line-transfer portion, the signal shielding trace is arranged on the second insulating layer, the third insulating layer covers the signal shielding trace, the first electrode plate is arranged on the third insulating layer, the fourth insulating layer covers the first electrode plate, and the second electrode plate is arranged on the fourth insulating layer; The signal shielding trace is connected to the line-turning portion through a first via hole, the first via hole passes through the second insulating layer, the line-turning portion is connected to the positive power supply voltage line through a second via hole, and the second via hole passes through the first insulating layer.

11. The display panel according to claim 6, wherein: The display panel includes a reference voltage line, and the pixel circuit also includes a second transistor, the first end of the second transistor is connected to the reference voltage line, the second end of the second transistor is connected to the second node, and the signal shielding line extends to the non-display area of the display panel and is connected to the reference voltage line in the non-display area.

12. The display panel according to claim 11, wherein: The display panel includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, wherein the first insulating layer is disposed on the substrate, the first electrode plate is disposed on the first insulating layer, the second insulating layer covers the first electrode plate, the second electrode plate is disposed on the second insulating layer, the third insulating layer covers the second electrode plate, the signal shielding trace is disposed on the third insulating layer, the fourth insulating layer covers the signal shielding trace, the data line is disposed on the fourth insulating layer, the fifth insulating layer covers the data line, and the reference voltage line is disposed on the fifth insulating layer; The reference voltage line is connected to the signal shielding line through a third via hole, and the third via hole passes through the fifth insulating layer and the fourth insulating layer.

13. The display panel according to claim 6, wherein: The display panel includes a cathode power line connected to the cathode of the light-emitting device. The signal shielding line extends to a non-display area of the display panel and is connected to the cathode power line in the non-display area.

14. A display device, characterized in that: Comprising the display panel according to any one of claims 1-13.

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