Silicon-on-insulator (SOI) carrier chip and manufacturing method thereof
By etching the well in a carrier chip with silicon on insulator (SOI) structure, the optical characteristics of the bottom surface of the well are consistent with the top silicon layer surface, and the problem of crosstalk of fluorescence signals of adjacent cells in live cell imaging devices is solved, and image contrast and imaging accuracy are improved.
Patent Information
- Application Number
- CN202380081810.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-11-27
- Filing Date
- 2023-11-27
- Publication Date
- 2025-08-12
AI Technical Summary
In the prior art, live cell imaging devices using opaque well arrays have crosstalk problems between fluorescent signals of adjacent cells, and the quality of the bottom well has an important impact on imaging performance.
A carrier chip with silicon on insulator (SOI) structure is used to form multiple wells by etching. The bottom surface of each well has similar optical reflection characteristics to the surface of the top silicon layer. The BOX layer is used as the etching stop layer to ensure that the optical characteristics of the bottom and top silicon layer surfaces are consistent and image contrast is improved.
The image contrast is enhanced, the distinction between the well periphery and the cell periphery is improved, the crosstalk of fluorescent signals of adjacent cells is reduced, and the imaging accuracy is improved.
Smart Images
Figure CN120476303A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims priority to U.S. Provisional Application No. 63 / 428,070, filed on November 27, 2022, the entire contents of which are incorporated herein by reference. Technical Field
[0003] The present disclosure relates generally to carrier chips for cell fluorescence imaging, and more particularly to silicon-on-insulator carrier chips. Background Art
[0004] Fluorescence imaging is commonly used to non-invasively image various biological cells. This allows for the study of biological processes in living cells or other biomaterials. Commercial methods for imaging living cells use live cell imagers and certain disposables that allow for the capture and maintenance of such cells. Live cell imaging involves time-lapse microscopy of living cells observed over time, for example by capturing images of the living cells. Several types of microscopes are used for live cell imaging, including phase contrast, quantitative phase contrast, fluorescence, and holographic tomography. In some cases, chips with multiple wells for placing living cells are used for this type of microscopy.
[0005] Figure 1 An example of a portion of a chip 100 having wells 110 is shown in FIG. Wells 110 are depressions within the silicon substrate (also referred to herein as substrate) of the chip and are arranged in rows and columns. For example, well 110-ij, where "i" and "j" are integers equal to or greater than "1", is located in row "i" and column "j". For example, but not limited to, a multi-well chip with 250,000 wells can be arranged in a 500 by 500 arrangement, where 1 ≤ i and j ≤ 500. The same multi-well chip can be arranged differently, in a 1000 by 250 arrangement, where 1 ≤ i ≤ 1000 and 1 ≤ j ≤ 250 (or vice versa). Each such chip is operated individually and used for fluorescence imaging with a specific microscope setup. In some cases, a bright-field microscope is used to illuminate the specimen with a white light source, and an image is formed by light that passes through the specimen and reflects back from the bottom surface of the wells. In some cases, multiple such chips are mounted on a holder, and the holder is operated and images are captured under the field of view of the microscope.
[0006] Most cell arrays are examined using inverted microscopes and are therefore fabricated on transparent substrates. However, using opaque well arrays with upright microscopes offers advantages, such as reduced crosstalk between fluorescent signals from adjacent cells. The surface quality of the well bottom has been determined to significantly impact the array's performance in increasing the optical signal for cell imaging.
[0007] Therefore, it would be advantageous to provide solutions that overcome the above challenges. Summary of the Invention
[0008] The following is an overview of several exemplary embodiments of the present disclosure. This overview is provided to provide a basic understanding of these embodiments for the convenience of the reader and does not fully limit the breadth of the present disclosure. This overview is not an extensive overview of all contemplated embodiments and is neither intended to identify key or important elements of all embodiments nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to a more detailed description that will be presented later. For convenience, the term "certain embodiments" may be used herein to refer to a single embodiment or multiple embodiments of the present disclosure.
[0009] Some exemplary embodiments disclosed herein include a carrier chip for capturing biological cells. The carrier chip includes a silicon-on-insulator (SOI) structure, wherein the SOI structure includes a top silicon layer; a bottom oxide (BOX) layer; a silicon substrate; and a plurality of wells, wherein each well in the plurality of wells is partially arranged in the top silicon layer and partially arranged in the BOX layer, and wherein a bottom surface of each well in the plurality of wells has optical reflectivity characteristics of a surface of the top silicon layer.
[0010] Some exemplary embodiments disclosed herein also include a method for manufacturing a carrier chip for capturing cells. The method includes: manufacturing a silicon-on-insulator (SOI) structure, the SOI structure including a top silicon layer, a bottom oxide (BOX) layer, and a silicon substrate; performing photolithographic formation of a plurality of wells, wherein each well in the plurality of wells is designed to capture at least one cell therein; etching the top silicon layer to form a plurality of wells; stripping an etching mask; and etching a BOX layer at the bottom of each well in the plurality of wells, wherein each well in the plurality of wells is partially arranged in the top silicon layer and partially arranged in the BOX layer, and wherein a bottom surface of each well in the plurality of wells has the optical reflectivity characteristics of a surface of the top silicon layer.
[0011] Some exemplary embodiments disclosed herein also include a method for manufacturing a carrier chip for capturing cells. The method includes: performing photolithographic formation on a semiconductor structure having multiple wells, wherein each well in the multiple wells is designed to capture at least one cell therein; etching a top silicon layer to form multiple wells; stripping off the etching mask; and etching a bottom oxide (BOX) layer on the bottom surface of each well in the multiple wells, wherein the semiconductor structure is a silicon-on-insulator (SOI) structure, the SOI structure including a top silicon layer, a BOX layer, and a silicon substrate, wherein each well in the multiple wells is partially arranged in the top silicon layer and partially arranged in the BOX layer, and wherein the bottom surface of each well in the multiple wells has substantially similar optical reflectivity properties to the top silicon layer.
[0012] BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The subject matter disclosed herein is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification.The foregoing and other objects, features and advantages of the disclosed embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings.
[0014] Figure 1 is a schematic diagram of a portion of a carrier chip having wells therein.
[0015] Figure 2 is a schematic cross-sectional view of a silicon-on-insulator (SOI) wafer before use according to one embodiment.
[0016] Figure 3 is a schematic cross-sectional view of a silicon-on-insulator (SOI) wafer after wells are etched therein, according to one embodiment.
[0017] Figure 4 is a schematic diagram of a cross-section of a silicon-on-insulator (SOI) wafer after wells are etched therein and a cell-trapping coating is added to the bottom of the wells, according to one embodiment.
[0018] Figure 5 is a schematic diagram of a cross-section of a silicon-on-insulator (SOI) wafer after etching a well therein including bottom oxide (BOX) controlled undercutting according to one embodiment.
[0019] Figure 6 This is a manufacturing flow of the carrier chip manufacturing steps according to the first embodiment.
[0020] Figure 7 This is a manufacturing flow of carrier chip manufacturing steps according to the second embodiment. DETAILED DESCRIPTION
[0021] It is important to note that the embodiments disclosed herein are merely examples of the many advantageous uses of the innovative teachings herein. In general, statements in this specification do not necessarily limit any of the various claimed embodiments. Furthermore, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be plural, and vice versa, without loss of generality. In the drawings, like numerals throughout the several views represent like parts.
[0022] A carrier chip including a plurality of wells is formed on a silicon-on-insulator (SOI) semiconductor wafer. The carrier chip is designed to capture biological cells in its wells. The SOI wafer includes a top single crystal silicon layer, a bottom oxide (BOX) layer, and a silicon substrate, wherein the top single crystal silicon layer may be an epitaxial silicon layer (epi silicon layer) or a polycrystalline silicon layer. The optical reflectivity of the surface of the top silicon layer and the surface of the substrate are substantially similar. By performing etching, a well-defined well depth is formed through the top silicon layer using the BOX layer as an etch stop layer. Once the BOX layer is etched out from the bottom of each well, the bottom of the well and the surface of the top silicon layer exhibit substantially similar optical reflectivity, thereby improving image contrast when an image of the carrier chip is taken. The improvement in image contrast can enhance the distinction between, for example, the periphery of the well and the periphery of the cells captured in the plurality of wells.
[0023] Now refer to Figure 2 , Figure 2 A schematic diagram of a cross-section of a silicon-on-insulator (SOI) wafer 200 before use is described according to an embodiment. The SOI wafer 200 includes three layers. A substrate layer 210 made of silicon provides the physical integrity of the structure. A bottom oxide (BOX) layer 220 forms an insulator between the substrate 210 and a top silicon layer 230, which is typically used to form electronic devices thereon or therein. Therefore, the top silicon layer 230 can also be referred to as a device layer and is used as a device layer. In one embodiment, the top silicon layer 230 is made of polysilicon or epitaxial polysilicon. Figure 2 The structure shown provides the basis for the embodiments discussed herein.
[0024] Figure 3 3 is a schematic diagram of a cross-section 300 of an SOI wafer after wells have been etched therein, according to one embodiment. First, as further explained herein, a well is formed in the top silicon layer 230 using an etching technique that generally stops at the BOX layer 220. The formation of the well (or cavity) in the top silicon layer 230 involves an initial etching of the silicon layer 230 to the BOX layer 220, but does not completely etch the BOX layer 220. The wells (or cavities) formed are arranged around the top silicon layer 230. Subsequently, the BOX layer in each well can be further etched as described herein to form a plurality of wells 310. Subsequent etching of the BOX layer 220 etches the BOX layer, which is exposed within the wells formed by the initial etching of the top silicon layer 230. The wells 310 extend from the surface of the top silicon layer 230 all the way to the top of the substrate 210. The well 310 is a cavity penetrating the top silicon layer 230 and the BOX layer 220 , and thus, the well 310 is partially disposed in the top silicon layer 220 and partially disposed in the BOX layer 220 .
[0025] For example, well 310 can be a hollow space surrounded by top silicon layer 230 and BOX layer 220. In another example, the sidewalls of well 320 can include top silicon layer 230 and BOX layer 220, and the bottom surface of well 320 can be substrate 210. This structure provides an advantage for the carrier chip in that the top silicon layer 230 and the surface at the bottom of well 310 have substantially similar optical reflective properties. As a result, the accuracy of image processing performed by the dedicated imaging device is improved, as better distinction is achieved between cells trapped in the well and their surroundings. Improved image contrast is achieved between the well periphery and the cell periphery for differentiation.
[0026] Figure 4 is a schematic diagram of a cross-section 400 of an SOI wafer after wells have been etched therein and a cell capture coating has been added to the bottom of the wells, according to one embodiment. Figure 3 In addition to the coatings already described in
[0045] , which are not repeated here for the sake of brevity, an additional coating 410 is added to the bottom of each well of the well 310. The coating 410 is an adhesion layer that is designed to improve the adhesion of captured cells to the well. The coating 410 can be removed only from the surface of the top silicon layer 230, while retaining the coating 410 on the bottom surface of the well 310. For example, during the photolithography and etching process, the adhesion layer can be deposited on the surface of the top silicon layer 230 and the bottom surface of the well 310. However, the photolithography and etching process described herein removes the adhesion layer on the surface of the top silicon layer 230, so that only the adhesion layer at the bottom surface of the well 310 serves as the coating 410 for capturing cells. The configuration described herein allows for effective adhesion and capture of cells within the well 310 rather than on the surface of the top silicon layer 230.
[0027] Figure 5 FIG2 is a schematic diagram of a cross-section 500 of an SOI wafer after etching wells therein (including BOX-controlled undercutting), according to one embodiment. Thus, the etching of the BOX layer 220 can be extended to undercut the device layers and form connecting channels 510 between the wells 310. This allows chemical and / or ionic communication between cells in adjacent wells 310. This process needs to be well controlled to avoid complete etching of the BOX layer 220 and delamination of the device layers (or top silicon layer 230).
[0028] In one embodiment, after the photolithography and etch mask formation steps, the top silicon layer 230 is etched using a Si reactive ion etching process or a deep reactive ion etching process to achieve the desired well wall angle. It should be noted that the photolithography process, etch mask type, and process sequence used for etch mask formation are the same as those used in microelectronics manufacturing. The actual choice of process and process sequence is universal and can be selected based on, for example, economics and the availability of tools and expertise at the manufacturing site. The versatility of the disclosed embodiments, such as, but not limited to, etch mask formation and etch mask type, is advantageous, so that the process can be used in a variety of settings and conditions.
[0029] Figure 6 600 is an example manufacturing flow for carrier chip fabrication steps according to the first embodiment. In this case, a hard mask option is shown. It should be understood that standard process steps (such as cleaning, dicing, etc.) have been omitted from the following description for the purpose of simplifying the description herein and without materially affecting the clarity of the disclosed embodiments. Those skilled in the art will appreciate that standard lithography steps not explicitly described herein may be performed between the fabrication steps described herein. Furthermore, specific steps described herein may be performed earlier or later in the process, where appropriate.
[0030] At 610, a starting material, such as an SOI wafer, is provided.
[0031] At 620, deposition of an etch hard mask is performed, which provides locations for wells (eg, well 310) on the SOI wafer.
[0032] At 630 , photolithographic formation of a well (eg, well 310 ) is performed.
[0033] At 640 , an etch of the hard mask is performed.
[0034] At 650 , a resist strip process is performed. In one embodiment, step 650 may be performed after step 660 .
[0035] At 660 , a top silicon layer etch, such as an etch of the top silicon layer 230 , is performed.
[0036] At 670 , a strip of the hard mask is performed. In one embodiment, step 670 may be performed after step 680 .
[0037] At 680, a BOX layer etch is performed, such as an etch of BOX layer 220. As described above, in one embodiment, an extension etch may be performed to extend a channel, such as channel 510, between adjacent wells.
[0038] Figure 7 700 is an example manufacturing flow for carrier chip fabrication steps according to the second embodiment. In this case, the resist mask option is shown. It should be understood that standard process steps (such as cleaning, dicing, etc.) have been omitted from the following description for the purpose of keeping the description concise and clear, and without materially affecting the clarity of the disclosed embodiments. One of ordinary skill in the art will appreciate that standard photolithography steps not explicitly described herein may be performed between the fabrication steps described herein. Furthermore, specific steps described herein may be performed earlier or later in the process, where appropriate.
[0039] At 710, a starting material, such as an SOI wafer, is provided.
[0040] At 720 , photolithographic formation of a well (eg, well 310 ) is performed.
[0041] At 730 , a top silicon layer etch, such as an etch of the top silicon layer 230 , is performed.
[0042] At 740, the mask is etched. In one embodiment, step S740 may be performed after step S750.
[0043] At 750, a BOX layer etch is performed, such as an etch (or strip) of BOX layer 220. As described above, in one embodiment, an extension etch may be performed to extend a channel, such as channel 510, between adjacent wells.
[0044] In one embodiment, shallow marks (e.g., for focusing, navigation, etc.) are etched into the top of the top silicon layer. This etching can be performed before etching the wells using photolithography and etching steps.
[0045] It should be noted that the well is shown as a circular tube penetrating the SOI surface for illustrative purposes only and should not be considered limited to this circular view. Other implementations are possible without departing from the scope of the disclosed embodiments. For example, but not limited to, from a top view, the well (i.e., the well periphery) can be any type of polygon, including triangle, square, hexagon, etc.
[0046] It should be further understood that the figures showing various cross-sections, particularly Figures 2 to 4The drawings are not meant to be to scale but are intended to clearly present the various aspects of the embodiments discussed herein. In the case of a polygonal well, when the top silicon layer 230 is a single crystal <100> When the silicon material is wet, a non-isotropic etching process can be used. In this case, the angle of the wall angle will conform to the crystal plane index. Wet etching can include etching with, for example, hot potassium hydroxide (KOH) solution, tetramethylammonium hydroxide (TMAH) solution or similar solutions known in the art. These wet etchings are performed using an etching hard mask based on silicon nitride (SiN) or silicon dioxide (SiO2).
[0047] In another embodiment, a transparent substrate can be used instead of silicon for substrate 210. The starting material of substrate 210 can be a transparent material, on which there is a BOX layer 220 and a top silicon layer 230. In one embodiment, glass (e.g., borosilicate glass, etc.) or fused quartz can be used as substrate 210, which can further eliminate the need for BOX layer 220. In one embodiment, if two reflective surfaces are required, or the substrate is optically transparent, a thin layer of titanium, amorphous silicon, or a process-compatible and biocompatible reflective material can be deposited to provide sufficient quality reflectivity.
[0048] All examples and conditional language described herein are intended for illustrative purposes to help the reader understand the principles of the disclosed embodiments and the concepts contributed by the inventors to further the art, and should be interpreted as not being limited to these specifically cited examples and conditions. In addition, all statements describing the principles, aspects, and embodiments of the disclosed embodiments herein, as well as specific examples thereof, are intended to encompass structural and functional equivalents thereof. Furthermore, such equivalents include currently known equivalents as well as equivalents developed in the future, i.e., any element developed to perform the same function, regardless of its structure.
[0049] It should be understood that any reference to an element herein using names such as "first," "second," etc. does not generally limit the number or order of those elements. Rather, these are generally used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements can be used, nor does it mean that the first element must precede the second element in some way. Furthermore, unless otherwise specified, a group of elements includes one or more elements.
[0050] As used herein, the phrase "at least one of" followed by a list of items means that any one of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a system is described as including "at least one of A, B, and C," the system may include: A alone, B alone, and C alone; 2A, 2B, 2C, 3A; a combination of A and B, a combination of B and C, a combination of A and C; a combination of A, B, and C, a combination of 2A and C; a combination of A, 3B, and 2C; and so on.
Claims
1. A carrier chip for capturing biological cells, comprising: A silicon-on-insulator (SOI) structure, wherein the SOI structure comprises: top silicon layer; Bottom oxide (BOX) layer; a silicon substrate; and A plurality of wells, wherein each well of the plurality of wells is disposed partially in the top silicon layer and partially in the BOX layer, wherein a bottom surface of each well of the plurality of wells has optical reflective properties of a surface of the top silicon layer.
2. The carrier chip according to claim 1, wherein: The top silicon layer surface and the silicon substrate surface have substantially similar optical reflective properties.
3. The carrier chip according to claim 2, wherein: The substantially similar optical reflective properties of the top silicon layer surface and the bottom surface of each well of the plurality of wells are designed to provide image contrast between the well periphery and the periphery of cells therein of the plurality of wells.
4. The carrier chip according to claim 1, further comprising: A channel connects a first well among the plurality of wells and a second well among the plurality of wells, wherein the first well and the second well are located adjacent to each other.
5. The carrier chip according to claim 4, wherein: The channel is designed for chemical communication between at least a first cell in the first well and a second cell in the second well. The carrier chip according to claim 4 , wherein: The channel is designed for ionic communication between at least a first cell in the first well and a second cell in the second well.
7. The carrier chip according to claim 1, wherein: The well periphery may be either circular or polygonal.
8. The carrier chip according to claim 1, further comprising: An adhesion layer is located on a bottom surface of each of the plurality of wells.
9. The carrier chip according to claim 1, wherein: The top silicon layer is any one of epitaxial silicon and polysilicon.
10. A method for manufacturing a carrier chip for capturing cells, the method comprising: fabricating a silicon-on-insulator (SOI) structure comprising a top silicon layer, a bottom oxide (BOX) layer, and a silicon substrate; performing photolithographic formation of a plurality of wells, wherein each well of the plurality of wells is designed to capture at least one cell therein; etching the top silicon layer to form a plurality of wells; stripping the etching mask; and etching a BOX layer at a bottom of each of the plurality of wells, wherein each of the plurality of wells is disposed partially in the top silicon layer and partially in the BOX layer, and The bottom surface of each well in the plurality of wells has the optical reflection property of the surface of the top silicon layer.
11. The method according to claim 10, wherein: The top silicon layer surface and the silicon substrate surface have substantially similar optical reflective properties.
12. The method according to claim 11, wherein The substantially similar optical reflective properties of the top silicon layer surface and the bottom surface of each well in the plurality of wells are designed to provide image contrast between a well periphery and a cell periphery of the plurality of wells.
13. The method according to claim 10, further comprising: An etch hard mask is deposited, wherein the etch hard mask is used to perform photolithographic formation on the SOI structure.
14. The method according to claim 10, wherein: After performing the photolithographic formation and before etching the top silicon layer, the method further comprises: etching the hard mask; and Resist stripping is performed.
15. The method according to claim 10, wherein Etching the BOX layer further includes: A via is etched connecting a first well of the plurality of wells and a second well of the plurality of wells.
16. The method according to claim 15, wherein The channel is designed for chemical communication between at least a first cell in the first well and a second cell in the second well.
17. The method according to claim 15, wherein: The channel is designed for ionic communication between at least a first cell in the first well and a second cell in the second well.
18. The method according to claim 10, wherein The well periphery may be either circular or polygonal.
19. The method according to claim 10, further comprising: An adhesion layer is deposited on a bottom surface of each of the plurality of wells.
20. The method according to claim 10, wherein The top silicon layer is any one of epitaxial silicon and polysilicon.
21. A method for manufacturing a carrier chip for capturing cells, the method comprising: photolithographically forming in a semiconductor structure a plurality of wells, wherein each well of the plurality of wells is designed to capture at least one cell therein; etching the top silicon layer to form a plurality of wells; stripping the etching mask; and etching a bottom oxide (BOX) layer at a bottom surface of each of the plurality of wells, The semiconductor structure is a silicon-on-insulator (SOI) structure, and the SOI structure includes a top silicon layer, a BOX layer, and a silicon substrate. wherein each well of the plurality of wells is disposed partially in the top silicon layer and partially in the BOX layer, and The bottom surface of each well in the plurality of wells has substantially similar optical reflective properties to the top silicon layer.
22. The method according to claim 21, wherein The top silicon layer and the silicon substrate have substantially similar optical reflective properties.
23. The method according to claim 22, wherein The substantially similar optical reflective properties of the top silicon layer surface and the bottom surface of each well in the plurality of wells are designed to provide image contrast enabling determination of the periphery of each well and the periphery of the cell.
24. The method according to claim 22, wherein Before performing the photolithography forming, the method further includes: An etch hard mask is deposited.
25. The method according to claim 22, wherein After performing the photolithographic formation and before etching the top silicon layer, the method further comprises: etching the hard mask; and Resist stripping is performed.
26. The method according to claim 22, wherein Etching the BOX layer further includes: A via is etched connecting a first well of the plurality of wells and a second well of the plurality of wells.
27. The method according to claim 26, wherein The channel is designed for chemical communication between at least a first cell in the first well and a second cell in the second well.
28. The method according to claim 26, wherein The channel is designed for ionic communication between at least a first cell in the first well and a second cell in the second well.
29. The method according to claim 22, wherein The well periphery may be either circular or polygonal.
30. The method of claim 21, further comprising: An adhesion layer is deposited on a bottom surface of each of the plurality of wells.