Apparatus and method for reducing parasitic signal components of sigma-delta modulator

Abstract

A method for reducing parasitic signal components in an output signal (360) of a sigma-delta modulator (110) is described in which the output signal (360) is generated by processing a digital input signal (310) in a signal processing path (111) of the sigma-delta modulator (110). In this case, a digital dither signal (300) is provided in the form of a pseudo-random sequence consisting of non-binary digital words (301). Furthermore, an intermediate signal (331) generated by processing the digital input signal (310) in a signal processing path (111) of the sigma-delta modulator (110) is combined with the digital dither signal (300) in order to produce a modified intermediate signal (340). The output signal (360) is then generated by processing the modified intermediate signal (340) in a signal processing path (111) of the sigma-delta modulator (110).

Description

Technical Field

[0001] The present invention relates to a method and a device for reducing spurious signal components of a sigma-delta modulator, which appear as idle tones in the output signal of the sigma-delta modulator when limit cycles occur. . Background Art

[0002] Delta-sigma modulation is used to encode analog signals into digital signals, for example in analog-to-digital converters (ADCs). Furthermore, this method is also used within digital-to-analog converters (DACs) within the context of converting digital signals to analog signals, converting digital signals with a high bit count and low frequency into digital signals with a low bit count and higher frequency. Under certain conditions, so-called limit cycles can occur in sigma-delta modulation. This is a parasitic, yet inherent, characteristic of digital sigma-delta modulators (SDMs). These limit cycles produce undesirable spectral lines (idle tones) in the modulator's output spectrum. To prevent limit cycles, a dither signal can be used, generated using a binary pseudorandom sequence (PRBS) generator. However, for certain sigma-delta modulators, the PRBS generator can only reduce the amplitude of the parasitic interference frequencies to a certain extent. Summary of the Invention

[0003] The object of the present invention may be to improve the reduction of parasitic interference frequencies in a sigma-delta modulator.

[0004] This object is achieved by means of the respective subject matter of the independent claims. Advantageous configurations of the invention are the subject matter of the respective dependent claims.

[0005] According to a first aspect of the present invention, a method is provided for reducing parasitic signal components in an output signal of a sigma-delta modulator, wherein the output signal is generated by processing a digital input signal in a signal processing path of the sigma-delta modulator. A digital dither signal in the form of a pseudo-random sequence composed of a sigma-delta modulator, wherein an intermediate signal generated by processing a digital input signal in a signal processing path of a sigma-delta modulator is combined with the digital dither signal to produce a modified intermediate signal, and wherein the output signal is produced by processing the modified intermediate signal in the signal processing path of the sigma-delta modulator. By using a dither signal in the form of a non-binary dither sequence (i.e., a pseudo-random sequence composed of non-binary digital words), the amplitude of undesired idle tones can be particularly effectively reduced.

[0006] In one embodiment, a digital dither signal is generated in a dither signal generator by processing a fed-back digital sequence using a shift register comprised of a plurality of sequentially connected flip-flops. The memory content of at least one flip-flop, available at the output of the shift register, is logically linked to the memory content of another flip-flop of the shift register in order to respectively generate a new bit of the feedback sequence, and the newly generated bit of the feedback sequence is then coupled to an input of the shift register. This generates a pseudo-random sequence in a particularly advantageous manner.

[0007] In another embodiment, to generate the digital dither signal, a pseudo-random intermediate sequence consisting of digital words is first generated based on the feedback sequence. This pseudo-random intermediate sequence is then converted into a pseudo-random sequence forming the digital dither signal using a reference table, wherein each digital word of the intermediate sequence is individually assigned a non-binary digital value. This reference table allows such a sequence generated using one or more shift registers to be converted into a sequence specifically suitable for the respective application.

[0008] In another embodiment, the individual bits of the non-binary digital word forming the pseudo-random sequence of the digital dither signal are generated temporally sequentially using a shift register, which is operated at a multiple of the clock rate of the sigma-delta modulator. This allows for a particularly simple design of the shift register.

[0009] In another embodiment, a digital dither signal is generated using a dither signal generator comprising a shift register assembly comprising a plurality of shift registers and a plurality of logic gates, each logic gate being individually assigned to a shift register. Each bit of the non-binary digital word of the digital dither signal is generated by a shift register individually assigned to that bit. This significantly increases the speed of generating the non-binary digital word. Therefore, the clock rate of the dither signal generator can, in principle, be adapted to the clock rate of the sigma-delta modulator.

[0010] In another embodiment, the feedback sequence of the shift register is formed by logically linking the storage contents of two different flip-flops of the shift register assembly. By linking the signals from the different flip-flops of the shift register assembly in this way, the pseudo-random sequence of the resulting jitter signal can be matched to the respective application.

[0011] According to another aspect of the present invention, an apparatus for reducing spurious signal components in a digital output signal of a sigma-delta modulator includes a sigma-delta modulator having a signal processing path configured to generate an output signal from a digital input signal; a dither signal generator configured to generate a digital dither signal in the form of a pseudo-random sequence of non-binary digital words; and a signal combiner configured to generate a modified intermediate signal by combining an intermediate signal generated by processing the input digital signal in the signal processing path with the non-binary digital dither signal in the signal processing path of the sigma-delta modulator. The signal processing path of the sigma-delta modulator is configured to generate the output signal by processing the modified intermediate signal. This apparatus can particularly effectively reduce the amplitude of undesirable idle tones in the output signal of the sigma-delta modulator.

[0012] In one embodiment, the dither signal generator includes a shift register and a logic gate associated with the shift register, wherein the shift register is composed of a plurality of sequentially connected flip-flops, wherein a first input of the logic gate is connected to an output of a flip-flop associated with an output stage of the shift register, and a second input of the logic gate is connected to an output of another flip-flop of the shift register, and wherein the output of the logic gate is connected to an input of the associated shift register. This makes it possible to generate a suitable dither signal in a particularly simple manner.

[0013] In another embodiment, the dither signal generator includes a shift register assembly consisting of a plurality of shift registers arranged in parallel with one another and a plurality of logic gates, wherein each shift register has a plurality of flip-flops connected in series, and each logic gate is individually assigned to one of the shift registers, wherein the inputs of the shift registers are connected to the outputs of the logic gates respectively assigned to the shift registers, and wherein each shift register is configured to process a feedback sequence provided by the logic gates respectively assigned to the shift registers, and thereby generate bits for a digital word of the digital dither signal generated by the dither signal generator in the current operating cycle. This significantly increases the speed of generating non-binary digital words. Therefore, in principle, the clock rate of the dither signal generator can be adapted to the clock rate of the sigma-delta modulator.

[0014] In another embodiment, the inputs of the logic gates are each connected to the outputs of two different flip-flops of the shift register assembly, wherein at least one of the inputs of at least one logic gate is connected to the output of a flip-flop that is part of a shift register to which the corresponding logic gate is not assigned. This linking of the signals from the different flip-flops of the shift register assembly can improve the quality of the pseudo-random sequence of the resulting jitter signal.

[0015] In another embodiment, a first input of at least one logic gate is connected to the output of a flip-flop associated with an output stage of the shift register, while a second input of the corresponding logic gate is connected to the output of a flip-flop not associated with an output stage of the shift register. This measure is also suitable for improving the quality of the pseudo-random sequence of the resulting jitter signal.

[0016] Finally, in another embodiment, the device further comprises a reference device, wherein the reference device is designed to convert the pseudo-random intermediate sequence generated by the shift register assembly into a pseudo-random sequence forming the digital dither signal using a reference table. With the help of this reference table, even relatively simple sequences generated using one or more shift registers can be converted into a sequence that is particularly suitable for the respective application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be described in more detail below with reference to the accompanying drawings.

[0018] Figure 1 Schematically shows a device with a sigma-delta modulator and a specially constructed dither signal generator,

[0019] Figure 2 Schematically shown Figure 1 Another embodiment of the device of the present invention comprises a jitter signal generator using a reference table,

[0020] Figure 3 The structure of a simple dither signal generator is schematically shown. The dither signal generator has a single shift register and a logic gate.

[0021] Figure 4 The structure of a dither signal generator is schematically shown. The dither signal generator has parallel shift registers and three logic gates, each of which is assigned to a shift register.

[0022] Figure 5 FIG. 4 shows a schematic structure of another dither signal generator having four parallel shift registers and four logic gates, each of which is assigned to a shift register.

[0023] Figure 6 Graphs showing by way of example different spectra of an output signal having a sigma-delta modulator, and

[0024] Figure 7 The flow chart of the method is schematically shown. DETAILED DESCRIPTION

[0025] Figure 1 A simplified block diagram of a device 100 according to the present invention is shown, which includes a sigma-delta modulator 110 and a dither signal generator 200 associated with the sigma-delta modulator. The sigma-delta modulator 110 has a signal processing path 111, which includes a loop filter 120, a signal combiner 140, and a quantizer 150. The quantizer processes a digital input signal 310 applied to a signal input 112 of the sigma-delta modulator 110 into a digital output signal 360 provided via a signal output 113 of the sigma-delta modulator 110.

[0026] Independently of this, the dither signal generator 200 generates a digital dither signal 300 in the form of a pseudo-random sequence of non-binary digital words. The dither signal 300 provided at the signal output 250 of the dither signal generator 200 is combined in the signal processing path 111 of the Σ-Δ modulator 110 with the intermediate signal 330 provided by the loop filter 120 in the signal processing path 111, in the present case by adding the two digital signals 300, 330 with the aid of the signal combiner 140. The modified intermediate signal 340 obtained in this way is then further processed in the quantizer 150, and the result of this processing is finally provided in the form of an output signal 360 at the signal output 113 of the Σ-Δ modulator 110. Figure 1 As shown, output signal 360 is also coupled into the front part of signal processing path 111 via feedback path 170. In this example, feedback into loop filter 120 is implemented.

[0027] In order to effectively reduce the occurrence of limit cycles and idle tones, the dither signal generator 200 generates a non-binary dither signal 300 in the form of a sequence of non-binary digital words 301. This is preferably achieved by means of a suitable shift register assembly 201, which comprises at least one shift register 210 and a logic gate 230 assigned to the shift register, the shift register and the logic gate being connected to each other in a suitable manner. Such a shift register arrangement 201 is Figure 2 As shown in Figure 2 Show Figure 1Another embodiment of the device 100 in FIG. 1 is a further embodiment of the device 100 in FIG. 2 . Here, the pseudo-random signal generated by the shift register component 201 can be used directly as the dither signal 300. However, as an alternative to this, the dither signal generator 200 can also have a reference device 240, which converts the intermediate signal 305 generated by the shift register component 201 into the actual dither signal 300 by means of a reference table or lookup table 241. For this purpose, each digital word 306 of the pseudo-random intermediate signal 305 generated by the shift register component 201 is assigned a corresponding digital word 301 of the dither signal 300. Such a reference device 240 is used in Figure 2 It is shown as an example in FIG.

[0028] As from Figure 2 As can also be seen in FIG, the loop filter 120 of the Σ-Δ modulator 110 can in principle comprise a plurality of integrators 121, 122 connected in series. In the present exemplary embodiment, the output signal 360 is coupled into each of the two integrators 121, 122 via the feedback path 170, wherein the first integrator 121 integrates the difference between the input signal 310 and the feedback sequence 303 generated from the output signal 360, and the second integrator 122 integrates the difference between the signal 320 resulting from the first integration and the feedback sequence 303. Furthermore, in the present case, the dither signal 300 is combined with the intermediate signal 330 provided by the second integrator 122. Figure 2 1 , a delay stage 160 can also be provided at the end of the signal processing path 111. By means of the delay stage 160 (which in this example comprises a flip-flop), the time relationship between the output signal 360 and the signals 310, 320, 330 present in the signal processing path 111 can be adjusted.

[0029] In order to minimize the interference signal components in the output signal 360 of the Σ-Δ modulator 110, it is necessary to generate a digital dither signal 300 in the form of a suitable pseudo-random sequence composed of non-binary digital words 301. The pseudo-random sequence should have a repetition cycle that is as long as possible, i.e., a duration after which the bits of the pseudo-random sequence repeat. To achieve this, a suitable shift register assembly 201 is used, which includes one or more shift registers 210j and a corresponding number of logic gates 230j, each of which is individually assigned to one of the shift registers 210j and is suitably connected to the shift register 210j.

[0030] to this end, Figure 3First, a shift register assembly 201 is shown, which has a single shift register 210 and an associated logic gate 230. In this example, the shift register 210 comprises a total of twenty flip-flops 2201 to 2202 connected in series. 20 , where the first seventeen flip-flops 2201 to 220 17 The processing stage 213 of the shift register 210 is formed, and the last three flip-flops 220 18 to 220 20 Forming the output stage 214 of the shift register 210. Figure 3 As can be seen in FIG. 2 , the associated logic gate 230 (which is designed in the present example as an XOR gate) is connected with its first signal input 231 to the last flip-flop 220 of the shift register 210. 20 and is connected to the trigger 220 assigned to the processing stage 213 by means of its second signal input 232. 17 . In addition, the output of the logic gate 233 is connected to the input 211 of the shift register 210. Therefore, the output signal of the logic gate 230 forms a feedback sequence 303 for the associated shift register 210. The special connection of the shift register 210 and the associated logic gate 230 described here can generate a particularly suitable pseudo-random signal, which is particularly distinguished by a very long repetition cycle. The output signal 305 provided at the output 212 of the shift register 210 is a pseudo-random bit sequence, which is divided into non-binary digital words with a length of a plurality of bits. Here, in this example, three bits 302 are respectively formed. n 、307 n If, as in the present case, the shift register arrangement 201 generates only one bit 302 per clock, n 、307 n , the internal clock rate of the shift register assembly must correspond to three times the clock rate of the Σ-Δ modulator 110. In principle, by means of Figure 3 The shift register component 201 of the conceptual design shown can also generate non-binary digital words having a length of two, four or more bits, wherein the clock rate of the dither signal generator 200 is then adjusted accordingly.

[0031] Furthermore, a shift register assembly having a plurality of parallel shift registers can also be used in order to generate the desired pseudo-random sequence consisting of non-binary digital words. Depending on the application, an arrangement in which, for a portion of the shift registers, a feedback sequence is generated from the storage contents of flip-flops from respectively different shift registers of the corresponding shift register assembly can also be advantageous. For this purpose, Figure 4 1 shows an exemplary embodiment of such a shift register assembly 201, which comprises a total of three shift registers 2101, 2102, 2103 extending in parallel with one another. In this example, the first shift register 2101 consists of flip-flops 2201 to 2207 connected in series, and the second shift register 2102 consists of flip-flops 2208 to 2209 connected in series. 14 The third shift register 2103 is composed of flip-flops 220 connected in series. 15 to 220 20 Here, the corresponding last trigger 2207, 220 14 and 220 20 The output stage 214 of the three shift registers 2101, 2102, and 2103 is formed. Figure 4 As can be seen in FIG, each shift register 2101, 2102, 2103 is assigned a logic gate 2301, 2302, 2303, which generates a feedback sequence 303 for the corresponding shift register 2101, 2102, 2103. Here, the signal input of each logic gate 2301, 2302, 2303 is connected to the signal output of two different flip-flops of the three shift registers 2101, 2102, 2103. Preferably, in each logic gate, the first signal input is connected to the flip-flops 2207, 2208 of the output stage 214 assigned to the shift register 2101, 2102, 2103. 14 and 220 20 The second signal input of the corresponding logic gate is connected to the trigger 2206, 220 of the processing stage 213 assigned to the shift register 2101, 2102, 2103. 13 and 220 19 In this example, the signal input terminal of the first logic gate 2301 is connected to the two triggers 220 of the second shift register 2102. 13 , 220 14 The output end of the second logic gate 2302 is connected to the signal input end of the second logic gate 2302 and the two triggers 220 of the third shift register 2103. 19 , 220 20, and the signal input of the third logic gate 2303 is connected to the signal outputs of the two flip-flops 2206 and 2207 of the first shift register 2101. In principle, the assignment of the inputs of the individual logic gates to the outputs of the flip-flops can vary depending on the application. Thus, for example, the signal inputs of one or more logic gates of the shift register assembly 201 can be connected to the signal outputs of flip-flops from two different shift registers.

[0032] As from Figure 4 As can also be seen in FIG, each of the three shift registers 2101, 2102, 2103 of the shift register assembly 201 generates a current digital word 301 of the dither signal 300 or of an intermediate sequence 305 preceding the dither signal 300. m 、306 m A single bit 302 n 、307 n Since each digital word in this case consists of 3 bits 302 n 、307 n The shift register component 201 shown here is formed, therefore, to operate at the same clock as the associated sigma-delta modulator 110 .

[0033] Figure 5 The present invention shows, by way of example, a dither signal generator 200 for generating a pseudo-random sequence in parallel consisting of digital words each having a length of four bits. The dither signal generator 200 includes a shift register assembly 201, which comprises a total of four shift registers 2101, 2102, 2103, and 2104 extending in parallel with one another, and four logic gates 2301, 2302, 2303, and 2304, each of which is individually assigned to one of the shift registers 2101, 2102, 2103, and 2104. In this example, a signal input of the first logic gate 2301 is connected to a flip-flop 220 of the fourth shift register 2104. 20 , and the other signal input terminal of the first logic gate 2301 is connected to the signal output terminal of the flip-flop 2205 of the first shift register 2101. In addition, one signal input terminal of the second logic gate 2302 is connected to the signal output terminal of the flip-flop 2204 of the first shift register 2101, and the other signal input terminal of the second logic gate 2302 is connected to the signal output terminal of the flip-flop 2205 of the second shift register 2102. 10 In addition, one signal input terminal of the third logic gate 2303 is connected to the signal output terminal of the trigger 2209 of the second shift register 2102, and the other signal input terminal of the third logic gate 2303 is connected to the signal output terminal of the trigger 2209 of the third shift register 2103.15 Finally, a signal input terminal of the fourth logic gate 2304 is connected to the trigger 220 of the third shift register 2103. 14 The other signal input terminal of the fourth logic gate 2304 is connected to the trigger 220 of the fourth shift register 2104. 20 signal output terminal of the .

[0034] To illustrate the effectiveness of the method described here, Figure 6 By way of example, a graph shows the spectra of output signals of a sigma-delta modulator in three different configurations, each with the same power and each having an idle tone of varying intensity. To facilitate comparison of the spectra, the dither signals used to generate the output signals also have the same power / variance. Curve 410 shows the spectrum of the output signal of the sigma-delta modulator, in which a binary dither signal is used to reduce the idle tone. At frequency f R In the case of , the spectrum 410 shows a spurious signal component (idle tone) with a relatively high peak 411. The second curve 420 is the spectrum of the output signal of the same Σ-Δ modulator, in which white noise is used to reduce the idle tone. It can be seen here that in the second spectrum 420, at the frequency f R In the case of , the parasitic signal components are reduced to a slightly greater extent. The third curve 430 is the spectrum of the output signal of the same Σ-Δ modulator, in which the non-binary dither signal is combined with the intermediate signal. This third curve shows that at the frequency f R In the case of , the parasitic signal components are reduced to a very great extent. In the present case, a sequence of 4-bit digital words is used as the dither signal, which sequence is generated by means of a shift register assembly comprising 26 flip-flops.

[0035] Figure 7A simplified flow chart of the method 500 described herein is shown. In a first step 510, a digital input signal 310 is provided at the input of the sigma-delta modulator 110. In a further method step 520, a digital dither signal 300 is generated in the dither signal generator 200 in the form of a pseudo-random sequence of non-binary digital words. To this end, in method step 521, a feedback sequence is first generated by logically linking the bits applied to the outputs of different flip-flops of a shift register assembly comprising at least one shift register. In method step 522, the fed-back digital sequence is processed by means of the associated shift register. This generates a non-binary dither signal, which is provided at the signal output 250 of the dither signal generator 200. In method step 530, the input signal 310 processed in the signal processing path of the sigma-delta modulator 110 is combined with the non-binary dither signal 300 generated by the dither signal generator 200 to generate a modified intermediate signal 340. In method step 540 , the modified intermediate signal 340 is processed in order to generate the digital output signal 360 . In method step 550 , the digital output signal is provided at the output of the Σ-Δ modulator 110 .

[0036] A conventional PRBS generator consists of a shift register with linear feedback of logic gates, wherein only a single bit is calculated in each clock cycle and the register is then shifted by only one position. This results in a seemingly random (pseudo-random) but deterministic binary sequence. The concept described here uses such a pseudo-random and deterministic binary sequence to suppress limit cycles and the idle tones associated therewith. Instead of calculating only one new bit in each clock cycle and then shifting the register by only one position, the next N bits can also be calculated in one clock cycle of the Σ-Δ modulator and the shift register can be shifted by N positions. In this case, a number consisting of N bits is generated in each clock cycle of the Σ-Δ modulator and thus 2 n possible states. The probability of a state being adopted is the same for all states. This seemingly random digital word can then be used with the aid of a reference table to generate a non-binary dither signal. Such a non-binary dither signal can more effectively reduce or prevent limit cycles in the sigma-delta modulator.

[0037] Although the present invention is described in more detail by way of preferred embodiments, the present invention is not limited to the disclosed examples. More specifically, those skilled in the art can also deduce other variations therefrom without departing from the scope of protection of the present invention.

Claims

1. A method for reducing parasitic signal components in an output signal (360) of a sigma-delta modulator (110), wherein: The output signal (360) is generated by processing a digital input signal (310) in a signal processing path (111) of the sigma-delta modulator (110), wherein a digital dithering signal (300) is provided in the form of a pseudo-random sequence of non-binary digital words (301), wherein an intermediate signal (331) generated by processing the digital input signal (310) in a signal processing path (111) of the Σ-Δ modulator (110) is combined with the digital dither signal (300) to produce a modified intermediate signal (340), and wherein the output signal (360) is produced by processing the modified intermediate signal (340) in the signal processing path (111) of the Σ-Δ modulator (110).

2. The method according to claim 1, in, By using a plurality of triggers connected in series (220 k ) composed of a shift register (210 j ) processes the feedback sequence (303), generates the digital dithering signal (300) in the dithering signal generator (200), Wherein, at least one trigger (220 k ) provided at the output terminal (212) of the shift register (210) and the storage content of the shift register (210) j ) of another trigger (220 k ) are logically associated with the storage contents of the shift register (210) so as to respectively generate new bits of the feedback sequence (303), and wherein the respectively newly generated bits of the feedback sequence (303) are coupled to be input into the shift register (210 j ) in the input terminal (211).

3. The method according to any one of the preceding claims, in, In order to generate the digital dither signal (300), first, a pseudo-random intermediate sequence (305) consisting of digital words (306) is generated based on the feedback sequence (303), and then, the pseudo-random intermediate sequence is converted into a pseudo-random sequence forming the digital dither signal (300) with the help of a reference table (241), wherein the reference table individually assigns a non-binary digital value to each digital word (306) of the intermediate sequence (305).

4. The method according to any one of the preceding claims, in, The shift register (210j) is used to sequentially generate the respective bits (302) of the non-binary digital word (301) of the pseudo-random sequence forming the digital jitter signal (300) in time. n ), running the shift register at a multiple of the clock rate of the Σ-Δ modulator (110).

5. The method according to any one of claims 1 to 3, wherein The digital jitter signal (300) is generated by means of a jitter signal generator (200), wherein the jitter signal generator comprises a shift register component (201), wherein the shift register component comprises a plurality of shift registers (210 j ) and multiple logic gates (230 j ), the logic gate is individually assigned to the shift register (210 j ), wherein each bit (302) of the non-binary digital word (301) of the digital dithering signal (300) n ) are respectively assigned to the bit (302 n ) is generated by the shift register (210j).

6. The method according to claim 5, wherein: By connecting two different flip-flops (220 k ) are logically associated to form shift registers (210 j ) feedback sequence (303).

7. A device (100) for reducing spurious signal components in a digital output signal (360) of a sigma-delta modulator (110), the device comprising: a sigma-delta modulator (110) having a signal processing path (111), the sigma-delta modulator being configured to generate an output signal (360) from a digital input signal (310), a dither signal generator (200) configured to generate a digital dither signal (300) in the form of a pseudo-random sequence of non-binary digital words (301), and a signal combiner (140) configured to generate a modified intermediate signal (340) by combining an intermediate signal (330) generated by processing the input digital signal (310) in the signal processing path (111) with a non-binary digital word dither signal (300) in the signal processing path (111) of the Σ-Δ modulator (110), wherein the signal processing path (111) of the Σ-Δ modulator (110) is configured to generate the output signal (360) by processing the modified intermediate signal (340).

8. The device according to claim 7, in, The jitter signal generator (200) includes a shift register (210 j ) and the shift register (210 j ) logic gate (230 j ), the shift register (210 j ) consists of a plurality of triggers connected in series (220 k ), wherein the logic gate (230 j ) is connected to the first input terminal (231) of the shift register (210 j ) of the output stage (214) of the trigger (220 k ) on the output terminal (221), and the logic gate (230 j ) is connected to the second input terminal (232) of the shift register (210 j ) on the output terminal (221) of another flip-flop (220k), and wherein the logic gate (230 j ) output terminal (233) and the associated shift register (210 j ) is connected to the input terminal (211).

9. The device (100) according to claim 7 or 8, in, The jitter signal generator (200) comprises a shift register component (201) which is composed of a plurality of shift registers (210) arranged in parallel with each other. j ) and multiple logic gates (230 j ), wherein the shift registers each have a plurality of triggers (220 k ), the logic gates are individually assigned to the shift register (210 j ) in a shift register, Among them, the shift register (210 j ) input terminal (211 j ) are respectively attached to the shift registers (210 j ) logic gate (230 j ) at the output terminal (233), and Among them, each shift register (210 j ) is configured to process the logic gates (230) respectively assigned to the shift registers. j ) separately provided feedback sequence (303), and in this case respectively generates bits (302) for the digital word (301) of the digital jitter signal (300) generated by the jitter signal generator (200) in the current working cycle n ).

10. The device (100) according to claim 9, wherein The logic gate (230 j ) are respectively attached to two different triggers (220 k ) at the output end (221), Wherein, at least one logic gate (230 j At least one of the input terminals (231, 232) of the trigger (220) is attached to the trigger (220 k ) output terminal (221): the trigger is a shift register (210 j ) part, the corresponding logic gate (230 j ) does not belong to the shift register.

11. The device (100) according to claim 10, wherein At least one logic gate (230 j ) is connected to the first input terminal (231) of the shift register (210 j ) of the output stage (214) of the trigger (220 k ) output terminal (221), and the corresponding logic gate (230 j ) is connected to a second input terminal (232) not associated with the shift register (210 j ) of the output stage (214) of the trigger (210 k ) on the output end (211).

12. The device (100) according to any one of claims 6 to 11, further comprising a reference device (240), wherein: The reference device is designed to convert, by means of a reference table (241), a pseudo-random intermediate sequence (305) generated by the shift register component (201) into a pseudo-random sequence forming the digital dither signal (300).

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