Sensing device, molecular entity sensing device and method for measuring current

Abstract

A sensing device, a molecular entity sensing device, and a method of measuring current are provided. The sensing arrangement comprises: a sensor device comprising an array of sensor elements, each sensor element being arranged to output a current dependent on an interaction at a respective sensor element; a detection circuit comprising a plurality of current measurement devices, where each current measurement device is configured to measure a current output by one or more of the sensor elements and to provide an output signal dependent on the current output by one or more of the sensor elements; wherein the sensing arrangement is configured to reset the plurality of current measurement devices at a start of each of a plurality of sensing frames such that an output of each of the current measurement devices is isolated from the array of sensor elements at least during a reset period.

Description

[0001] This invention is a divisional application of the invention patent application with the application date of February 4, 2020, application number 202080022571.9, and the invention name of "Current measuring device, molecular entity sensing device, method for measuring current, method for sensing molecular entity". Technical Field

[0002] The present invention relates to measuring small electric currents with high sensitivity, particularly but not exclusively in the context of sensing molecular entities, for example through interactions between molecular entities and nanopore sensors. Background Art

[0003] It is known to use nanopore sensors comprising membrane proteins inserted into an amphiphilic membrane to sense molecular entities. The interaction between the molecular entity and the membrane protein can result in a property modulation of the electrical signal appearing across the amphiphilic membrane. For example, the ionic current flowing through the membrane protein acting as a protein pore can be modulated by the interaction. By monitoring the electrical signal appearing across the amphiphilic membrane, the property modulation can be detected and the molecular entity can thereby be sensed. Various technologies based on this principle have been proposed, one example being disclosed in WO-2008 / 102120.

[0004] Sensing molecular entities using nanopore sensors provides a method for identifying individual molecules and molecular entities. There are a wide range of possible applications, such as sequencing DNA or other nucleic acids; sensing chemical or biological molecules for security and defense; detecting biomarkers for diagnostics; screening ion channels for drug development; and label-free analysis of interactions between biomolecules.

[0005] For DNA sequencing, the detected current is typically in the range of 20 pA to 100 pA, and in the case of an open pore, the current is in the range of 50 pA to 500 pA. Electronic detection of such currents is challenging. A multichannel device combined with a sensor array can be used. Such a device can be implemented using an application-specific integrated circuit (ASIC).

[0006] Sensitive current measurement is also required in other applications. For example, medical X-ray detectors are known that detect the charge generated by X-ray quanta in direct and indirect conversion materials. Such detectors also typically use ASICs, and the minimum charge detection level can be around 10,000 electrons, of which about 1,000 electrons are RMS noise. X-ray detectors can operate by accumulating charge on capacitors. For example, the charge can be accumulated over a period of a few milliseconds. The accumulated charge can be read out into a charge amplifier within a few microseconds. In this type of configuration, the current level is therefore in the nanoampere region. X-ray detectors that employ thousands of sensing channels are known.

[0007] The charge levels achieved in known nanopore sequencing applications are similar to those achieved in known X-ray detectors. Similar noise levels are also required, typically corresponding to a current noise of approximately 2 pA RMS at 10 kHz sampling.

[0008] Figure 1 An example current measurement apparatus is shown, which is configured to measure current flowing through a nanopore. A corresponding arrangement, adapted where appropriate, may be provided for use with a medical X-ray detector or other charge or current measuring device.

[0009] The example device includes a charge integrating amplifier 102 (which may also be referred to as a charge amplifier) that functions to integrate the charge flowing through the nanopore represented by resistor 101. A 50 pA current will generate a voltage of approximately 50 mV within 100 microseconds, with the component values shown in the figure. After 100 microseconds, the integrating capacitor ( Figure 1 A switch (not shown) on the 100 fF capacitor in the circuit resets the circuit. Figure 2 It is schematically shown how the voltage output rises over time during the integration process.

[0010] The inherent noise performance can be roughly analyzed as follows. Figure 3 Shown Figure 1 The main noise source in the device. Resistor R PORE (with resistance R PORE ) represents the resistance of the nanopore. The noise in the resistor is represented by V NPORE Indicates. R PORE Typically will be in the range of 3 GOhm to 20 GOhm or higher and will produce Proportional white noise V NPORE , where k B is Boltzmann's constant, and T is the temperature. The amplifier noise source is shown as V NAMP , and for a CMOS integrated amplifier, at 1 Hz it will typically be about , down to the white noise floor above 100 kHz The important component is the capacitance of the amphiphilic membrane (which can be a lipid bilayer), which is labeled C BL . C BL is relatively large, typically about 30 pF. Finally, the electrode resistance R ELE and the associated noise V NELE . R ELE The value of may typically be around 4 kOhm.

[0011] Although the nanopore resistance RPORE Very high, but it passes through the capacitor C BL is heavily filtered and, except at very low frequencies, its contribution to the overall RMS noise is negligible. NAMP and electrode resistance noise V NELE is the main contribution, because it is amplified by the capacitance C BL and the capacitance C of the integrating capacitor FB Typically, this ratio is about 300. The RMS current noise under these conditions is about 5 pA RMS, which is relatively high. The RMS current noise can be reduced by applying known filtering techniques. For example, by Figure 3 By applying correlated double sampling (CDS) and low-pass (LP) filtering, it is possible to reduce the noise level to approximately 1.4 pA, which is acceptable for many applications, including detecting biomolecules in nanopores. Correlated double sampling acts as a high-pass filter, thus combining to form a bandpass filter at the sampling rate (or integration period) of the circuit.

[0012] Known circuitry, particularly sensing circuitry or those used to implement the noise reduction techniques discussed above, can undesirably increase power consumption and require additional heat dissipation. This can limit practical applications, particularly where large arrays of circuitry are required to provide high throughput and / or where implementation in a small and / or battery-powered device is desired. Summary of the Invention

[0013] It is an object of the present invention to at least partially address one or more of the problems discussed above.

[0014] According to one aspect, a current measuring device is provided, comprising: a first charge amplifier configured to integrate a current to be measured; a processing circuit configured to filter an output from the first charge amplifier using a first low-pass filter module and a second low-pass filter module; and a second charge amplifier configured to integrate a current originating from a filtered output from the first charge amplifier, wherein: the device is configured to reset the first charge amplifier at the beginning of each of a plurality of sensing frames; the processing circuit is configured to obtain at least a first sample of the output from the first charge amplifier within each sensing frame; and the sampling of the first sample alternates from one sensing frame to the next between sampling through the first low-pass filter module and sampling through the second low-pass filter module.

[0015] Alternating sampling from one sensing frame to the next avoids the need for a buffer, thereby allowing the circuitry to be implemented with fewer amplifiers. This helps save power and / or limit heat dissipation without compromising noise suppression performance.

[0016] In one embodiment, the first low-pass filter module includes a first RC filter, and the second low-pass filter module includes a second RC filter. During each sensing frame in which sampling of a first sample is not performed by the first low-pass filter module, the first sample from the previous sensing frame is stored in the form of charge on a capacitive component of the first RC filter; and during each sensing frame in which sampling of the first sample is not performed by the second low-pass filter module, the first sample from the previous sensing frame is stored in the form of charge on a capacitive component of the second RC filter. The capacitive component of the first RC filter includes a first plurality of capacitors, and during each sensing frame in which sampling of the first sample is performed by the first low-pass filter module, charge representing information about the current to be measured is sampled by sampling only a selected subset of the first plurality of capacitors to apply selected attenuation to charge representing information about the current to be measured; and the capacitive component of the second RC filter includes a second plurality of capacitors, and during each sensing frame in which sampling of the first sample is performed by the second low-pass filter module, charge representing information about the current to be measured is sampled by sampling only a selected subset of the second plurality of capacitors to apply selected attenuation to charge representing information about the current to be measured.

[0017] Thus, a circuit system is provided that allows selective attenuation to be applied without requiring an amplifier or introducing additional noise sources. This may facilitate power conservation and / or limit heat dissipation.

[0018] In one embodiment, a first sample and a second sample of the output of the first charge amplifier are obtained within each sensing frame, and the processing circuit is configured to perform correlated double sampling using the first sample and the second sample. The processing circuit further includes at least one additional low-pass filter module; and the device is configured to sample the second sample through the at least one additional low-pass filter module.

[0019] In one embodiment, the at least one further low-pass filter module consists of one further low-pass filter module; and the device is configured such that sampling of the second samples is performed only through the further low-pass filter module for all sensing frames.

[0020] Implementing correlated double sampling using only a single further low-pass filter module reduces the silicon area requirement relative to an arrangement providing a plurality of separate further low-pass filter modules.

[0021] In one embodiment, within each sensing frame in which each of the first, second, and additional low-pass filter modules obtains a sample, the corresponding low-pass filter module is reset. The low-pass filter module reset is performed by bypassing the resistive component of the RC filter of each low-pass filter module. The reset of each low-pass filter module is timed so that each of the first and second samples is sampled at an equal time after the reset of the low-pass filter module that samples the sample.

[0022] This approach means that the first sample is obtained at exactly the same point during the settling of the low pass filter module as the second sample, which means that any effects of settling are the same for both samples and cancel out when the difference between the samples is obtained as part of the correlated double sampling procedure.

[0023] In one embodiment, the at least one additional low-pass filter module includes a third low-pass filter module and a fourth low-pass filter module, and the device is configured such that sampling of the second sample alternates from one sensing frame to the next sensing frame between sampling by the third low-pass filter module and sampling by the fourth low-pass filter module.

[0024] This approach allows correlated double sampling to be implemented using relatively simple circuit timing.

[0025] In one embodiment, the first charge amplifier is configured such that integration of current is performed simultaneously across the first capacitive element and the second capacitive element, and resetting the first charge amplifier is performed by allowing charge stored on the second capacitive element to flow into the first capacitive element and at least partially offset the charge stored on the first capacitive element.

[0026] This charge-balancing soft reset method facilitates the reduction of low-frequency noise, such as that which may be generated by noise folding. It also allows integration of the input signal to be performed with minimal or no interruption, allowing the circuit to react to events occurring during the reset period that would otherwise be undetected. Furthermore, the method can eliminate the need for correlated double sampling, thereby providing the charge amplifier with more time to stabilize (e.g., throughout the sensing frame), which means that amplifier bandwidth and bias current can be reduced, thereby reducing power consumption.

[0027] According to one aspect, a current measuring device is provided, comprising: a first charge amplifier configured to integrate a current to be measured; a processing circuit configured to filter an output from the first charge amplifier; and a second charge amplifier configured to integrate a current originating from a filtered output from the first charge amplifier, wherein: the first charge amplifier is configured such that the integration of the current is performed simultaneously across a first capacitive element and a second capacitive element, and the resetting of the first charge amplifier is performed by allowing charge stored on the second capacitive element to flow to the first capacitive element and at least partially offset the charge stored on the first capacitive element.

[0028] According to one aspect, a current measuring device is provided, comprising: a first charge amplifier configured to integrate a current to be measured; a processing circuit configured to filter an output from the first charge amplifier; and a second charge amplifier configured to integrate a current originating from the filtered output from the first charge amplifier, wherein: the processing circuit is configured such that information about the current to be measured is propagated from the first charge amplifier to the second charge amplifier through the processing circuit in the form of an amount of charge representing the current to be measured.

[0029] According to one aspect, a method for measuring current is provided, the method comprising: integrating a current to be measured using a first charge amplifier; filtering an output from the first charge amplifier using a first low-pass filter module and a second low-pass filter module; and integrating a current originating from the filtered output from the first charge amplifier using a second charge amplifier, wherein: the first charge amplifier is reset at the beginning of each of a plurality of sensing frames; at least a first sample of the output from the first charge amplifier is obtained within each sensing frame; and the sampling of the first sample alternates from one sensing frame to the next between sampling by the first low-pass filter module and sampling by the second low-pass filter module.

[0030] According to one aspect, a method for measuring current is provided, the method comprising: integrating a current to be measured using a first charge amplifier; filtering an output from the first charge amplifier; and integrating a current originating from the filtered output from the first charge amplifier using a second charge amplifier, wherein: the integration of the current by the first charge amplifier is performed simultaneously across a first capacitive element and a second capacitive element, and the resetting of the first charge amplifier is performed by allowing charge stored on the second capacitive element to flow to the first capacitive element and at least partially offset the charge stored on the first capacitive element.

[0031] According to one aspect, a method of measuring current is provided, the method comprising: integrating a current to be measured using a first charge amplifier; filtering an output from the first charge amplifier using a processing circuit; and integrating a current derived from the filtered output from the first charge amplifier using a second charge amplifier, wherein: the processing circuit is configured such that information about the current to be measured is propagated from the first charge amplifier to the second charge amplifier through the processing circuit in the form of an amount of charge representing the current to be measured.

[0032] According to one aspect, a sensing apparatus is provided, comprising: a sensor device comprising an array of sensor elements, each sensor element being arranged to output a current that depends on an interaction at the corresponding sensor element; a detection circuit comprising a plurality of current measuring devices, wherein each current measuring device is configured to measure a current output by one or more of the sensor elements and to provide an output signal that depends on the current output by one or more of the sensor elements; wherein the sensing apparatus is configured to reset the plurality of current measuring devices at the beginning of each of a plurality of sensing frames, such that, at least during a reset period, the output of each of the current measuring devices is isolated from the array of sensor elements.

[0033] According to one aspect, a sensing device is provided, comprising: a sensor device comprising an array of sensor elements, the array of sensor elements comprising a first sensor element, each sensor element in the array being arranged to output a current that depends on an interaction at the corresponding sensor element; and a detection circuit comprising a plurality of detection channels, each detection channel having a current measuring device, wherein each current measuring device is configured to measure a current output by one or more of the sensor elements and to provide an output that depends on the current output by one or more of the sensor elements, the plurality of detection channels comprising a first detection channel having a first current measuring device, wherein the sensing device is configured to isolate a first current measuring device from a first sensor element in the array of sensor elements coupled to the first detection channel in the event of a fault in the first sensor element so as to prevent or reduce interference in the plurality of detection channels caused by the first detection channel of the plurality of detection channels.

[0034] According to one aspect, a molecular entity sensing device is provided, comprising the sensing device as described above, wherein the interaction is an interaction between a molecular entity and a corresponding sensor element.

[0035] According to one aspect, a method for measuring current is provided, comprising: outputting a current that depends on interactions at sensor elements in an array of sensor elements; measuring the output current using a first current measuring device and providing an output signal that depends on the output current; and isolating the output of the first current measuring device from the array of sensor elements during a reset period. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figures 1 to 3 Having been described above, embodiments of the invention will now be described, by way of example only, with reference to the remaining drawings, in which corresponding reference numerals indicate corresponding parts, and in which:

[0037] Figure 4 Describes the use Figure 1 Example prior art signal processing chain for circuit measuring current;

[0038] Figure 5 depicts an example current measurement device;

[0039] Figure 6 Depicts an example of a low-pass filter without an amplifier;

[0040] Figure 7 Depicts the operation Figure 5 Timing diagram of a low-pass filter without an amplifier;

[0041] Figure 8 Depicts Figure 5 a portion of a current measurement device adapted to perform correlated double sampling;

[0042] Figure 9 Depicts the operation Figure 8 Timing diagram of the current measuring device;

[0043] Figure 10 Depicts Figure 8 A variant of a current measuring device requiring fewer different low-pass filter modules;

[0044] Figure 11 Depicts the operation Figure 10 Timing diagram of the current measuring device;

[0045] Figure 12-15 is a schematic diagram depicting the origin of residual correlated double sampling noise and how to avoid the same by extracting a first sample and a second sample at equal times after a reset operation;

[0046] Figure 16 depicts an arrangement in which a SAR ADC is provided after a second charge amplifier to provide a digital output signal;

[0047] Figure 17 Depicts Figure 16 An example of an arrangement based on an alternative to a multi-slope ADC;

[0048] Figure 18 depicts an example architecture for implementing readout from multiple channels in a matrix array;

[0049] Figure 19 depicts a charge amplifier in a configuration suitable for detecting small currents from a sensor;

[0050] Figure 20 Depicts the operation Figure 19 Timing diagram of the circuit;

[0051] Figure 21 Depicts Figure 19 Combination of a charge amplifier and sensor of the type depicted in;

[0052] Figure 22 depicts an example arrangement for implementing a charge balancing soft reset;

[0053] Figure 23 Depicts Figure 22 A variation of the arrangement in which the use of a buffer amplifier reduces the loading of the operational amplifier;

[0054] Figure 24depicts a test circuit for selectively implementing a hard reset mode and a charge balancing soft reset mode;

[0055] Figure 25 Will use Figure 24 A graph comparing the noise of the two reset modes obtained by the test circuit;

[0056] Figure 26 is a schematic diagram illustrating how to reduce switching noise using the charge balancing soft reset mode;

[0057] Figure 27 Depicts the corresponding Figure 8 a portion of the current measuring device adapted for a charge balancing soft reset mode;

[0058] Figure 28 Depicts the operation Figure 27 Timing diagram of the current measuring device;

[0059] Figure 29 Depicts Figure 27 a variation of the arrangement in which only a single pair of resistor elements is used instead of two pairs of resistor elements to implement the two low-pass filter modules;

[0060] Figure 30 Depicts Figure 27 and 29 a variation of the arrangement in which separate resistor elements are not used to implement the two low-pass filter modules;

[0061] Figure 31 A molecular sensing device is depicted; and

[0062] Figure 32 Depicts Figure 31 An example sensor arrangement of a molecular sensing device. DETAILED DESCRIPTION

[0063] Figure 4 Describes the use Figure 1An example of a circuit for measuring current in a prior art signal processing chain. The signal processing chain is configured to measure current in an array of cells. Each cell can be referred to as a pixel. The pixels can be arranged in columns and rows. Noise reduction is implemented using correlated double sampling (CDS) and a low-pass (LP) filter. At point 150, the current to be measured is input to a charge amplifier 102. The output from charge amplifier 102 is input to an RC filter 103 (acting as an LP filter). An RC filter buffer 104 is provided between charge amplifier 102 and a CDS amplifier with a second-stage gain 105. The output from the CDS amplifier with a second-stage gain 105 is input to a pixel sample and hold buffer 106. Pixel sample and hold buffer 106 temporarily stores a certain amount of charge representing the measured current before the pixel can be read out. A row multiplexing system 107 is provided for performing row multiplexing. The output from the row multiplexing system 107 is input to a column sample and hold buffer 108. A column multiplexing system 109 is provided for performing column multiplexing. The output from column multiplexing system 109 is input to analog-to-digital converter (ADC) data buffer 110. The output from ADC data buffer 110 is input to successive approximation register (SAR) ADC 111 (including digital-to-analog converter (DAC) 112 and comparator 113).

[0064] Figure 4 The arrangement includes six amplifiers and one comparator (within the SAR ADC 111) for various configurations. Embodiments of the present disclosure reduce power consumption by providing an arrangement that allows the current measurement device 200 to be implemented with fewer amplifiers.

[0065] Figure 5 An example current measurement device 200 is depicted. The current measurement device 200 includes a first charge amplifier 201 configured to integrate the current to be measured (input at point 250). Processing circuitry is provided that filters the output from the first charge amplifier 201. A second charge amplifier 202 integrates the current derived from the filtered output from the first charge amplifier 201.

[0066] The current measurement device 200 reduces the current consumption relative to the RC filter 103 and the RC filter buffer 104 by replacing the RC filter 103 and the RC filter buffer 104 with a low-pass filter 204 without an amplifier. Figure 4 The amplifier-less low-pass filter provides the same noise suppression performance without requiring any amplifiers, thereby reducing power consumption.

[0067] In one class of embodiments, the amplifier-avoiding strategy extends to the entire signal path between first charge amplifier 201 and second charge amplifier 202. In such embodiments, the processing circuitry is configured such that information about the current to be measured, in the form of the amount of charge representing the current to be measured (optionally, solely in the form of the amount of charge), propagates through the processing circuitry from first charge amplifier 201 to second charge amplifier 202. This can be achieved by configuring the processing circuitry (i.e., the circuitry that carries the charge between first charge amplifier 201 and second charge amplifier 202) to consist solely of passive components and externally controllable switches. The following embodiments describe various techniques for implementing this strategy efficiently and with minimal silicon area requirements.

[0068] refer to Figure 6 and 7 An example operation of the low pass filter 204 without an amplifier is described. Figure 6 As shown, the amplifier-less low pass filter 204 includes a first low pass filter module 206 and a second low pass filter module 207. The terms "first" and "second" are used herein as labels to distinguish between the two low pass filter modules. The term "module" is used to refer to an element that provides the required functionality of each low pass filter module and is used interchangeably with other equivalent terms such as "unit" or "device". The first low pass filter module 206 includes a first RC filter and the second low pass filter module 207 includes a second RC filter. The time period over which a single different measurement of current is made (which may involve extracting one or more samples of the integrated current) is referred to herein as a sensing frame. By alternating the use of the first low pass filter module 206 and the second low pass filter module 207 within different sensing frames, it is possible to avoid the need for an RC filter buffer 104, as shown in FIG. Figure 4 The filter buffer is used in the arrangement.

[0069] Figure 7 Depicts an example timing diagram showing Figure 5 and 6 An example operation of the low-pass filter 204 without an amplifier is depicted in FIG. Figure 7 The horizontal axis in represents time. The vertical axis shows the changes of five signals 211-215 (described below) over time. Figure 7 In the timing diagram of FIG, four sensing frames are shown. The four sensing frames include two first sensing frames 221 and two second sensing frames 222. The first sensing frames 221 and the second sensing frames 222 are alternated.

[0070] A reset signal 211 is applied at the switch labeled 211. When the reset signal 211 is high, the first charge amplifier 201 is reset. The first charge amplifier 201 is thus reset at the beginning of each of the sensing frames 221, 222.

[0071] The flip signal 212 is applied to Figure 6 2. When the inversion signal 212 is high, the capacitive component of the first low-pass filter module 206 is connected to the output of the first charge amplifier 201. When the inversion signal 212 is low, the capacitive component of the second low-pass filter module 207 is connected to the output of the first charge amplifier 201. Therefore, the capacitive component of the first low-pass filter module 206 is connected to the output of the first charge amplifier 201 during each first sensing frame 221, and the capacitive component of the second low-pass filter module 207 is connected to the output of the first charge amplifier 201 during each second sensing frame 222.

[0072] Signal 213 represents the output 213 of the first charge amplifier 201. During each sensing frame 221, 222, the output 213 continues to ramp up as the charge is integrated from the point immediately after the reset signal 211 goes low to the point when the reset signal 211 next goes high at the end of the sensing frame 221, 222. Processing circuitry, downstream of the first charge amplifier 201, obtains at least one sample of the output 213 from the first charge amplifier 201 in order to obtain a measure of the current input at point 250.

[0073] Signal 214 represents the signal level available for output from first low-pass filter module 206. Signal 214 ramps up within each first sensing frame 221 (when first low-pass filter module 206 is connected to output 213 of first charge amplifier 201) and remains flat within each second sensing frame 222, while the capacitive components of first low-pass filter module 206 retain the charge sampled during the previous first sensing frame 221. First low-pass filter module 206 is therefore in storage mode during each second sensing frame 222. The charge sampled by first low-pass filter module 206 within each first sensing frame 221 can be read out at any time during the following second sensing frame 222.

[0074] Signal 215 represents the signal level available for output from second low-pass filter module 207. Signal 215 ramps up within each second sensing frame 222 (when second low-pass filter module 207 is connected to output 213 of first charge amplifier 201) and remains flat within each first sensing frame 221, while the capacitive components of second low-pass filter module 207 retain the charge sampled during the previous second sensing frame 222. Second low-pass filter module 207 is therefore in storage mode during each first sensing frame 221. The charge sampled by second low-pass filter module 207 within each second sensing frame 222 can be read out at any time during the next first sensing frame 221.

[0075] By following Figure 7 The timing diagram uses Figure 6 The circuit can obtain the first sample of the output 213 of the first charge amplifier 201 in each sensing frame 221, 222 without the need for an RC filter buffer (and associated amplifier) by alternating sampling between sampling through the first low-pass filter module 206 and sampling through the second low-pass filter module 207. The total number of amplifiers required to implement the processing circuit is reduced, and power consumption and / or heat dissipation is also reduced.

[0076] Figure 5 The current measuring device 200 is replaced by using Figure 6 The capacitive components of the plurality of capacitors of each of the single capacitors of the first low pass filter module 206 and the second low pass filter module 207 shown implement the second stage gain (corresponding to providing a second stage gain in the presence of Figure 4 The second stage gain of 105 functions within the CDS amplifier to further reduce the need for amplifiers.

[0077] Therefore, an embodiment is provided in which each sensing frame (eg, Figure 7 In the second sensing frame 222 in the example of FIG, the first sensing frame (eg, Figure 7 The samples of the first sensing frame 221 (in the example of FIG. 2 ) are stored in the form of electric charge on the capacitive components of the first plurality of capacitors 2061 in the first RC filter comprising the first low-pass filter module 206 .

[0078] Similarly, in each sensing frame (eg, Figure 7 In the example of the first second sensing frame 221), the first second sensing frame (eg, Figure 7The samples of the second sensing frame 222 in the example of FIG. 2 are stored in the form of electric charge on the capacitive components of the second plurality of capacitors 2071 in the second RC filter comprising the second low-pass filter module 207 .

[0079] During each second sensing frame 222, a selected attenuation (i.e., a negative gain) is applied to the charge representing information about the current to be measured by sampling charge from only a selected subset of the first plurality of capacitors 2061. Similarly, during each first sensing frame 221, a selected attenuation (i.e., a negative gain) is applied to the charge representing information about the current to be measured by reading charge from only a selected subset of the second plurality of capacitors 2071.

[0080] exist Figure 5 In the example of FIG, 2 , the first plurality of capacitors 2061 includes four capacitors. In other embodiments, the first plurality of capacitors 2061 includes a different number of capacitors. In one embodiment, within each first sensing frame 221, all capacitors in the first plurality of capacitors 2061 are connected to the circuit (all switches shown in the first low-pass filter module 206 are closed), so that the first low-pass filter module 206 operates optimally in RC filter mode (i.e., to achieve maximum filtering). Within each second sensing frame 222, selected switches in the first low-pass filter module 206 are opened, so that only a subset of the capacitors in the first plurality of capacitors 2061 are connected to the circuit. This makes only a portion of the total charge stored on the first plurality of capacitors available for readout, thereby applying the desired attenuation. During the readout time within each second sensing frame, the switches activated by AND gate 2062 (when signal 212 is low and readout signal Srr is high) allow the charge stored on the first plurality of capacitors 2061 to be read out.

[0081] The second plurality of capacitors 2071 is configured to operate in a similar manner. In this example, the second plurality of capacitors 2071 includes four capacitors, but a different number can be provided if desired. Within each second sensing frame 222, all capacitors in the second plurality of capacitors 2071 are connected to the circuit (all switches shown in the second low-pass filter module 207 are closed), so that the second low-pass filter module 207 operates optimally in RC filter mode (i.e., to achieve maximum filtering). Within each first sensing frame 221, selected switches in the second low-pass filter module 207 are opened to connect only a subset of the capacitors in the second plurality of capacitors 2071 to the circuit. This makes only a portion of the total charge stored on the second plurality of capacitors available for readout, thereby applying the desired attenuation. At the readout time within each first sensing frame 221, the switch activated by the AND gate 2072 (when both 212 and Srr are high) allows the charge stored on the capacitors to be read out.

[0082] Example timing diagrams are shown in Figure 5 The timing is shown for the case where there are multiple rows of pixels to allow readout from the array. Multiple readout signals Srr-r0, Srr-r1, ..., Srr-rn are then provided for row 0, row 1, ..., row n. The Srr signals are arranged to be read out from each of the rows at different times.

[0083] Figure 8 and 10 Depicts Figure 5 Both arrangements are examples of a class of embodiments in which a first sample and a second sample of the output 213 of the first charge amplifier 201 are obtained within each sensing frame 221, 222, and the processing circuit is configured to perform correlated double sampling using the first sample and the second sample.

[0084] Figure 8 An example timing diagram of the arrangement is shown in Figure 9 middle. Figure 10 An example timing diagram of the arrangement is shown in Figure 11 Signals 211-213 correspond to the above reference Figure 7 Signals 211-213 are described. Additional signals 216 and 217 are provided to implement correlated double sampling. Signal 216 determines when the first sample of the correlated double sampling is obtained within each sensing frame 221, 222, at the point where the signal falls from high to low. Signal 217 indicates when the second sample of the correlated double sampling is obtained within each sensing frame 221, 222, at the point where the signal falls from high to low.

[0085] To perform correlated double sampling, the processing circuit includes a Figure 5 At least one additional low-pass filter module is arranged. Figure 8 and 10 In one class of embodiments, which is an example, sampling of the first sample alternates between sampling by the first low-pass filter module 206 and sampling by the second low-pass filter module 207 from one sensing frame 221 to the next sensing frame 222. Figure 8 and 9 In the example of FIG, the first sample is sampled by the first low-pass filter module 206 in each first sensing frame 221 and read out from the first low-pass filter module 206 (when in the storage mode) in the following second sensing frame 222. The first sample is sampled by the second low-pass filter module 207 in each second sensing frame 222 and read out from the second low-pass filter module 207 (when in the storage mode) in the following first sensing frame 221. Figure 8 and10 Two possibilities for sampling the second sample in this scenario are depicted respectively. In both cases, the sampling of the second sample is performed by at least one further low-pass filter module.

[0086] exist Figure 8 In an arrangement of , the at least one further low pass filter module comprises a third low pass filter module 208 and a fourth low pass filter module 209. In this arrangement, sampling of the second sample alternates between sampling by the third low pass filter module 208 and sampling by the fourth low pass filter module 209 from one sensing frame 221 to the next sensing frame 222. Figure 8 and 9 In the example of FIG, the second sample is sampled by the third low-pass filter module 208 in each first sensing frame 221 and read out from the third low-pass filter module 208 (when in the storage mode) in the following second sensing frame 222. The second sample is sampled by the fourth low-pass filter module 209 in each second sensing frame 222 and read out from the fourth low-pass filter module 209 (when in the storage mode) in the following first sensing frame 221.

[0087] In the illustrated example, the third low-pass filter module 208 includes a third RC filter, and the fourth low-pass filter module 209 includes a fourth RC filter. Each of the third and fourth RC filters can be configured in any of the manners described above for the first and second RC filters, respectively. In the illustrated embodiment, the capacitive component of the third RC filter includes a third plurality of capacitors 2081. In one embodiment, the capacitive component of the fourth RC filter includes a fourth plurality of capacitors 2091. In the illustrated example, each of the plurality of capacitors 2081 and 2091 includes four capacitors. In other embodiments, one or both of the third and fourth pluralities of capacitors 2081 and 2091 can include a different number of capacitors. The third and fourth pluralities of capacitors 2081 and 2091 can operate in the same manner as the first and second pluralities of capacitors 2061 and 2071. That is, when the respective third or fourth RC filter operates as a filter, all capacitors can be connected to the circuit to optimize filtering. When reading the respective third or fourth RC filter, only a subset of the capacitors may be connected to the circuit so as to make only a portion of the total charge stored on the plurality of capacitors available for readout, thereby applying the desired attenuation.

[0088] In one embodiment, by having Figure 8 The low-pass filter module (eg, Figure 8 The output of the first plurality of capacitors 2061 or the second plurality of capacitors 2071 in FIG. 1 is combined with the output of the low-pass filter module (eg, Figure 8 The difference between the first sample and the second sample within each sensing frame 221, 222 is implemented by combining the outputs of the third plurality of capacitors 2081 or the fourth plurality of capacitors 2091 in the first and second sensing frames 221, 222. Thus, the first and second low-pass filter modules 206, 207 are connected to the output lines 231 and 232 leading to the second charge amplifier 202 in an inverse configuration relative to the connections of the third and fourth low-pass filter modules 208, 209 to the output lines 231 and 232.

[0089] Figure 10 An example of an embodiment is depicted in which the sampling of the second samples is performed for all sensing frames by means of the same single low pass filter in at least one further low pass filter module. In the example shown, there is only one further low pass filter module 208. For all sensing frames, the sampling of the second samples is performed by means of only a single further low pass filter module. This is achieved by arranging the low pass filter module in question to be reset within each sensing frame 221, 222 to obtain a sample for each low pass filter in the first low pass filter module 206, the second low pass filter module 207 and the further low pass filter module 208, without the need for two further low pass filter modules (e.g. Figure 8 and 9 In an embodiment of the present invention, the second sample is obtained in the case of a reset (e.g., the first low-pass filter module 206 is reset at least within the sensing frame 221 in which the first low-pass filter module 206 obtains the first sample, the second low-pass filter module 207 is reset at least within the sensing frame 222 in which the second low-pass filter module 207 obtains the first sample, and the additional low-pass filter module 208 is reset within each sensing frame 221 and 222 for obtaining the second sample). The reset of the low-pass filter modules is performed by bypassing the resistive component of the RC filter of each low-pass filter module. In addition, low noise is achieved by arranging the timing of the reset of each low-pass filter module so that the samples are obtained at equal times after the reset of the low-pass filter module that samples each of the first and second samples.

[0090] Figure 11 An example timing diagram is shown. Signals 211-213 correspond to the above reference Figure 7 Further signals 216 and 217 are provided to implement correlated double sampling. Further further signals 218 and 219 are provided to enable the Figure 10The low-pass filter modules 206, 207, and 208 are reset by a switch connected in parallel with the resistors labeled R1 and R2 in FIG. Each low-pass filter module 206, 207, and 208 in this example is thus reset by bypassing the resistive components of the RC filter in each low-pass filter module. Signals 211-213 and 216-219 cause the first sample to be obtained by the first low-pass filter module 206 within each first sensing frame 221 and the first sample to be obtained by the second low-pass filter module 207 within each second sensing frame 222. A second sample is obtained by the additional low-pass filter module 208 within each sensing frame (i.e., each first sensing frame 221 and each second sensing frame 222). This functionality is enabled by obtaining the samples for each of the first and second samples at equal times after the reset of the low-pass filter modules that sample them. This is achieved in the illustrated example by including a pulse in signal 218 or 219 that coincides with the start of each of the pulses in signals 216 and 217 and is shorter in length than each of the pulses in signals 216 and 217. Thus, at the start of each pulse in signal 216, which controls when the first sample is obtained, signal 218 resets all low-pass filter modules (i.e., bypasses the resistive components, allowing the capacitive components to be directly connected to first charge amplifier 201). Resetting each low-pass filter module causes the multiple capacitors to rapidly charge to a voltage defined by the charge at the output of first charge amplifier 201 at the corresponding point in time. Following each reset of a low-pass filter module, the low-pass filter module is allowed to stabilize before extracting the first or second sample.

[0091] The two signals 216 and 217 implementing correlated double sampling overlap with the two signals 218 and 219 implementing reset. Signals 216 and 218 operate together, and signals 217 and 219 operate together. The first sample and the second sample are obtained on the falling edges of the pulses in signals 216 and 217. To achieve ideal noise performance, the time difference between the falling edges of the pulses in signals 218 and 216 should be the same as the time difference between the falling edges of the pulses in signals 219 and 217 (an example of satisfying the above optional requirement: the samples for the first and second samples are obtained at the same time after the reset of the low-pass filter module).

[0092] Reference above Figure 10 and 11The noise in a circuit of the type described has two components: a switching component and a continuous component. When the reset signal to first charge amplifier 201 is released (i.e., goes low), the broadband noise of first charge amplifier 201 is folded into the baseband defined by the sampling frequency. This causes the first charge amplifier 201 to randomly offset with each field. This is the switching component of the noise. In addition to the switching component of the noise, continuous components, such as those from the first charge amplifier, also contribute.

[0093] Correlated double sampling aims to reduce the switching component of noise, i.e., the low-frequency component. RC filtering implemented by the low-pass filter module reduces the continuous component of noise. However, the output from each low-pass filter module requires time to settle to the ramp output of the first charge amplifier 201. Therefore, when performing correlated double sampling, a long delay may be introduced before the first sample is obtained. However, this is undesirable because it results in a reduction in the measured signal, effectively increasing the noise. An alternative approach is to obtain the first sample before the low-pass filter module settles, but this may result in a residual switching component of noise.

[0094] These impacts such as Figure 12-15 In display. Figure 12-15 The horizontal axis in each of represents time. Figure 12 The vertical axis in FIG represents the output 213 of the first charge amplifier 201 (showing a ramp corresponding to the integration of the current to be measured) for three example implementations (each representing a different implementation of random noise consisting of the continuous component 301 and the switching component 302 mentioned above). The switching component of the noise causes the ramp (depicted by the three smooth background curves) to shift vertically (after the first charge amplifier 201 comes out of reset and begins integrating charge). The continuous component of the noise is shown as a rapidly fluctuating signal superimposed on top of each smooth background curve. Applying a low-pass filter (e.g., one or more of the low-pass filter modules described above) to the output results in the following: Figure 13 Filtering smoothes the continuous component 301 of the noise, but has no effect on the switching component 302 of the noise. The figure shows the correlated double sampling points corresponding to signal 216 and signal 217 (the former indicates the time when the first sample is sampled, and the latter indicates the time when the second sample is sampled). Correlated double sampling should completely remove the switching component 302 of the noise. However, as Figure 14 As indicated (which shows the filtered output signal 214 in the presence of only the switching component 302 of noise (the continuous component 301 of noise has been artificially set to zero for clarity)), the first sample is taken before the filter settles to the continuous (straight line portion) ramp. This results in Figure 14 The residual correlated double sampling noise 303 is indicated by the dashed curve in FIG.

[0095] The method described above with reference to Figures 10 and 11 reduces or eliminates any negative effects of this effect by arranging the samples obtained at the same time after the reset of the low-pass filter module that samples the first and second samples of the correlated double sampling. As a result, the first sample is obtained at exactly the same point in the low-pass filter module's settling period as the second sample.

[0096] Figure 15 The method is shown. The dashed curve 304 schematically depicts the stabilization of the low pass filter module just before sampling each of the first sample and the second sample (at points 216 and 217, respectively). The method does not wait for the low pass filter module to stabilize, but instead obtains the first sample and the second sample simultaneously after the stabilization begins. Correlated double sampling involves extracting the difference between the two samples (the first sample and the second sample) and thus eliminating the residual switching component of the noise (the residual switching component makes the same contribution to the first sample and the second sample). Figure 11 In FIG, the timing diagram shows the pulses in the 216 and 217 signals. The output of the low pass filter module begins to stabilize within the corresponding pulses in the 216 and 217 signals, and the first sample and the second sample are sampled as the corresponding pulses in the 216 and 217 signals go low. Therefore, when the pulses in the 216 and 217 signals are high, Figure 15 The dashed curve 304 in corresponds to the output of the low-pass filter module.

[0097] Although more complex in terms of timing signals, Figure 10 and 11 The method can be used in the low pass filter module with Figure 8 and 9 The method can be implemented with fewer capacitors and fewer resistors, thereby saving silicon area.

[0098] Figure 16 An embodiment is depicted in which a SAR ADC 310 is provided after the second charge amplifier 202 to provide a digital output signal 312. This arrangement may be used in conjunction with the above referenced embodiment. Figure 5-15 The SAR ADC is compatible with any of the embodiments discussed. Using a SAR ADC reduces power requirements relative to other ADCs, but other ADCs may still be used as alternatives. If a SAR ADC is used after the second charge amplifier 202, providing the SAR ADC after the second charge amplifier 202 may improve amplifier efficiency (i.e., may be implemented using fewer amplifiers).

[0099] SAR ADCs are one of the most power-efficient ADC architectures, but there are some issues to consider. SAR ADCs are typically limited to 10 bits of linearity. Techniques such as sigma delta modulation can achieve higher linearity, but this can increase power consumption. Another issue is that SAR ADCs can be relatively large, so it may be desirable to multiplex several columns into each SAR ADC provided. This approach would require rapidly driving the SAR ADC's large input load, which can increase power consumption.

[0100] Another ADC architecture is a multi-slope ADC. Using this architecture with the second charge amplifier 202 allows the charge readout from the pixel and the analog-to-digital conversion to be performed within the same module. This is efficient in terms of circuit area and power. Figure 17 An example arrangement of a multi-slope ADC architecture 320 incorporating the second charge amplifier 202 is shown. The multi-slope ADC architecture 320 can be used with the above referenced Figure 5-15 Any combination of the embodiments discussed may be used.

[0101] The multi-slope ADC architecture 320 includes the second charge amplifier 202, a first charge DAC feedback unit 321, a second charge DAC feedback unit 322, a comparator 323, and a digital control unit 324 configured to output a digital output signal 312. In operation, the charge received from the upstream circuitry derived from the first charge amplifier 201 (as described above with reference to FIG. Figure 5-15 The voltage (described above) is presented by the second charge amplifier 202 as a voltage to the comparator 323 of the multi-slope ADC architecture 320. After settling to the correct voltage, analog-to-digital conversion can continue. This can be accomplished through current or charge feedback. Figure 17 Depicts an example of charge feedback. Figure 17 The multi-slope ADC architecture 320 provides dual functionality for pixel charge readout and ADC conversion, saving power and silicon area. The multi-slope ADC architecture 320 can be adapted to operate in single-slope mode, but this reduces the conversion rate and may be impractical for some applications.

[0102] Figure 18The schematic diagram shows an architecture for implementing readout from multiple channels (which may be referred to as pixels) in a matrix array. Each channel is labeled C(i,j), where i represents the row number and j represents the column number. Each channel includes circuitry for measuring current, which may be based on the above reference. Figure 5-15 In the example shown, each column provides N channels (arranged horizontally). The N channels can be configured as follows: Figure 5 The N channels in each column are connected to an integrated component 340(j) configured to perform the dual functions of charge readout (via the second charge amplifier 202) and analog-to-digital conversion, as described above with reference to Figure 15 and 16 Described above. Figure 15 and 16 Any of the embodiments discussed may be used to implement the integrated components 340(j). In the example shown, M columns are provided, so there are M integrated components 340(j), each of which outputs a digital output signal 312 that can be read from the ASIC using any of a number of standard techniques. Figure 5 1 and 2. The row controller 330 is shown addressing the Srr signal. The Srr signal is activated once per sensing frame 221, 222 per channel C(i, j). In the embodiment shown, each integrated component 340(j) addresses a single column. In other embodiments, one or more of the integrated components 340(j) can be configured to address multiple columns.

[0103] The following description introduces an alternative reset mechanism for resetting a charge amplifier, which is referred to herein as charge balancing soft reset. Following this introduction, embodiments utilizing charge balancing soft reset will be described.

[0104] Figure 19 A charge amplifier 410 is depicted in a configuration suitable for detecting small currents from a sensor element. The sensor element behaves as a current source, and the charge amplifier performs a charge-to-voltage conversion by integrating the charge.

[0105] When the reset switch 400 is turned off, the capacitor C FB The input current i in The gain of the circuit is determined by the feedback network. In some applications, a resistor is used in parallel with the feedback capacitor, but this is impractical when currents in the pA range must be sensed and therefore require very high gains. In such cases, the amplifier is Figure 20 Reset after each integration interval shown.

[0106] During reset, the integration of the input current is interrupted. The reset operation causes noise folding, which increases the output noise level. The noise from the operational amplifier (OpAmp) 405 can be represented by the input noise voltage source v n indicates; see Figure 21 .

[0107] Figure 21 Depicts Figure 19 The combination of a charge amplifier 410 of the type depicted in FIG. 4 and a sensor 401 (which acts as a source of the current measured by the charge amplifier 410 ) provides Cs / Cs for the OpAmp 405 noise voltage vn. FB At the moment when the reset switch 400 is disconnected, the voltage gain of the integral capacitor C FB The amplified OpAmp 405 noise is sampled on the CMOS circuit. In the time domain, this is seen as a randomly varying offset voltage at the beginning of each integration period and corresponds to the noise folding effect typically analyzed in the frequency domain. To limit the overall noise, the output signal of the charge amplifier 410 is typically filtered using low-pass and / or high-pass filters. The filters can be passive or discrete-time. For example, a correlated double sampling (CDS) filter can be applied as a high-pass filter. A high-pass filter is an effective means of filtering low-frequency noise, which can be high in practical OpAmps 405. Most CMOS amplifiers are dominated by 1 / f noise at low frequencies.

[0108] An alternative charge balancing soft reset method is now described. The charge balancing soft reset method replaces the above referenced Figure 19-21 The charge amplifier reset operation is described. The charge balancing soft reset method facilitates the reduction of low frequency noise, such as that which may be generated by noise folding. The charge balancing soft reset method is also compatible with output filtering for further noise reduction.

[0109] An additional advantage of the charge balancing soft reset method is that the integration of the input signal occurs without interruption. Figure 19-21 In the hard reset method of the arrangement, the charge amplifier 410 does not react to the input current while the charge amplifier 410 is held in reset. The charge balancing soft reset method allows uninterrupted integration, which makes it possible to react to events that would otherwise not be captured during the reset period.

[0110] The charge balancing soft reset method may be implemented in a manner that the charge amplifier 410 is still effectively reset once within the sensing frame T.

[0111] Figure 22 Depicts an arrangement for implementing a charge balancing soft reset method. If it is assumed that Figure 22If an ideal OpAmp 405 is used within the charge amplifier 410 (eg, with no input offset, no noise, and infinite open-loop gain), then at the end of the integration period the feedback capacitor C FB The voltage across the terminals is equal to v out (T) – V ref In the arrangement shown, the second capacitor C f Connect the output voltage to the reference voltage V ref The condition is that the control signal 403 is low.

[0112] As long as the control signal 403 is low, C f The voltage across C is equal to FB voltage across it, and if C f =C FB , then C f The charge at will be equal to C FB When the control signal 403 becomes high, the capacitor C f is disconnected from the output and connected to the amplifier signal input, such as virtual ground. This results in the capacitor C f Discharge to C FB This makes the capacitor C FB During this charge balancing process, integration of the input signal continues.

[0113] In order to accurately cancel the charge at the end of the integration period, C f = C FB If the charge amplifier 410 has a programmable capacitor C FB The programmable gain of the capacitor C f It must also be programmable.

[0114] No additional control signal is required to implement the charge balance soft reset. Figure 19 In the embodiment of the present invention, the reset signal 400 of the reset switch is used to control the charge balancing switch, such as Figure 22 In Figure 22 The circuit of FIG. 40 receives a switch of the balanced signal 403. Therefore, the power dissipation is not increased.

[0115] Figure 22 The circuit adds a capacitive load to the output of the OpAmp 405. Depending on the nature of the OpAmp 405 and the capacitor value, the stability of the circuit may be reduced. Figure 23 An alternative embodiment for reducing the load of OpAmp 405 by introducing a buffer amplifier 406 is shown in FIG. If the buffer amplifier 406 has a gain of A, then the capacitor C f Needs to be scaled to Cf =C FB / A to achieve the correct amount of charge during the feedback period. A buffer amplifier 406 can also be introduced to FB This saves chip area by reducing the size of the capacitor.

[0116] Due to the mismatch, the value of the replica capacitor will not be an exact replica of the integrating capacitor. This can cause a systematic offset in the output voltage. Other imperfections, such as charge injection from the switching network, can also cause a systematic output offset. If desired, this offset can be removed by high-pass filtering the output signal.

[0117] Figure 24 Describes the ability to implement the above reference Figure 19-21 The test circuits for both hard reset mode and charge balancing soft reset mode are described. It is possible to select between the two modes for comparison. The noise spectral density of the OpAmp 405 appears as 1 / f at the frequency of interest, for example f < 1 / T, where T is the integration interval (size of the sensing frame). In the test experiments, the charge amplifier 410 was evaluated using an integration interval of T = 100 microseconds, while the low-pass filter 412 was operated at a 10 kHz corner frequency. The timing of the CDS high-pass filter is programmable and defined by signal 414. The input-referred noise current (vertical axis) is measured on Figure 25 4 shows the time from reset signal 400 to CDS signal 414. The solid line shows the noise variation in charge balancing soft reset mode. The dashed line shows the noise variation in hard reset mode. Charge balancing soft reset mode achieves lower circuit noise in all cases. The minimum noise reduction is approximately 15%. The impact of low-frequency noise is most noticeable shortly after the reset action, when up to a factor of two noise reduction is achieved.

[0118] Reference above Figure 8 The current measurement device described reduces power requirements by reducing the number of amplifiers required to implement the current measurement function. However, the large number of components required to implement the circuit means that a considerable amount of silicon area is required. Figure 10 The described current measurement device reduces the amount of silicon area required for implementation by reducing the number of resistors and capacitors required for the low-pass filter module. In the above section, a charge balancing soft reset mechanism is disclosed for achieving low noise current sensing in combination with an RC filter and correlated double sampling.

[0119] The challenge with all of these approaches is that the circuitry used for implementation must be sufficiently fast, which can be achieved by providing appropriate amplifier bandwidth and bias current. Figure 11When timing such as those depicted in , the circuit needs to settle to its operating point in a period much shorter than the sensing frame, for example up to a factor of 100. Providing high amplifier bandwidth and bias current may result in higher power requirements and higher noise (due to the wider bandwidth).

[0120] The following describes an embodiment that utilizes the charge-balancing soft reset mechanism described above to create a low-power circuit by eliminating the need for circuit stabilization during the reset period and the need for correlated double sampling. Only one sample is then required for each sensing frame (as opposed to two samples for correlated double sampling, one at the beginning and one at the end of the sensing frame). This approach means that the amplifiers involved can reach stability using the entire sensing frame rather than at most one-hundredth of a sensing frame. This means that amplifier bandwidth and bias current can be significantly reduced. This reduces power consumption. Low noise is also maintained. The circuitry required to implement this approach is simple and adds little to no silicon area requirements.

[0121] As mentioned above Figure 19-25 The principle of charge balancing (which may also be referred to as charge feedback) involves sampling the output of the charge amplifier and feeding the sampled output back to the input at regular intervals to bring the output back to a reset level. In principle, this compensates for the switching component of the noise. However, resetting the charge amplifier causes the noise to fold over. Under normal reset conditions, the charge amplifier is a buffer with a gain of 1 up to its unity gain bandwidth. Now consider that the noise frequency is well beyond the sampling rate (e.g. 10 MHz when the sampling rate is 10 kHz). The noise is sampled in buffer mode and results in a full gain of 1 when the charge amplifier is below the unity gain bandwidth. Then, when exiting reset to inverting charge amplifier mode, the charge amplifier is presented with a capacitance C equal to the capacitance at the input of the charge amplifier (e.g. the capacitance of the amphiphilic membrane when the device is used to measure current associated with a nanopore) and an integrating capacitance C. FB (See e.g. Figure 19 ) gives a gain of, for example, 30 to 300, but it takes several microseconds for this to occur (i.e., the noise folds back to low frequencies). Since most of the noise is at high frequencies, this effect is significant and results in a large switching component of the noise, much larger than the continuous noise in charge mode. In charge reset mode, the charge amplifier is always in inverting charge amplification mode. Therefore, no gain is seen at high frequencies due to the amplifier's characteristics (see above). When charge balancing is used, the noise folds back, resulting in a lower gain due to the charge amplifier's characteristics. This means that the switching component of the noise is significantly lower. This improvement is achieved regardless of the amplifier's unity gain bandwidth (assuming a single-pole amplifier).

[0122] Figure 26A graph of gain G versus frequency schematically illustrates these concepts, where 421 represents the charge gain, 422 represents the unity gain, and the gain reduction from the amplifier is represented by 423 (i.e., the noise receives the lower gain corresponding to curve 422 rather than the gain of curve 421 and therefore has less impact). Analyzing the noise (simplified for illustrative purposes), it is found that for the normal reset mode of operation, the noise from the charge amplifier in the time domain can be characterized as two components: a continuous component Vn and a switching component Vns. Comb and rect functions are suitable because the system resets within a short period of time, and as the circuit releases, the sampled noise value changes each sensing frame. Therefore, the comb function samples the noise value Vns once per sensing frame, and convolution with the rectangular function extends this value to the integration period within the sensing frame. This integration period can be referred to as Tint. Tint is a small amount less than the sampling period Ts. The reset period Treset is very short. Assume that the noise is effectively zero when the circuit is reset because the gain G is 1 (the charge amplifier is a unity gain buffer), whereas it is large in the integrating mode (e.g., the capacitance of the amphiphilic film and the integrating capacitance C described above). FB It is possible to evaluate the noise by Fourier transformation. If the amplifier characteristics are added, the continuous component Vn of the noise has a gain associated with the integrator, and the switching component of the noise has a gain associated with the uniform gain buffer. Then, when the mode is switched to charge integration mode and the noise is sampled in buffer mode, it will have a gain G. The following equation shows these steps through the equation, where C PORE represents the capacitance of the amphiphilic membrane, and C FB Represents the integrating capacitor:

[0123]

[0124] The Fourier transform yields the following:

[0125]

[0126] Adding the amplifier characteristics gives us the following:

[0127]

[0128] If we now consider charge feedback mode, the system is always in charge integrating mode, so when we add the amplifier characteristics, we see that the equations change slightly, but the impact is significant.

[0129]

[0130] The Fourier transform yields the following:

[0131]

[0132] Adding the amplifier characteristics gives us the following:

[0133]

[0134] If we take the ratio of the second terms representing the switching component of the noise, we find that for high frequencies, i.e. when A(f) is less than G, the ratio is much greater than 1. Therefore, the charge balancing soft reset method outperforms the normal hard reset method by a large factor:

[0135]

[0136] Taking A(f) to have a single pole at frequency f0 and integrating over all frequencies, we find that the ratio becomes

[0137]

[0138] Note that with correlated double sampling, the switching component of the noise obtained in the circuit is a residual effect due to imperfect correlated double sampling. Therefore, correlated double sampling also significantly reduces switching noise. The key point is that correlated double sampling can be avoided by using the variable balance soft reset method, as this method alone significantly reduces switching noise.

[0139] Thus, in summary, a circuit is provided that does not perform correlated double sampling, produces low noise, and does not require a hard reset. Thus, the problems of previous circuits are eliminated, and a single sampling circuit can be created with very low power and good noise performance.

[0140] In addition, the above reference Figure 8 and 10 Circuits of embodiments of the type described require relatively large passive components (e.g., capacitors). Charge balancing soft reset methods can be used with circuits corresponding to Figure 8 and 10 Fewer components are required to implement compared to either approach, and single sampling (per sensing frame) means less storage is required. Therefore, circuits based on the charge-balanced soft reset approach can offer efficiencies in terms of silicon area required for implementation. These advantages are illustrated in the example embodiments shown below.

[0141] Reference above Figure 5-18 Any of the embodiments discussed may be adapted to use a charge balancing soft reset approach rather than a hard reset, but certain benefits in terms of power savings and silicon area requirements will be gained by avoiding the use of correlated double sampling.

[0142] Examples in Figures 27-30In an embodiment implementing the charge balancing soft reset method, the first charge amplifier 201 is configured such that simultaneously across the first capacitive element 431 (which may correspond to, for example, the capacitive element referred to above as C FB The first charge amplifier 201 is then reset by allowing the charge stored on the second capacitive element 432 to flow to the first capacitive element 431 and at least partially cancel out the charge stored on the first capacitive element.

[0143] Figure 27 Described as above Figure 5 In the embodiment configured in, instead of driving the hard reset signal 211 at the switch (such as Figure 5 In the case of the charge balancing soft reset method, the charge balancing soft reset method is implemented instead. The timing diagram is shown in Figure 28 In and with Figure 7 1 (where corresponding elements have corresponding reference numerals). First charge amplifier 201 integrates the currents simultaneously measured across first capacitive element 431 (e.g., one or more capacitors) and second capacitive element 432 (e.g., one of a plurality of capacitors). Reset is then performed by allowing the charge stored on second capacitive element 432 to flow to first capacitive element 431 and cancel the charge stored on the first capacitive element.

[0144] As reference Figure 5 As described in detail, the first charge amplifier 201 is periodically reset by a reset signal 211 that defines a series of sensing frames 221 and 222. A sensing frame in which the flip signal 212 is primarily high may be referred to as a first sensing frame 221. A sensing frame in which the flip signal 212 is primarily low may be referred to as a second sensing frame 222. The first sensing frame 221 and the second sensing frame 222 therefore alternate in time. Sampling alternates between sampling by the first low-pass filter module 206 and sampling by the second low-pass filter module 207 to avoid the need for an RC filter buffer. The first low-pass filter module 206 filters the output of the first charge amplifier 201 within each first sensing frame 221, and at the end of the first sensing frame 221, the capacitor components of the RC filter of the first low-pass filter module are isolated by the flip signal 212 to store charge. At each second sensing frame 222, the second low-pass filter module 207 filters the output of the first charge amplifier 201, and at the end of the second sensing frame 222, the charge is isolated and stored by the non-flip signal 212. Also within each second sensing frame 222, the Srr signal activates (after being ANDed with the flip signal 212) the output switch of the channel, thereby sending charge along output lines 231 and 232 toward the second charge amplifier 202. The first plurality of capacitors 2061 and the second plurality of capacitors 2071 are as described above with reference to FIG. Figure 5 The described operates to allow a selected attenuation to be applied to the charge representing information about the desired current by reading out the charge from only a selected subset of the first plurality of capacitors 2061 or the second plurality of capacitors 2071 (depending on from which it is read out).

[0145] When the reset signal 211 goes high, the charge in the second capacitive element 432 is forced into the input of the first charge amplifier 201. The first charge amplifier 201 is forced to remove this charge by sending an opposite charge through the first capacitive element 431. This returns the first charge amplifier 201 to its center point, effectively resetting the first charge amplifier 201. Once all the charge in the first capacitive element 431 has been removed, the reset signal 211 can go high again, allowing the output of the first charge amplifier 201 to recharge the first capacitive element 431. As a result, the reset period is effectively zero, and the entire integration period is free to integrate current, which is not the case when a hard reset is performed using a switch directly across the integrating capacitor (e.g. Figure 5 This approach increases the amount of time available to achieve maximum signal, and thereby achieves low input referred current noise. This effect is reflected in the reference Figure 26 Beyond the discussion of the impact of promoting low noise.

[0146] Figure 29 Depicts Figure 27 A variation of the arrangement of , in which only a single pair of resistor elements is used instead of two pairs of resistor elements to implement the two low pass filter modules 206 and 207. Using the same timing (e.g. Figure 28 depicted), but the connection to the capacitor is now after the resistor (in the Figure 29 to the right of the resistor) instead of just after the first charge amplifier 201 (in the Figure 29 Towards the left side of the resistor). Reducing the number of components required reduces silicon area requirements.

[0147] Figure 30 A further variant is depicted in which the bandwidth of the first charge amplifier 201 is arranged so low that a differential resistance component is no longer required, i.e. the output impedance of the first charge amplifier 201 provides filtering of the signal in combination with the capacitor. This further reduces the silicon area requirements.

[0148] The above embodiments are essentially distinct. A single-ended version of the circuit can be implemented as a routine based on the above teachings and will provide similar advantages. The performance of the single-ended version in terms of signal dynamic range and noise may generally be lower, but it may benefit from lower power requirements because no common-mode feedback circuitry is required within the amplifier.

[0149] One or more of the above current measuring devices can be used for example Figure 31 The molecular entity sensing device 1 is schematically depicted in FIG. The sensing device 1 comprises a sensor device 2 and a detection circuit 3. In one embodiment, the sensor device 2 comprises an array of sensor elements 56 (see Figure 32 In one embodiment, the detection circuit 3 includes a plurality of current measuring devices according to any of the embodiments disclosed above. Each current measuring device measures the current output by one or more of the sensor elements 56 and provides an output (e.g., a digital output) that is dependent on the current output by the one or more of the sensor elements 56.

[0150] In one embodiment, each of the sensor elements 56 comprises an ion channel. In one embodiment, the ion channel comprises a nanopore. In one embodiment, the ion channel comprises a membrane protein. In one embodiment, each of the sensor elements 56 is arranged to support an amphiphilic membrane into which the membrane protein can be inserted. The interaction between the molecular entity and the sensor element 56 in this case is an interaction between the molecular entity and the membrane protein in the amphiphilic membrane.

[0151] In one embodiment, the sensor device 2 is a device as described in detail in US 2011 / 0120871 A1, which is incorporated herein by reference. Without being limited to the generality of the teachings therein, a sensor device 2 of this type has the following features: Figure 32 The construction shown in cross section in FIG. 1 includes a body 20 in which a plurality of wells 21 are formed, each well being a recess in which a well electrode 22 is disposed. A large number of wells 21 are provided to optimize the data collection rate of the apparatus 1. In general, there may be any number of wells 21, typically 256 or 1024, but Figure 32 Only a few wells 21 are shown in . Each well 21 and the corresponding well electrode 22 is an example of a sensor element 56 .

[0152] In this embodiment, the body 20 is covered by a cover 23 that extends over the body 20 and is hollow to define a chamber 24 into which each of the wells 21 opens. A common electrode 25 is disposed within the cover 23. Each sensor element 56 is arranged to output a current that is dependent on the interaction between the molecular entity and the sensor element 56, as described with reference to the following exemplary configuration.

[0153] In the embodiment shown, the sensor device 2 is prepared to form an amphiphilic membrane across each well 21 and insert membrane proteins into the amphiphilic membrane. This preparation can be achieved using the techniques and materials described in detail in US2011 / 0120871A1, which can be summarized as follows. An aqueous solution is introduced into the chamber 24 to form an amphiphilic membrane across each well 21, thereby separating the aqueous solution in the well 21 from the remaining volume of aqueous solution in the chamber 24. For example, the membrane protein is provided to the aqueous solution by introducing it into the aqueous solution before or after it is introduced into the chamber 24 or by being deposited on the inner surface of the chamber 24. The membrane protein spontaneously inserts from the aqueous solution into the amphiphilic membrane. This spontaneous insertion is a dynamic process, and therefore there is statistical variation in the number of membrane proteins inserted into a single amphiphilic membrane, which generally has a Poisson distribution.

[0154] Other sensor devices suitable for the present invention are disclosed in WO2014064449A1.

[0155] With respect to any given well 21, once an amphiphilic membrane has been formed and a membrane protein has been inserted therein, the well 21 can function as part of a sensor element 56 configured to sense interactions between a molecular entity and the membrane protein. These interactions are random physical events. The output electrical signal across the amphiphilic membrane depends on the interactions, as the interactions result in changes in the characteristics of the output electrical signal. For example, where the membrane protein is a protein pore, there is typically an interaction between the protein pore and a specific molecular entity (the analyte) that modulates ion flow through the pore. Modulation of ion flow through the pore results in a change in the characteristics of the current flowing through the pore. The molecular entity can be a molecule or a portion of a molecule, such as a DNA base. Such interactions are typically very brief, requiring high temporal resolution and continuous monitoring if it is desired to detect each interaction.

[0156] Any membrane can be used according to the various aspects described herein. Suitable membranes are well known in the art. The membrane can be an amphiphilic layer or a solid layer. An amphiphilic layer is a layer formed by amphiphilic molecules such as phospholipids, which have both hydrophilic and lipophilic properties. The amphiphilic molecules can be synthetic or naturally occurring. Non-naturally occurring amphiphiles and amphiphiles that form monolayers are known in the art and include, for example, block copolymers (Gonzalez-Perez et al., Langmuir, 2009, 25, 10447-10450). The copolymer can be a triblock, tetrablock, or pentablock copolymer. The membrane can be a triblock or diblock copolymer membrane.

[0157] Membranes formed from block copolymers hold several advantages over biological lipid membranes. Because triblock copolymers are synthetic, the exact construction can be carefully controlled to provide the correct chain length and properties required to form membranes and interact with pores and other proteins.

[0158] Block copolymers can also be constructed from subunits that are not classified as lipid submaterials, for example, hydrophobic polymers can be prepared from siloxanes or other non-hydrocarbon monomers. The hydrophilic subsegments of the block copolymers can also have low protein binding properties, which allows the production of membranes that are highly resistant when exposed to raw biological samples. This head group unit can also be derived from non-classical lipid head groups.

[0159] Compared to biological lipid membranes, triblock copolymer membranes also have increased mechanical and environmental stability, such as much higher operating temperature or pH ranges.The synthetic nature of block copolymers provides a platform for tailoring polymer-based membranes for a wide range of applications.

[0160] The membrane may be one of the membranes disclosed in US 2015 / 0265994 A1 or US 2015 / 0285781 A1, which are hereby incorporated by reference in their entirety. These documents also disclose suitable polymers.

[0161] Amphiphilic molecules can be chemically modified or functionalized to facilitate coupling of polynucleotides.

[0162] The amphiphilic layer can be a single layer or a double layer. The amphiphilic layer is typically planar. The amphiphilic layer can be curved. The amphiphilic layer can be supported. The amphiphilic layer can be concave. The amphiphilic layer can be suspended from raised posts such that the peripheral area of the amphiphilic layer (where it is connected to the posts) is higher than the area of the amphiphilic layer. This can allow the microparticles to travel, move, slide, or roll along the membrane as described above.

[0163] The membrane may be a lipid bilayer. Suitable lipid bilayers are disclosed in WO2008 / 102121, WO2009 / 077734 and WO2006 / 100484.

[0164] Methods for forming lipid bilayers are known in the art. Lipid bilayers are typically formed by the method of Montal and Mueller (Proc. Natl. Acad. Sci. USA., 1972; 69: 3561-3566), in which a lipid monolayer is carried on an aqueous solution / air interface on either side of a pore perpendicular to the interface.

[0165] The solid-state layer can be formed from both organic and inorganic materials, including but not limited to microelectronic materials, insulating materials such as Si3N4, Al2O3, and SiO, organic and inorganic polymers such as polyamide, plastics such as Teflon®, or elastomers such as two-component addition-cured silicone rubber, and glass. The solid-state layer can be formed from graphene. Suitable graphene layers are disclosed in WO 2009 / 035647. Yusko et al., Nature Nanotechnology, 2011;6:253-260 and U.S. Patent Application No. 2013 / 0048499 describe protein delivery to transmembrane pores in a solid-state layer without the use of microparticles.

[0166] Any transmembrane pore can be used. The pore can be biological or artificial. Suitable pores include, but are not limited to, protein pores, polynucleotide pores, and solid-state pores. The pore can be a DNA origami pore (Langecker et al., Science, 2012;338:932-936).

[0167] The transmembrane pore can be a transmembrane protein pore. A transmembrane protein pore is a polypeptide or collection of polypeptides that allows hydrated ions, such as byproducts of polynucleotide treatment with a polymerase, to flow from one side of the membrane to the other side of the membrane. In one embodiment of the present invention, a transmembrane protein pore can form a pore that allows hydrated ions driven by an applied potential to flow from one side of the membrane to the other. A transmembrane protein pore can allow polynucleotides to flow from one side of a membrane, such as a triblock copolymer membrane, to the other side. A transmembrane protein pore allows polynucleotides, such as DNA or RNA, to move through the pore.

[0168] The transmembrane protein pore can be a monomer or an oligomer. The pore can be composed of several repeating subunits, such as at least 6, at least 7, at least 8, at least 9, at least 10, at least 11, at least 12, at least 13, at least 14, at least 15, or at least 16 subunits. The pore can be a hexamer, heptamer, octamer, or nonamer. The pore can be a homo-oligomer or a hetero-oligomer.

[0169] Transmembrane protein pores typically include a barrel or channel through which ions can flow. The subunits of the pore typically surround a central axis and contribute strands to a transmembrane beta barrel or channel or a transmembrane alpha-helical bundle or channel. The barrel or channel of a transmembrane protein pore typically includes amino acids that promote interactions with nucleotides, polynucleotides, or nucleic acids. These amino acids may be located near the constriction of the barrel or channel. Transmembrane protein pores typically include one or more positively charged amino acids, such as arginine, lysine, or histidine, or aromatic amino acids such as tyrosine or tryptophan. These amino acids typically promote interactions between the pore and the nucleotides, polynucleotides, or nucleic acids.

[0170] Transmembrane protein pores for use according to the present invention can be derived from β-barrel pores or α-helical bundle pores. Transmembrane pores can be derived from or based on Msp, α-hemolysin (α-HL), lysin, CsgG, ClyA, Sp1, and the hemolytic protein fragaceatoxin C (FraC). Transmembrane protein pores can be derived from CsgG. Suitable pores derived from CsgG are disclosed in WO 2016 / 034591. Transmembrane pores can be derived from lysin. Suitable pores derived from lysin are disclosed in WO 2013 / 153359.

[0171] An analyte (including, for example, a protein, peptide, small molecule, polypeptide, or polynucleotide) can be present in an analyte. The analyte can be any suitable sample. The analyte can be a biological sample. Any of the embodiments of the methods described herein can be performed in vitro on an analyte obtained or extracted from any organism or microorganism. The organism or microorganism is typically an archaeon, a prokaryote, or a eukaryote, and typically belongs to one of the five kingdoms: Plantae, Animalia, Fungi, Prokaryotes, and Protista. In some embodiments, various aspects of the methods described herein can be performed in vitro on an analyte obtained or extracted from any virus.

[0172] The analyte can be a fluid sample. The analyte can include a body fluid. The body fluid can be obtained from a human or an animal. The human or animal may have, be suspected of having, or be at risk of having a disease. The analyte can be urine, lymph, saliva, mucus, semen, or amniotic fluid, but can also be whole blood, plasma, or serum. Typically, the analyte is of human origin, but alternatively, it can be from another mammal, such as a commercially raised animal such as a horse, cattle, sheep, or pig, or alternatively, it can be a pet such as a cat or dog.

[0173] Alternatively, the analyte may be of plant origin.

[0174] The analyte can be a non-biological sample. The non-biological sample can be a fluid sample. An ionic salt such as potassium chloride can be added to the sample to affect ion flow through the nanopore.

[0175] A polynucleotide may be single-stranded or double-stranded. At least a portion of a polynucleotide may be double-stranded.

[0176] A polynucleotide can be a nucleic acid, such as deoxyribonucleic acid (DNA) or ribonucleic acid (RNA). A polynucleotide can include an RNA strand hybridized to a DNA strand. A polynucleotide can be any synthetic nucleic acid known in the art, such as peptide nucleic acid (PNA), glycerol nucleic acid (GNA), threose nucleic acid (TNA), locked nucleic acid (LNA), or other synthetic polymers with nucleotide side chains. A polynucleotide can be of any length.

[0177] Any number of polynucleotides can be studied. For example, the method can involve characterizing 2, 3, 4, 5, 6, 7, 8, 9, 10, 20, 30, 50, 100 or more polynucleotides. If two or more polynucleotides are characterized, they can be different polynucleotides or two instances of the same polynucleotide.

[0178] Polynucleotides may be naturally occurring or artificial.

[0179] The method may involve measuring two, three, four, or five or more properties of a polynucleotide. The one or more properties may be selected from: (i) the length of the polynucleotide, (ii) the identity of the polynucleotide, (iii) the sequence of the polynucleotide, (iv) the secondary structure of the polynucleotide, and (v) whether the polynucleotide is modified.

[0180] For (iii), the sequence of the polynucleotide can be determined as previously described. Suitable sequencing methods, in particular those using electrical measurements, are described in: Stoddart D et al., Proc. Natl. Acad. Sci. USA, 12;106(19):7702-7; Lieberman KR et al., J Am Chem Soc. 2010;132(50):17961-72; and International Application WO 2000 / 28312.

[0181] Secondary structure can be measured in a variety of ways. For example, if the method involves electrical measurements, changes in residence time or changes in ionic current flowing through the pore can be used to measure secondary structure. This allows for the differentiation of regions of single-stranded and double-stranded polynucleotides.

[0182] The presence or absence of any modification can be measured. The method may include using one or more proteins or using one or more markers, tags or spacers to determine whether the polynucleotide is modified by methylation, oxidation, damage or not. Specific modifications will cause specific interactions with the pore, which can be measured using the methods described below.

[0183] In some embodiments of various aspects described herein, the method may involve further characterizing the target polynucleotide.When the target polynucleotide is in contact with the pore, one or more measurements are taken as the polynucleotide moves relative to the pore, the one or more measurements being indicative of one or more properties of the target polynucleotide.

[0184] The method may involve determining whether a polynucleotide is modified or not. The presence or absence of any modification may be measured. The method may include using one or more proteins or using one or more markers, tags or spacers to determine whether a polynucleotide is modified by methylation, by oxidation, by damage or not.

[0185] Also provided is a kit for characterizing a target polynucleotide. The kit includes components of a pore and a membrane as disclosed herein. The membrane can be formed from the components. The pore can be present in the membrane. The kit can include components of any of the membranes disclosed above, such as an amphiphilic layer or a triblock copolymer membrane.

[0186] Also provided is a device for characterizing a target analyte, such as a target polynucleotide. The device comprises a plurality of pores and a plurality of membranes as disclosed herein. The plurality of pores may be present in a plurality of membranes. The number of pores and membranes may be equal. Each membrane may contain a single pore.

[0187] A device for characterizing an analyte of interest may comprise an array of pores as disclosed herein in a plurality of membranes.

[0188] The device may further include instructions for performing the method. The device may be any conventional device for analyte analysis, such as an array or chip. Any of the embodiments discussed above with reference to the method are equally applicable to the device of the present invention. The device may further include any features present in the kit as disclosed herein.

[0189] The apparatus may be arranged to perform the methods as disclosed herein.

[0190] The apparatus may include a sensor device capable of supporting a plurality of wells and a membrane and operable to perform analyte characterization using the wells and membrane; and at least one port for delivering a material for performing the characterization.

[0191] Alternatively, the apparatus may comprise a sensor device capable of supporting a plurality of wells and a membrane and operable to perform analyte characterisation using the wells and membrane; and at least one reservoir for holding material for performing the characterisation.

[0192] The apparatus may include a sensor device capable of supporting the membrane and the plurality of pores and membranes and operable to perform analyte characterization using the pores and membranes; at least one reservoir for holding a material for performing the characterization; a fluid system configured to controllably supply material from the at least one reservoir to the sensor device; and one or more containers for receiving corresponding samples, the fluid system configured to selectively supply analytes from the one or more containers to the sensor device.

[0193] The apparatus may be any of those described in WO 2009 / 077734, WO 2010 / 122293, WO 2011 / 067559 or WO 00 / 28312.

[0194] Control of the movement of the analyte relative to the nanopore, such as translocation speed, rejection of the analyte, etc., can be managed by the systems and methods disclosed in US2017 / 0233804A1, which is incorporated herein by reference in its entirety. Rejection of the analyte by the nanopore sensor can include ejection of the analyte from the nanopore.

[0195] According to the teachings herein, the features described above and in the accompanying drawings of the present invention are interchangeable and compatible. The present invention has been described above by way of example only and can be modified within the spirit and scope of the present invention, which extends to equivalents of the features described and combinations of one or more of the features described herein. The present invention also lies in any individual feature described or suggested herein.

Claims

1. A sensing device comprising: a sensor device comprising an array of sensor elements, each sensor element being arranged to output a current dependent on an interaction at the respective sensor element; a detection circuit comprising a plurality of current measurement devices, wherein each current measurement device is configured to measure a current output by one or more of the sensor elements and to provide an output signal dependent on the current output by one or more of the sensor elements; Wherein the sensing apparatus is configured to reset the plurality of current measuring devices at the beginning of each of a plurality of sensing frames such that an output of each of the current measuring devices is isolated from the sensor element array at least during a reset period.

2. The sensing device according to claim 1, wherein Each of the plurality of current measurement devices comprises a charge amplifier having an input coupled to an output of the one or more sensor elements and configured to integrate the current output from the one or more sensor elements, the apparatus being further configured to isolate the output of the charge amplifier from the input of the charge amplifier during the reset period.

3. The sensing device according to claim 2, wherein: Each current measuring device further comprises at least one capacitive element, and the sensing arrangement is further configured to integrate the current across the at least one capacitive element.

4. The sensing device according to claim 3, wherein: Each current measuring device also includes a reset switch, and the sensing arrangement is further configured to operate the reset switch to discharge the at least one capacitive element during the reset period, and wherein isolating the output of each of the current measuring devices from the sensor element array prevents or reduces interference in the event of a failure of at least one sensor element in the sensor element array.

5. The sensing device according to claim 4, wherein Each charge amplifier is configured so that integration of current is performed simultaneously on the first capacitive element and the second capacitive element, and the resetting of each charge amplifier is performed by allowing the charge stored on the second capacitive element to flow to the first capacitive element and at least partially offset the charge stored on the first capacitive element.

6. A sensing device comprising: a sensor device comprising an array of sensor elements, the array of sensor elements comprising a first sensor element, each sensor element in the array being arranged to output a current that is dependent on an interaction at the respective sensor element; as well as a detection circuit comprising a plurality of detection channels, each detection channel having a current measurement device, wherein each current measurement device is configured to measure a current output by one or more of the sensor elements and provide an output dependent on the current output by the one or more of the sensor elements, the plurality of detection channels including a first detection channel having a first current measurement device, Wherein, the sensing device is configured to isolate the first current measuring device from the first sensor element in the sensor element array coupled to the first detection channel in the event of a fault in the first sensor element, so as to prevent or reduce interference in the multiple detection channels caused by the first detection channel in the multiple detection channels.

7. The sensing device according to claim 6, wherein: Each sensor element comprises a sensor element output, and the fault in the first sensor element causes a current path having a resistance below a first threshold to be formed between the sensor element output of the first sensor element and other sensor elements in the array of sensor elements.

8. The sensing device according to claim 7, wherein: The sensor element output is an output electrode, and the sensor element array includes a common electrode shared by each output electrode, and the fault causes the current path to be formed between the output electrode of the first sensor element and the common electrode.

9. The sensing device of claim 8 , wherein each sensor element comprises: a well having a fluid disposed therein, the output electrode of the corresponding sensor element being disposed in the well; and film, formed between the output electrode and the common electrode of the corresponding sensor element, in, The failure is a rupture of the membrane.

10. The sensing device according to claim 6, wherein Each current measuring device has an output, and the sensing apparatus is further configured to reset the current measuring devices of the plurality of detection channels at the beginning of each of a plurality of sensing frames such that the output of each current measuring device is isolated from the sensor element array at least during a reset period.

11. The sensing device according to claim 10, wherein: The current measuring devices of the multiple detection channels are multiple charge amplifiers, each charge amplifier is configured to integrate the current output from the corresponding sensor element, wherein each charge amplifier is configured so that the integration of the current is performed simultaneously on the first capacitance element and the second capacitance element of the corresponding current measuring device, and the reset of the corresponding charge amplifier is performed by allowing the charge stored on the second capacitance element to flow to the first capacitance element and at least partially offset the charge stored on the first capacitance element.

12. The sensing device according to claim 11, wherein The plurality of charge amplifiers each include an operational amplifier, each first capacitive element is coupled between a first input of a corresponding operational amplifier and an output of the corresponding operational amplifier, and each second capacitive element is coupled between a second input of a corresponding operational amplifier and a reset switch, wherein the reset switch is configured to selectively couple the second capacitive element to the output of the operational amplifier and the first input of the first operational amplifier.

13. The sensing device according to claim 12, wherein: The apparatus is configured such that during the reset period, the second capacitive element is disconnected from the output of the operational amplifier and connected to the first input of the operational amplifier.

14. A molecular entity sensing device, comprising the sensing device according to claim 6, in, The interaction is between a molecular entity and a corresponding sensor element.

15. The sensing device according to claim 14, wherein Each of the sensor elements includes a nanopore having a membrane; and The sensing arrangement is further configured such that, when the membrane is ruptured, a current path is formed between two or more of the sensor elements having a resistance below a first threshold.

16. A method for measuring current, comprising: outputting a current dependent upon the interaction at sensor elements in the array of sensor elements; measuring an output current using a first current measurement device and providing an output signal dependent on the output current; as well as The output of the first current measurement device is isolated from the array of sensor elements during a reset period.

17. The method according to claim 16, wherein: The measuring is performed using a pair of capacitive elements, and the method further includes discharging the pair of capacitive elements during a reset period.

18. The method according to claim 17, wherein The first current measurement device is a charge amplifier, and the measuring comprises integrating the current output by the sensor element using the pair of capacitive elements.

19. The method according to claim 16, wherein The isolation prevents or reduces disturbances that occur in the second current measuring device in the event of a fault in the sensor element.

20. The method according to claim 16, wherein The interaction is between the molecular entity and the sensor element.

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