Data reading method and device, storage equipment, storage medium and program product

Abstract

The embodiment of the invention provides a data reading method and device, storage equipment, a storage medium and a program product, and relates to the technical field of storage. The method comprises the following steps: dynamically creating a cache linked list, a read linked list and a DMA linked list for an NAND unit with a read request, storing read request information that a read instruction is not issued to the same NAND unit by using the cache linked list, storing read request information that a read instruction is issued to the same NAND unit by using the read linked list, and storing read request information that a DMA instruction is issued to the same NAND unit by using the DMA linked list. When the read request is processed, the read request information needing to be operated on the NAND unit is rapidly screened out through the idle state, the read instruction execution time and the DMA instruction execution time, invalid traversal of the linked list is avoided, concurrent processing can be carried out on the read request information in different linked lists, and therefore the data reading performance is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data reading method, apparatus, storage device, storage medium and program product. Background Art

[0002] In the field of storage devices, such as embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), or Solid State Drive (SSD), when a host requests to read data, the storage device needs to read data from the NAND flash memory unit according to the read and write request.

[0003] Currently, a linked list is commonly used to cache read operations of NAND flash memory cells. When a large number of NAND flash memory cells need to be read, the number of linked list nodes will increase, and traversing the linked list will bring additional performance overhead, which will affect data reading performance. Summary of the Invention

[0004] In view of this, an object of the present invention is to provide a data reading method, apparatus, storage device, storage medium and program product, which can improve the reading performance of the storage device.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, the present invention provides a data reading method, the method comprising:

[0007] When a NAND unit corresponding to a cache linked list is in an idle state, a read instruction is issued to the corresponding NAND unit based on the read request information in the cache linked list, and the read request information of the issued read instruction is migrated from the cache linked list to the corresponding read linked list;

[0008] Based on the read request information of the completed data read in the target read linked list, a DMA instruction is issued to the corresponding NAND unit, and the read request information of the issued DMA instruction is migrated from the read linked list to the corresponding DMA linked list; the target read linked list is determined according to the read instruction execution time corresponding to the read request information of the linked list header;

[0009] The read request information of the target DMA linked list that has completed data reading is removed; the target DMA linked list is determined according to the DMA instruction execution time corresponding to the read request information of the linked list header; the NAND unit has a one-to-one correspondence with the cache linked list, the read linked list, and the DMA linked list.

[0010] In an optional implementation, the sending a read instruction to the corresponding NAND unit based on the read request information in the cache linked list includes:

[0011] Based on the NAND address of the read request information of the link header in the cache link list, a read instruction is issued to the corresponding NAND unit;

[0012] The read instruction issuing time of the read request information of the link list header in the cache link list is updated, and the state of the corresponding NAND unit is set to the working state.

[0013] In an optional embodiment, the sending of a DMA instruction to a corresponding NAND unit based on the read request information of the completed data read in the target read linked list includes:

[0014] Determine the read linked list whose read instruction execution time corresponding to the read request information of the linked list head reaches the preset read time threshold as the target read linked list;

[0015] If the data corresponding to the read request information of the link header in the target read linked list has been read into the register of the NAND unit, a DMA instruction is issued to the corresponding NAND unit based on the read request information of the link header in the target read linked list, and the DMA instruction issuance time of the read request information of the link header in the target read linked list is updated.

[0016] In an optional implementation manner, removing the read request information of the target DMA linked list for which data reading has been completed includes:

[0017] Determining a DMA instruction completion time according to a preset data amount and a reading rate of the DMA instruction;

[0018] Determine a DMA linked list whose DMA instruction execution time corresponding to the read request information of the linked list header reaches the DMA instruction completion time as a target DMA linked list;

[0019] If the data corresponding to the read request information of the link header in the target DMA linked list has been read into the memory, the read request information of the link header in the target DMA linked list is removed, and the state of the NAND unit corresponding to the target DMA linked list is set to an idle state.

[0020] In an optional embodiment, the method further comprises:

[0021] When receiving a pending read request, determining a NAND address of the pending read request according to the logical address of the pending read request;

[0022] Determine a NAND unit to be processed according to the NAND address of the pending read request;

[0023] generating read request information of the pending read request according to the NAND address of the pending read request;

[0024] A cache linked list corresponding to the to-be-processed NAND unit is obtained, and read request information of the to-be-processed read request is added to the cache linked list corresponding to the to-be-processed NAND unit.

[0025] In an optional embodiment, obtaining the cache linked list corresponding to the NAND unit to be processed includes:

[0026] If the cache linked list corresponding to the NAND unit to be processed does not exist, a new cache linked list for the NAND unit to be processed is created.

[0027] In a second aspect, the present invention provides a data reading device, comprising:

[0028] a read module, configured to, when a NAND cell corresponding to a cache linked list is in an idle state, issue a read instruction to the corresponding NAND cell based on the read request information in the cache linked list, and migrate the read request information of the issued read instruction from the cache linked list to the corresponding read linked list;

[0029] A direct access module is configured to issue a DMA instruction to a corresponding NAND unit based on the read request information of the target read linked list for which data has been read, and to migrate the read request information of the issued DMA instruction from the read linked list to the corresponding DMA linked list; the target read linked list is determined according to the read instruction execution time corresponding to the read request information in the linked list header;

[0030] A processing module is used to remove the read request information of the target DMA linked list for which data reading has been completed; the target DMA linked list is determined according to the DMA instruction execution time corresponding to the read request information in the link list header; the NAND unit has a one-to-one correspondence with the cache linked list, the read linked list, and the DMA linked list.

[0031] In a third aspect, the present invention provides a storage device comprising a NAND flash memory and a memory, wherein the NAND flash memory stores data; the memory can execute a computer program to implement the data reading method described in any of the aforementioned embodiments.

[0032] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a memory, implements the data reading method as described in any one of the aforementioned embodiments.

[0033] In a fifth aspect, the present invention provides a program product, which, when executed by a memory, implements the data reading method as described in any one of the aforementioned embodiments.

[0034] Compared to the prior art, the data reading method, apparatus, storage device, storage medium, and program product provided by the embodiments of the present invention dynamically create a cache linked list, a read linked list, and a DMA linked list for NAND cells with read requests. The cache linked list is used to store read request information for the same NAND cell for which no read instruction has been issued, the read linked list is used to store read request information for the same NAND cell for which a read instruction has been issued, and the DMA linked list is used to store read request information for the same NAND cell for which a DMA instruction has been issued. When processing a read request, the read request information that needs to be operated on the NAND cell is quickly filtered out based on the idle state, read instruction execution time, and DMA instruction execution time, thereby avoiding invalid traversal of the linked list and being able to concurrently process read request information in different linked lists, thereby effectively improving data reading performance.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 A schematic flow chart of a data reading method provided by an embodiment of the present invention is shown.

[0038] Figure 2 Another flow chart of a data reading method provided by an embodiment of the present invention is shown.

[0039] Figure 3 A block diagram of a data reading device provided by an embodiment of the present invention is shown.

[0040] Figure 4 A block diagram of a storage device provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0042] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely intended to represent selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0043] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0044] In storage devices like eMMC, UFS, or SSDs, data read by the host may reside on the same NAND flash memory unit (i.e., NAND cell). This can cause commands to be executed asynchronously across different NAND cells. To enable concurrent data reads from all NAND cells, the industry generally uses a linked list to cache NAND operation nodes, performing data reads by sequentially traversing the NAND operation nodes. For a large number of NAND operation nodes, the number of linked list nodes increases accordingly, and the overhead of traversing the linked list can impact data read performance.

[0045] Based on this, the data reading method, apparatus, storage device and storage product provided by the embodiments of the present invention dynamically create a cache linked list, a read linked list and a DMA linked list for NAND units with read requests. The cache linked list is used to store read request information for the same NAND unit for which no read instructions have been issued, the read linked list is used to store read request information for the same NAND unit for which read instructions have been issued, and the DMA linked list is used to store read request information for the same NAND unit for which DMA instructions have been issued. When processing read requests, the read request information that needs to be operated on the NAND unit is quickly filtered out based on the idle state, read instruction execution time and DMA instruction execution time, thereby avoiding invalid traversal of the linked list and being able to concurrently process read request information in different linked lists, thereby effectively improving data reading performance.

[0046] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Please refer to Figure 1 , Figure 1 A flow chart of a data reading method provided by an embodiment of the present invention is shown. The method comprises the following steps:

[0048] Step S10: When the NAND unit corresponding to the cache linked list is in an idle state, a read instruction is issued to the corresponding NAND unit based on the read request information in the cache linked list, and the read request information of the issued read instruction is migrated from the cache linked list to the corresponding read linked list.

[0049] In an embodiment of the present invention, a NAND unit can be a die or a plane in asynchronous multiplane independent (AMPI) mode, and can be set according to actual application, which is not limited by the present invention. The cache list, read list, and DMA list all use the NAND unit identifier as an index, that is, the NAND unit identifier is used to identify the NAND unit, cache list, read list, and DMA list, and the NAND unit identifier is globally uniformly addressed.

[0050] Traverse and obtain the NAND cell identifiers corresponding to multiple cache linked lists, and use the NAND cell identifiers to find the status of the corresponding NAND cell. When the NAND cell corresponding to the cache linked list is in an idle state, it means that the corresponding NAND cell has not performed a read operation. A read request information can be retrieved from the cache linked list corresponding to the NAND cell in the idle state, and a read instruction (i.e., a NAND read instruction) is issued to the corresponding NAND cell based on the retrieved read request information. Finally, the retrieved read request information is added to the read linked list corresponding to the same NAND cell identifier. Obviously, using the idle state can quickly screen out NAND cells that can process read instructions, which can reduce the time of traversing and parsing the linked list nodes, reduce latency, and significantly improve read performance.

[0051] Step S20: Based on the read request information of the completed data reading in the target read linked list, a DMA instruction is issued to the corresponding NAND unit, and the read request information of the issued DMA instruction is migrated from the read linked list to the corresponding DMA linked list; the target read linked list is determined according to the read instruction execution time corresponding to the read request information of the link list header.

[0052] In an embodiment of the present invention, a target read linked list is determined from read linked lists corresponding to multiple NAND units based on the read instruction execution time. When the read request information in the target read linked list has completed the data reading corresponding to the read instruction, a direct memory access (DMA) instruction is issued to the corresponding NAND unit based on the read request information. The read request information that has completed the data reading is removed from the target read linked list and added to the DMA linked list corresponding to the same NAND unit identifier.

[0053] Step S30, remove the read request information of the target DMA linked list that has completed data reading; the target DMA linked list is determined according to the DMA instruction execution time corresponding to the read request information in the link list header; the NAND unit has a one-to-one correspondence with the cache linked list, the read linked list, and the DMA linked list.

[0054] In an embodiment of the present invention, a target DMA linked list is determined from the DMA linked lists corresponding to multiple NAND units based on the DMA instruction execution time. When the read request information in the target DMA linked list has completed the data reading of the DMA instruction, the read request information of the completed DMA instruction is removed from the DMA linked list, and the data corresponding to the read request is returned to the host, completing the data reading process.

[0055] In summary, the data reading method provided by the embodiment of the present invention dynamically creates a cache linked list, a read linked list, and a DMA linked list for NAND cells with read requests. The cache linked list is used to store read request information for the same NAND cell for which no read instructions have been issued, the read linked list is used to store read request information for the same NAND cell for which read instructions have been issued, and the DMA linked list is used to store read request information for the same NAND cell for which DMA instructions have been issued. When processing read requests, the idle state, read instruction execution time, and DMA instruction execution time are used to quickly filter out read request information that requires an operation on the NAND cell, thereby avoiding invalid traversal of the linked list and being able to concurrently process read request information in different linked lists, thereby effectively improving data reading performance.

[0056] Optionally, in actual applications, the read request information includes a NAND address and a time when the read instruction is issued. As to how to issue the read instruction using the NAND address, a possible implementation is provided below. Figure 1 The sub-step of issuing a read instruction to the corresponding NAND unit based on the read request information in the cache linked list in step S10 may include:

[0057] Based on the NAND address of the read request information of the link head in the cache linked list, a read instruction is issued to the corresponding NAND unit; the read instruction issuance time of the read request information of the link head in the cache linked list is updated, and the state of the corresponding NAND unit is set to the working state.

[0058] In an embodiment of the present invention, when the NAND unit corresponding to the cache linked list is in an idle state, the read request information of the link head in the cache linked list (i.e., the read request information stored earliest in the cache linked list) is removed from the cache linked list, and a read instruction is issued to the corresponding NAND unit according to the NAND address of the removed read request information, so that the data corresponding to the NAND address in the corresponding NAND unit is read into the register of the corresponding NAND unit.

[0059] After the read instruction is issued, the read instruction issuance time of the removed read request information is updated to the current system time, and the corresponding read linked list is obtained according to the NAND unit identifier corresponding to the cache linked list. If the corresponding read linked list does not exist, a read linked list corresponding to the same NAND unit identifier is created, and the removed read request information is added to the end of the read linked list corresponding to the same NAND unit identifier.

[0060] Finally, the state of the NAND unit corresponding to the same NAND unit identifier is set to the working state to indicate that the NAND unit is performing the data reading task. It should be noted that after the cache linked lists corresponding to the NAND units in the idle state are processed, the read request information in the read linked list can be processed.

[0061] It can be seen that the embodiment of the present invention effectively tracks the scheduling status of each read request by maintaining the read instruction issuance time of the read request information, accurately manages the usage of the NAND unit by maintaining the status of the NAND unit, avoids invalid traversal of the linked list, and significantly optimizes the efficiency of data reading.

[0062] Optionally, in actual applications, the read request information further includes the time at which the DMA instruction is issued. As to how to issue the DMA instruction, a possible implementation is provided below. Figure 1 The sub-step of issuing a DMA instruction to the corresponding NAND unit based on the read request information of the completed data read in the target read linked list in step S20 may include:

[0063] The read linked list whose read instruction execution time corresponding to the read request information of the link list header reaches the preset read time threshold is determined as the target read linked list; if the data corresponding to the read request information of the link list header in the target read linked list has been read into the register of the NAND unit, a DMA instruction is issued to the corresponding NAND unit based on the read request information of the link list header in the target read linked list, and the DMA instruction issuance time of the read request information of the link list header in the target read linked list is updated.

[0064] In an embodiment of the present invention, for a read linked list that has already issued a read instruction, each read linked list is traversed, and the difference between the current system time and the read instruction issuance time of the read request information in the link head of the read linked list is determined as the read instruction execution time corresponding to the read request information in the link head. When the read instruction execution time is greater than or equal to a preset read time threshold, the corresponding read linked list is determined as the target read linked list. The preset read time threshold may be a typical value of the execution time of a read instruction (e.g., NAND read) disclosed by a NAND manufacturer.

[0065] Each target read list is processed in turn, and a query instruction is sent to the NAND unit corresponding to the target read list to check whether the read instruction has been completed. If the read instruction has not been completed, the next target read list is processed. If the read instruction is completed, it means that the data corresponding to the read request at the head of the link in the target read list has been read into the register of the NAND unit.

[0066] For the target read linked list whose read instruction has been executed, first send a DMA instruction to the corresponding NAND unit according to the NAND address corresponding to the read request information of the linked list header, so that the DMA controller reads the data corresponding to the NAND address from the register of the NAND unit and writes it into the memory. The DMA instruction issuance time of the read request information of the linked list header in the target read linked list is updated to the current system time, and the read request information of the linked list header in the target read linked list is removed from the target read linked list and added to the end of the DMA linked list corresponding to the same NAND unit identifier. It should be noted that after the target read linked list has been processed, the read request information in the DMA linked list can continue to be processed.

[0067] It can be seen that the embodiment of the present invention uses the read instruction execution time to quickly filter out the target read linked list of the query instruction (query whether the read instruction is completed) that needs to be issued, and only processes the target read linked list, which can avoid the traversal operation of all read linked lists and effectively reduce the time to determine whether the read instruction is completed, thereby improving the efficiency of data reading.

[0068] Optionally, a possible implementation method for issuing a DMA instruction is provided below. Figure 1 The sub-steps of step S30 may include:

[0069] The DMA instruction completion time is determined according to the preset data volume and the reading rate of the DMA instruction; the DMA chain list whose DMA instruction execution time corresponding to the read request information of the chain list header reaches the DMA instruction completion time is determined as the target DMA chain list; if the data corresponding to the read request information of the chain list header in the target DMA chain list has been read into the memory, the read request information of the chain list header in the target DMA chain list is removed, and the state of the NAND unit corresponding to the target DMA chain list is set to the idle state.

[0070] In an embodiment of the present invention, a NAND unit reads and writes data in units of pages. For example, the amount of data stored in each page can be set as a preset data amount. The ratio of the preset data amount to the read rate of the DMA instruction is determined as the DMA instruction completion time. The difference between the current system time and the DMA instruction issuance time of the read request information of the link head in the DMA linked list is determined as the DMA instruction execution time corresponding to the read request information of the link head. When the DMA instruction execution time corresponding to the read request information of the link head is greater than or equal to the DMA instruction completion time, the corresponding DMA linked list is determined as the target DMA linked list.

[0071] Each target DMA list is processed in turn, and a query command is sent to the corresponding NAND unit of the target DMA list to check whether the DMA instruction has been completed. If the DMA instruction has not been completed, the next target DMA list is processed. If the DMA instruction is completed, it means that the data corresponding to the read request of the list head in the target DMA list has been read into the memory.

[0072] For the target DMA linked list where DMA instructions have been executed, the read request information at the link list header is removed from the target DMA linked list, and the data corresponding to the removed read request information in the memory is returned to the host. The NAND cell corresponding to the target DMA linked list is then retrieved based on the NAND cell identifier, and the state of the corresponding NAND cell is set to idle. It should be noted that after the target DMA linked list is processed, the cache linked list, read linked list, and DMA linked list are processed in a loop until all data read by the host is transmitted to the host.

[0073] It can be seen that the embodiment of the present invention uses the DMA instruction execution time to quickly filter out the target DMA linked list of the query instruction (query whether the DMA instruction is completed) that needs to be issued, and only processes the target DMA linked list, which can avoid the traversal operation of all DMA linked lists and effectively reduce the time for determining whether the DMA instruction is completed, thereby improving the efficiency of data reading.

[0074] Optionally, a possible implementation of how to process a new read request is provided below.

[0075] Please refer to Figure 2 , the method further comprises the following steps:

[0076] Step S40: When a pending read request is received, a NAND address of the pending read request is determined according to the logical address of the pending read request.

[0077] In an embodiment of the present invention, upon receiving a read request from a host (i.e., a pending read request), the corresponding physical address is searched in an address mapping table based on the logical address of the pending read request to obtain the NAND address of the pending read request. The address mapping table is used to record the correspondence between logical addresses and NAND addresses, where the NAND address is the physical address of the NAND cell where the data corresponding to the pending read request is stored.

[0078] Step S50: determining the NAND unit to be processed according to the NAND address of the read request to be processed.

[0079] In the embodiment of the present invention, the NAND address of the pending read request is parsed to obtain the pending NAND unit identifier, and the NAND unit corresponding to the pending NAND unit identifier is the pending NAND unit.

[0080] Step S60: Generate read request information of the pending read request according to the NAND address of the pending read request.

[0081] Step S70 , obtaining a cache linked list corresponding to the NAND unit to be processed, and adding the read request information of the read request to be processed to the cache linked list corresponding to the NAND unit to be processed.

[0082] In an embodiment of the present invention, a read request information corresponding to a pending request is applied for and initialized, the NAND address of the pending read request is recorded in the newly applied read request information, the read request information of the pending request is obtained, and the corresponding cache linked list is obtained according to the pending NAND unit identifier. If the cache linked list corresponding to the pending NAND unit identifier exists, the read request information of the pending read request is added to the end of the cache linked list corresponding to the pending NAND unit identifier.

[0083] As can be seen, the embodiment of the present invention sets up a separate cache linked table for each NAND cell and stores read requests accessing the same NAND cell in the cache linked table corresponding to the NAND cell. By setting up a separate cache linked table for each NAND cell, read requests can be managed in an orderly manner and processed in a timely manner, laying a solid foundation for improving data reading efficiency.

[0084] Optionally, a possible implementation method for obtaining the cache linked list is provided below. Figure 2 The sub-step of obtaining the cache linked list corresponding to the NAND unit to be processed in step S70 may include:

[0085] If the corresponding cache linked list does not exist for the NAND unit to be processed, a new cache linked list for the NAND unit to be processed is created.

[0086] In an embodiment of the present invention, if the cache linked list corresponding to the identifier of the NAND unit to be processed does not exist, a new cache linked list is created, and the identifier of the NAND unit to be processed is used to identify the newly created cache linked list to obtain the cache linked list corresponding to the NAND unit to be processed. This can realize the dynamic creation of a cache linked list for the NAND unit, while improving the data reading efficiency and reducing the cache resource occupancy as much as possible.

[0087] It should be noted that in addition to dynamically creating cache lists for NAND cells, read lists and DMA lists corresponding to NAND cells are also dynamically created when read request information is added to the read list or DMA list. Furthermore, when the cache list, read list, or DMA list is empty, it is promptly destroyed to ensure the proper use of cache resources.

[0088] In order to more clearly illustrate the data reading method provided in the embodiment of the present application, an exemplary description is given in combination with a comparison with the prior art.

[0089] In the prior art, all linked list nodes corresponding to read requests are managed using the same linked list. Upon receiving a read request from the host, the physical address of the NAND unit storing the corresponding data is searched in an address mapping table based on the logical address of the read request, obtaining the NAND address of the read request. Based on the NAND address, a linked list node corresponding to the read request is generated and added to the end of the linked list.

[0090] When processing a read request, the existing technology needs to traverse each linked list node in the linked list and issue corresponding instructions to the linked list nodes that need to perform NAND operations, including read instructions, query instructions for checking whether the read instructions are completed, DMA instructions, and query instructions for detecting whether the DMA instructions are completed. When there are more NAND units, there are correspondingly more linked list nodes, and the overhead caused by traversing the linked list has a great impact on the reading performance.

[0091] As a possible implementation, for example, there are four NAND cells, the linked list depth is 32, and the fourth NAND cell is idle. In extreme cases, it may be necessary to traverse all linked list nodes before finding a matching read request, or even find that no matching read request exists. Traversing each linked list node requires obtaining the linked list node address, verifying the node's legitimacy, and then determining the status of the corresponding NAND cell.

[0092] Assume that a matching read request is found only after traversing halfway through the linked list (i.e., the 16th linked list node). For each linked list node traversed, the node must first be visited to determine if it is valid, and then compared to see if it meets the requirements. Assuming a CPU frequency of 200 Hz, each execution step requires 3 clock cycles, or 15 nanoseconds, so a complete traversal takes 0.75 microseconds (16 * 3 * 15). A read request requires traversing the execution instructions to execute the read command, the query instruction to check if the read command is complete, and the query instruction to detect if the DMA instruction is complete. This results in a performance loss of approximately 2 microseconds (0.75 * 3). In most cases, after traversing, no idle NAND cells are found, resulting in an ineffective traversal. Reading 4K of data typically takes about 12 microseconds. Reducing ineffective linked list traversals can improve performance by approximately 20%.

[0093] In an embodiment of the present invention, an independent cache linked list, read linked list and DMA linked list are dynamically created for each NAND unit with a read request. The cache linked list that needs to issue a read instruction is screened in the idle state, and there is no need to traverse it at all, so that the read instruction can be issued to the NAND unit in the idle state as soon as possible. In addition, the read linked list and the DMA linked list are preliminarily screened based on the read instruction issuance time and the DMA instruction issuance time, so as to avoid performing query operations on the NAND unit corresponding to each read linked list or the NAND unit corresponding to the DMA linked list. The read request information that needs to perform the NAND operation can be found in the cache linked list, the read linked list and the DMA linked list as soon as possible, so as to avoid invalid access to the NAND unit, thereby performing concurrent access to different NAND units, saving data reading time as much as possible, and improving the read performance of the storage device.

[0094] Based on the same inventive concept, the basic principles and technical effects of the data reading device provided in the embodiment of the present invention are the same as those in the above embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above embodiment.

[0095] Please refer to Figure 3 , Figure 3 The data reading device 300 provided in the embodiment of the present invention is a block diagram of the data reading device 300. The data reading device 300 includes a reading module 301, a direct access module 302 and a processing module 303.

[0096] The read module 301 is configured to issue a read instruction to the corresponding NAND unit based on the read request information in the cache list when the NAND unit corresponding to the cache list is in an idle state, and to migrate the read request information of the issued read instruction from the cache list to the corresponding read list;

[0097] The direct access module 302 is configured to issue a DMA instruction to the corresponding NAND unit based on the read request information of the completed data read in the target read linked list, and migrate the read request information of the issued DMA instruction from the read linked list to the corresponding DMA linked list; the target read linked list is determined according to the read instruction execution time corresponding to the read request information in the linked list header;

[0098] The processing module 303 is used to remove the read request information of the target DMA linked list that has completed data reading; the target DMA linked list is determined according to the DMA instruction execution time corresponding to the read request information in the linked list header; the NAND unit has a one-to-one correspondence with the cache linked list, the read linked list, and the DMA linked list.

[0099] In summary, the data reading device provided by the embodiment of the present invention dynamically creates a cache linked list, a read linked list, and a DMA linked list for NAND cells with read requests. The cache linked list is used to store read request information for the same NAND cell for which no read instructions have been issued, the read linked list is used to store read request information for the same NAND cell for which read instructions have been issued, and the DMA linked list is used to store read request information for the same NAND cell for which DMA instructions have been issued. When processing read requests, the device quickly filters out read request information that requires an operation on the NAND cell based on the idle state, read instruction execution time, and DMA instruction execution time, thereby avoiding invalid traversal of the linked lists and being able to concurrently process read request information in different linked lists, thereby effectively improving data reading performance.

[0100] Optionally, the read module 301 is specifically used to send a read instruction to the corresponding NAND unit based on the NAND address of the read request information of the link header in the cache link list; update the read instruction sending time of the read request information of the link header in the cache link list, and set the status of the corresponding NAND unit to the working status.

[0101] Optionally, the direct access module 302 is specifically configured to determine a read linked list whose execution time of a read instruction corresponding to the read request information of the linked list head reaches a preset read time threshold as a target read linked list;

[0102] If the data corresponding to the read request information of the link header in the target read linked list has been read into the register of the NAND unit, a DMA instruction is issued to the corresponding NAND unit based on the read request information of the link header in the target read linked list, and the DMA instruction issuance time of the read request information of the link header in the target read linked list is updated.

[0103] Optionally, the processing module 303 is specifically used to determine the DMA instruction completion time based on the preset data volume and the reading rate of the DMA instruction; determine the DMA linked list whose DMA instruction execution time corresponding to the read request information of the linked list header reaches the DMA instruction completion time as the target DMA linked list; if the data corresponding to the read request information of the linked list header in the target DMA linked list has been read into the memory, remove the read request information of the linked list header in the target DMA linked list, and set the state of the NAND unit corresponding to the target DMA linked list to the idle state.

[0104] Optionally, the processing module 303 is also used to, when receiving a pending read request, determine the NAND address of the pending read request based on the logical address of the pending read request; determine the pending NAND unit based on the NAND address of the pending read request; generate read request information of the pending read request based on the NAND address of the pending read request; obtain a cache linked list corresponding to the pending NAND unit, and add the read request information of the pending read request to the cache linked list corresponding to the pending NAND unit.

[0105] Optionally, the processing module 303 is specifically configured to create a new cache linked list for the NAND unit to be processed if a corresponding cache linked list does not exist for the NAND unit to be processed.

[0106] Please refer to Figure 4 , Figure 4 A block diagram of a storage device 400 is provided for an embodiment of the present invention. Storage device 400 includes NAND flash memory 401 and memory 402. The components of NAND flash memory 401 and memory 402 are electrically connected to each other, either directly or indirectly, to enable data transmission or exchange. For example, these components may be electrically connected via one or more communication buses or signal lines.

[0107] The NAND flash memory 401 includes multiple NAND cells for storing data, and the memory 402 is used to store computer programs and perform corresponding functions. For example, when the memory 402 executes the computer program, the data reading method disclosed in the above embodiments can be implemented.

[0108] It should be understood that Figure 4 The structure shown is only a schematic diagram of the structure of the storage device 400. The storage device 400 may also include Figure 4 More or fewer components than shown, or with Figure 4 Different configurations shown. Figure 4 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0109] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by the memory 402, the data reading method disclosed in the above embodiments is implemented.

[0110] The embodiment of the present invention further provides a program product, which implements the data reading method disclosed in the above embodiments when executed by the memory 402 .

[0111] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a portion of code, and the module, program segment or a portion of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0112] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0113] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0114] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A data reading method, characterized in that: The method comprises: When a NAND unit corresponding to a cache linked list is in an idle state, a read instruction is issued to the corresponding NAND unit based on the read request information in the cache linked list, and the read request information of the issued read instruction is migrated from the cache linked list to the corresponding read linked list; Based on the read request information of the completed data read in the target read linked list, a DMA instruction is issued to the corresponding NAND unit, and the read request information of the issued DMA instruction is migrated from the read linked list to the corresponding DMA linked list; the target read linked list is determined according to the read instruction execution time corresponding to the read request information of the linked list header; The read request information of the target DMA linked list that has completed data reading is removed; the target DMA linked list is determined according to the DMA instruction execution time corresponding to the read request information of the linked list header; the NAND unit has a one-to-one correspondence with the cache linked list, the read linked list, and the DMA linked list.

2. The data reading method according to claim 1, wherein: The sending of a read instruction to the corresponding NAND unit based on the read request information in the cache linked list includes: Based on the NAND address of the read request information of the link header in the cache link list, a read instruction is issued to the corresponding NAND unit; The read instruction issuing time of the read request information of the link list header in the cache link list is updated, and the state of the corresponding NAND unit is set to the working state.

3. The data reading method according to claim 1, wherein: The sending of a DMA instruction to a corresponding NAND unit based on the read request information of the completed data read in the target read linked list includes: Determine the read linked list whose read instruction execution time corresponding to the read request information of the linked list head reaches the preset read time threshold as the target read linked list; If the data corresponding to the read request information of the link header in the target read linked list has been read into the register of the NAND unit, a DMA instruction is issued to the corresponding NAND unit based on the read request information of the link header in the target read linked list, and the DMA instruction issuance time of the read request information of the link header in the target read linked list is updated.

4. The data reading method according to claim 1, wherein: The removing of the read request information of the completed data reading in the target DMA linked list includes: Determining a DMA instruction completion time according to a preset data amount and a reading rate of the DMA instruction; Determine a DMA linked list whose DMA instruction execution time corresponding to the read request information of the linked list header reaches the DMA instruction completion time as a target DMA linked list; If the data corresponding to the read request information of the link header in the target DMA linked list has been read into the memory, the read request information of the link header in the target DMA linked list is removed, and the state of the NAND unit corresponding to the target DMA linked list is set to an idle state.

5. The data reading method according to claim 1, wherein: The method further comprises: When receiving a pending read request, determining a NAND address of the pending read request according to the logical address of the pending read request; Determine a NAND unit to be processed according to the NAND address of the pending read request; generating read request information of the pending read request according to the NAND address of the pending read request; A cache linked list corresponding to the to-be-processed NAND unit is obtained, and read request information of the to-be-processed read request is added to the cache linked list corresponding to the to-be-processed NAND unit.

6. The data reading method according to claim 5, characterized in that: The obtaining of the cache linked list corresponding to the NAND unit to be processed includes: If the cache linked list corresponding to the NAND unit to be processed does not exist, a new cache linked list for the NAND unit to be processed is created.

7. A data reading device, characterized in that: The device comprises: a read module, configured to, when a NAND cell corresponding to a cache linked list is in an idle state, issue a read instruction to the corresponding NAND cell based on the read request information in the cache linked list, and migrate the read request information of the issued read instruction from the cache linked list to the corresponding read linked list; A direct access module is configured to issue a DMA instruction to a corresponding NAND unit based on the read request information of the target read linked list for which data has been read, and to migrate the read request information of the issued DMA instruction from the read linked list to the corresponding DMA linked list; the target read linked list is determined according to the read instruction execution time corresponding to the read request information in the linked list header; A processing module is used to remove the read request information of the target DMA linked list for which data reading has been completed; the target DMA linked list is determined according to the DMA instruction execution time corresponding to the read request information in the link list header; the NAND unit has a one-to-one correspondence with the cache linked list, the read linked list, and the DMA linked list.

8. A storage device, characterized in that: It comprises a NAND flash memory and a memory, wherein the NAND flash memory stores data; and the memory can execute a computer program to implement the data reading method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a memory, the data reading method according to any one of claims 1 to 6 is implemented.

10. A program product, characterized in that When the program product is executed by a memory, the data reading method according to any one of claims 1 to 6 is implemented.

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