Low-power-consumption storage system, method and equipment and storage medium

Abstract

The invention provides a low-power-consumption storage system, method and device and a storage medium, and is applied to the technical field of computers, the system comprises a host and a host bus adapter HBA, and the host is connected with the HBA through a PCIe bus; the HBA comprises a first controller, a processor unit and a cache unit, and the first controller is used for obtaining a first target request from a submission queue of a host memory; the cache unit is used for storing to-be-processed information carried by the first target request; the processor unit is used for processing the to-be-processed information and generating response information of the to-be-processed information according to the type of the first target request; and writing the response information into the cache unit, and feeding back the response information to a completion queue of the host memory. According to the technical scheme, a transmission mechanism is optimized, so that power consumption is greatly reduced, the operation cost pressure is relieved, and heat is reduced so as to reduce heat dissipation cost. And high-efficiency data transmission and system stability are guaranteed in performance.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a low-power storage system, method, device, and storage medium. Background Art

[0002] SATA (Serial Advanced Technology Attachment) is a serial interface standard used to connect computers and storage devices. It supports hot plugging and has higher data transfer rates and better signal integrity than the parallel ATA interface. It is widely used in personal computers and servers.

[0003] Mechanical hard drives, especially SATA HDDs, consume relatively high power. For enterprise data centers, deploying large numbers of these drives and operating them for extended periods of time consumes significant amounts of electricity, significantly increasing electricity bills and placing significant pressure on operating costs. Furthermore, high power consumption generates significant heat, requiring enterprises to invest in additional cooling equipment and energy to maintain a suitable data center temperature and ensure the proper operation of hard drives and other equipment, further driving up operating costs. Under high load, mechanical hard drives' power consumption climbs even higher, causing drive temperatures to rise, impacting read / write speeds and response times, and reducing overall storage system performance. Prolonged high power consumption and high temperatures accelerate the aging of hard drive components, increasing the risk of failure and reducing drive reliability and lifespan, threatening the security of enterprise data and the stability of storage systems. Summary of the Invention

[0004] The present application provides a low-power storage system, method, device and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present application, a low-power storage system is provided, characterized in that the system includes: a host and a host bus adapter HBA, the host being connected to the HBA via a PCIe bus; the HBA including a first controller, a processor unit, and a cache unit, wherein:

[0006] The first controller is configured to obtain a first target request from a submission queue of a host memory;

[0007] The cache unit is configured to store the to-be-processed information carried by the first target request;

[0008] The processor unit is configured to process the to-be-processed information according to the type of the first target request, generate response information of the to-be-processed message, and write the response information into a cache unit;

[0009] The first controller is further configured to feed the response information back to the completion queue of the host memory.

[0010] In one embodiment, the system further includes a plurality of hard disk storage devices connected to the HBA via a SATA bus; the HBA further includes a host memory buffer, the host memory buffer being arranged on the memory side of the host and including a plurality of buffer partitions; the first controller includes a plurality of namespaces;

[0011] The processor unit is further configured to establish a first mapping relationship between the namespace and the hard disk storage device, and to establish a second mapping relationship between the hard disk storage device and the buffer zone.

[0012] In one embodiment, before processing the information to be processed and generating response information of the message to be processed, the processor unit is configured to:

[0013] Determining a target hard disk storage device according to the first target request and the first mapping relationship;

[0014] A target buffer zone partition is determined according to the target hard disk storage device and the second mapping relationship.

[0015] In one embodiment, the first target request includes user data and a command word;

[0016] When the first target request is a write request, the processor unit, when processing the to-be-processed information and generating response information of the to-be-processed message according to the type of the first target request, is specifically configured to:

[0017] Transferring the user data to the target buffer partition;

[0018] A response word for the command word is generated according to the user data to obtain the response information.

[0019] In one embodiment, when the first target request is a read request, the processor unit, when processing the to-be-processed information and generating response information of the to-be-processed message according to the type of the first target request, is specifically configured to:

[0020] querying in the target buffer partition whether there is user data of the first target request;

[0021] If the user data of the first target request exists in the target buffer partition, the user data is sent to the memory address indicated by the first target request, and a response word is generated according to the user data to obtain the response information.

[0022] In one embodiment, the HBA further includes a second controller;

[0023] If the user data of the first target request does not exist in the target buffer partition, the second controller is used to read the user data from the target hard disk storage device, send the user data to the memory address specified by the first target request, and generate a response word based on the user data to obtain the response information.

[0024] In one embodiment, when there is a first target request and it is a write request:

[0025] The second controller is further configured to perform protocol conversion on the first target request and send the converted request to a corresponding target hard disk storage device, so as to write the user data into the target hard disk storage device;

[0026] When there are multiple first target requests and they are write requests:

[0027] The processor unit is further configured to sort and aggregate the multiple first target requests according to a preset rule to obtain at least one second target request;

[0028] The second controller is further configured to perform protocol conversion on the second target request and send the converted request to the corresponding target hard disk storage device, so as to write the user data into the target hard disk storage device.

[0029] According to a second aspect of the present application, a low-power storage method is provided, which is applied to a low-power storage system. The system includes a host and a host bus adapter (HBA). The host is connected to the HBA via a PCIe bus. The HBA includes a first controller, a processor unit, and a cache unit. The method includes:

[0030] Obtaining, by the first controller, a first target request from a submission queue of a host memory;

[0031] Using the cache unit to store the to-be-processed information carried by the first target request;

[0032] Processing the information to be processed, generating response information of the information to be processed, and writing the response information into the cache unit according to the type of the first target request, by the processor unit;

[0033] The response information is fed back to the completion queue of the host memory through the first controller.

[0034] In one embodiment, the system further includes a plurality of hard disk storage devices; the plurality of hard disk storage devices are connected to the HBA via a SATA bus; the HBA further includes a host memory buffer, the host memory buffer being arranged on a memory side of the host and including a plurality of buffer partitions; the first controller includes a plurality of namespaces, and the method further includes:

[0035] A first mapping relationship between the namespace and the hard disk storage device is established by the processor unit, and a second mapping relationship between the hard disk storage device and the buffer zone is established.

[0036] In one embodiment, before the processor unit processes the information to be processed and generates response information of the information to be processed, the method further includes:

[0037] Determining a target hard disk storage device according to the first target request and the first mapping relationship;

[0038] A target buffer zone partition is determined according to the target hard disk storage device and the second mapping relationship.

[0039] In one embodiment, the first target request includes user data and a command word. When the first target request is a write request, the processor unit processes the information to be processed and generates response information of the information to be processed according to the type of the first target request, specifically including:

[0040] Transferring the user data to the target buffer partition;

[0041] A response word for the command word is generated according to the user data to obtain the response information.

[0042] In one embodiment, when the first target request is a read request, processing the to-be-processed information and generating response information of the to-be-processed information by the processor unit according to the type of the first target request specifically includes:

[0043] querying in the target buffer partition whether there is user data of the first target request;

[0044] If the user data of the first target request exists in the target buffer partition, the user data is sent to the memory address indicated by the first target request, and a response word is generated according to the user data to obtain the response information.

[0045] In one embodiment, the HBA further includes a second controller, and when the target buffer partition does not contain user data of the first target request, the method further includes:

[0046] Reading the user data from the target hard disk storage device through the second controller;

[0047] Sending the user data to the memory address specified by the first target request;

[0048] A response word is generated according to the user data to obtain the response information.

[0049] In one embodiment, when there is a first target request and it is a write request, the method further includes:

[0050] The second controller performs protocol conversion on the first target request and sends the converted request to the corresponding target hard disk storage device, so as to write the user data into the target hard disk storage device;

[0051] When there are multiple first target requests and they are write requests, the method further includes:

[0052] sorting and aggregating the plurality of first target requests according to a preset rule by the processor unit to obtain at least one second target request;

[0053] The second controller performs protocol conversion on the second target request and sends it to the corresponding target hard disk storage device, so as to write the user data into the target hard disk storage device.

[0054] According to a third aspect of the present application, an electronic device is provided, including:

[0055] at least one processor; and

[0056] a memory communicatively connected to the at least one processor; wherein,

[0057] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0058] According to a fourth aspect of the present application, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method described in the present application.

[0059] The present application discloses a low-power storage system, method, device and storage medium. The system includes: a host and a host bus adapter HBA, wherein the host is connected to the HBA via a PCIe bus; the HBA includes a first controller, a processor unit and a cache unit, wherein: the first controller is used to obtain a first target request from a submission queue of the host memory; the cache unit is used to store the pending information carried by the first target request; the processor unit is used to process the pending information and generate response information of the pending message according to the type of the first target request; the response information is written into the cache unit and fed back to the completion queue of the host memory. In terms of power consumption, the technical solution of the present application optimizes the transmission mechanism to significantly reduce energy consumption, reduce electricity bills and alleviate operating cost pressures. In terms of heat dissipation, reduced power consumption reduces heat generation and reduces heat dissipation costs. In terms of performance, it ensures efficient data transmission, improves read and write speeds and responsiveness. In terms of reliability and lifespan, it reduces hard disk power consumption and temperature, reduces failures, and enhances data security and storage system stability.

[0060] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an illustrative and non-limiting manner, in which:

[0062] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0063] Figure 1 A schematic diagram of the structure of a low-power storage system according to an embodiment of the present application is shown;

[0064] Figure 2 A schematic diagram of the implementation process of sorting and aggregation by processor units according to an embodiment of the present application is shown;

[0065] Figure 3 The schematic diagram of the implementation process of the low power storage method of the embodiment of the present application is shown Figure 1 ;

[0066] Figure 4 The schematic diagram of the implementation process of the low power storage method of the embodiment of the present application is shown Figure 2 ;

[0067] Figure 5 A schematic diagram of the structure of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0068] In order to make the purpose, features, and advantages of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0069] Before further explaining the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0070] PCIe: A high-speed serial computer expansion bus standard, the full name is Peripheral Component Interconnect Express. It uses an efficient point-to-point connection protocol, has high-speed, low-latency, high-bandwidth transmission characteristics, supports hot plugging, and is widely used in various high-performance components and peripherals in modern computer systems. It is the core technology for connecting modern high-performance hardware.

[0071] NVMe: NVMe (Non-Volatile Memory Express) is a communication protocol based on the PCIe (PCI-Express) interface, designed specifically for SSDs (solid-state drives) to provide high-speed, low-latency storage access.

[0072] NVMe communication is implemented using a paired submission queue (SQ) and completion queue (CQ) mechanism. The upstream host software places commands into the SQ. The controller places completion results into the corresponding completion queue (CQ). The SQ and CQ queues are allocated in the upstream host's memory.

[0073] RAID (Redundant Array of Independent Disks) is a data storage technology that combines multiple independent physical hard drives into a single logical storage unit. This improves the storage system's data read and write speeds, enhances data redundancy, and improves fault tolerance. Different RAID levels can achieve different performance and security goals.

[0074] SATA (Serial Advanced Technology Attachment) is an interface standard for connecting computers and storage devices. It uses serial transmission and supports hot plugging. Compared to the previous Parallel ATA (Parallel ATA) interface, SATA offers higher data transfer rates, better signal integrity, and excellent compatibility. It has become one of the mainstream interface standards for modern computer storage devices and is widely used in personal computers, servers, and other devices.

[0075] This application provides a low-power storage system, such as Figure 1 As shown, the system includes: a host and a host bus adapter HBA. The host bus adapter (HBA) is a hardware component that connects the host and the storage device and is responsible for protocol conversion (such as NVMe to SATA) and data transmission.

[0076] The upstream of the HBA is connected to the host system via the PCIe bus, fully supports the NVMe standard protocol, and appears as a standard NVMe storage device on the host side. Figure 1 As shown, the HBA includes a first controller, a processor unit and a cache unit, wherein:

[0077] The first controller is configured to obtain a first target request from a submission queue of a host memory.

[0078] In this example, the first controller is an NVMe controller that complies with the NVMe specification and implements the standard functions defined therein. Specifically, the host sends the NVMe standard I / O request R host The first controller receives the I / O request from the host system from the submission queue (SQ) in the host memory, which is specified by the NVMe protocol.

[0079] The cache unit is used to store the to-be-processed information carried by the first target request.

[0080] In this example, the cache unit acts as a temporary storage unit inside the HBA to cache I / O request data from the host to alleviate the speed difference between the NVMe protocol (based on the high-speed PCIe bus) and downstream low-speed storage devices (such as Serial Advanced Technology Attachment Hard Disk Drive, SATA HDD), avoiding data congestion or delay caused by protocol conversion.

[0081] The processor unit is configured to process the information to be processed, generate response information of the message to be processed, and write the response information into a cache unit according to the type of the first target request.

[0082] The first controller is further configured to feed the response information back to the completion queue of the host memory.

[0083] In this example, after the operation of the first target request is completed, the execution result of the request is fed back to the host through the CQ (Completion Queue), thereby fully fulfilling the I / O interaction process specified by the NVMe protocol specification. Specifically: the processor unit generates a completion queue entry that complies with the NVMe specification, which contains the operation status (success / failure) and data address information of the first target request, and writes the response information back to the cache unit, and finally feeds back the response information to the completion queue of the host memory through the first controller.

[0084] The present disclosure provides a low-power storage system, which includes: a host and a host bus adapter HBA, the host is connected to the HBA via a PCIe bus; the HBA includes a first controller, a processor unit and a cache unit, wherein: the first controller is used to obtain a first target request from a submission queue of the host memory; the cache unit is used to store the pending information carried by the first target request; the processor unit is used to process the pending information and generate response information of the pending message according to the type of the first target request; the response information is written into the cache unit and fed back to the completion queue of the host memory. In terms of power consumption, the technical solution of the present application optimizes the transmission mechanism to significantly reduce energy consumption, reduce electricity expenses and alleviate operating cost pressures. In terms of heat dissipation, reduced power consumption reduces heat generation and reduces heat dissipation costs. In terms of performance, it ensures efficient data transmission, improves read and write speeds and responsiveness. In terms of reliability and lifespan, it reduces hard disk power consumption and temperature, reduces failures, and enhances data security and storage system stability.

[0085] In one example, if Figure 1 As shown, the system also includes multiple hard disk storage devices, which are connected to the HBA via a SATA bus; the HBA also includes a host memory buffer, which is set on the memory side of the host and includes multiple buffer partitions; the first controller includes multiple namespaces; the processor unit is also used to establish a first mapping relationship between the namespace and the hard disk storage device, and to establish a second mapping relationship between the hard disk storage device and the buffer partition.

[0086] In this example, the system further includes multiple hard disk storage devices (such as SATA HDDs) connected to the HBA via a SATA bus; the HBA further includes a host memory buffer (HMB) provided on the memory side of the host and divided into multiple logical buffer partitions; multiple namespaces (NS) are configured in the first controller (NVMe controller); the processor unit is further configured to establish a first mapping relationship between the namespace and the hard disk storage device, and a second mapping relationship between the hard disk storage device and the buffer partition, as follows:

[0087] Namespaces (NS) are a core concept defined in the Non-Volatile Memory Express (NVMe) protocol. They abstract the storage resources of physical storage devices (such as SATA HDDs and SSDs) into logical storage units, presenting them as independent logical disks on the host. Each namespace can be managed independently and supports different access permissions, data formats, and performance configurations.

[0088] HBA is used to manage the working mode of the hard disk array of the downstream hard disk storage device, and establish the mapping relationship between the NVMe namespace NS (Namespace) and the hard disk storage device, that is, the first mapping relationship. The first mapping relationship can be one-to-one, one-to-many or many-to-one. Figure 1 As shown, the NVMe namespace NS[1] presented by the NVMe controller is mapped to the downstream hard disk storage device [1]; the NVMe namespace NS[2] presented by the NVMe controller is mapped to the downstream hard disk storage device hard disk [2] and hard disk storage device [3]. It should be noted that this application does not restrict the mapping relationship between namespaces and hard disk storage devices, as long as each NVMe namespace NS corresponds to the storage space of a specific hard disk storage device.

[0089] HMB (Host Memory Buffer) is a feature introduced in the NVMe 1.2 standard that allows the NVMe controller to use the host system's memory (RAM) as a buffer, reducing the need for DRAM within the NVMe device, thereby lowering costs and improving performance. With HMB, NVMe devices can fully utilize the high speed and large capacity of the host memory to store NVMe command queues, completion queues, and other management information, thereby reducing reliance on the DRAM within the NVMe device.

[0090] In addition to connecting to the host, the HBA also connects to multiple hard disk storage devices downstream through the SATA bus and is responsible for identifying and initializing the hard disk storage devices, such as scanning downstream hard disk storage devices to obtain device identification (such as HDDID) and storage capacity; the HBA is also responsible for planning the HMB buffer located in the host side memory and establishing a mapping relationship between the downstream hard disk storage devices and the partitions in the HMB buffer, that is, the second mapping relationship. Figure 1 As shown, the storage data of SATA HDD[1] corresponds to HMB buffer partition[1]; the storage data of SATA HDD[2] corresponds to HMB buffer partition[2]. It should be noted that this application does not restrict the mapping relationship between hard disk storage devices and buffer partitions. It only needs to ensure that each downstream hard disk storage device corresponds to a buffer partition in the HMB.

[0091] In one example, before processing the information to be processed and generating response information for the message to be processed, the processor unit is used to: determine the target hard disk storage device based on the first target request and the first mapping relationship; and determine the target buffer partition based on the target hard disk storage device and the second mapping relationship.

[0092] In this example, when the host sends the first target request through the NVMe protocol, the processor unit parses the namespace identifier (NS ID) and the logical block address (LBA) in the first target request, and queries the first mapping relationship T nS , associate the namespace with the target hard disk storage device (such as SATA HDD) (for example, NS[1] is mapped to HDD[1]), thereby determining the target hard disk storage device. Subsequently, according to the second mapping relationship T buf , locate the target buffer partition in the host memory buffer corresponding to the determined target hard disk storage device (such as HDD[1]→HMB buffer partition[1]).

[0093] Through the double-layer mapping mechanism (namespace → target hard disk storage device → target buffer partition), the host's first target request is converted step by step into the precise location of the physical storage location and buffer area. For example, if the request is for the namespace NS[2] and the LBA range is 0x1000-0x2000, the processor unit uses the first mapping relationship T ns Determine that NS[2] corresponds to SATAHDD[2] and SATA HDD[3], and then according to the second mapping relationship T bufDirect data operations to HMB buffer partitions [2] and [3]. Through this design, the system achieves data path isolation and refined cache management: each SATA HDD occupies an exclusive HMB buffer partition, avoiding conflicts in the storage of data from multiple hard drives in the buffer. At the same time, combined with the high-speed access characteristics of HMB, data read and write operations are completed in the buffer first, and physical hard drives are accessed only when necessary, thereby reducing the frequency of hard drive activation. This mechanism significantly reduces the power consumption of SATA HDDs, and at the same time, through the dynamic management of mapping relationships, ensures the flexibility and scalability of the system.

[0094] In one example, the first target request includes user data and a command word.

[0095] When the first target request is a write request, the processor unit processes the pending information and generates response information of the pending message according to the type of the first target request, and is specifically used to: transfer the user data to the target buffer partition; generate a response word for the command word based on the user data to obtain the response information.

[0096] In this example, the system software running on the internal processor of the HBA parses the information in the command word of the first target request to identify the command operation type of the first target request and determines whether the request is a data write request or a data read request.

[0097] When the first target request is a write request, the processor unit performs the following operations:

[0098] Parse the namespace identifier and logical block address in the write request, determine the target hard disk storage device based on the first mapping relationship, and associate it with the corresponding target buffer partition through the second mapping relationship. Through direct memory access (DMA) technology, user data is directly moved from the internal cache unit of the HBA to the target buffer partition of the HMB, thereby eliminating the need for CPU intervention and significantly improving transmission efficiency. At the same time, the HBA system software complies with the message format specified by the NVMe standard, generates a response word corresponding to the command word of the first target request, that is, the response information, and sets the status information of the response word to 0, and then writes the response word to the cache unit in the HBA.

[0099] Finally, the NVMe controller returns the completion response word in the HBA cache unit to the CQ queue located in the host memory. At this point, the processing flow of the first target request from the host being a write request ends.

[0100] In one example, when the first target request is a read request, the processor unit processes the information to be processed and generates response information of the message to be processed according to the type of the first target request, and is specifically used to: query whether there is user data of the first target request in the target buffer partition; if there is user data of the first target request in the target buffer partition, send the user data to the memory address indicated by the first target request, and generate a response word based on the user data to obtain the response information.

[0101] In this example, when the first target request is a read request, the processor unit performs the following operations:

[0102] Parse the namespace identifier and logical block address in the read request, determine the target hard disk storage device based on the first mapping relationship, and associate it with the corresponding target buffer partition through the second mapping relationship. Query the target buffer partition to see whether there is user data matching the logical block address. If the user data of the first target request exists in the target buffer partition, transfer the user data directly from the target buffer partition to the memory address specified by the host request through direct memory access technology; if not, trigger the downstream SATA protocol conversion process. The specific conversion process will be described in detail in subsequent embodiments.

[0103] If the target buffer partition contains user data for the first target request, the system software in the HBA complies with the message format specified by the NVMe standard, generates a response word corresponding to the command word of the first target request, i.e., the response information, sets the status information of the response word to 0 (indicating normal completion of the operation), and then writes the response word to the cache unit in the HBA. Finally, the NVMe controller returns the completion response word in the HBA cache unit to the CQ queue in the host memory.

[0104] In one example, the HBA also includes a second controller; if the user data of the first target request does not exist in the target buffer partition, the second controller is used to read the user data from the target hard disk storage device, send the user data to the memory address specified by the first target request, and generate a response word based on the user data to obtain the response information.

[0105] In this example, the second controller is a SATA controller. If the user data of the first target request does not exist in the target buffer partition, the SATA controller of the HBA performs the following operations:

[0106] The second controller initiates a read operation on the target hard disk storage device via the SATA bus, retrieving user data from the hard disk's physical sectors. The read user data is sent directly to the host's requested memory address using direct memory access technology, eliminating CPU intervention and reducing latency.

[0107] If the target buffer partition contains user data for the first target request, the system software in the HBA complies with the message format specified by the NVMe standard, generates a response word corresponding to the command word of the first target request, i.e., the response information, sets the status information of the response word to 0 (indicating normal completion of the operation), and then writes the response word to the cache unit in the HBA. Finally, the NVMe controller returns the completion response word in the HBA cache unit to the CQ queue in the host memory.

[0108] HBAs serve as a critical bridge between host servers and external storage devices, converting the host server system's internal bus interface (such as PCIe) to an external storage device interface (such as SATA). This simplifies the design of host system external interface compatibility and reduces the complexity of host system design while enabling efficient data transfer between the host system and external storage devices. By providing efficient interface conversion, data transmission, and protocol processing capabilities, HBAs support storage system flexibility, performance, and scalability.

[0109] In one example, when there is a first target request and it is a write request: the second controller is also used to perform protocol conversion on the first target request and send it to the corresponding target hard disk storage device to write the user data to the target hard disk storage device; when there are multiple first target requests and they are write requests: the processor unit is also used to sort and aggregate the multiple first target requests according to preset rules to obtain at least one second target request; the second controller is also used to perform protocol conversion on the second target request and send it to the corresponding target hard disk storage device to write the user data to the target hard disk storage device.

[0110] In this example, when there is only one first target request and it is a write request, the second controller is used to perform protocol conversion on the first target request and send it to the corresponding target hard disk storage device to write the user data to the target hard disk storage device.

[0111] Similarly, when there are multiple first target requests and they are write requests, the processor unit needs to perform sorting and aggregation to reduce the access frequency of the second controller SATA HDD and improve the access efficiency of SATA transactions. Figure 2As shown, multiple write requests are received from the host side in chronological order, including IO[1], IO[2], IO[3], IO[4], IO[5], and IO[6]. After the HBA system software analyzes the characteristics of the six write requests, it is found that the LBA addresses accessed by IO[1], IO[2], and IO[3] are adjacent to LBA a, LBA c, and LBA b, respectively. They can be reordered according to the preset rules (for example, LBAa, LBA b, and LBA c), and aggregated to form a single sequential write request IO[1′] for the SATA HDD device; it is found that the LBA addresses accessed by IO[4], IO[5], and IO[6] are adjacent to LBA x, LBA z, and LBA y, respectively. They can be reordered according to the preset rules (for example, LBA x, LBA y, and LBA z), and aggregated to form a single sequential write request IO[2′] for the SATA HDD device. Obviously, through HMB's buffering, aggregation, and reordering, the initial six I / O random write requests from the host are transformed into two sequential write requests for the SATA HDD, effectively improving the access efficiency of the SATA HDD device, extending the idle window duration of the HDD device, and reducing the operating time of the HDD device.

[0112] Subsequently, the second controller (SATA controller) converts the aggregated second target request (NVMe protocol) into a command word that complies with the SATA protocol, and sends the converted command word to the target hard disk storage device through the SATA bus, and uses direct memory access to complete the user data write operation, for example, batch writing the aggregated user data to the hard disk physical sector.

[0113] The core functions of the solution described in this application are mainly implemented by the HBA system software, and the solution provides a high degree of flexibility in the selection of HMB cache management algorithms and strategies. This solution adopts the standard NVMe protocol upstream, which can be seamlessly compatible with the existing NVMe system drivers on the host side; it adopts the SATA controller downstream, which can be compatible with the mainstream SATA HDD devices on the market. With the help of the HMB cache area on the host side, the DRAM dependence of the HBA adapter is reduced, and the design cost is effectively reduced. By implementing strategies such as data buffering, aggregation, and sorting, the proportion of random access of downstream SATA standard I / O requests is reduced, and the frequency of SATA requests is reduced, thereby effectively reducing the operating power consumption of SATA HDD devices.

[0114] The present application also provides a low-power storage method, which is applied to a low-power storage system, wherein the system includes a host and a host bus adapter HBA, wherein the host is connected to the HBA via a PCIe bus, and the HBA includes a first controller, a processor unit, and a cache unit. Figure 3As shown, the method includes:

[0115] Step 301: Obtain a first target request from a submission queue of a host memory through the first controller.

[0116] In this example, the first controller is an NVMe controller that complies with the NVMe specification and implements the standard functions defined therein. Specifically, the host sends the NVMe standard I / O request R host The first controller receives the I / O request from the host system from the submission queue (SQ) in the host memory, which is specified by the NVMe protocol.

[0117] Step 302: Utilize the cache unit to store the to-be-processed information carried by the first target request.

[0118] In this example, the cache unit acts as a temporary storage unit inside the HBA to cache I / O request data from the host to alleviate the speed difference between the NVMe protocol (based on the high-speed PCIe bus) and downstream low-speed storage devices (such as Serial Advanced Technology Attachment Hard Disk Drive, SATA HDD), avoiding data congestion or delay caused by protocol conversion.

[0119] Step 303: Processing the information to be processed according to the type of the first target request by the processor unit generates response information of the information to be processed and writes the response information into the cache unit.

[0120] Step 304: Feedback the response information to the completion queue of the host memory through the first controller.

[0121] In this example, after the operation of the first target request is completed, the execution result of the request is fed back to the host through the CQ (Completion Queue), thereby fully fulfilling the I / O interaction process specified by the NVMe protocol specification. Specifically: the processor unit generates a completion queue entry that complies with the NVMe specification, which contains the operation status (success / failure) and data address information of the first target request, and writes the response information back to the cache unit, and finally feeds back the response information to the completion queue of the host memory through the first controller.

[0122] In one example, the system also includes multiple hard disk storage devices; the multiple hard disk storage devices are connected to the HBA via a SATA bus, and the HBA also includes a host memory buffer, which is set on the memory side of the host and includes multiple buffer partitions; the first controller includes multiple namespaces, and the method also includes: establishing a first mapping relationship between the namespace and the hard disk storage device through the processor unit, and establishing a second mapping relationship between the hard disk storage device and the buffer partition.

[0123] In this example, the system further includes multiple hard disk storage devices (such as SATA HDDs) connected to the HBA via a SATA bus; the HBA further includes a host memory buffer (HMB) provided on the memory side of the host and divided into multiple logical buffer partitions; multiple namespaces (NS) are configured in the first controller (NVMe controller); the processor unit is further configured to establish a first mapping relationship between the namespace and the hard disk storage device, and a second mapping relationship between the hard disk storage device and the buffer partition, as follows:

[0124] Namespaces (NS) are a core concept defined in the Non-Volatile Memory Express (NVMe) protocol. They abstract the storage resources of physical storage devices (such as SATA HDDs and SSDs) into logical storage units, presenting them as independent logical disks on the host. Each namespace can be managed independently and supports different access permissions, data formats, and performance configurations.

[0125] HBA is used to manage the working mode of the hard disk array of the downstream hard disk storage device, and establish the mapping relationship between the NVMe namespace NS (Namespace) and the hard disk storage device, that is, the first mapping relationship. The first mapping relationship can be one-to-one, one-to-many or many-to-one. Figure 1 As shown, the NVMe namespace NS[1] presented by the NVMe controller is mapped to the downstream hard disk storage device [1]; the NVMe namespace NS[2] presented by the NVMe controller is mapped to the downstream hard disk storage device hard disk [2] and hard disk storage device [3]. It should be noted that this application does not restrict the mapping relationship between namespaces and hard disk storage devices, as long as each NVMe namespace NS corresponds to the storage space of a specific hard disk storage device.

[0126] HMB (Host Memory Buffer) is a feature introduced in the NVMe 1.2 standard that allows the NVMe controller to use the host system's memory (RAM) as a buffer, reducing the need for DRAM within the NVMe device, thereby lowering costs and improving performance. With HMB, NVMe devices can fully utilize the high speed and large capacity of the host memory to store NVMe command queues, completion queues, and other management information, thereby reducing reliance on the DRAM within the NVMe device.

[0127] In addition to connecting to the host, the HBA also connects to multiple hard disk storage devices downstream through the SATA bus and is responsible for identifying and initializing the hard disk storage devices, such as scanning downstream hard disk storage devices to obtain device identification (such as HDDID) and storage capacity; the HBA is also responsible for planning the HMB buffer located in the host side memory and establishing a mapping relationship between the downstream hard disk storage devices and the partitions in the HMB buffer, that is, the second mapping relationship. Figure 1 As shown, the storage data of SATA HDD[1] corresponds to HMB buffer partition[1]; the storage data of SATA HDD[2] corresponds to HMB buffer partition[2]. It should be noted that this application does not restrict the mapping relationship between hard disk storage devices and buffer partitions. It only needs to ensure that each downstream hard disk storage device corresponds to a buffer partition in the HMB.

[0128] In one example, before processing the information to be processed by the processor unit and generating response information of the information to be processed, the method also includes: determining the target hard disk storage device based on the first target request and the first mapping relationship; and determining the target buffer partition based on the target hard disk storage device and the second mapping relationship.

[0129] In this example, when the host sends the first target request through the NVMe protocol, the processor unit parses the namespace identifier (NS ID) and the logical block address (LBA) in the first target request, and queries the first mapping relationship T ns , associate the namespace with the target hard disk storage device (such as SATA HDD) (for example, NS[1] is mapped to HDD[1]), thereby determining the target hard disk storage device. Subsequently, according to the second mapping relationship T buf , locate the target buffer partition in the host memory buffer corresponding to the determined target hard disk storage device (such as HDD[1]→HMB buffer partition[1]).

[0130] Through the double-layer mapping mechanism (namespace → target hard disk storage device → target buffer partition), the host's first target request is converted step by step into the precise location of the physical storage location and buffer area. For example, if the request is for the namespace NS[2] and the LBA range is 0x1000-0x2000, the processor unit uses the first mapping relationship T ns Determine that NS[2] corresponds to SATAHDD[2] and SATA HDD[3], and then according to the second mapping relationship T buf Direct data operations to HMB buffer partitions [2] and [3]. Through this design, the system achieves data path isolation and refined cache management: each SATA HDD occupies an exclusive HMB buffer partition, avoiding conflicts in the storage of data from multiple hard drives in the buffer. At the same time, combined with the high-speed access characteristics of HMB, data read and write operations are completed in the buffer first, and physical hard drives are accessed only when necessary, thereby reducing the frequency of hard drive activation. This mechanism significantly reduces the power consumption of SATA HDDs, and at the same time, through the dynamic management of mapping relationships, ensures the flexibility and scalability of the system.

[0131] In one example, the first target request includes user data and a command word. When the first target request is a write request, the processor unit processes the information to be processed and generates response information for the information to be processed according to the type of the first target request, specifically including: transferring the user data to the target buffer partition; generating a response word for the command word based on the user data to obtain the response information.

[0132] In this example, the system software running on the internal processor of the HBA parses the information in the command word of the first target request to identify the command operation type of the first target request and determines whether the request is a data write request or a data read request.

[0133] When the first target request is a write request, the processor unit performs the following operations:

[0134] Parse the namespace identifier and logical block address in the write request, determine the target hard disk storage device based on the first mapping relationship, and associate it with the corresponding target buffer partition through the second mapping relationship. Through direct memory access (DMA) technology, user data is directly moved from the internal cache unit of the HBA to the target buffer partition of the HMB, thereby eliminating the need for CPU intervention and significantly improving transmission efficiency. At the same time, the HBA system software complies with the message format specified by the NVMe standard, generates a response word corresponding to the command word of the first target request, that is, the response information, and sets the status information of the response word to 0, and then writes the response word to the cache unit in the HBA.

[0135] Finally, the NVMe controller returns the completion response word in the HBA cache unit to the CQ queue located in the host memory. At this point, the processing flow of the first target request from the host being a write request ends.

[0136] In one example, when the first target request is a read request, the processor unit processes the information to be processed and generates response information for the information to be processed according to the type of the first target request, specifically including: querying in the target buffer partition whether there is user data of the first target request; if the user data of the first target request exists in the target buffer partition, sending the user data to the memory address indicated by the first target request, and generating a response word based on the user data to obtain the response information.

[0137] In this example, when the first target request is a read request, the processor unit performs the following operations:

[0138] Parse the namespace identifier and logical block address in the read request, determine the target hard disk storage device based on the first mapping relationship, and associate it with the corresponding target buffer partition through the second mapping relationship. Query the target buffer partition to see whether there is user data matching the logical block address. If the user data of the first target request exists in the target buffer partition, transfer the user data directly from the target buffer partition to the memory address specified by the host request through direct memory access technology; if not, trigger the downstream SATA protocol conversion process. The specific conversion process will be described in detail in subsequent embodiments.

[0139] If the target buffer partition contains user data for the first target request, the system software in the HBA complies with the message format specified by the NVMe standard, generates a response word corresponding to the command word of the first target request, i.e., the response information, sets the status information of the response word to 0 (indicating normal completion of the operation), and then writes the response word to the cache unit in the HBA. Finally, the NVMe controller returns the completion response word in the HBA cache unit to the CQ queue in the host memory.

[0140] In one example, the HBA also includes a second controller. When the user data of the first target request does not exist in the target buffer partition, the method also includes: reading the user data from the target hard disk storage device through the second controller; sending the user data to the memory address specified by the first target request; generating a response word based on the user data to obtain the response information.

[0141] In this example, the second controller is a SATA controller. If the user data of the first target request does not exist in the target buffer partition, the SATA controller of the HBA performs the following operations:

[0142] The second controller initiates a read operation on the target hard disk storage device via the SATA bus, retrieving user data from the hard disk's physical sectors. The read user data is sent directly to the host's requested memory address using direct memory access technology, eliminating CPU intervention and reducing latency.

[0143] If the target buffer partition contains user data for the first target request, the system software in the HBA complies with the message format specified by the NVMe standard, generates a response word corresponding to the command word of the first target request, i.e., the response information, sets the status information of the response word to 0 (indicating normal completion of the operation), and then writes the response word to the cache unit in the HBA. Finally, the NVMe controller returns the completion response word in the HBA cache unit to the CQ queue in the host memory.

[0144] In one example, when there is a first target request and it is a write request, the method further includes: performing protocol conversion on the first target request through the second controller and sending it to the corresponding target hard disk storage device to write the user data to the target hard disk storage device; when there are multiple first target requests and they are write requests, the method further includes: sorting and aggregating the multiple first target requests according to preset rules through the processor unit to obtain at least one second target request; performing protocol conversion on the second target request through the second controller and sending it to the corresponding target hard disk storage device to write the user data to the target hard disk storage device.

[0145] In this example, when there is only one first target request and it is a write request, the second controller is used to perform protocol conversion on the first target request and send it to the corresponding target hard disk storage device to write the user data to the target hard disk storage device.

[0146] Similarly, when there are multiple first target requests and they are write requests, the processor unit needs to perform sorting and aggregation to reduce the access frequency of the second controller SATA HDD and improve the access efficiency of SATA transactions. Figure 2As shown, in chronological order, multiple write requests are received from the host side as the first target request, including IO[1], IO[2], IO[3], IO[4], IO[5] and IO[6]. After the HBA system software analyzes the characteristics of the six write requests, it is found that the LBA addresses accessed by IO[1], IO[2] and IO[3] are adjacent to LBA a, LBA c and LBA b respectively, and can be reordered according to the preset rules (for example, LBA a, LBAb and LBAc), and aggregated to form a single sequential write request IO[1^'] for the SATA HDD device; it is found that the LBA addresses accessed by IO[4], IO[5] and IO[6] are adjacent to LBA x, LBAz and LBA y respectively, and can be reordered according to the preset rules (for example, LBA x, LBAy and LBA z), and aggregated to form a single sequential write request IO[2^'] for the SATA HDD device. Obviously, through HMB's buffering, aggregation, and reordering, the initial six I / O random write requests from the host are transformed into two sequential write requests for the SATA HDD, effectively improving the access efficiency of the SATA HDD device, extending the idle window duration of the HDD device, and reducing the operating time of the HDD device.

[0147] Subsequently, the second controller (SATA controller) converts the aggregated second target request (NVMe protocol) into a command word that complies with the SATA protocol and sends the converted command word to the target hard disk storage device via the SATA bus. It then uses direct memory access to complete the read and write operations of the user data. For example, it batch writes the aggregated user data to the physical sectors of the hard disk or batch reads data from the HMB buffer.

[0148] In one example, if Figure 4 As shown, the above low-power storage method is described in detail through the following embodiments:

[0149] Step 401: When the HBA adapter is initialized, the HBA system software requests a specific capacity of NVMe HMB high-speed memory from the host according to the NVMe specification. At the same time, it identifies and scans the downstream SATA HDD devices, and allocates a specific size of HMB buffer partition to each HDD device based on the number and storage capacity of the HDD devices, and establishes a mapping table T from SATA HDD devices to HMB buffer partitions. buf In addition, set up the NVMe namespace NS and establish a mapping table T between NS and downstream HDD devices ns .

[0150] Step 402: The host sends the NVMe standard I / O request R hostStore it in the NVMe SQ queue in the host memory and notify the NVMe controller inside the HBA adapter that there is a new request waiting to be processed.

[0151] Step 403: The NVMe controller inside the HBA sends R host The command control words and user data carried by I / O are moved to the HBA internal cache.

[0152] Step 404: The system software running on the HBA internal processor analyzes R host Information in the command control word to identify R host The command operation type is determined, that is, whether the request is a data write request or a data read request.

[0153] Step 405: The HBA system software determines R host If the data operation type is a data write type I / O request, step 406 is executed; otherwise, if it is a data read request, the process jumps to step 410.

[0154] Step 406: The HBA system software generates a host The namespace NS and LBA address information in the command word are used to search the mapping table T. ns To determine R host The requested target SATA HDD device then searches the mapping table T buf To determine the corresponding target HMB buffer partition D buf Then, through the PCIe bus, DMA (Direct Memory Access) is used to transfer R host The user data carried is moved to D buf .

[0155] Step 407: The HBA system software complies with the message format specified by the NVMe standard and generates R host The corresponding completion response word is set, and the status information of the response word is set to 0 (indicating that the operation is completed normally), and then the response word is written into the cache in the HBA.

[0156] Step 408: The NVMe controller returns the completion response word in the HBA cache to the CQ queue in the host memory. At this point, the NVMe write I / O request R from the host is host The processing flow ends.

[0157] Step 409: HBA system software parses R hostThe LBA address of the data is aggregated and reordered with previous I / O requests buffered in the HMB cache partition to form a new SATA standard I / O request, thereby reducing the proportion of random access and the frequency of SATA requests. Afterwards, based on specific policies (such as timeout, the number of aggregates reaching a threshold, etc., which are not limited by the present invention), the SATA controller stores the data to the designated SATA HDD device for persistent storage.

[0158] Step 410: The HBA system software generates a host The namespace NS and LBA address information in the command word are used to search the mapping table T. ns To determine R host The requested target SATA HDD device, and then look up the mapping table T buf To determine the corresponding HMB buffer partition D buf . And in D buf Searches the .sysfile to see if there is a backup of the requested data.

[0159] Step 411: Determine D buf Check whether there is a backup of the requested data. If so, jump to step 412 ; if not, jump to step 414 .

[0160] Step 412: The HBA system software reads the requested user data from the HMB via the PCIe bus using DMA and sends it to the R host The command word specifies the memory address, and then generates a completion response word according to the message format specified by the NVMe standard, and writes the response word into the cache in the HBA.

[0161] Step 413: The NVMe controller returns the completion response word to the CQ queue located in the host memory, thereby completing the entire read I / O request R host The processing flow ends.

[0162] Step 414: The HBA system software generates a SATA standard I / O request for the HDD, schedules the SATA controller to read user data from the specified SATA HDD device, and sends the user data to the R device via the PCIe bus. host The specified memory address generates a completion response word according to the message format specified by the NVMe standard and writes the response word to the cache in the HBA.

[0163] According to an embodiment of the present application, the present application also provides an electronic device and a readable storage medium.

[0164] Figure 5A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0165] like Figure 5 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. Various programs and data required for the operation of the device 800 can also be stored in the RAM 803. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0166] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0167] The computing unit 801 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the low-power storage method. For example, in some embodiments, the low-power storage method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the low-power storage method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the low-power storage method in any other appropriate manner (e.g., by means of firmware).

[0168] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0169] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the program code is executed by the processor or controller, the functions / operations specified in the flow charts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0170] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0171] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0172] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0173] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0174] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved. This is not a limitation herein.

[0175] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0176] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A low-power storage system, characterized in that: The system includes: a host and a host bus adapter HBA, wherein the host is connected to the HBA via a PCIe bus; the HBA includes a first controller, a processor unit, and a cache unit, wherein: The first controller is configured to obtain a first target request from a submission queue of a host memory; The cache unit is configured to store the to-be-processed information carried by the first target request; The processor unit is configured to process the to-be-processed information according to the type of the first target request, generate response information of the to-be-processed message, and write the response information into a cache unit; The first controller is further configured to feed the response information back to the completion queue of the host memory.

2. The system according to claim 1, wherein: The system further includes a plurality of hard disk storage devices connected to the HBA via a SATA bus; the HBA further includes a host memory buffer, the host memory buffer being arranged on the memory side of the host and including a plurality of buffer partitions; the first controller includes a plurality of namespaces; The processor unit is further configured to establish a first mapping relationship between the namespace and the hard disk storage device, and to establish a second mapping relationship between the hard disk storage device and the buffer zone.

3. The system according to claim 2, characterized in that Before processing the information to be processed and generating response information of the message to be processed, the processor unit is configured to: Determining a target hard disk storage device according to the first target request and the first mapping relationship; A target buffer zone partition is determined according to the target hard disk storage device and the second mapping relationship.

4. The system according to claim 3, characterized in that The first target request includes user data and a command word; When the first target request is a write request, the processor unit, when processing the to-be-processed information and generating response information of the to-be-processed message according to the type of the first target request, is specifically configured to: Transferring the user data to the target buffer partition; A response word for the command word is generated according to the user data to obtain the response information.

5. The system according to claim 4, characterized in that When the first target request is a read request, the processor unit, when processing the to-be-processed information and generating response information of the to-be-processed message according to the type of the first target request, is specifically configured to: querying in the target buffer partition whether there is user data of the first target request; If the user data of the first target request exists in the target buffer partition, the user data is sent to the memory address indicated by the first target request, and a response word is generated according to the user data to obtain the response information.

6. The system according to claim 5, characterized in that The HBA further includes a second controller; If the user data of the first target request does not exist in the target buffer partition, the second controller is used to read the user data from the target hard disk storage device, send the user data to the memory address specified by the first target request, and generate a response word based on the user data to obtain the response information.

7. The system according to claim 6, characterized in that When there is a first target request and it is a write request: The second controller is further configured to perform protocol conversion on the first target request and send the converted request to a corresponding target hard disk storage device, so as to write the user data into the target hard disk storage device; When there are multiple first target requests and they are write requests: The processor unit is further configured to sort and aggregate the multiple first target requests according to a preset rule to obtain at least one second target request; The second controller is further configured to perform protocol conversion on the second target request and send the converted request to the corresponding target hard disk storage device, so as to write the user data into the target hard disk storage device.

8. A low-power storage method, applied to a low-power storage system, wherein the system includes a host and a host bus adapter (HBA), wherein the host is connected to the HBA via a PCIe bus, and the HBA includes a first controller, a processor unit, and a cache unit, wherein: The method comprises: Obtaining, by the first controller, a first target request from a submission queue of a host memory; Using the cache unit to store the to-be-processed information carried by the first target request; Processing the information to be processed, generating response information of the information to be processed, and writing the response information into the cache unit according to the type of the first target request, by the processor unit; The response information is fed back to the completion queue of the host memory through the first controller.

9. The method according to claim 8, characterized in that The system further includes a plurality of hard disk storage devices; the plurality of hard disk storage devices are connected to the HBA via a SATA bus; the HBA further includes a host memory buffer, the host memory buffer being arranged on a memory side of the host and including a plurality of buffer partitions; the first controller includes a plurality of namespaces, and the method further includes: A first mapping relationship between the namespace and the hard disk storage device is established by the processor unit, and a second mapping relationship between the hard disk storage device and the buffer zone is established.

10. The method according to claim 9, characterized in that Before processing the information to be processed and generating response information of the information to be processed by the processor unit, the method further includes: Determining a target hard disk storage device according to the first target request and the first mapping relationship; A target buffer zone partition is determined according to the target hard disk storage device and the second mapping relationship.

11. The method according to claim 10, characterized in that The first target request includes user data and a command word. When the first target request is a write request, the processor unit processes the information to be processed and generates response information of the information to be processed according to the type of the first target request, specifically including: Transferring the user data to the target buffer partition; A response word for the command word is generated according to the user data to obtain the response information.

12. The method according to claim 11, characterized in that When the first target request is a read request, processing the to-be-processed information and generating response information of the to-be-processed information by the processor unit according to the type of the first target request specifically includes: querying in the target buffer partition whether there is user data of the first target request; If the user data of the first target request exists in the target buffer partition, the user data is sent to the memory address indicated by the first target request, and a response word is generated according to the user data to obtain the response information.

13. The method according to claim 12, characterized in that The HBA further includes a second controller. When the target buffer partition does not contain user data of the first target request, the method further includes: Reading the user data from the target hard disk storage device through the second controller; Sending the user data to the memory address specified by the first target request; A response word is generated according to the user data to obtain the response information.

14. The system according to claim 13, wherein: When there is a first target request and it is a write request, the method further includes: The second controller performs protocol conversion on the first target request and sends the converted request to the corresponding target hard disk storage device, so as to write the user data into the target hard disk storage device; When there are multiple first target requests and they are write requests, the method further includes: sorting and aggregating the plurality of first target requests according to a preset rule by the processor unit to obtain at least one second target request; The second controller performs protocol conversion on the second target request and sends it to the corresponding target hard disk storage device, so as to write the user data into the target hard disk storage device.

15. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 8 to 14.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 8 to 14.

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