Data transmission system and host device

Abstract

The invention discloses a data transmission system and host equipment, and relates to the technical field of communication, and the system comprises a direct storage access module and a preset first-in first-out queue; wherein the direct storage access module is connected with a preset communication bus through the preset first-in first-out queue; the direct storage access module is used for receiving a read-write control command of the central processing unit; performing security detection on the read-write control command to obtain a security detection result; if the security detection result is that the detection is passed, interacting with the preset communication bus by utilizing a target queue in a preset first-in first-out queue, and processing the read-write control command; according to the invention, DMA data transmission between the CPU and the preset communication bus can be realized, the data transmission speed of the host equipment through the communication bus is accelerated, the working efficiency of the CPU is improved, the overall performance of the system is further improved, and the transmission stability of the system is ensured.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a data transmission system and a host device. Background Art

[0002] The I3C (Improved Inter-Integrated Circuit) protocol is a two-wire serial communication technology consisting of the SCL (clock) and SDA (data) lines. I3C supports multi-master mode, improving system scalability and enabling application in more complex systems. I3C features a soft interrupt function, eliminating the need for additional interrupt pins, saving I / O pins and, in turn, physical resources. I3C also features dynamic addressing, allowing devices to be added and changed at any time after the bus is initialized and assigned addresses without hardware redesign. This ensures that each device is assigned a unique address, preventing address conflicts. Compared to communication protocols such as SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit), I3C offers higher communication speeds and greater flexibility. Furthermore, the I3C bus is compatible with I2C devices. These advantages have made the I3C bus widely used.

[0003] As system performance requirements continue to increase, the efficiency of data transmission between host and host devices must be improved. This is especially true for large data transfers. This means that using a single communication bus (such as the I3C bus) for data transmission is no longer sufficient for current applications. Therefore, increasing the speed at which host devices can transmit data via the communication bus is an urgent issue. Summary of the Invention

[0004] The present invention aims to provide a data transmission system and a host device, which can accelerate the speed of data transmission by the host device through a communication bus by using DMA (Direct Memory Access) transmission.

[0005] To solve the above technical problems, the present invention provides a data transmission system, comprising: a direct storage access module and a preset first-in-first-out queue; wherein the direct storage access module is connected to a preset communication bus via the preset first-in-first-out queue; the preset first-in-first-out queue includes a sending queue and / or a receiving queue; and the preset communication bus is an integrated circuit bus or an improved inter-integrated circuit;

[0006] The direct storage access module is used to receive read and write control commands from the central processing unit; perform security checks on the read and write control commands to obtain security check results; if the security check result is a pass, use the target queue in the preset first-in-first-out queue to interact with the preset communication bus to process the read and write control commands; the read and write control commands include read commands and / or write commands, the security check includes illegal address segment detection, and the target queue is the queue corresponding to the working mode of the preset communication bus in which the direct storage access module is located.

[0007] In another aspect, the direct storage access module is connected to the central processing unit via an advanced extensible interface bus; the direct storage access module includes:

[0008] a read control module, configured to receive a read command from the central processing unit; perform a security check on the read command using the first detection module to obtain a security check result; and if the security check result is a pass, read the host data corresponding to the read command into a target queue in the sending queue;

[0009] The first detection module is configured to perform a security detection on the read command, obtain a security detection result, and feed it back to the read control module.

[0010] In another aspect, the preset communication bus is an improved internal integrated circuit, the operating mode includes a master-slave mode and a data transmission mode, and the transmit queue includes a first transmit queue and a second transmit queue; the first transmit queue is a single data first-in-first-out queue, and the second transmit queue is a dual data rate first-in-first-out queue;

[0011] The read control module includes:

[0012] A slave read control module is used to start when the master-slave mode is the slave mode; receive a read command from the central processing unit; use the first detection module to perform a safety check on the read command to obtain a safety check result; if the safety check result is a pass, then when the data transmission mode is the single data rate mode, the host data corresponding to the read command is read into the first sending queue; when the data transmission mode is the double data rate mode, the host data corresponding to the read command is read into the second sending queue.

[0013] In another aspect, the read control module further includes:

[0014] A host read control module is used to start when the master-slave mode is the host mode; receive a read command from the central processing unit; use the first detection module to perform a security check on the read command to obtain a security check result; if the security check result is a pass, the host data corresponding to the read command is read into the first sending queue.

[0015] On the other hand, the first detection module is specifically used to perform security detection on the read command based on the illegal address segment configuration information corresponding to the read control module recorded in the register in the direct storage access module, and obtain and feedback the security detection result to the read control module; wherein, the illegal address segment configuration information includes the initial address, the detection length and the detection transmission type, and the detection transmission type in the illegal address segment configuration information corresponding to the read control module is a write transmission.

[0016] On the other hand, the first detection module is also used to output error information when the feedback security detection result of the read command is detection failure, if the error configuration information recorded by the register in the direct storage access module is an error identifier; if the error configuration information is an error shielding identifier, no error information is output.

[0017] On the other hand, before reading the host data corresponding to the read command into the target queue in the sending queue, the method further includes:

[0018] Determining whether the writable space in the target queue can accommodate the host data;

[0019] If so, the step of reading the host data corresponding to the read command into the target queue in the sending queue is executed.

[0020] In another aspect, the direct storage access module comprises:

[0021] a write control module configured to receive a write command from the central processing unit; perform a security check on the write command using a second detection module to obtain a security check result; and if the security check result indicates a pass, write data corresponding to the write command received from the preset communication bus into a target queue in the receive queue;

[0022] The second detection module is configured to perform a security detection on the write command, obtain the security detection result, and feed it back to the write control module.

[0023] In another aspect, the direct memory access module further comprises: a register and advanced high performance bus interface module;

[0024] Among them, the advanced high-performance bus interface module is connected to the register, the first detection module and the second detection module respectively; the register is used to store central processing unit communication configuration information, preset communication bus communication configuration information and security detection configuration information; the security detection configuration information includes illegal address segment configuration information.

[0025] In addition, the present invention also provides a host device, including: a central processing unit and the above-mentioned data transmission system.

[0026] A data transmission system provided by the present invention includes: a direct storage access module and a preset first-in-first-out queue; wherein the direct storage access module is connected to a preset communication bus via the preset first-in-first-out queue; the preset first-in-first-out queue includes a sending queue and / or a receiving queue; the preset communication bus is an integrated circuit bus or an improved internal integrated circuit; the direct storage access module is used to receive read and write control commands from a central processing unit; a security check is performed on the read and write control commands to obtain a security check result; if the security check result is a pass, a target queue in the preset first-in-first-out queue is used to interact with the preset communication bus to process the read and write control commands; the read and write control commands include read commands and / or write commands, the security check includes illegal address segment detection, and the target queue is a queue corresponding to the working mode of the preset communication bus in which the direct storage access module is located.

[0027] As can be seen, the present invention, through the provision of a direct memory access module, enables DMA data transmission between a CPU (Central Processing Unit) and a preset communication bus. This accelerates data transmission via the communication bus in the host device, increases CPU efficiency, and further improves overall system performance. Furthermore, through security checks in the direct memory access module, system transmission stability is ensured. Furthermore, the present invention also provides a host device that also exhibits the aforementioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0029] Figure 1 A structural block diagram of a data transmission system provided by an embodiment of the present invention;

[0030] Figure 2 A schematic structural diagram of another data transmission system provided by an embodiment of the present invention;

[0031] Figure 3 A schematic structural diagram of a read control module provided by an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of a DMA read process provided by an embodiment of the present invention;

[0033] Figure 5 A schematic structural diagram of a write control module provided by an embodiment of the present invention;

[0034] Figure 6 The present invention provides a flow chart of a DMA write process. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0036] Please refer to Figure 1 , Figure 1 This is a block diagram of a data transmission system provided by an embodiment of the present invention. The system may include: a direct storage access module 10 and a preset first-in-first-out queue 20; wherein the direct storage access module 10 is connected to a preset communication bus via the preset first-in-first-out queue 20; the preset first-in-first-out queue 20 includes a sending queue and / or a receiving queue; the preset communication bus is an integrated circuit bus or an improved inter-integrated circuit;

[0037] The direct storage access module 10 is used to receive read and write control commands from the central processing unit; perform security checks on the read and write control commands and obtain security check results; if the security check result is a pass, the target queue in the preset first-in first-out queue 20 is used to interact with the preset communication bus to process the read and write control commands; the read and write control commands include read commands and / or write commands, the security check includes illegal address segment detection, and the target queue is the queue corresponding to the working mode of the preset communication bus in which the direct storage access module 10 is located.

[0038] It is understandable that the preset communication bus in this embodiment may be a bus for the central processing unit (CPU) to communicate with external devices via the direct memory access (DMA) module 10, such as the preset communication bus may be an I2C bus or an I3C bus.

[0039] DMA is a direct memory access technology that enables data transfer based on hardware systems. The DMA transfer process does not require CPU participation. After the DMA transfer is complete, an interrupt request is generated to notify the CPU. This allows the CPU to handle other tasks during the DMA transfer, reducing the CPU burden. To address the need to transfer large amounts of data between devices connected via a predefined communication bus (such as I3C devices), this embodiment utilizes DMA operations to rapidly transfer data related to the predefined communication bus, utilizing the direct memory access module 10. This improves the speed and efficiency of data processing and significantly enhances system performance.

[0040] Correspondingly, the specific connection method between the direct storage access module 10 and the CPU in this embodiment can be set by the designer. For example, the direct storage access module 10 can be connected to the CPU via an AXI (Advanced eXtensibleInterface) bus, that is, the data movement of the DMA operation is realized through the transmission method of the AXI bus; the direct storage access module 10 can also be connected to the CPU via other communication buses. As long as the direct storage access module 10 can utilize the connection with the CPU to realize the data movement of the DMA operation, this embodiment does not impose any restrictions on this.

[0041] Accordingly, the read and write control commands in this embodiment can be commands sent by the CPU via the read and / or write channels (i.e., read and / or write commands), used to control data transmission via a predetermined communication bus. For example, when the direct memory access module 10 is connected to the CPU via an AXI bus, the read and write control commands can include commands received via the AXI bus's read channel (i.e., read commands) and commands received via the AXI bus's write channel (i.e., write commands), thereby implementing DMA data transfer via the AXI bus. The AXI bus not only separates the read and write channels but also supports capabilities such as AXI outstanding (concurrent transactions), resulting in more efficient data transmission.

[0042] It should be noted that the specific structure of the direct storage access module 10 in this embodiment can be customized by the designer based on the usage scenario and user needs. For example, the direct storage access module 10 may include a first detection module and a read control module for performing security checks and processing on the read command. For example, the read control module may be configured to receive a read command from the central processing unit; utilize the first detection module to perform a security check on the read command and obtain a security check result; if the security check result is a pass, the host data corresponding to the read command is read into the target queue of the send queue. The first detection module may be configured to perform a security check on the read command, obtain the security check result, and feed it back to the read control module.

[0043] Accordingly, the direct storage access module 10 may also include a second detection module and a write control module for performing security checks and processing on the above-mentioned write commands; for example, the write control module is used to receive write commands from the central processing unit; the second detection module is used to perform security checks on the write commands and obtain security check results; if the security check result is a pass, the data corresponding to the write command received from the preset communication bus is written to the target queue in the receive queue; the second detection module is used to perform security checks on the write commands, obtain and feed back the security check results to the write control module. Accordingly, the direct storage access module 10 may also include a first detection module, a read control module, a second detection module and a write control module to enable the corresponding module to perform DMA read or write operations according to the configuration selection. This embodiment does not impose any restrictions on this.

[0044] Among them, the preset first-in-first-out queue 20 in this embodiment can be a pre-set first-in-first-out queue (FIFO) for storing data transmitted via a preset communication bus. The specific number and type of the preset first-in-first-out queue 20 in this embodiment can be set by the designer according to the practical scenario and user needs. For example, when the direct storage access module 10 includes a first detection module and a read control module, the preset first-in-first-out queue 20 can include a sending queue; for example, when the preset communication bus is an I3C bus, since the I3C protocol supports two data transmission modes, SDR (Single Data Rate) and DDR (Double Data Rate), the sending queue can include a first sending queue and a second sending queue; the first sending queue is a single data first-in-first-out queue (such as Figure 3 The second transmit queue is a dual data rate first-in first-out queue (e.g. Figure 3 Tx_ddr fifo in .

[0045] Correspondingly, the working mode of the preset communication bus may include a master-slave mode (i.e., a device state, such as Figure 3 The device_role in the master-slave mode and the data transmission mode are configured accordingly. The read control module may include: a slave read control module configured to start when the master-slave mode is slave mode; receive a read command from the central processing unit; perform a security check on the read command using a first detection module to obtain a security check result; if the security check result is passed, the host data corresponding to the read command is read into a first transmit queue when the data transmission mode is single data rate mode; and the host data corresponding to the read command is read into a second transmit queue when the data transmission mode is double data rate mode. In other words, the first transmit queue can serve as the target queue when the direct storage access module 10 is in the I3C slave state and SDR mode; and the second transmit queue can serve as the target queue when the direct storage access module 10 is in the I3C slave state and DDR mode.

[0046] Correspondingly, the read control module may further include: a host read control module, configured to start when the master-slave mode is the master mode; receive a read command from the central processing unit; perform a security check on the read command using the first detection module to obtain a security check result; if the security check result is a pass, read the host data corresponding to the read command into the first sending queue. In other words, the first sending queue can be used as a target queue when the direct storage access module 10 is in the I3C master state, such as Figure 3 As shown, the slave read control module (such as the state machine FSM) can be connected to the input end of the multiplexer (Demux), the first output end of the multiplexer (Demux) can be connected to the second transmit queue (Tx_ddr fifo), the second output end of the multiplexer can be connected to the first input end of the multiplexer (MUX), the host read control module can be connected to the second input end of the multiplexer, and the output end of the multiplexer can be connected to the first transmit queue (Tx_fifo).

[0047] In another embodiment, the sending queue may further include a third sending queue, a host read control module, which is used to start when the master-slave mode is the master mode; receive a read command from the central processor; use the first detection module to perform a security check on the read command to obtain a security check result; if the security check result is a pass, the host data corresponding to the read command is read into the third sending queue. That is to say, the third sending queue can be used as a target queue when the direct storage access module 10 is in the I3C host state, such as Figure 2 As shown, the host read control module can be connected to the third transmit queue (TXFIFO) in the I3C host module; the slave read control module can be connected to the first transmit queue (TX FIFO) and the second transmit queue (TX DDR FIFO) in the I3C slave module through a multiplexer (Demux).

[0048] Wherein, when the direct storage access module 10 includes the second detection module and the write control module, the preset first-in-first-out queue 20 may include a receiving queue; for example, when the preset communication bus is an I3C bus, the receiving queue may include a first receiving queue and a second receiving queue; the first receiving queue is a single data first-in-first-out queue (such as Figure 5 The second receive queue is a dual data rate first-in first-out queue (such as Rx_fifo in Figure 5 Rx_ddr fifo in .

[0049] Correspondingly, the write control module may include: a slave write control module configured to start when the master-slave mode is the slave mode; receive a write command from the central processing unit; perform a security check on the write command using a first detection module to obtain a security check result; if the security check result is a pass, write the data corresponding to the write command received from the preset communication bus to a first receive queue when the data transmission mode is the single data rate mode; and write the data corresponding to the write command received from the preset communication bus to a second receive queue when the data transmission mode is the double data rate mode. In other words, the first receive queue can serve as the target queue when the direct storage access module 10 is in the I3C slave state and SDR mode; and the second receive queue can serve as the target queue when the direct storage access module 10 is in the I3C slave state and DDR mode.

[0050] Accordingly, the write control module may further include: a host write control module, configured to start when the master-slave mode is the master mode; receive a write command from the central processing unit; perform a security check on the write command using the first detection module to obtain a security check result; if the security check result is a pass, write the host data corresponding to the write command to the first receive queue. In other words, the first receive queue can be used as a target queue when the direct storage access module 10 is in the I3C master state, such as Figure 5 As shown, the slave write control module (such as the state machine FSM) can be connected to the input end of the multiplexer (Demux), the first output end of the multiplexer can be connected to the second receive queue (Rx_ddr fifo), the second output end of the multiplexer can be connected to the first input end of the multiplexer (MUX), the host write control module can be connected to the second input end of the multiplexer, and the output end of the multiplexer can be connected to the first receive queue (Rx_fifo).

[0051] In another embodiment, the receiving queue may further include a third receiving queue, a host write control module, which is used to start when the master-slave mode is the master mode; receive a write command from the central processing unit; use the first detection module to perform a security check on the write command to obtain a security check result; if the security check result is a pass, the host data corresponding to the write command is written to the third receiving queue. That is to say, the third queue can be used as a target queue when the direct storage access module 10 is in the I3C host state, such as Figure 2 As shown, the host write control module can be connected to the third receive queue (RXFIFO) in the I3C host module; the slave write control module can be connected to the first receive queue (RX FIFO) and the second receive queue (RX DDR FIFO) in the I3C slave module through a multiplexer (Demux).

[0052] It should be noted that the specific detection content of the security detection performed by the direct storage access module 10 on the read and write control commands in this embodiment can be set by the designer according to practical scenarios and personal needs. For example, the security detection can include illegal address segment detection to avoid serious errors caused by accessing illegal addresses; the security detection can also include transmission mode detection to avoid serious errors caused by different transmission modes. For example, the direct storage access module 10 can use the illegal address segment configuration information stored in the internal register to perform security detection on the read and write control commands; for example, when the direct storage access module 10 includes a first detection module and a read control module, the first detection module can be specifically used to perform security detection on the read command based on the illegal address segment configuration information corresponding to the read control module recorded in the register of the direct storage access module 10, obtain and feedback the security detection result to the read control module; wherein the illegal address segment configuration information includes the initial address, the detection length and the detection transmission type, and the detection transmission type in the illegal address segment configuration information corresponding to the read control module is a write transmission, that is, when the transmission type of the acquired command is a write transmission, it is determined that the detection fails.

[0053] Correspondingly, when the direct storage access module 10 includes a second detection module and a write control module, the second detection module can be specifically used to perform security detection on the write command based on the illegal address segment configuration information corresponding to the write control module recorded in the register in the direct storage access module 10, and obtain and feedback the security detection result to the write control module; wherein, the detection transmission type in the illegal address segment configuration information corresponding to the write control module is read transmission.

[0054] Correspondingly, the direct storage access module 10 provided in this embodiment may further include a register and an AHB (Advanced High-performance Bus) interface module; wherein the AHB interface module is connected to the register, the first detection module, and the second detection module respectively; the register is used to store central processing unit communication configuration information, preset communication bus communication configuration information, and security detection configuration information; the security detection configuration information includes illegal address segment configuration information.

[0055] For example, the AHB interface module distinguishes different AHB interface selection signals through different address divisions. In this embodiment, there are three groups of AHB interfaces, namely the AHB interface of the first detection module, the AHB interface of the second detection module, and the AHB interface of the register. The AHB interface module divides the AHB selection end into three groups according to different addresses, corresponding to these three groups of AHB interfaces. When the configuration address is within the corresponding group division address interval, the group of AHB interfaces is selected, and then the corresponding AHB information configuration can be performed on the group of AHB interfaces.

[0056] Accordingly, the registers in this embodiment can be used to store and record certain data transmission information, and control signal values and data values can be written by configuring the corresponding registers. For example, the content stored and recorded in the registers can be divided into three parts. The first part is the CPU communication configuration information configured through the registers for communication with the CPU, such as the AXI bus read and write address, read and write length, read and write start and stop conditions, and related interrupt configurations. The second part is the preset communication bus communication configuration information for communication with a preset communication bus (such as the I3C bus), such as the I3C device ID (code), bus mode, command configuration, and interrupts. The third part is the security detection configuration information used for security detection, such as the initial address to be detected, the detection length, and the transfer type (read or write).

[0057] It should be noted that in the case where the security check result in this embodiment is a failure to pass (i.e., a test failure), the designer can configure it by himself, such as directly discarding the read / write control command that failed the test; or notifying the CPU to reconfigure the read / write control command; or reporting an error to determine that the access is an illegal access when the masked address segment (i.e., illegal address segment) and the transmission mode detection coincide, and prompt the user by reporting an error. At this time, the error can be corrected by reconfiguring, thereby reducing errors in the transmission process and making the DMA transmission system more stable. Furthermore, whether to report an error can be selected by register configuration to accommodate different application scenarios; for example, the first detection module can also be configured to output an error message if the error configuration information recorded in the register of the direct storage access module 10 is an error flag when the feedback security check result of the read command is a failure to pass the test; if the error configuration information is an error mask flag, then no error message is output; that is, the security check configuration information recorded in the register can also include error configuration information.

[0058] Correspondingly, in this embodiment, the direct storage access module 10 can use the target queue in the preset first-in-first-out queue 20 to interact with the preset communication bus after the security check result is passed. Before processing the read-write control command, it can first detect whether the available space of the target queue meets the processing requirements of the read-write control command; if so, execute the step of using the target queue in the preset first-in-first-out queue 20 to interact with the preset communication bus to process the read-write control command; if not, wait until the available space of the target queue meets the requirements, and then execute the step of using the target queue in the preset first-in-first-out queue 20 to interact with the preset communication bus to process the read-write control command.

[0059] For example, before reading the host data corresponding to the read command into the target queue in the sending queue, the read control module can also determine whether the writable space in the target queue can meet the host data; if so, the step of reading the host data corresponding to the read command into the target queue in the sending queue is executed. Figure 3 As shown in the figure, the read control module can be used to read tasks issued by the CPU into a specified memory unit (i.e., the target queue). It mainly includes the host read control module and the slave read control module. The host read control module is only enabled when I3C is operating in master mode. Regardless of whether I3C is in SDR mode or DDR mode, the host data will be read into the Tx_fifo. The slave read module is only enabled when I3C is operating in slave mode. The slave read module determines which FIFO to enter based on the configuration signal indicating whether I3C is entering DDR mode. When I3C is in SDR mode, tasks read from the AXI bus are placed in the Tx_fifo; when I3C is in DDR mode, tasks read from the AXI bus are placed in the Tx_ddr fifo. The read control module can support the host device to actively stop the assigned task through register configuration and also supports interrupt reporting. This DMA operation supports AXI outstanding operations to speed up DMA transfers.

[0060] For example, the DMA read process can be as follows Figure 4 As shown in the figure, after configuring the start signal, when I3C is acting as a master, the I3C master's read control module is used. First, the address is detected using the first detection module. If the address detection fails, the device returns to the IDLE (standby) state and needs to restart the configuration. If the address detection is successful, the task of applying for the AXI bus can be started. Next, the remaining space (writable space) in the corresponding receive queue and the size of the remaining tasks are determined to see if the minimum length of an AXI-initiated transaction can be controlled through hardware. If these requirements are met, the task is issued via the AXI read bus. If not, the device continues to wait until the requirements are met before initiating an AXI bus request. If a task is not completed, the writable space determination, AXI bus application, and AXI bus read operations are automatically repeated until all read tasks are completed. After the task is completed, an interrupt is reported. When I3C is acting as a slave, the process operation is similar to that of the master.

[0061] Correspondingly, such as Figure 5As shown, the read control module can be used to move the data received by the I3C bus to the specified memory unit (i.e., the target queue). The AXI write data movement control of the read control module can include two independent control modules, namely the host write control module and the slave write control module. The host mode and slave mode are controlled by the current device role status of the IP; only when the IP works in the specified host or slave mode can the task instruction of writing to the register be executed normally; the data read from the I3C bus needs to be stored in the target queue cache before entering the direct storage access module 10. Figure 6 The DMA write process shown is similar to the DMA read process. It also starts with a start signal and determines whether there is enough readable space in the cache (i.e., the corresponding transmit queue) to initiate an AXI bus request. The cache is controlled according to the device role (i.e., master-slave mode) and SDR / DDR mode (i.e., data transmission mode) configured by the IP.

[0062] In this embodiment, the embodiment of the present invention can realize DMA data transmission between the CPU and the preset communication bus through the setting of the direct storage access module 10, thereby accelerating the speed at which the host device transmits data through the communication bus, improving the CPU working efficiency, and further improving the overall performance of the system; and through the security detection in the direct storage access module 10, the stability of the system transmission is guaranteed.

[0063] Corresponding to the above method embodiment, an embodiment of the present invention further provides a host device. The host device described below and the data transmission system described above can refer to each other.

[0064] A host device includes a central processing unit and the data transmission system provided by the above embodiment.

[0065] The data transmission system may include: a direct memory access (DMA) module and a preset first-in-first-out queue; wherein the direct memory access module is connected to a preset communication bus via the preset first-in-first-out queue; the preset first-in-first-out queue includes a sending queue and / or a receiving queue; and the preset communication bus is an integrated circuit bus (I2C) or an improved inter-integrated circuit (I3C);

[0066] A direct storage access module is configured to receive read and write control commands from a central processing unit (CPU); perform security checks on the read and write control commands to obtain security check results; and if the security check result indicates a pass, utilize a target queue in a preset first-in-first-out queue to interact with a preset communication bus to process the read and write control commands; the read and write control commands include read commands and / or write commands, the security check includes illegal address segment detection, and the target queue is a queue corresponding to the working mode of the preset communication bus in which the direct storage access module is located.

[0067] In some embodiments, the central processing unit may be connected to a direct memory access module in the data transmission system via an AXI (Advanced eXtensible Interface) bus.

[0068] In some embodiments, the predetermined communication bus is a modified inter-integrated circuit.

[0069] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. Regarding the host device disclosed in the embodiments, since it corresponds to the system disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the system description.

[0070] The above describes in detail a data transmission system and host device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concepts of the present invention. It should be noted that those skilled in the art may make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A data transmission system, characterized in that: include: A direct storage access module and the preset first-in-first-out queue; wherein the direct storage access module is connected to a preset communication bus via the preset first-in-first-out queue; the preset first-in-first-out queue includes a sending queue and / or a receiving queue; and the preset communication bus is an integrated circuit bus or an improved inter-integrated circuit; The direct storage access module is used to receive the read and write control commands from the central processing unit; perform security detection on the read and write control commands and obtain security detection results; If the security check result is passed, the target queue in the preset first-in-first-out queue is used to interact with the preset communication bus to process the read and write control commands; the read and write control commands include read commands and / or write commands, the security check includes illegal address segment detection, and the target queue is the queue corresponding to the working mode of the preset communication bus in which the direct storage access module is located.

2. The data transmission system according to claim 1, characterized in that The direct storage access module is connected to the central processing unit via an advanced extensible interface bus; the direct storage access module includes: a read control module, configured to receive a read command from the central processing unit; perform a security check on the read command using the first detection module to obtain a security check result; and if the security check result is a pass, read the host data corresponding to the read command into a target queue in the sending queue; The first detection module is configured to perform a security detection on the read command, obtain a security detection result, and feed it back to the read control module.

3. The data transmission system according to claim 2, characterized in that The preset communication bus is an improved internal integrated circuit, the operating modes include a master-slave mode and a data transmission mode, and the sending queue includes a first sending queue and a second sending queue; the first sending queue is a single data first-in-first-out queue, and the second sending queue is a dual data rate first-in-first-out queue; The read control module includes: A slave read control module is used to start when the master-slave mode is the slave mode; receive a read command from the central processing unit; use the first detection module to perform a safety check on the read command to obtain a safety check result; if the safety check result is a pass, then when the data transmission mode is the single data rate mode, the host data corresponding to the read command is read into the first sending queue; when the data transmission mode is the double data rate mode, the host data corresponding to the read command is read into the second sending queue.

4. The data transmission system according to claim 3, characterized in that The read control module also includes: A host read control module is used to start when the master-slave mode is the host mode; receive a read command from the central processing unit; use the first detection module to perform a security check on the read command to obtain a security check result; if the security check result is a pass, the host data corresponding to the read command is read into the first sending queue.

5. The data transmission system according to claim 2, characterized in that The first detection module is specifically used to perform security detection on the read command based on the illegal address segment configuration information corresponding to the read control module recorded in the register in the direct storage access module, and obtain and feedback the security detection result to the read control module; wherein, the illegal address segment configuration information includes the initial address, the detection length and the detection transmission type, and the detection transmission type in the illegal address segment configuration information corresponding to the read control module is a write transmission.

6. The data transmission system according to claim 2, characterized in that The first detection module is also used to output error information when the feedback security detection result of the read command is detection failure, if the error configuration information recorded by the register in the direct storage access module is an error identifier; if the error configuration information is an error shield identifier, no error information is output.

7. The data transmission system according to claim 2, characterized in that Before reading the host data corresponding to the read command into the target queue in the sending queue, the method further includes: Determining whether the writable space in the target queue can accommodate the host data; If so, the step of reading the host data corresponding to the read command into the target queue in the sending queue is executed.

8. The data transmission system according to any one of claims 1 to 7, characterized in that: The direct storage access module includes: a write control module configured to receive a write command from the central processing unit; perform a security check on the write command using a second detection module to obtain a security check result; and if the security check result indicates a pass, write data corresponding to the write command received from the preset communication bus into a target queue in the receive queue; The second detection module is configured to perform a security detection on the write command, obtain the security detection result, and feed it back to the write control module.

9. The data transmission system according to claim 8, characterized in that The direct storage access module also includes: a register and an advanced high-performance bus interface module; Among them, the advanced high-performance bus interface module is connected to the register, the first detection module and the second detection module respectively; the register is used to store central processing unit communication configuration information, preset communication bus communication configuration information and security detection configuration information; the security detection configuration information includes illegal address segment configuration information.

10. A host device, characterized in that: include: A central processing unit and a data transmission system according to any one of claims 1 to 9.

Images