Task execution method based on circuit trigger request, integrated circuit and electronic equipment

Abstract

The invention discloses a task execution method based on a circuit trigger request, an integrated circuit and electronic equipment, and belongs to the field of circuit design. The task execution method based on the circuit trigger request comprises the steps that under the condition that a circuit needs to execute a corresponding task based on the trigger request, a target trigger request with the storage moment meeting a first preset condition and the priority meeting a second preset condition is read from M sets of storage spaces, each set in the M sets of storage spaces comprises N storage positions, and N is a positive integer; for n trigger requests received at the moment m1, the n trigger requests are stored in the m1th group of storage spaces of the M groups of storage spaces according to the priorities of the n trigger requests, M is greater than or equal to 1, m1 is greater than or equal to 1 and less than or equal to M, and n is greater than or equal to 1 and less than or equal to N; in response to the target trigger request, the circuit executes a task corresponding to the target trigger request. According to the method, the multiple paths of trigger requests can be cached and read according to the time sequence and the priority sequence, the arbitration effect on the trigger requests is improved, and then the working efficiency of a circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit design, and in particular to a task execution method based on circuit trigger request, an integrated circuit, and an electronic device. Background Art

[0002] In circuit design, some circuits require a trigger request to begin operation. Once the circuit completes its operation and returns to an idle state, it can receive a new trigger request. Some circuits only require a single trigger request, while others require multiple trigger requests to complete different tasks.

[0003] However, when triggering a circuit, existing integrated circuits often do not process the priority of trigger requests perfectly, resulting in low circuit operating efficiency. Summary of the Invention

[0004] In view of the above problems, the present application provides a task execution method based on circuit trigger requests, which can cache and read multiple trigger requests in time sequence and priority order to trigger the circuit to execute the corresponding task, thereby improving the arbitration effect of the trigger request and thus improving the working efficiency of the circuit.

[0005] In the first aspect, the present application provides a task execution method based on a circuit trigger request, the method comprising: when the circuit needs to execute the corresponding task based on the trigger request, reading a target trigger request whose storage moment satisfies a first preset condition and whose priority satisfies a second preset condition from M groups of storage spaces, wherein each group in the M groups of storage spaces includes N storage locations, and for n trigger requests received at time m1, the m1th group of storage spaces in the M groups of storage spaces stores n trigger requests according to the priority of the n trigger requests, M≥1, 1≤m1≤M, 1≤n≤N; in response to the target trigger request, the circuit executes the task corresponding to the target trigger request.

[0006] In the technical solution of the embodiment of the present application, when the circuit needs to perform a corresponding task based on a trigger request, the target trigger request whose storage time meets the first preset condition and whose priority meets the second preset condition is first read from the M group storage space, and then responds to the target trigger request, so that the circuit performs the task corresponding to the target trigger request. It can cache and read multiple trigger requests in time sequence and priority order to trigger the circuit to perform the corresponding task, thereby improving the arbitration effect of the trigger request and thereby improving the working efficiency of the circuit.

[0007] In some embodiments, for n trigger requests received at time m1, the n trigger requests are stored in the m1th group storage space of M groups of storage spaces according to the priority of the n trigger requests, including: for n trigger requests received at time m1, obtaining information of the n trigger requests; based on the information of the n trigger requests, storing the n trigger requests in the m1th group storage space according to the priority of the n trigger requests.

[0008] In some embodiments, the information of the trigger request includes storage time information and a priority number; based on the information of the n trigger requests, the n trigger requests are stored in the m1th group storage space according to the priority of the n trigger requests, including: based on the storage time information of the received trigger request, determining the m1th group storage space corresponding to the storage time information from the M groups of storage space; according to the priority number, the n trigger requests are respectively stored in n storage locations in the m1th group storage space, wherein the n storage locations correspond to the n priority numbers.

[0009] In some embodiments, the first preset condition represents the first storage moment, and the second preset condition represents the minimum priority number; reading the target trigger request whose storage moment satisfies the first preset condition and whose priority satisfies the second preset condition from the M group storage space includes: according to the first preset condition, reading the trigger request in the m2 group storage space from the M group storage space, 1≤m2≤M, wherein the trigger request in the m2 group storage space is the first group of requests stored in the M group storage space; determining the trigger request corresponding to the minimum priority number from the m2 group storage space as the target trigger request.

[0010] In some embodiments, each storage location includes a storage identifier, the storage identifier includes a first storage identifier and a second storage identifier, the first storage identifier indicates that the storage location does not store a trigger request, the second storage identifier indicates that the storage location stores a trigger request, and the priority number is associated with the storage location.

[0011] In some embodiments, a trigger request corresponding to the minimum priority number in the m2th group of storage spaces is determined as a target trigger request, including: for the m2th group of storage spaces, sequentially reading the storage identifiers based on each storage space in the m2th group of storage spaces; if the read storage identifiers are all the first storage identifiers, then continue to read the storage identifier of the next storage space; if the read storage identifier is the second storage identifier, then determine the number of trigger requests in the m2th group of storage spaces; in the case where the number of trigger requests is single, use the trigger request in the storage position corresponding to the second storage identifier as the target trigger request; in the case where the number of trigger requests is multiple, determine the storage position corresponding to the second storage identifier corresponds to the minimum priority number, and use the trigger request in the storage position corresponding to the second storage identifier as the target trigger request; after completing the task corresponding to the target trigger request, continue to read the storage identifier of the next storage space.

[0012] On the other hand, the present application provides an integrated circuit, which includes: a storage unit, the storage unit includes a storage space, the storage space is configured into M groups, each group of storage space includes N storage locations, for n trigger requests received at time m1, the m1th group of storage space in the M groups of storage spaces is configured to store n trigger requests according to the priority of the n trigger requests, M≥1, 1≤m1≤M, 1≤n≤N; a trigger matching circuit, connected to the storage unit, is configured to read a target trigger request whose storage time meets a first preset condition and whose priority meets a second preset condition from the M groups of storage space when the circuit needs to perform a corresponding task based on the trigger request, so as to respond to the target trigger request, and the circuit performs the task corresponding to the target trigger request.

[0013] In some embodiments, the integrated circuit also includes: a judgment circuit, which is respectively connected to the trigger matching circuit and the storage unit, and is configured to judge whether all the trigger requests that meet the first preset condition at the storage moment are read, and when it is judged that all the trigger requests at the storage moment are read, issue a trigger request instruction to read the next group of storage space according to the first preset condition.

[0014] On the other hand, the present application provides an electronic device including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method of any of the above embodiments when executing the computer program.

[0015] On the other hand, the present application provides a chip, which includes the integrated circuit of any one of the above embodiments.

[0016] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the drawings to represent the same components. In the drawings: Figure 1 A flowchart of a task execution method based on a circuit trigger request according to an embodiment of the present application is shown; Figure 2 A flowchart of receiving and storing a trigger request according to an embodiment of the present application is shown; Figure 3 A flowchart of trigger request reading and releasing according to an embodiment of the present application is shown; Figure 4 A schematic diagram of an integrated circuit according to an embodiment of the present application is shown; Figure 5 A schematic diagram showing storage and reading of a circuit trigger request according to an embodiment of the present application is shown; Figure 6 A schematic diagram of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0020] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0021] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0023] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0024] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0025] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0026] In circuit design, some circuits require a trigger request to begin operation. Once the circuit completes its operation and returns to an idle state, it can receive a new trigger request. Some circuits only require a single trigger request, while others require multiple trigger requests to complete different tasks.

[0027] However, when triggering a circuit, existing integrated circuits often do not process the priority of trigger requests perfectly, resulting in low circuit operating efficiency.

[0028] In integrated circuits, circuit trigger requests are generally categorized as single or multiple triggers. Triggering is relatively simple: upon receiving a trigger request, the circuit begins operation. Once the operation is complete, it receives a second trigger request and completes the second operation. If a circuit is already operating, it cannot respond to new trigger requests and will be ignored. Therefore, a buffer circuit is needed to store trigger requests. Once the circuit completes its operation and returns to idle state, the buffer circuit releases the trigger, allowing the triggered circuit to resume operation.

[0029] Multiple trigger requests occur when a circuit has multiple different yet similar functions. Different trigger requests can trigger corresponding tasks, but the circuit can only operate in one task at a time. Multiple trigger requests present additional challenges because multiple trigger requests may arrive simultaneously. These challenges include: 1. Buffering and arbitration of multiple simultaneous trigger requests; 2. Buffering of multiple triggers that are not triggered simultaneously; 3. Buffering of multiple simultaneous triggers. In existing integrated circuits, the solutions to these issues are generally: 1. Simply ignoring new trigger requests while the circuit is operating; 2. Buffering them, ignoring their chronological order, and triggering them at a fixed priority.

[0030] In view of this, the present application proposes a task execution method based on circuit trigger requests, which can cache and read multiple trigger requests in time sequence and priority order to trigger the circuit to execute the corresponding task, thereby improving the circuit's arbitration effect on the trigger request and thus improving the circuit's working efficiency.

[0031] In the technical solution of the embodiment of the present application, when the circuit needs to perform a corresponding task based on a trigger request, the target trigger request whose storage time meets the first preset condition and whose priority meets the second preset condition is first read from the M group storage space, and then responds to the target trigger request, so that the circuit performs the task corresponding to the target trigger request. It can cache and read multiple trigger requests in time sequence and priority order to trigger the circuit to perform the corresponding task, thereby improving the working efficiency of the circuit.

[0032] Figure 1 A flow chart of a task execution method based on a circuit trigger request according to an embodiment of the present application is shown.

[0033] like Figure 1 As shown, the task execution method 100 based on circuit trigger request provided in an embodiment of the present application includes steps S110 to S120.

[0034] Step S110, when the circuit needs to perform a corresponding task based on a trigger request, read a target trigger request whose storage moment meets the first preset condition and whose priority meets the second preset condition from M groups of storage spaces, wherein each group in the M groups of storage spaces includes N storage locations, and for n trigger requests received at time m1, the m1th group of storage spaces in the M groups of storage spaces stores n trigger requests according to the priority of the n trigger requests, M≥1, 1≤m1≤M, 1≤n≤N.

[0035] Exemplarily, the M group of storage spaces can be, for example, a synchronous FIFO (first-in, first-out data structure) with a depth of M. The first preset condition can be, for example, the moment when the trigger request is first stored. The second preset condition can be, for example, the trigger request with the smallest priority number. The trigger request can be, for example, a pulse signal for triggering a circuit function. For example, when the triggered circuit is in an idle state, it can be determined that the circuit needs to perform a corresponding task based on the trigger request. At this time, if a trigger request is cached in the storage space, the trigger request with the smallest priority number (highest priority) stored at the earliest moment is read from the M group of storage spaces based on the first-in, first-out principle, that is, time first and then number first, that is, the target trigger request.

[0036] The storage space used to store trigger requests, such as a first-in, first-out buffer (FIFO storage space), has multiple layers of depth. Adding a layer means the FIFO address, i.e., the write pointer, increases by 1. Each write pointer address corresponds to a FIFO layer. M groups of storage space have M layers, each layer having multiple storage bits (storage locations), e.g., N, for storing trigger requests at the same moment. The number of trigger requests satisfies 1 ≤ n ≤ N. The M groups of storage space can store trigger requests at M moments in chronological order. Each group of storage space can store multiple trigger requests at the same moment. For n trigger requests received at time m1, n trigger requests can be stored in the m1th group of storage space in priority order. The priority order of trigger requests at the same moment is sorted according to a fixed priority number, e.g., trigger 0 > trigger 1 > trigger 2, etc. For example, the priority number of one trigger request can be represented as "trigger 0" or "0." For another trigger request, the priority number can be represented as "trigger 1" or "1," and so on.

[0037] Step S120 , in response to the target trigger request, the circuit executes the task corresponding to the target trigger request.

[0038] Exemplarily, according to the trigger request (target trigger request) with the earliest storage time and the highest priority, the trigger circuit executes a task corresponding to the target trigger request and based on the circuit function.

[0039] In the technical solution of the embodiment of the present application, when the circuit needs to perform a corresponding task based on a trigger request, the target trigger request whose storage time meets the first preset condition and whose priority meets the second preset condition is first read from the M group storage space, and then responds to the target trigger request, so that the circuit performs the task corresponding to the target trigger request. It can cache and read multiple trigger requests in time sequence and priority order to trigger the circuit to perform the corresponding task, thereby improving the arbitration effect of the trigger request and thereby improving the working efficiency of the circuit.

[0040] In one example, the execution of a circuit trigger request requires a storage space based on a cache trigger request, which can cache the trigger request according to the first-in-first-out principle so that the triggered circuit can read and execute it in the order of priority of time first and then sequence number when it is idle. The details are explained below.

[0041] Exemplarily, for the n trigger requests received at time m1, the n trigger requests are stored in the m1th group storage space of the M group storage space according to the priority of the n trigger requests. For example, first, for the n trigger requests received at time m1, the information of the n trigger requests is obtained; then, based on the information of the n trigger requests, the n trigger requests are stored in the m1th group storage space according to the priority of the n trigger requests.

[0042] Specifically, each storage location includes a storage identifier, and the storage identifier includes a first storage identifier and a second storage identifier. The first storage identifier indicates that the storage location does not store a trigger request, and the second storage identifier indicates that the storage location stores a trigger request. The priority number is associated with the storage location.

[0043] For example, each layer of the first-in, first-out cache (FIFO storage space) used to store trigger requests has multiple storage bits (storage locations), each of which records a trigger request. 1 (second storage identifier) indicates a trigger request, and 0 (first storage identifier) indicates no trigger request. Each layer of storage space represents a storage moment. It should be noted that the storage moment is not a fixed time; as soon as a trigger request is received, it is immediately stored in the cache. Trigger requests at the same moment refer to trigger requests at the same time, which can be one or multiple trigger requests. If there is only one trigger request at the same moment, then only one corresponding bit in this layer is 1. If there are multiple trigger requests at the same moment, then multiple corresponding bits in this layer are 1.

[0044] For example, the trigger requests in the first-in-first-out cache naturally have a time order, and the position of the bit in the same layer represents the information of the trigger request. The information of the trigger request may include, for example, storage time information and priority number. Based on the information of the trigger request (priority number), the trigger requests at the same time can be stored in the corresponding bit positions of the same layer in order from the lowest bit to the highest bit. The priority number of the trigger request is fixedly connected to the bit position, for example, trigger 1 is fixedly connected to bit 1.

[0045] Exemplarily, the information of the trigger request includes storage time information and a priority number; based on the information of n trigger requests, n trigger requests are stored in the m1th group storage space according to the priority of the n trigger requests. For example, first, based on the storage time information of the received trigger request, the m1th group storage space corresponding to the storage time information is determined from the M groups of storage space; then, according to the priority number, the n trigger requests are respectively stored in n storage locations in the m1th group storage space, where the n storage locations correspond to the n priority numbers.

[0046] Specifically, for example, based on the information of the n trigger requests received at time m1, the storage time information can be obtained as time m1. Based on the m1 storage time information of the trigger request, the n trigger requests can be stored in the corresponding m1-th group storage space; then, based on the information of the n trigger requests received, the priority number of each trigger request is obtained, and the n trigger requests are stored in n storage locations in the m1-th group storage space according to the priority order. The priority order is, for example, trigger 0>trigger 1>trigger 2... The priority number of each trigger request is fixedly connected to a bit (storage location), that is, trigger 0 is fixedly connected to the lowest bit of the bit, that is, trigger 0 is fixedly connected to bit0.

[0047] Figure 2 A trigger request receiving and storing flow chart of an embodiment of the present application is shown.

[0048] like Figure 2 As shown, the triggered circuit is always in a state of waiting for triggering. When one or more trigger requests are received, the trigger requests at the same moment will be stored in the same layer of the first-in-first-out cache (storage space). When a new trigger request arrives at the second moment, all trigger requests at the second moment will be stored in the second layer of the first-in-first-out cache.

[0049] In the technical solution of the embodiment of the present application, each group of M groups of storage spaces includes N storage locations, and the number of trigger requests stored in each group of storage spaces is less than or equal to N. For the n trigger requests received at time m1, based on the storage time information of the received trigger request, the m1th group of storage space corresponding to the storage time information is determined from the M groups of storage spaces, and then the n trigger requests are stored in the n storage locations in the m1th group of storage space according to the priority number, respectively. This supports the storage of continuous trigger requests without waiting time, thereby solving the caching problem of simultaneous multiple trigger requests and the caching problem of non-simultaneous trigger requests, and improving the caching efficiency of trigger requests to improve the circuit working efficiency.

[0050] Based on the priority order of time first and sequence number second, the M group of storage spaces for caching circuit trigger requests can be used to read the target trigger request that meets the first preset condition and the second preset condition from the M group of storage spaces when the triggered circuit is in an idle state to execute the corresponding task. Figure 3 Provide a detailed description.

[0051] Figure 3 A flowchart of trigger request reading and releasing according to an embodiment of the present application is shown.

[0052] For example, Figure 3 As shown, the first preset condition represents the first storage moment, and the second preset condition represents the minimum priority number; the target trigger request whose storage moment meets the first preset condition and whose priority meets the second preset condition is read from the M group storage space. For example, first, according to the first preset condition, the trigger request in the m2 group storage space is read from the M group storage space, 1≤m2≤M, wherein the trigger request in the m2 group storage space is the first group of requests stored in the M group storage space; then, the trigger request corresponding to the minimum priority number is determined from the m2 group storage space as the target trigger request.

[0053] Exemplarily, a trigger request corresponding to the minimum priority number in the m2th group of storage space is determined as a target trigger request. For example, first, for the m2th group of storage space, the storage identifiers based on each storage space in the m2th group of storage space are read in sequence; if the read storage identifiers are all the first storage identifiers, then continue to read the storage identifier of the next storage space; if the read storage identifier is the second storage identifier, then determine the number of trigger requests in the m2th group of storage space; in the case where the number of trigger requests is single, use the trigger request in the storage position corresponding to the second storage identifier as the target trigger request; in the case where the number of trigger requests is multiple, determine the minimum priority number corresponding to the storage position corresponding to the second storage identifier, and use the trigger request in the storage position corresponding to the second storage identifier as the target trigger request; then, after completing the task corresponding to the target trigger request, continue to read the storage identifier of the next storage space.

[0054] Specifically, continue to refer to Figure 3 When the triggered circuit is idle, it is determined that the circuit needs to perform a corresponding task based on the trigger request. If the trigger request cache of the M group storage space is not empty, the first layer of trigger request stored (the trigger request in the m2 group storage space, that is, meeting the first preset condition) is read out and it is determined whether it contains one trigger request or multiple trigger requests. If it is a single trigger request, the trigger request (target trigger request) is immediately released and triggers the triggered circuit to perform the corresponding task. If there are multiple trigger requests at the same moment, the trigger requests of this layer are stored, and then the storage identifiers of this layer of storage space are checked bit by bit from the lowest bit to the highest bit. If a trigger request is detected in this bit, that is, a trigger request (the trigger request with the lowest priority sequence number, which meets the second preset condition) is stored in the lowest bit, and the storage identifier read is the second storage identifier, then the trigger request (target trigger request, i.e., trigger n in the figure) is released to trigger the corresponding triggered circuit. The triggered circuit enters the working state based on the corresponding target trigger request, waits for the triggered circuit to complete its operation and enter the idle state again, and then checks the next bit. If no trigger request is stored in this bit, the storage identifier corresponding to the storage location becomes the first storage identifier, and checks of the next bit continue until the last bit is detected. Then, when the triggered circuit is idle again, the trigger request of the next layer (the next storage moment) is read. This cycle repeats until the trigger request in the cache is empty, thereby reading the trigger requests based on the first-in, first-out principle.

[0055] In the technical solution of the embodiment of the present application, according to the first preset condition, the trigger request in the m2th group storage space that is first stored is read from the M group storage space, and then the storage identifier based on each storage space in the m2th group storage space is read in sequence. When the read storage identifier is the second storage identifier, the storage position corresponding to the second storage identifier is determined from the m2th group storage space to have the minimum priority number, and the trigger request in the storage position corresponding to the second storage identifier is used as the target trigger request, thereby first releasing the trigger request in chronological order, and for simultaneous trigger requests, triggering them in order from the lowest bit to the highest bit, realizing time and serial number arbitration of the storage trigger request, solving the problem of release sorting of simultaneous and non-simultaneous multiple trigger requests, and the arbitration problem of release order of simultaneous multiple trigger requests, thereby improving the working efficiency of the circuit.

[0056] Figure 4 A schematic diagram of an integrated circuit according to an embodiment of the present application is shown.

[0057] An embodiment of the present application provides an integrated circuit 400 , which includes: a storage unit 401 , a trigger matching circuit 402 , and a judgment circuit 403 .

[0058] Storage unit 401, storage unit 401 includes storage space, the storage space is configured into M groups, each group of storage space includes N storage locations, for n trigger requests received at time m1, the m1th group of storage space of the M groups of storage space is configured to store n trigger requests according to the priority of the n trigger requests, M≥1, 1≤m1≤M, 1≤n≤N.

[0059] Exemplarily, storage unit 401 may include a synchronous FIFO with a depth of M and a width of N as storage space. N trigger requests require N bits (storage locations) of FIFO width to store the trigger requests. A depth of M means that a FIFO with M rows (M groups) can cache trigger requests at M times, with the FIFO address incremented by 1 for each additional row. For n trigger requests received at time m1, the n trigger requests are stored in the m1-th group storage space according to their priority. Each trigger request priority has a fixed correspondence with one of the n storage locations.

[0060] The trigger matching circuit 402 is connected to the storage unit 401 and is configured to read a target trigger request whose storage time meets the first preset condition and whose priority meets the second preset condition from the M group storage space when the circuit needs to perform a corresponding task based on a trigger request, so as to respond to the target trigger request and the circuit performs the task corresponding to the target trigger request.

[0061] Exemplarily, when the circuit is in an idle state, the multi-way trigger request of the first row (corresponding to the first storage moment) of the FIFO cache can be read by the trigger matching circuit 402, and multi-way matching can be performed to read the target trigger request with the smallest priority number of the first storage moment based on the first-in-first-out principle, so that the circuit can perform the corresponding task.

[0062] The judgment circuit 403 is connected to the trigger matching circuit 402 and the storage unit 401 respectively, and is configured to judge whether all the trigger requests that meet the first preset condition at the storage moment are read, and when it is judged that all the trigger requests at the storage moment are read, issue a trigger request instruction to read the next group of storage space according to the first preset condition.

[0063] For example, the judgment circuit 403 can be used to determine whether all the trigger requests of the first row of the FIFO cache have been read and cleared, until the trigger requests of the entire row are triggered and the circuit to be triggered is in an idle state again, and the judgment circuit 403 issues a request to read the FIFO, that is, reads the trigger request instruction of the next group of storage space to release the trigger request of the next row of FIFO.

[0064] In the technical solution of the embodiment of the present application, through the storage space of the storage unit, for the n trigger requests received at time m1, the n trigger requests are stored in the m1 group storage space according to the priority of the n trigger requests, so as to cache the non-simultaneous trigger requests and simultaneous multi-channel trigger requests. When the circuit needs to perform the corresponding task based on the trigger request, the target trigger request whose storage time meets the first preset condition and whose priority meets the second preset condition is read from the M group storage space through the trigger matching circuit. The judgment circuit judges whether all the trigger requests whose storage time meets the first preset condition are read. When it is judged that all the trigger requests at the storage time are read, the trigger request instruction for reading the next group of storage space is issued according to the first preset condition, thereby realizing time and serial number arbitration of the storage trigger request according to the priority order of time first and serial number second, thereby improving the working efficiency of the circuit.

[0065] Figure 5 A schematic diagram of storing and reading a circuit trigger request according to an embodiment of the present application is shown.

[0066] like Figure 5As shown, a synchronous FIFO with a depth of M and a width of n is used as a trigger buffer. For n trigger requests, a FIFO width of n bits is required. Each bit in n corresponds to a trigger request, and the position of a trigger request in n is fixed. A FIFO with a depth of M rows can buffer triggers at M times. The relationship between rows is that the FIFO address increases by 1 with each additional row. The storage time is not fixed; when one or more trigger requests arrive at the same time, it is defined as a time. Trigger requests at the same time are stored in the same FIFO row. Triggers at different times are stored in different FIFO rows according to the time. A 1 in the corresponding bit in each row indicates a trigger request, while a 0 indicates no trigger request. For example, a row with the contents b000...1101 indicates that trigger 0, trigger 2, and trigger 3 are stored simultaneously.

[0067] When the triggered circuit is idle, and all trigger requests in the multi-trigger detection circuit have been triggered, the trigger buffer FIFO is not empty, and the circuit initiates a read request from the FIFO buffer. The first row of the FIFO is read out. This row contains the information of the multi-channel trigger request first stored in the FIFO. This row of information is matched by the trigger matching circuit. If only one trigger request is matched, the corresponding trigger request will directly trigger the triggered circuit, and then wait for the triggered circuit to be idle before continuing to issue read FIFO requests. If multiple triggers are matched, the multi-trigger detection circuit will check for corresponding triggers in the order of 0, 1, 2..., and if a corresponding trigger request is detected, it will trigger the triggered circuit, and then the trigger request will be cleared. The circuit will continue to search for the next trigger request, and wait for the triggered circuit to be idle before issuing another trigger request. This continues until the entire row of information is detected and all stored trigger requests are cleared. When the waiting triggered circuit is idle, the full completion judgment circuit is triggered to issue a read request from the FIFO to release the trigger buffer of the next row.

[0068] Figure 6 A schematic diagram of an electronic device according to an embodiment of the present application is shown.

[0069] An embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method in any of the above embodiments are implemented.

[0070] like Figure 6 As shown, for ease of understanding, the embodiment of the present application shows a specific electronic device 600.

[0071] The electronic device 600 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are intended to be examples only and are not intended to limit implementations of the present disclosure described and / or claimed herein.

[0072] like Figure 6 As shown, electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. Various programs and data required for the operation of electronic device 600 may also be stored in RAM 603. Computing unit 601, ROM 602, and RAM 603 are connected to each other via bus 604. An input / output (I / O) interface 605 is also connected to bus 604.

[0073] Multiple components in the electronic device 600 are connected to the I / O interface 605, including an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, an optical disk, etc.; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the electronic device 600 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0074] The computing unit 601 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods described above. For example, in some embodiments, any one or more of the methods described above may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed onto the electronic device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the computing unit 601, one or more steps of any one or more of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform any one or more of the methods described above via any other suitable means (e.g., via firmware).

[0075] An embodiment of the present application provides a chip, which includes the integrated circuit in any one of the above embodiments.

[0076] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this application, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing it in a suitable manner if necessary, and then storing it in a computer memory.

[0077] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having logic gate circuits for implementing logic functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A task execution method based on circuit trigger request, characterized in that: The method comprises: In a case where the circuit needs to perform a corresponding task based on a trigger request, reading target trigger requests whose storage moments satisfy a first preset condition and whose priorities satisfy a second preset condition from M groups of storage spaces, wherein each group of the M groups of storage spaces includes N storage locations, and for n trigger requests received at time m1, an m1-th group of storage spaces of the M groups of storage spaces stores the n trigger requests according to the priorities of the n trigger requests, where M≥1, 1≤m1≤M, and 1≤n≤N; In response to the target trigger request, the circuit executes a task corresponding to the target trigger request.

2. The task execution method based on circuit trigger request according to claim 1, characterized in that: For n trigger requests received at time m1, storing the n trigger requests in the m1th group of storage spaces of the M groups of storage spaces according to their priorities includes: For the n trigger requests received at the time m1, obtaining information of the n trigger requests; Based on the information of the n trigger requests, the n trigger requests are stored in the m1-th group storage space according to the priorities of the n trigger requests.

3. The task execution method based on circuit trigger request according to claim 2, characterized in that: The trigger request information includes storage time information and priority sequence number; storing the n trigger requests in the m1-th group storage space according to the priority of the n trigger requests based on the information of the n trigger requests includes: Based on the received storage time information of the trigger request, determining an m1-th group of storage spaces corresponding to the storage time information from the M groups of storage spaces; According to the priority numbers, the n trigger requests are respectively stored in n storage locations in the m1-th group of storage spaces, wherein the n storage locations correspond to the n priority numbers.

4. The task execution method based on circuit trigger request according to any one of claims 1 to 3, characterized in that: The first preset condition represents the earliest storage time, and the second preset condition represents the minimum priority sequence number; The step of reading a target trigger request from the M groups of storage spaces, the target trigger request having a storage time that satisfies a first preset condition and a priority that satisfies a second preset condition, includes: According to the first preset condition, reading the triggering requests in the m2-th group of storage spaces from the M groups of storage spaces, 1≤m2≤M, wherein the triggering requests in the m2-th group of storage spaces are the first group of requests stored in the M groups of storage spaces; A trigger request corresponding to a minimum priority number is determined from the m2 th group of storage spaces as the target trigger request.

5. The task execution method based on circuit trigger request according to claim 4, characterized in that: Each of the storage locations includes a storage identifier, and the storage identifier includes a first storage identifier and a second storage identifier. The first storage identifier indicates that the storage location does not store a trigger request, and the second storage identifier indicates that the storage location stores a trigger request. The priority number is associated with the storage location.

6. The task execution method based on circuit trigger request according to claim 5, characterized in that: The step of determining the trigger request corresponding to the minimum priority sequence number from the m2-th group of storage spaces as the target trigger request includes: For the m2th group of storage spaces, sequentially read the storage identifier based on each of the storage spaces in the m2th group of storage spaces; If the storage identifiers read are all the first storage identifiers, continue reading the storage identifier of the next storage space; If the read storage identifier is the second storage identifier, determining the number of trigger requests in the m2-th group of storage spaces; In a case where the number of the trigger request is only one, taking the trigger request in the storage location corresponding to the second storage identifier as the target trigger request; In the case where there are multiple trigger requests, determining that the storage location corresponding to the second storage identifier corresponds to the minimum priority sequence number, and using the trigger request in the storage location corresponding to the second storage identifier as the target trigger request; After the task corresponding to the target trigger request is completed, the storage identifier of the next storage space is read.

7. An integrated circuit, characterized in that: The circuit comprises: a storage unit, the storage unit including storage space, the storage space being configured into M groups, each group of storage space including N storage locations, for n trigger requests received at time m1, an m1th group of storage space of the M groups of storage space being configured to store the n trigger requests according to a priority of the n trigger requests, M ≥ 1, 1 ≤ m1 ≤ M, 1 ≤ n ≤ N; A trigger matching circuit is connected to the storage unit and is configured to read a target trigger request whose storage time satisfies a first preset condition and whose priority satisfies a second preset condition from the M group of storage spaces when the circuit needs to perform a corresponding task based on the trigger request, so as to respond to the target trigger request and the circuit performs the task corresponding to the target trigger request.

8. The integrated circuit according to claim 7, wherein: The integrated circuit further comprises: The judgment circuit is connected to the trigger matching circuit and the storage unit respectively, and is configured to judge whether all the trigger requests that meet the first preset condition at the storage moment are read, and when it is judged that all the trigger requests at the storage moment are read, issue a trigger request instruction to read the next group of storage space according to the first preset condition.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A chip, characterized in that: The chip comprises the integrated circuit according to any one of claims 7 to 8.

Images