Timing controller, and display device and system including same

Abstract

A timing controller is provided. The timing controller includes: a plurality of registers located in a power gating region and configured to store a plurality of setting values; an image processing circuit configured to receive an image signal and perform image processing on the image signal based on the plurality of setting values; a recovery memory located outside the power gating region and configured to store the plurality of setting values; and a bus controller configured to receive the plurality of setting values and store the plurality of setting values in the plurality of registers and the recovery memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0022081 filed on February 15, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a timing controller and a display device and system including the timing controller. Background Art

[0004] A display panel displays images and provides various visual information to the user. The display panel includes multiple pixels, each of which emits light of a certain brightness to display an image. A display driver may include a display driver integrated circuit (DDI) to process image signals and drive the pixels.

[0005] Power gating can be used to reduce the power consumption of the DDI between a power-down state and a power-up state. The DDI may store settings for processing video signals in registers. When the DDI is in a power-down state, these settings may be lost. To prevent the loss of these settings, a method is needed to maintain the settings stored in the registers. Summary of the Invention

[0006] One or more example embodiments provide a timing controller that restores a set value to a register when switching from a power-down state to a power-up state, and a display device and system including the timing controller.

[0007] One or more example embodiments provide a smaller-sized timing controller, and a display device and system including the same.

[0008] One or more example embodiments provide a timing controller with reduced power consumption, and a display device and system including the same.

[0009] According to an aspect of an example embodiment, a timing controller includes: a plurality of registers located in a power gating region and configured to store a plurality of setting values;

[0010] an image processing circuit configured to receive an image signal and perform image processing on the image signal based on the plurality of setting values;

[0011] a recovery memory located outside the power-gated region and configured to store the plurality of setting values; and

[0012] A bus controller is configured to receive the plurality of setting values and store the plurality of setting values in the plurality of registers and the restore memory.

[0013] According to another aspect of the example embodiment, a display device includes: a pixel array including a plurality of pixels, a plurality of gate lines and a plurality of source lines respectively connected to the plurality of pixels; a driving circuit configured to send signals for driving the plurality of pixels to the plurality of source lines based on image data; and a timing controller configured to receive a plurality of setting values, store the plurality of setting values in a plurality of registers and a recovery memory, receive an image signal, process the image signal based on the plurality of setting values stored in the plurality of registers to obtain a processed image signal, generate the image data based on the processed image signal, and provide the image data to the driving circuit.

[0014] According to another aspect of the example embodiments, a display system includes: a host device configured to output a plurality of addresses and a plurality of setting values corresponding to the plurality of addresses; and a display device configured to store the plurality of setting values in a plurality of registers indicated by the plurality of addresses, store the plurality of setting values in a recovery memory based on a plurality of memory addresses corresponding to the plurality of addresses, and restore the plurality of setting values stored in the recovery memory to the plurality of registers. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects and features will become more apparent from the following description of embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 is an example block diagram of a display system according to an example embodiment;

[0017] Figure 2 is a block diagram illustrating a timing controller according to an example embodiment;

[0018] Figure 3 is a diagram showing a portion of a timing controller according to an exemplary embodiment;

[0019] Figure 4 is a diagram illustrating a bus controller, a bus-memory interface circuit, a register core, and a recovery memory during data storage according to an example embodiment;

[0020] Figure 5 is a diagram illustrating a bus controller, a bus-memory interface circuit, a register core, and a recovery memory during data reading according to an example embodiment;

[0021] Figure 6is a diagram illustrating a bus controller, a recovery control circuit, a register core, and a recovery memory during data recovery according to an example embodiment;

[0022] Figure 7 is a timing diagram illustrating a power gating operation of a display device according to an exemplary embodiment;

[0023] Figure 8 is a timing diagram illustrating the operation of the timing controller during power-up according to an exemplary embodiment;

[0024] Figure 9 shows a display device according to an example embodiment;

[0025] Figure 10 shows a register core according to an example embodiment;

[0026] Figure 11 is a block diagram illustrating a selection signal generator according to an example embodiment;

[0027] Figure 12 shows a register core according to an example embodiment; and

[0028] Figure 13 A display system according to an example embodiment is shown. DETAILED DESCRIPTION

[0029] Hereinafter, example embodiments are described in detail with reference to the accompanying drawings. Throughout the specification, identical parts are represented by identical reference numerals, and their repeated description is omitted. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to another element or layer, or there can be an intermediate element or layer. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and can be implemented in various other forms. Each example embodiment provided in the following description does not exclude that another example or one or more features of another example embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure are associated.

[0030] Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.In the methods described in this specification with reference to the drawings, the order of operations may be changed, several operations may be combined, certain operations may be divided, and certain operations may not be performed.

[0031] Unless explicit expressions such as "one" or "single" are used, singular expressions in this specification may be interpreted as singular or plural. In addition, the terms "first," "second," and the like are used to explain various constituent elements, and the constituent elements are not limited to these terms. These terms are only used to distinguish one constituent element from another constituent element.

[0032] Figure 1 is an example block diagram of a display system according to an example embodiment.

[0033] refer to Figure 1 , the display system 100 may include a display device 110 and a host device 120 .

[0034] The display device 110 may receive image data IS transmitted from the host device 120 and display an image according to the image data IS. The display device 110 may include a pixel array 111, a driving circuit 112, and a timing controller 113. In some example embodiments, the display device 110 may further include a power supply circuit, such as a DC / DC converter, which provides a driving voltage to the pixel array 111, the driving circuit 112, and the timing controller 113.

[0035] In an exemplary embodiment, the pixel array 111 may display an image to a user based on image data received from the host device 120. The pixel array 111 may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an inorganic light emitting diode (ILED) display, a micro light emitting diode (μLED) display, an active matrix OLED display (AMOLED), a transparent OLED (TOLED) display, or the like. The pixel array 111 may include a plurality of pixels, a plurality of gate lines and a plurality of source lines respectively connected to the plurality of pixels. In an exemplary embodiment, the plurality of pixels may emit light of a primary color, such as red, green, blue, white, or yellow.

[0036] The driving circuit 112 receives image data, control signals, and the like from the timing controller 113 and outputs signals for driving the pixel array 111. The signals for driving the pixel array 111 may be transmitted to the plurality of pixels via a plurality of gate lines and a plurality of source lines. In an exemplary embodiment, the driving circuit 112 may generate gate signals and data signals for driving the plurality of pixels included in the pixel array 111 and provide the gate signals and data signals to the plurality of pixels. The plurality of pixels included in the pixel array 111 may emit image light in response to the signals provided by the driving circuit 112.

[0037] The timing controller 113 can generate image data, control signals, and the like to be provided to the driving circuit 112 based on an image signal IS received from the host device 120. The timing controller 113 can receive the image signal IS, process the image signal IS based on pre-stored settings, and generate image data based on the processed image signal IS. The timing controller 113 can generate a control signal for controlling the driving circuit 112 based on an externally received drive control signal CTRL, and transmit the control signal and image data to the driving circuit 112. The drive control signal CTRL can include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a main clock signal MCLK, and a data enable signal DE.

[0038] The timing controller 113 may include an image processing circuit 114 , a register 115 , an interface circuit 116 , and a recovery memory 117 .

[0039] The image processing circuit 114 may perform image processing on the image signal IS. For example, the image processing circuit 114 may compensate, scale, dim, color calibrate, or gamma calibrate the image signal IS. The image processing circuit 114 may generate image data based on the image-processed image signal IS.

[0040] In some example embodiments, the image processing circuit 114 may read the setting values stored in the register 115 and perform image processing on the image signal IS based on the setting values. Since the image processing circuit 114 performs various image processing, various setting values corresponding to the respective image processing may be stored in the register 115.

[0041] The register 115 may store a setting value received from the host device 120. The register 115 may receive a command CMD indicating write, an address ADDR, and data DQ of the register 115 from the host device 120, and store the input value as data DQ in a region corresponding to the address ADDR.

[0042] In some example embodiments, at least a portion of the image processing circuit 114 and at least a portion of the registers 115 may be power gated. During power gating, power to at least a portion of the image processing circuit 114 and at least a portion of the registers 115 may be interrupted.

[0043] The interface circuit 116 may interface with the host device 120. In some example embodiments, when a command CMD indicating a write, an address ADDR, and data DQ are input from the host device 120, the interface circuit 116 may store the data DQ in the register 115 indicated by the address ADDR. The interface circuit 116 may store the data DQ at an address of the recovery memory 117 corresponding to the address ADDR.

[0044] In some example embodiments, the interface circuit 116 may store the setting values in the restoration memory 117 and restore the setting values stored in the restoration memory 117 to the register 115. The setting values stored in the register 115, to which power supply is interrupted during the power gating period, may be lost or damaged, and thus cannot be used by the image processing circuit 114 after the power gating period ends. The interface circuit 116 may restore the setting values stored in the restoration memory 117 to the register 115 after the power gating period ends. Then, the image processing circuit 114 may use the restored setting values in the register 115 even after the power gating period ends. The interface circuit 116 may store the setting values corresponding to each register 115 in the register 115 based on the address of the restoration memory 117.

[0045] In some example embodiments, the interface circuit 116 may store the setting value in the recovery memory 117, receive a command CMD instructing reading from the host device 120, read the setting value from the recovery memory 117, and output the setting value to the host device 120. The interface circuit 116 may receive the read command CMD from the host device 120 and may not read the setting value stored in the register 115. Therefore, according to example embodiments, since wiring for reading the setting value from the register 115 is not required, area overhead may be reduced. This will be referred to later. Figures 9 to 12 Provide a description.

[0046] The recovery memory 117 may store setting values received from the host device 120. The recovery memory 117 may be implemented as a volatile memory. The volatile memory may be implemented as a random access memory (RAM), a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a thyristor RAM (T-RAM), a zero capacitor RAM (Z-RAM), or a two-transistor RAM (TTRAM).

[0047] In some example embodiments, the interface circuit 116 and the recovery memory 117 may not be power-gated. During a power-gated period, the setting value stored in the register 115 is volatilized, but the setting value stored in the recovery memory 117 may be maintained.

[0048] The host device 120 may be a computing device or system that controls the display device 110 to display an image desired by a user from an external source on the pixel array 111. The host device 120 may transmit image data IS based on the content to be presented to the user to the display device 110. The host device 120 may provide a drive control signal CTRL for controlling the display device 110 to the display device 110. The drive control signal CTRL may include a command CMD, an address ADDR, and data DQ. The data DQ may include a setting value for controlling the display device 110. In some example embodiments, the host device 120 may provide a command CMD such as sleep or wake-up to the display device 110. The host device 120 may provide a command CMD to write the setting value to the register 150 to the display device 110. The host device 120 may provide a command CMD to read the setting value from the display device 110.

[0049] Figure 2 is a block diagram illustrating a timing controller according to example embodiments.

[0050] refer to Figure 2 The timing controller 200 may include a power gating region 210. During a power gating period, power supply to the power gating region 210 may be interrupted. Power gating may not mean directly interrupting power supply to the power gating region 210, but may indicate shutting down a power gating module (PG) 290 connecting the power gating region 210 and a power source.

[0051] The timing controller may include a bus controller 220 , a register core 230 , an image processing circuit 240 , a bus-memory interface circuit 250 , a recovery memory 260 , a reload controller 270 , a power management unit (PMU, e.g., a power management circuit) 280 , and a power gating module (PG) 290 .

[0052] The bus controller 220 can receive data from the host device ( Figure 1 120) receives command CMD, address ADDR and data DQ.

[0053] The bus controller 220 may receive a command CMD indicating a write instruction, an address ADDR indicating a register 231a, 231b, 231c, ..., 231h, and data DQ from the host device 120, and store the data DQ in a register corresponding to the address ADDR among the registers 231a, 231b, 231c, ..., 231h. The bus controller 220 may receive a command CMD indicating a read instruction from the host device 120, and output the set value stored in the recovery memory 260 as data DQ to the host device 120 via the bus-memory interface circuit 250.

[0054] The register core 230 may include a plurality of registers 231a, 231b, 231c, ..., 231h and a multiplexer circuit 232 connected to the plurality of registers 231a, 231b, 231c, ..., 231h. The plurality of registers 231a, 231b, 231c, ..., 231h may store setting values used in corresponding intellectual property (IP) 241b, 241c, 241d, ..., 241j.

[0055] The multiplexer circuit 232 may select a register to store the data DQ among the plurality of registers 231 a , 231 b , 231 c , . . . , 231 h and provide the data DQ provided from the bus controller 220 to the selected register.

[0056] The image processing circuit 240 may process an input image signal IS and generate image data DATA. The image processing circuit 240 may include multiple IPs 241a, 241b, 241c, 241d, ..., 241j that process the image signal IS. Here, an IP refers to circuitry, logic, or a combination thereof that may be included in the image processing circuit 240. The multiple IPs 241a, 241b, 241c, 241d, ..., 241j may independently handle different multimedia processing tasks. Each of the multiple IPs 241a, 241b, 241c, 241d, ..., 241j may process the image signal IS sequentially or in parallel. In some example embodiments, the multiple IPs 241b, 241c, 241d, ..., 241j may perform image processing using setting values stored in the multiple registers 231a, 231b, 231c, ..., 231h. Each of the plurality of IPs 241b, 241c, 241d, ..., 241j may read a setting value stored in a corresponding register among the plurality of registers 231a, 231b, 231c, ..., 231h and perform image processing according to the setting value.

[0057] The bus-memory interface circuit 250 may receive an address ADDR and data DQ from the bus controller 220, and control the recovery memory 260 to store the data DQ in an area corresponding to the address ADDR of the recovery memory 260. The bus-memory interface circuit 250 may receive an address ADDR from the bus controller 220, and control the recovery memory 260 to output a set value stored in an area corresponding to the address ADDR of the recovery memory 260.

[0058] The recovery memory 260 can store at least some of the multiple setting values stored in the multiple registers 231a, 231b, 231c, ..., 231h. The recovery memory 260 can include multiple areas corresponding to multiple addresses ADDR. Each of the multiple areas can be previously associated with the address ADDR. The recovery memory 260 can receive the address ADDR and data DQ and store the data DQ in the area associated with the address ADDR. The recovery memory 260 can receive the address ADDR and output the data DQ stored in the area associated with the address ADDR.

[0059] The reload controller 270 may read the setting value stored in the restore memory 260 and output the setting value to the bus controller 220. In some example embodiments, the reload controller 270 may generate a restore address corresponding to the setting value. The reload controller 270 may receive a load signal LOAD from the power management unit 280 and generate the restore address based on the load signal LOAD. For example, the reload controller 270 may generate the restore address based on a value counted since receiving the load signal LOAD at an enable level. The reload controller 270 may send the setting value and the restore address to the bus controller 220. The bus controller 220 may send the setting value and the restore address to the register core 230. The register core 230 may store the setting value in a register corresponding to the restore address among registers 231a, 231b, 231c, ..., 231h.

[0060] The power management unit 280 may perform power gating based on characteristics of the image signal IS and / or the command CMD. For example, the power management unit 280 may determine a vertical blanking period based on the image signal IS and / or the command CMD, and may perform power gating to interrupt power to the power-gated region 210 during the vertical blanking period. In some example embodiments, the power management unit 280 may receive a power gating control signal PG_CS that interrupts power to the power-gated region and output a power gating signal PG_EN that controls the operation of the power gating module 290. The power gating control signal PG_CS may be generated based on the image signal IS and / or the command CMD. The power management unit 280 may generate a load signal LOAD based on the power gating control signal PG_CS and output the load signal LOAD to the reload controller 270.

[0061] The power gating module 290 can selectively supply VVDD to circuits in the power-gated region 210. The power gating module 290 can selectively supply VVDD to the registers 231a, 231b, 231c, ..., 231h, the multiplexer circuit 232, and the IPs 241b, 241c, 241d, ..., 241j of the power-gated region 210. The power gating module 290 can independently supply VVDD to the registers 231a, 231b, 231c, ..., 231h, the multiplexer circuit 232, and the IPs 241b, 241c, 241d, ..., 241j within the power-gated region 210. The power gating module 290 can selectively supply VVDD to all circuits within the power-gated region 210. The power gate control module 290 may include a plurality of switch units (e.g., switch circuits or transistors), each of which is associated with a different circuit in the power gated region 210. The power gate control module 290 may include a driver module or an intermediate software intelligence layer to independently control the plurality of switch units to selectively connect and disconnect the circuits in the power gated region 210 and the power supply that provides power VDD. The power gate control module 290 may receive a power gate control signal PG_EN at an enable level and interrupt the supply of power VDD to the power gated region 210. The power gate control module 290 may receive a power gate control signal PG_EN at a disable level and supply power VDD to the power gated region 210.

[0062] The timing controller 200 receives a command CMD from the host device 120 to read the set values stored in the plurality of registers 231a, 231b, 231c, ..., 231h and outputs the values stored in the restore memory 260 to the host device 120. This eliminates the need for additional wiring and multiplexers to read the set values stored in the plurality of registers 231a, 231b, 231c, ..., 231h, thereby reducing chip size. Furthermore, in the prior art, the plurality of registers are configured as data retention flip-flops, so that the set values stored in the plurality of registers are retained even when power gating is in effect. In contrast, in the timing controller 200 according to the exemplary embodiment, when power gating ends, the reload controller 270 restores the set values to the plurality of registers 231a, 231b, 231c, ..., 231h, thereby eliminating the need for data retention flip-flops and reducing chip size and power consumption.

[0063] Figure 3 is a diagram illustrating a portion of a timing controller according to an example embodiment.

[0064] refer to Figure 3, the timing controller 300 may include a bus controller 310 , a bus-memory interface circuit 320 , a reload controller 330 , a recovery memory 340 , and a power management unit (PMU) 350 .

[0065] The bus controller 310 can receive data from the host device ( Figure 1 The bus controller 310 receives a command CMD, an address ADDR, and data DQ from the register core REG_CORE. The bus controller 310 may receive a command CMD indicating a write, send the address ADDR and data DQ to the register core REG_CORE, and send the address ADDR and data DQ to the bus-memory interface circuit 320. The bus controller 310 may receive a command CMD indicating a read, and send the address ADDR to the bus-memory interface circuit 320. The bus controller 310 may receive data DQ from the bus-memory interface circuit 320. In some example embodiments, the bus controller 310 may receive the address ADDR and data DQ from the reload controller 330. The bus controller 310 may send the address ADDR and data DQ received from the reload controller 330 to the register core REG_CORE. The bus controller 310 may include a command decoder 311, a data read / write circuit 312, and a multiplexer circuit 313.

[0066] The command decoder 311 may receive a command CMD sent from the host device 120. The command decoder 311 may decode the received command CMD and generate a control signal CS and / or a power gating control signal PG_CS. The control signal CS may be provided to the data read / write circuit 312, and the power gating control signal PG_CS may be provided to the power management unit 350.

[0067] The data read / write circuit 312 can perform write and read operations based on the control signal CS. The data read / write circuit 312 can perform a write operation by sending an address ADDR and data DQ to the register core REG_CORE and the bus-memory interface circuit 320. The data read / write circuit 312 can perform a read operation by sending an address ADDR to the bus-memory interface circuit 320.

[0068] The multiplexer circuit 313 may output one of the address ADDR and data DQ output from the data read / write circuit 312 and the address ADDR and data DQ output from the reload controller 330. Based on the level of the load signal LOAD, the multiplexer circuit 313 may output one of the address ADDR and data DQ output from the data read / write circuit 312 and the address ADDR and data DQ output from the reload controller 330. For example, when the load signal LOAD is at an enable level, the multiplexer circuit 313 may output the address ADDR and data DQ output from the reload controller 330 to the register core REG_CORE. When the load signal LOAD is at a disable level, the multiplexer circuit 313 may output the address ADDR and data DQ output from the data read / write circuit 312 to the register core REG_CORE.

[0069] The bus-memory interface circuit 320 may receive an address ADDR and data DQ from the bus controller 310. The bus-memory interface circuit 320 may transmit input data DIN to the recovery memory 340 based on the memory address SADDR and the data DQ corresponding to the address ADDR. The input data DIN may be stored at the memory address SADDR of the recovery memory 340. The bus-memory interface circuit 320 may receive an address ADDR from the bus controller 310. The bus-memory interface circuit 320 may transmit the memory address SADDR corresponding to the address ADDR to the recovery memory 340, and receive output data DOUT stored at the memory address SADDR from the recovery memory 340. The bus-memory interface circuit 320 may include a bus interface circuit 321, an interface controller 322, a memory interface circuit 323, a working memory 324, and a bus 326. The bus interface circuit 321, the interface controller 322, the memory interface circuit 323, and the working memory 324 may communicate with each other via the bus 326.

[0070] The bus interface circuit 321 may provide a physical connection between the bus controller 310 and the bus-memory interface circuit 320. That is, the bus interface circuit 321 may provide an interface connection with the bus-memory interface circuit 320 according to the bus format of the bus controller 310.

[0071] The memory interface circuit 323 may communicate with the recovery memory 340. The memory interface circuit 323 may send data to the recovery memory 340 and receive data read from the recovery memory 340. In an example embodiment, the memory interface circuit 323 may be connected to the recovery memory 340 through one channel. In another example embodiment, the memory interface circuit 323 may be connected to the recovery memory 340 through multiple channels.

[0072] The interface controller 322 can control the operation of the bus interface circuit 321 according to a command received through the bus controller 310. The interface controller 322 can receive an address ADDR and data DQ from the bus controller 310 through the bus interface circuit 321, and determine a memory address SADDR corresponding to the address ADDR based on the register-memory mapping table 325. The interface controller 322 can send the memory address SADDR and input data DIN to the recovery memory 340 through the memory interface circuit 323, and store the input data DIN in the recovery memory 340. The interface controller 322 can receive an address ADDR from the bus controller 310 through the bus interface circuit 321, and determine a memory address SADDR corresponding to the address ADDR based on the register-memory mapping table 325. The interface controller 322 can read the output data DOUT by sending the memory address SADDR to the recovery memory 340 via the memory interface circuit 323.

[0073] The working memory 324 can store instructions and data executed and processed by the interface controller 322. The working memory 324 can also be implemented as a volatile memory (such as DRAM or static RAM (SRAM)) or a non-volatile memory (such as PRAM or flash memory). The working memory 324 can store a register-memory mapping table 325. Figure 4 and Figure 5 The register-memory mapping table 325 is described.

[0074] The reload controller 330 may receive a load signal LOAD from the power management unit 350. The reload controller 330 may receive the load signal LOAD at an enable level and generate an address ADDR and a memory address SADDR. The reload controller 330 may transmit the memory address SADDR to the recovery memory 340 and receive output data DOUT output from the recovery memory 340. The reload controller 330 may output the output data DOUT as data DQ to the bus controller 310. The reload controller 330 may output the data DQ together with the address ADDR. The reload controller 330 may include a bus interface circuit 331, an address generator 332, a memory interface circuit 333, a counter circuit 335, and a bus 336. The bus interface circuit 331, the address generator 332, the memory interface circuit 333, and the counter circuit 335 may communicate with each other via the bus 336.

[0075] The bus interface circuit 331 may provide a physical connection between the reload controller 330 and the bus controller 310. That is, the bus interface circuit 331 may provide an interface connection with the bus controller 310 according to the bus format of the reload controller 330. The bus interface circuit 331 may include a delay circuit 334. The delay circuit 334 may delay an address ADDR to be output to the bus controller 310 and output the address ADDR together with the data DQ.

[0076] The memory interface circuit 333 may communicate with the recovery memory 340. The memory interface circuit 333 may transmit data to the recovery memory 340. The memory interface circuit 333 may output a memory address SADDR to the recovery memory 340 and receive data read from the memory address SADDR of the recovery memory 340. In an example embodiment, the memory interface circuit 333 may be connected to the recovery memory 340 through one channel. In another example embodiment, the memory interface circuit 333 may be connected to the recovery memory 340 through multiple channels.

[0077] The counter circuit 335 may count the clock signal (eg, rising edges or falling edges), and may start counting when receiving the load signal LOAD at an enable level. The counter circuit 335 may output the count value to the address generator 332 .

[0078] The address generator 332 may generate an address ADDR and a memory address SADDR based on a value output by the counter circuit 335. The address generator 332 may output the memory address SADDR to the memory interface circuit 333 and output the address ADDR to the delay circuit 334.

[0079] The power management unit 350 may receive a power gating control signal PG_CS. The power management unit 350 may have any one of a power gating state, an idle state, and a reload state. When the power management unit 350 receives the power gating control signal PG_CS at an enable level, the power management unit 350 may change to the power gating state.

[0080] When the power gating control signal PG_CS transitions from the enable level to the disable level, the power management unit 350 changes the power gating state to the reload state and may maintain the reload state for a predetermined period of time. The power management unit 350 may output the load signal LOAD at the enable level in the reload state. The power management unit 350 may change to the idle state after the predetermined period of time has elapsed. The power management unit 350 may output the load signal LOAD to the multiplexer circuit 313 and the counter circuit 335.

[0081] Figure 4is a diagram illustrating a bus controller, a bus-memory interface circuit, a register core, and a recovery memory during data storage according to example embodiments.

[0082] Reference Figure 4 The bus controller 410 may receive a write command CMD_WR, an address ADDR, and data DQ. The bus controller 410 may output the address ADDR and data DQ to the register core 420 and the bus-memory interface circuit 430. The bus controller 410 may include a data read / write circuit 411 and a multiplexer circuit 412.

[0083] The data read / write circuit 411 can be based on the host device ( Figure 1 The multiplexer circuit 412 outputs the address ADDR and the data DQ sent from the data read / write circuit 411 to the multiplexer circuit 412 based on the write command CMD_WR received by the multiplexer circuit 412 (e.g., the write command CMD_WR received by the multiplexer circuit 412). The multiplexer circuit 412 can output the address ADDR and the data DQ sent from the data read / write circuit 411 based on the level of the load signal LOAD. For example, when the load signal LOAD is at a disable level, the multiplexer circuit 412 can output the address ADDR and the data DQ sent from the data read / write circuit 411 to the register core 420 and the bus-memory interface circuit 430. For example, when the load signal LOAD is at an enable level, the multiplexer circuit 412 can output the data DQ and the address ADDR output from the reload controller to the register core 420 and the bus-memory interface circuit 430.

[0084] The register core 420 may include a plurality of registers 421 corresponding to a plurality of addresses AA0, ..., AAFF. Each of the plurality of registers may store data DV. For example, the register corresponding to address AA2 may store a setting value SFR_A. The register core 420 may store data DQ in a register corresponding to the address ADDR based on the address ADDR and data DQ input from the bus controller 410. For example, if the address ADDR input to the register core 420 is "AA3" and the input data DQ is "FF", the register core 420 may store "FF" in the register corresponding to the address ADDR "AA3".

[0085] The bus-memory interface circuit 430 may determine a memory address SADDR corresponding to the address ADDR based on the address ADDR input from the bus controller 410. The bus-memory interface circuit 430 may include an address mapping table 431 in which the address ADDR and the memory address SADDR are mapped. The bus-memory interface circuit 430 may determine the memory address SADDR corresponding to the input address ADDR based on the address mapping table 431. The bus-memory interface circuit 430 may provide the determined memory address SADDR and input data DIN to the recovery memory 440. Here, the input data DIN may include data DQ input from the bus controller 410. For example, if the address ADDR input to the bus-memory interface circuit 430 is "AA3" and the input data DQ is "FF", the bus-memory interface circuit 430 may output a memory address SADDR "1" corresponding to "AA3" and input data DIN "FF".

[0086] The recovery memory 440 may receive a memory address SADDR and input data DIN from the bus-memory interface circuit 430. The recovery memory 440 may include a plurality of storage areas 441 corresponding to the memory address SADDR. The recovery memory 440 may store the input data DIN in the area corresponding to the memory address SADDR received from the bus-memory interface circuit 430. For example, if the memory address SADDR input to the recovery memory 440 is "1" and the input data DIN is "FF", the recovery memory 440 may store the data DV "FF" in the corresponding area.

[0087] According to an example embodiment, data DQ input from the host device 120 may be written to both the register core 420 and the recovery memory 440. According to an example embodiment, when a command CMD_RD to read data DV stored in the register 421 of the register core is received from the host device 120, the data DV stored in the recovery memory 440 may be output to the host device 120.

[0088] Figure 5 is a diagram illustrating a bus controller, a bus-memory interface circuit, a register core, and a recovery memory during data reading according to example embodiments.

[0089] refer to Figure 5 The bus controller 510 may receive a read command CMD_RD and an address ADDR. The bus controller 510 may output the address ADDR to the bus-memory interface circuit 530. The bus controller 510 may include a data read / write circuit 511 and a multiplexer circuit 512.

[0090] The data read / write circuit 511 can be based on the host device ( Figure 1 The multiplexer circuit 512 outputs the address ADDR sent from the data read / write circuit 511 based on the read command CMD_RD received by the multiplexer circuit 512 (e.g., the read command CMD_RD received by the multiplexer circuit 512). The multiplexer circuit 512 may output the address ADDR sent from the data read / write circuit 511 based on the level of the load signal LOAD. For example, when the load signal LOAD is at a disabled level, the multiplexer circuit 512 may output the address ADDR sent from the data read / write circuit 511 to the register core 520 and the bus-memory interface circuit 530.

[0091] Even if the address ADDR is input from the bus controller 510 , the register core 520 may not output the data DV from the register corresponding to the address ADDR.

[0092] In some example embodiments, when receiving the read command CMD_RD, the bus controller 510 may not output the address ADDR to the register core 520 .

[0093] The bus-memory interface circuit 530 may determine a memory address SADDR corresponding to the address ADDR based on the address ADDR input from the bus controller 510. The bus-memory interface circuit 530 may provide the determined memory address SADDR to the recovery memory 540. For example, if the address ADDR input to the bus-memory interface circuit 530 is "AA3", the bus-memory interface circuit 530 may output a memory address SADDR "1" corresponding to "AA3".

[0094] The recovery memory 540 may receive a memory address SADDR from the bus-memory interface circuit 530. The recovery memory 540 may output a value DV stored in an area corresponding to the memory address SADDR received from the bus-memory interface circuit 530. For example, if the memory address SADDR input to the recovery memory 540 is “1”, the recovery memory 540 may output data DV “FF” stored in an area corresponding to “1” as output data DOUT.

[0095] The bus-memory interface circuit 530 may transmit the output data DOUT output from the recovery memory 540 as data DQ to the bus controller 510. Then, the bus controller 510 may output the data DQ to the host device 120.

[0096] According to example embodiments, when a command CMD_RD to read data DV stored in the register 521 of the register core is received from the host device 120 , the data DV stored in the recovery memory 540 may be output to the host device 120 .

[0097] Figure 6 is a diagram illustrating a bus controller, a recovery control circuit, a register core, and a recovery memory during data recovery according to example embodiments.

[0098] Reference Figure 6 The power management unit 610 may receive the power gating control signal PG_CS. When the power gating control signal PG_CS transitions from an enable level to a disable level, the power management unit 610 may output the load signal LOAD at an enable level. For example, the power management unit 610 may output the load signal LOAD at an enable level for a predetermined period of time starting from the transition of the power gating control signal PG_CS from the enable level to the disable level. The power management unit 610 may output the load signal LOAD to the multiplexer 641 and the counter circuit 621.

[0099] The restore controller 620 may receive a load signal LOAD at an enable level and generate a memory address SADDR and a restore address PADDR. The restore controller 620 may include a counter circuit 621, an address generator 622, and a delay circuit 623.

[0100] The counter circuit 621 may receive a load signal LOAD and a clock signal CLK. The counter circuit 621 may count the clock signal CLK when the load signal LOAD is at an enable level. The counter circuit 621 may output a count value LOAD_CNT to the address generator 622.

[0101] The address generator 622 may generate a memory address SADDR and a resume address PADDR based on the count value LOAD_CNT. The memory address SADDR and resume address PADDR corresponding to the count value LOAD_CNT may be preset. The address generator 622 may output the memory address SADDR to the resume memory 630. The address generator 622 may output the resume address PADDR to the delay circuit 623. The resume address PADDR may include the address of the register 651.

[0102] The delay circuit 623 may receive the resume address PADDR, delay the resume address PADDR, and output the resume address PADDR as the address ADDR. The address ADDR may be output to the bus controller 640 together with the output data DOUT transmitted from the resume memory 630 through the delay circuit 623. When the output data DOUT is read from the resume memory 630, the resume address PADDR may be delayed by the delay circuit 623.

[0103] The recovery memory 630 may receive the memory address SADDR and output the value DV stored in the memory address SADDR as output data DOUT.

[0104] The bus controller 640 may receive the data DQ and the address ADDR output from the recovery controller 620. The data read / write circuit 642 may output the data DQ and the address ADDR output from the recovery controller 620 based on the level of the load signal LOAD. For example, when the load signal LOAD is at an enable level, the data read / write circuit 642 may output the data DQ and the address ADDR output from the recovery controller 620 to the register core 650.

[0105] The register core 650 may store the data DQ in a register corresponding to the address ADDR based on the address ADDR and the data DQ input from the bus controller 640 .

[0106] Because power supply to the register 651 is interrupted during power gating, data stored in the register 651 may not be maintained. According to example embodiments, when the power gating period ends, data stored in the restoration memory 630 may be restored to the register 651. Therefore, since the register core 650 does not include a data retention flip-flop for retaining data during power gating, the size and power consumption of the register core 650 may be reduced.

[0107] Figure 7 is a timing diagram illustrating a power gating operation of a display device according to example embodiments.

[0108] See Figure 7 , video data can be activated at time t0. At this time, the power management unit is in the idle state (PMU_STATE) and can output a power gate signal (PG_EN) at a disabled level. Because the power gate signal (PG_EN) is at a disabled level, power VVDD can be supplied to the register core (REG_CORE). The user value (USER_VALUE) stored in the register core (REG_CORE) can be maintained.

[0109] At time t1, the sleep command SLEEP may be input and the vertical blank period VERTICALBLANK may start. At time t2, the input of the sleep command SLEEP may be completed.

[0110] After the sleep command SLEEP is input, at time t3, the state PMU_STATE of the power management unit may change from the idle state IDLE to the power gate state PWR_GATE. The power management unit may output a power gate signal PG_EN at an enable level. Because the power gate signal PG_EN is at the enable level, the power supply VVDD to the register core REG_CORE may be interrupted. The user value USER VALUE stored in the register core REG_CORE may change to the invalid state INVALID.

[0111] At time t4, an awakening command AWAKE may be input. Upon inputting the awakening command AWAKE, the power management unit state PMU_STATE may change from the power gate state PWR_GATE to the reload state RELOAD at time t5. The power management unit may output a power gate signal PG_EN at a disable level. Because the power gate signal PG_EN is at a disable level, VVDD may be supplied to the register core REG_CORE. Because the power gate signal PG_EN changes from an enable level to a disable level, the load signal LOAD may change to an enable level.

[0112] At time t6 , the value DV stored in the restore memory may be output from the restore memory as output data DOUT by the load signal LOAD being at an enable level.

[0113] At time t7, the output data DOUT may be updated in the register core REG_CORE and the user value USER_VALUE may be restored to the register core REG_CORE.

[0114] At time t8, the state PMU_STATE of the power management unit may be changed from the reload state RELOAD to the idle state IDLE. At time t9, the video data may be activated ACTIVE VIDEO again.

[0115] Figure 8 is a timing diagram illustrating operations during power-up of a display driving device according to example embodiments.

[0116] Reference Figure 8 At time t20, the state PMU_STATE of the power management unit may change from the power gate state PWR_GATE to the reload state RELOAD. Therefore, the load signal LOAD may change to an enable level.

[0117] When the load signal LOAD is at the enable level (period t21 to t30), a count value LOAD_CNT can be output by counting the rising edges of the clock signal CLK. A memory address SADDR and a restore address PADDR can be generated based on the count value LOAD_CNT. At time t22, output data DOUT "SFR_A" can be output based on the memory address SADDR "0" generated at time t21 and output to the restore memory.

[0118] The restoration address PADDR may be delayed by a delay period DELAY PERIOD from time t21 and output as the address ADDR to the register core at time t23 , and the output data DOUT may be output as the data DQ to the register core.

[0119] At time t24, data DQ "SFR_A" may be stored in register REG_A of the register core. Similarly, from t25 to t30, data DQ may be stored in each register of the register core.

[0120] Figure 9 A display device according to an example embodiment is shown.

[0121] Reference Figure 9 The display device 900 may include a pixel array 910 including a plurality of pixels PX and a display driver 920. The pixel array 910 may be connected to the pixel array 910. The display driver 920 may output signals for driving the pixels PX to the pixel array 910.

[0122] The display driving device 920 may include an image processing circuit 921 and a register core 922. The image processing circuit 921 may perform image processing on an input image signal based on a setting value stored in the register core 922. The display driving device 920 may have a length along the X axis and a width along the Y axis.

[0123] Figure 10 shows a register core according to an example embodiment, and Figure 11 is a block diagram illustrating a selection signal generator according to example embodiments.

[0124] refer to Figure 10The register core 1000 may receive input data DI and a plurality of selection signals SEL1, ..., SELi, and store the input data DI in each of a plurality of registers REG_A, REG_B, REG_C, ..., REG_Z based on the plurality of selection signals SEL1, ..., SELi. The register core 1000 may receive a read selection signal SEL_RD, and selectively output the data stored in the plurality of registers REG_A, REG_B, REG_C, ..., REG_Z as output data DO based on the read selection signal SEL_RD.

[0125] The register core 1000 may include a plurality of registers REG_A, REG_B, REG_C, ..., REG_Z, a plurality of input multiplexer circuits MUX0, MUX1, MUX2, ..., MUXk, and an output multiplexer circuit MUX_OUT. Figure 10 , REG_Z and a plurality of input multiplexer circuits MUX0, MUX1, MUX2, . . . , MUXk connected to one output multiplexer circuit MUX_OUT are shown, but the register core 1000 may include Figure 10 Multiple register core groups MUX_OUT, REG_A, REG_B, REG_C, ..., REG_Z, MUX0, MUX1, MUX2, ..., MUXk.

[0126] Reference together Figure 10 and 11 , the register core 1100 may include selection signal generators 1110 and 1112. The selection signal generator 1110 may be from the bus controller ( Figure 3 310) receives a write control signal WR_ACCESS and an address ADDR, and outputs a plurality of selection signals SEL1, ..., SELi for selecting one of a plurality of input multiplexer circuits MUX0, MUX1, MUX2, ..., MUXk.

[0127] The selection signal generator 1112 may receive a read control signal RD_ACCESS and an address ADDR from the bus controller 310 and output a selection signal SEL_RD selecting one of data input to a plurality of output multiplexer circuits MUX_OUT based on the address ADDR.

[0128] Multiple input multiplexer circuits MUX0, MUX1, MUX2, ..., MUXk may be connected to multiple registers REG_A, REG_B, REG_C, ..., REG_Z. Multiple input multiplexer circuits MUX0, MUX1, MUX2, ..., MUXk may select one of input data DI and outputs of multiple registers REG_A, REG_B, REG_C, ..., REG_Z based on multiple selection signals SEL1, ..., SELi, and output the selected data to the multiple registers REG_A, REG_B, REG_C, ..., REG_Z.

[0129] The output multiplexer circuit MUX_OUT can be connected to the multiple registers REG_A, REG_B, REG_C, ..., REG_Z through multiple wirings 1010a, 1010b, 1010c, ..., 1010z. The output multiplexer circuit MUX_OUT can output data output from the multiple registers REG_A, REG_B, REG_C, ..., REG_Z as output data DO based on the read selection signal SEL_RD.

[0130] Because multiple wirings 1010a, 1010b, 1010c, ..., 1010z are connected to the input terminal 1020 of the output multiplexer circuit MUX_OUT, the overall size of the display driving device can be increased by the length in the X-axis direction and the width in the Y-axis direction occupied by the multiple wirings 1010a, 1010b, 1010c, ..., 1010z.

[0131] Figure 12 A register core according to an example embodiment is shown.

[0132] refer to Figure 12 The register core 1200 may receive input data DI and a plurality of selection signals SEL1, ..., SELi, and store the input data DI in each of a plurality of registers REG_A, REG_B, REG_C, ..., REG_Z based on the plurality of selection signals SEL1, ..., SELi. The register core 1200 may include a plurality of registers REG_A, REG_B, REG_C, ..., REG_Z and a plurality of input multiplexer circuits MUX0, MUX1, MUX2, ..., MUXk.

[0133] although Figure 12 A plurality of registers REG_A, REG_B, REG_C, ..., REG_Z and a plurality of input multiplexer circuits MUX0, MUX1, MUX2, ..., MUXk are shown, but the register core 1000 may include Figure 12Multiple register core groups MUX_OUT, REG_A, REG_B, REG_C, ..., REG_Z, MUX0, MUX1, MUX2, ..., MUXk.

[0134] Multiple input multiplexer circuits MUX0, MUX1, MUX2, ..., MUXk may be connected to multiple registers REG_A, REG_B, REG_C, ..., REG_Z. Multiple input multiplexer circuits MUX0, MUX1, MUX2, ..., MUXk may select one of input data DI and outputs of multiple registers REG_A, REG_B, REG_C, ..., REG_Z based on multiple selection signals SEL1, ..., SELi, and output the selected data to the multiple registers REG_A, REG_B, REG_C, ..., REG_Z.

[0135] The display driving device according to the example embodiment may not include an output multiplexer circuit and a plurality of wirings connecting the output multiplexer circuit and the plurality of registers REG_A, REG_B, REG_C, . . . , REG_Z. Figure 10 Compared with the display driving device of FIG. 1 , the size of the display driving device is smaller because the display driving device does not include an area caused by the length in the X-axis direction and the width in the Y-axis direction occupied by a plurality of wirings.

[0136] Figure 13 A display system according to an example embodiment is shown.

[0137] Reference Figure 13 , a display system 1300 according to an example embodiment may include a processor 1310 , a memory 1320 , a display device 1330 , and a peripheral device 1340 , which are electrically connected to a system bus 1350 .

[0138] The processor 1310 controls input and output of data from the memory 1320 , the display device 1330 , and the peripheral device 1340 , and may perform image processing of image data transmitted between the corresponding devices.

[0139] The memory 1320 may include volatile memory (such as dynamic random access memory (DRAM)) and / or non-volatile memory (such as flash memory). The memory 1320 may include DRAM, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), NOR flash memory, NAND flash memory, and fusion flash memory (e.g., memory combined with static random access memory (SRAM) buffer and NAND flash memory and NOR interface logic). The memory 1320 may store image data obtained from the peripheral device 1340 or image signals processed by the processor 1310.

[0140] The display device 1330 may include a display panel 1331 and a display driver device 1332. The display driver device 1332 may include Figures 1 to 12 The timing controller described in

[13] is provided. The display driver device 1332 can display an image signal applied via the system bus 1350 on the display panel 1331. The display driver device 1332 may also include a power-gated region, wherein an image processing circuit that processes image signals and a register storing setting values used in the image processing circuit are located in the power-gated region. The display driver device 1332 may also include a restore memory that stores setting values when the power-gated region is in a power-gated state. When the power-gated state of the power-gated region ends, the display driver device 1332 can restore the setting values to the register using the setting values stored in the restore memory.

[0141] The peripheral device 1340 may be a device that converts a moving picture (such as a camera, scanner, or webcam) or a still image into an electrical signal. Image data obtained by the peripheral device 1340 may be stored in the memory 1320 or displayed on the display panel 1331 in real time.

[0142] The display system 1300 may be implemented in a mobile electronic product such as a smart phone, but is not limited thereto, and may be implemented in various types of electronic products that display images.

[0143] In some example embodiments, reference Figures 1 to 12 Each constituent element described or a combination of two or more constituent elements may be implemented by a digital circuit, a programmable or non-programmable logic device or array, or an application-specific integrated circuit (ASIC) or the like.

[0144] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A timing controller comprising: a plurality of registers located in the power-gated region and configured to store a plurality of setting values; an image processing circuit configured to receive an image signal and perform image processing on the image signal based on the plurality of setting values; a recovery memory located outside the power-gated region and configured to store the plurality of setting values; as well as A bus controller is configured to receive the plurality of setting values and store the plurality of setting values in the plurality of registers and the restore memory.

2. The timing controller according to claim 1, wherein The bus controller is further configured to receive a read command and an address indicating one of the plurality of registers, and output a setting value read based on a memory address corresponding to the address of the restore memory to the outside.

3. The timing controller according to claim 2 , further comprising a bus-memory interface circuit configured to receive the address from the bus controller, store a mapping table in which the address and the memory address are mapped, and transmit the setting value read from the recovery memory to the bus controller based on the memory address.

4. The timing controller according to claim 1, further comprising: a power gating circuit configured to selectively supply power from a power source to the power gating region; as well as The power management circuit is configured to output a power gating signal at an enable level to the power gating circuit during a power gating period to control the power gating circuit to not supply power to the power gating region during the power gating period. 5 . The timing controller according to claim 4 , further comprising a reload controller configured to read the plurality of setting values stored in the recovery memory and store the plurality of setting values in the plurality of registers when the power gating period ends.

6. The timing controller according to claim 5, wherein the power management circuit is further configured to output the load signal at the enable level at the end of the power gating period, and The bus controller is further configured to receive the plurality of setting values read by the reload controller, and store the plurality of setting values in the plurality of registers when the load signal is at the enable level.

7. The timing controller according to claim 6, wherein the reload controller comprises: a counter circuit configured to count a clock signal based on the load signal being at the enable level; an address generator configured to generate an address indicating one of the plurality of registers and a memory address corresponding to the address based on a value output by the counter circuit; a memory interface circuit configured to output the memory address to the recovery memory and receive data stored in the memory address; as well as The delay circuit is configured to delay the address so that the address is output together with the data. 8 . The timing controller according to claim 1 , wherein the image processing circuit includes a plurality of processing circuits configured to process the image signal using the plurality of setting values. 9 . The timing controller of claim 8 , wherein at least one processing circuit of the plurality of processing circuits is located in the power-gated region.

10. The timing controller according to claim 1, further comprising a plurality of input multiplexer circuits, the plurality of input multiplexer circuits comprising a first input multiplexer circuit and a second input multiplexer circuit, wherein the plurality of registers include a first register and a second register, wherein the first register is connected between the input and the output of the first input multiplexer circuit, wherein the second register is connected between the input and output of the second input multiplexer circuit, and The plurality of input multiplexer circuits are configured to output one of the plurality of setting values based on a plurality of selection signals. 11 . The timing controller according to claim 10 , further comprising a selection signal generator configured to receive a plurality of addresses corresponding to the plurality of registers and generate the plurality of selection signals based on the plurality of addresses.

12. A display device comprising: a pixel array comprising a plurality of pixels, a plurality of gate lines and a plurality of source lines respectively connected to the plurality of pixels; a driving circuit configured to transmit signals for driving the plurality of pixels to the plurality of source lines based on image data; as well as A timing controller is configured to receive a plurality of setting values, store the plurality of setting values in a plurality of registers and a recovery memory, receive an image signal, process the image signal based on the plurality of setting values stored in the plurality of registers to obtain a processed image signal, generate the image data based on the processed image signal, and provide the image data to the driving circuit. 13 . The display device of claim 12 , wherein the plurality of registers are power gated during a power gating period. 14 . The display device of claim 13 , wherein the timing controller is further configured to restore the plurality of setting values stored in the restoration memory to the plurality of registers when the power gating period ends. 15 . The display device of claim 14 , wherein the timing controller is further configured to process the image signal based on the plurality of setting values restored to the plurality of registers at the end of the power gating period. 16 . The display device of claim 12 , wherein the timing controller is further configured to receive a command for reading the plurality of setting values and output the plurality of setting values stored in the restoration memory.

17. The display device according to claim 16, wherein the timing controller is further configured to receive the command and an address indicating one of the plurality of registers, determine a memory address corresponding to the address, and output a setting value among the plurality of setting values stored in an area of the recovery memory corresponding to the memory address.

18. A display system comprising: a host device configured to output a plurality of addresses and a plurality of setting values corresponding to the plurality of addresses; as well as A display device is configured to store the plurality of setting values in a plurality of registers indicated by the plurality of addresses, store the plurality of setting values in a restoration memory based on a plurality of memory addresses corresponding to the plurality of addresses, and restore the plurality of setting values stored in the restoration memory to the plurality of registers. 19 . The display system according to claim 18 , wherein the display device is further configured to restore the plurality of setting values stored in the restoration memory to the plurality of registers when a power gating period ends.

20. The display system according to claim 18, wherein the host device is further configured to output at least one of the plurality of addresses and a read command, and The display device is further configured to output at least one setting value among the plurality of setting values from the restoration memory to the host device based on at least one address among the plurality of addresses.

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