Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel is provided with fan-out connecting lines, the fan-out connecting lines are connected with first-class data lines, and first-class control transistors and second-class control transistors are arranged between signal input lines and two corresponding second-class data lines respectively. The first type control transistors and the second type control transistors are arranged between the signal input lines and the two corresponding fan-out connecting lines, so that the frame can be reduced; the second type of data lines connected with the first sub-pixel units are electrically connected with the first type of control transistors, and the second type of data lines connected with the second sub-pixel units are electrically connected with the second type of control transistors, so that the second type of data lines connected with the first sub-pixel units are similar or even the same in interference of the adjacent second type of data lines; the display uniformity is improved, and display abnormity is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the refresh rate of display devices is getting higher and higher. Correspondingly, the number of signal lines required in display devices is increasing, while the channels of driver chips are limited. Increasing the signal lines requires increasing the number of driver chips, which will lead to increased costs, increased borders and other problems. In order to solve the above problems, existing display devices have proposed a mux (multiplexing) technology. Even if two signal lines are connected to the channel of a driver chip under the control of the multiplexing line, there is no need to increase the driver chip when the frequency increases and the number of signal lines increases, thus reducing costs and reducing the border. In order to further reduce the border, the display device will adopt FIAA (Fanout In AA, setting the fan-out traces in the display area) technology. However, in actual use, it was found that when the display device adopts the Real RGB arrangement, the use of mux technology and FIAA technology at the same time will cause display abnormalities.

[0003] Therefore, when existing display devices using the Real RGB arrangement adopt both the mux technology and the FIAA technology, technical problems such as display abnormality may occur. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a display device to alleviate the technical problem of display abnormality that occurs when existing display devices using a Real RGB arrangement simultaneously use mux technology and FIAA technology.

[0005] To achieve the above-mentioned object, according to a first aspect of the present application, a display panel is provided, comprising a plurality of pixel units, each of the pixel units comprising a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit of different luminous colors, wherein within each pixel unit, the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit are sequentially arranged along a first direction; the display panel comprises:

[0006] Multiple scan lines;

[0007] a plurality of data lines, each of the data lines being connected to a sub-pixel unit of the same luminous color, and the plurality of data lines comprising a plurality of first-type data lines and a plurality of second-type data lines;

[0008] a plurality of fan-out connection lines electrically connected to the first type of data lines, wherein the plurality of data lines and the plurality of fan-out connection lines are arranged at intervals along a first direction;

[0009] a plurality of signal input lines, some of which are electrically connected to two second-type data lines, and some of which are electrically connected to two fan-out connection lines, and a first-type control transistor and a second-type control transistor are respectively provided between the signal input line and the corresponding two second-type data lines, a first-type control transistor and a second-type control transistor are respectively provided between the signal input line and the corresponding two fan-out connection lines, a gate of the first-type control transistor is connected to a first signal control line, and a gate of the second-type control transistor is connected to a second signal control line, an input time period of an effective level of the first signal control line does not overlap with an input time period of an effective level of the scan line, and an input time period of an effective level of the second signal control line overlaps with an input time period of an effective level of the scan line;

[0010] The second-type data line connected to the first sub-pixel unit is electrically connected to the first-type control transistor, and the second-type data line connected to the second sub-pixel unit is electrically connected to the second-type control transistor.

[0011] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0012] Embodiments of the present application provide a display panel and a display device; the display panel is configured to reduce the border by setting a fan-out connection line so that the fan-out connection line is connected to the first-type data line, and a first-type control transistor and a second-type control transistor are respectively provided between the signal input line and the corresponding two second-type data lines, and a first-type control transistor and a second-type control transistor are provided between the signal input line and the corresponding two fan-out connection lines; and the second-type data line connected to the first sub-pixel unit is electrically connected to the first-type control transistor, and the second-type data line connected to the second sub-pixel unit is electrically connected to the second-type control transistor, so that the second-type data line connected to the first sub-pixel unit is subject to similar or even identical interference from adjacent second-type data lines, thereby improving display uniformity and avoiding display abnormalities.

[0013] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0015] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0016] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0017] Figure 2 This is a first schematic diagram of the pixel arrangement and signal line arrangement of the display panel provided in an embodiment of the present application.

[0018] Figure 3 for Figure 2 Schematic diagram of the pixel arrangement of the display panel and the connection relationship between the signal lines and transistors.

[0019] Figure 4 This is a second schematic diagram of the pixel arrangement and signal line arrangement of the display panel provided in an embodiment of the present application.

[0020] Figure 5 for Figure 4 Schematic diagram of the pixel arrangement of the display panel and the connection relationship between the signal lines and transistors.

[0021] Figure 6 This is a timing diagram of some signal lines in the display panel provided in an embodiment of the present application.

[0022] Figure 7 A schematic diagram of a comparative display device provided in an embodiment of the present application.

[0023] Figure 8 A schematic diagram of another comparative display device provided in an embodiment of the present application.

[0024] Figure 9 A schematic diagram of another comparative display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "connection" and "electrical connection" should be understood in a broad sense. For example, it can mean direct connection or indirect connection through an intermediate medium, internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0027] In order to illustrate the principle of the technical problem of the embodiment of the present application, some comparative display devices are provided. It is understandable that these comparative display devices cannot be used as the prior art in the embodiment of the present application. In order to reduce the frame and reduce the cost, the comparative display devices will use both mux technology and FIAA technology. When the pixel arrangement of the comparative display device is SPR (Sub Pixel Rendering) design (for example, Figure 7 In the example, the red sub-pixel 311 and the blue sub-pixel 313 are located in the same column, and the green sub-pixel 312 is located in a separate column. Figure 7 As shown, the data line DL and the fan-out line FL can be designed in a 1:1 ratio. Two multiplexing lines (i.e., the first multiplexing line Mux01 and the second multiplexing line Mux02) and the control tube T001 are used to control the signal input of the data line DL, and adjacent fan-out lines FL are connected to the same multiplexing line, so that the comparison display device can display normally.

[0028] When the pixel arrangement in the comparative display device is a Real RGB arrangement (the red sub-pixel 311, the blue sub-pixel 313, and the green sub-pixel 312 are located in a separate column, and the red sub-pixel 311, the green sub-pixel 312, and the blue sub-pixel 313 are arranged in sequence), the ratio of the data line DL to the fan-out line FL is 2:1, and two multiplexing lines (i.e., the first multiplexing line Mux01 and the second multiplexing line Mux02) are used to control the signal input of the data line. For example, Figure 8 As shown, if the control tubes T001 connected to the data lines DL are still alternately electrically connected to different multiplexing lines, the control tubes T001 connected to the data lines of the sub-pixels of the same luminous color will be electrically connected to different multiplexing lines, for example Figure 8The first data line DL and the fourth data line DL both drive the red sub-pixel 311, but the control tubes T001 connected to the first data line DL and the fourth data line DL are electrically connected to different multiplexing lines, and the opening time of different multiplexing lines is different from that of the scanning line, so that the data line DL connected to the same control tube T001 as the first multiplexing line Mux01 is pre-charged, and the data line DL connected to the same control tube T001 as the second multiplexing line Mux02 is directly charged, which will cause the charging voltages of the first data line DL and the fourth data line DL to be different, resulting in inconsistent brightness of sub-pixels of the same luminous color, resulting in display abnormality.

[0029] In response to the above problems, Figure 9 As shown, some other comparative display devices make the control transistor connected to the data line DL connected to the red sub-pixel 311 electrically connected to the same multiplexing line (for example Figure 9 The control transistors connected to the data line DL connected to the red sub-pixel 311 are all electrically connected to the first multiplexing line Mux01), and the control transistor T001 connected to the data line DL connected to the green sub-pixel 312 is electrically connected to different multiplexing lines (for example Figure 9 The control transistor T001 connected to the second data line DL connected to the green sub-pixel 312 is electrically connected to the first multiplexing line Mux01, and the control transistor T001 connected to the fifth data line DL connected to the green sub-pixel 312 is connected to the second multiplexing line Mux02. This causes the control transistor T001 connected to the data line DL connected to the blue sub-pixel 313 to be electrically connected to different multiplexing lines. Furthermore, the control transistor T001 connected to the fan-out line FL adjacent to the data line DL connected to the red sub-pixel 311 is connected to different multiplexing lines (for example, the control transistor T001 connected to the fan-out line FL to the left of the fourth data line DL is connected to the second multiplexing line Mux02, and the control transistor T001 connected to the fan-out line FL to the left of the tenth data line DL is connected to the first multiplexing line Mux01). This will cause the different data lines connected to the red sub-pixel to be subjected to inconsistent interference, resulting in display anomalies. Therefore, existing display devices using a Real RGB arrangement will experience display anomalies when using both mux technology and FIAA technology.

[0030] In response to the above technical problems, embodiments of the present application provide a display panel and a display device to alleviate the above technical problems.

[0031] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 2 This is a first schematic diagram of the pixel arrangement and signal line arrangement of the display panel provided in an embodiment of the present application. Figure 3 for Figure 2Schematic diagram of the pixel arrangement of the display panel and the connection relationship between the signal lines and transistors. Figure 4 This is a second schematic diagram of the pixel arrangement and signal line arrangement of the display panel provided in an embodiment of the present application. Figure 5 for Figure 4 Schematic diagram of the pixel arrangement of the display panel and the connection relationship between the signal lines and transistors. Figure 6 This is a timing diagram of some signal lines in the display panel provided in an embodiment of the present application.

[0032] like Figures 1 to 6 As shown, an embodiment of the present application provides a display panel, which includes a plurality of pixel units 11, each of which includes a first sub-pixel unit 111, a second sub-pixel unit 112, and a third sub-pixel unit 113 of different luminous colors. In each of the pixel units, the first sub-pixel unit 111, the second sub-pixel unit 112, and the third sub-pixel unit 113 are arranged in sequence along a first direction X.

[0033] Specifically, for ease of explanation, the following embodiments are described using the light-emitting colors of the first sub-pixel unit 111, the second sub-pixel unit 112, and the third sub-pixel unit 113 as red, green, and blue, respectively, that is, the first sub-pixel unit 111, the second sub-pixel unit 112, and the third sub-pixel unit 113 are red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. However, the embodiments of the present application are not limited to this, and the light-emitting colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit can be green, red, and blue, respectively.

[0034] Specifically, such as Figure 1 As shown, the display panel 1 includes multiple scan lines SCL and multiple data lines Data, each of the scan lines SCL controls a row of pixel units to write data signals, and each of the data lines inputs data signals to a column of sub-pixel units to make the sub-pixel units display or not display.

[0035] Specifically, such as Figure 1 As shown, in order to reduce the border, the data line Data includes a first-class data line Data1 and a second-class data line Data2, and the display panel 1 also includes a fan-out connection line FIAA, which is connected to the first-class data line Data1. The first-class data line Data1 is connected to the driver chip through the fan-out connection line FIAA, so there is no need to wind from both sides of the display panel 1 to the lower border, thereby reducing the border of the display panel 1.

[0036] In some embodiments, as Figures 1 to 6As shown, the display panel 1 includes a plurality of pixel units 11, each of the pixel units 11 includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged in sequence. In each of the pixel units, the red sub-pixel, the green sub-pixel, and the blue sub-pixel are arranged in sequence along a first direction X; the display panel 1 includes a plurality of scan lines SCL, a plurality of data lines Data, a plurality of fan-out connection lines FIAA, and a plurality of signal input lines SL, each of the data lines Data is connected to a sub-pixel unit of the same luminous color, and the plurality of data lines Data include a plurality of first-type data lines Data1 and a plurality of second-type data lines Data2; a plurality of fan-out connection lines FIAA are electrically connected to the first-type data lines Data1, and the plurality of data lines Data and the plurality of fan-out connection lines FIAA are arranged at intervals along the first direction X; a plurality of signal input lines SL, some of the signal input lines SL are connected to two of the second-type data lines D ata2 is electrically connected, part of the signal input line SL is electrically connected to the two fan-out connection lines FIAA, and a first-type control transistor T01 and a second-type control transistor T02 are respectively provided between the signal input line SL and the corresponding two second-type data lines Data2, a first-type control transistor T01 and a second-type control transistor T02 are respectively provided between the signal input line SL and the corresponding two fan-out connection lines FIAA, a gate of the first-type control transistor T01 is connected to the first signal control line Mux1, and a gate of the second-type control transistor T02 is connected to the second signal control line Mux2, an input time period of an effective level of the first signal control line Mux1 does not overlap with an input time period of an effective level of the scan line SCL, and an input time period of an effective level of the second signal control line Mux2 overlaps with an input time period of an effective level of the scan line SCL;

[0037] The second-type data line Data2 connected to the red sub-pixel is electrically connected to the first-type control transistor T01 , and the second-type data line Data2 connected to the green sub-pixel is electrically connected to the second-type control transistor T02 .

[0038] An embodiment of the present application provides a display panel, which can reduce the border by setting a fan-out connection line FIAA to connect the fan-out connection line FIAA to the first-type data line Data1, and respectively providing a first-type control transistor T01 and a second-type control transistor T02 between the signal input line SL and the corresponding two second-type data lines Data2.

[0039] At the same time, the embodiment of the present application electrically connects the second-type data line Data2 connected to the red sub-pixel to the first-type control transistor T01, so that the second-type data line Data2 connected to the red sub-pixel is controlled by the first signal control line Mux1, and the second-type data line Data2 connected to the green sub-pixel is electrically connected to the second-type control transistor T02, so that the second-type data line Data2 connected to the green sub-pixel is controlled by the second signal control line Mux2. The red sub-pixel is arranged adjacent to the green sub-pixel, so that the second-type data line Data2 connected to each red sub-pixel is interfered with by the second-type data line Data2 controlled by the second signal control line Mux2, so that the second-type data line Data2 connected to each red sub-pixel is interfered with by the adjacent second-type data line Data2, thereby improving display uniformity and avoiding display abnormalities.

[0040] For example, if Figure 3 As shown, the first second-class data line Data31, the fourth second-class data line Data34, the seventh second-class data line Data37, and the tenth second-class data line Data40 are all connected to red sub-pixels, and these second-class data lines are all connected to the first-class control transistor T01, and the first-class control transistor T01 is controlled by the same signal control line (i.e., the first signal control line Mux1). The signal input of each red sub-pixel is synchronized, thereby avoiding uneven display due to asynchronous signal input, so that the display uniformity of each red sub-pixel is better; similarly, the display uniformity of each green sub-pixel is better.

[0041] At the same time, if Figure 6 As shown, taking the scan line SCL including the first scan line Pscan1 and the second scan line Pscan2 as an example, Figure 6 It can be seen that the effective level of the first signal control line Mux1 is staggered with the effective level of the first scan line Pscan1 and the second scan line Pscan2, while the effective level of the second signal control line Mux2 overlaps with the effective level of the second scan line Pscan2. When the writing of the data line is controlled by the first signal control line Mux1 and the second signal control line Mux2, the control transistor is first turned on through the first signal control line Mux1 to input the voltage to the data line. When the first scan line Pscan1 turns on the switching transistor in the pixel driving circuit, the voltage stored on the data line is written, that is, the data line controlled by the first signal control line Mux1 is pre-charged; and when the second signal control line Mux2 turns on the control transistor to write the data signal, the second scan line Pscan2 will simultaneously turn on the switching transistor to complete the writing of the data, that is, the data line controlled by the second signal control line Mux2 is directly charged.

[0042] Because the data lines controlled by the second signal control line Mux2 are directly charged, they are less susceptible to or even no interference from other signal lines. However, the data lines controlled by the first signal control line Mux1 are pre-charged and are more susceptible to interference from other signal lines. Therefore, the data lines controlled by the first signal control line Mux1 can be interfered with by the data lines controlled by the second signal control line Mux2 or by the fan-out connection lines controlled by the second signal control line Mux2. If the signal control lines electrically connected to the signal lines on both sides of the data lines controlled by the first signal control line Mux1 are different, data writing discrepancies can occur, resulting in vertical streaks.

[0043] In the embodiment of the present application, Figure 3 It can be seen that in the embodiment of the present application, the second-category data lines on the right side of the first second-category data line Data31, the fourth second-category data line Data34, the seventh second-category data line Data37, and the tenth second-category data line Data40 are all controlled by the second signal control line Mux2, so that the first second-category data line Data31, the fourth second-category data line Data34, the seventh second-category data line Data37, and the tenth second-category data line Data40 are subject to similar or even identical interference from the signal lines on the right side, thereby improving display uniformity and avoiding display abnormalities.

[0044] Specifically, the first type of control transistors T01 includes a first sub-type control transistor T1 and a second sub-type control transistor T3 , and the second type of control transistors T02 includes a third sub-type control transistor T2 and a fourth sub-type control transistor T4 .

[0045] Specifically, such as Figure 1 As shown, the display panel 1 includes a display area 101 and a non-display area 102 . The non-display area 102 can be arranged on one side, two sides, three sides or four sides of the display area 101 . The non-display area 102 can be bent to the back side of the display panel 1 .

[0046] Specifically, such as Figures 1 to 6As shown, the display area 101 is provided with an array of pixel units 11 arranged along a first direction X and a second direction Y, with the angle between the first direction X and the second direction Y being greater than 0 and less than or equal to 90 degrees. The pixel unit 11 includes multiple sub-pixel units, and each column of sub-pixel units emits the same luminous color. The non-display area 102 is provided with a driver chip 12, which integrates a multiplexing control circuit. The multiplexing control circuit includes a signal control line Mux, a first type of control transistor T01, and a second type of control transistor T02. The signal control line includes a first signal control line Mux1 and a second signal control line Mux2. The first type of control transistor T01 includes a first sub-type control transistor T1, a second sub-type control transistor T3, and a third sub-type control transistor. The second type of control transistor T02 includes a third sub-type control transistor T2, a second sub-type control transistor T3, and a fourth sub-type control transistor T4. By integrating the multiplexing control circuit into the driver chip 12, the bezel can be reduced.

[0047] Specifically, such as Figure 1 As shown, the display area 101 is provided with a first type of data line Data1, a second type of data line Data2 and a fan-out connection line FIAA. Figure 1 As can be seen, the first type of data line Data1 may not be directly connected to the driver chip 12, but may be connected to the driver chip 12 through the adapter line ZL and the fan-out connection line FIAA to realize signal input, thereby reducing the bottom frame and the left and right frames. The second type of data line Data2 may be directly connected to the driver chip 12.

[0048] It can be understood that, for the sake of convenience of explanation, in the embodiment of the present application, some of the data lines directly connected to the driver chip and some of the data lines connected to the driver chip through the fan-out connection line FIAA are named as second-class data lines and first-class data lines, respectively. However, in actual design, the width and other designs of the first-class data line Data1 and the second-class data line Data2 may not be different.

[0049] Specifically, for ease of explanation, the longitudinal portion and the transverse portion of a line connecting the first type of data line Data1 are named fan-out connection line FIAA and adapter line ZL respectively, but the fan-out connection line FIAA and the adapter line ZL transmit the same signal, and their width and other designs may not differ.

[0050] It can be understood that the embodiment of the present application shows the design of the first-class data line Data1, the second-class data line Data2, the fan-out connection line and the adapter line on the left side. It can be understood that the first-class data line Data1, the second-class data line Data2, the fan-out connection line and the adapter line on the right side can be symmetrical with the first-class data line Data1, the second-class data line Data2, the fan-out connection line and the adapter line on the left side respectively.

[0051] It can be understood that in the embodiment of the present application, due to space limitations, two signal lines can be set in the corresponding area of each column of sub-pixel units. In the setting area corresponding to the second-type data line Data2, the two signal lines on each column of sub-pixel units can be composed of: a second-type data line Data2, a fan-out connection line FIAA; or a second-type data line Data2, a high-potential power line VDD; in the setting area corresponding to the first-type data line Data1, the two signal lines on each column of sub-pixel units can be composed of: a first-type data line Data1, a low-potential power line; or a first-type data line Data1, a high-potential power line VDD; and the arrangement of the signal lines in the setting area of the first-type data line Data1 is the same as the arrangement of the same number of signal lines in the setting area of the second-type data line Data2, the only difference is that some signal lines in the setting area of the first-type data line Data1 are used as low-potential power lines, and some signal lines in the setting area of the second-type data line Data2 are used as fan-out connection lines FIAA.

[0052] In some embodiments, the fan-out connection line FIAA electrically connected to the first sub-pixel unit 111 is electrically connected to the second sub-class control transistor T3, and the fan-out connection line FIAA electrically connected to the second sub-pixel unit 112 is electrically connected to the fourth sub-class control transistor T4.

[0053] Specifically, it can be seen from the above embodiments that when the data lines connected to red sub-pixels of the same luminous color are controlled by different signal control lines, uneven display will occur. Similarly, when the fan-out connection lines connected to red sub-pixels of the same luminous color are controlled by different signal control lines, the charging time of each red sub-pixel may be different, resulting in uneven display. Figure 3 As shown, in the embodiment of the present application, the first fan-out connection line FIAA1 and the fifth fan-out connection line FIAA5 connected to the red sub-pixel are both electrically connected to the second sub-class control transistor T3, and the second fan-out connection line FIAA2 and the fourth fan-out connection line FIAA4 connected to the green sub-pixel are both connected to the fourth sub-class control transistor T4, so that the signal input of the red sub-pixel is synchronized, and the signal input of the green sub-pixel is synchronized, thereby avoiding uneven display caused by asynchronous signal input.

[0054] Specifically, such as Figure 3 As shown, taking the ratio of the data lines Data to the fan-out connection lines FIAA as 2:1 as an example, a repeating unit 21 may include 12 second-type data lines Data2 and 6 fan-out connection lines FIAA.

[0055] like Figure 2As shown, the first-class data line Data1 includes a first-class data line Data11, a second-class data line Data12, a third-class data line Data13, a fourth-class data line Data14, a fifth-class data line Data15, a sixth-class data line Data16, a seventh-class data line Data17, an eighth-class data line Data18, a ninth-class data line Data19, a tenth-class data line Data20, an eleventh-class data line Data21, and a twelfth-class data line Data22, which are arranged in sequence, and each first-class data line can be arranged and connected to a corresponding column of sub-pixel units.

[0056] Specifically, such as Figure 2 As shown, the second-category data line Data2 includes a first second-category data line Data31, a second second-category data line Data32, a third second-category data line Data33, a fourth second-category data line Data34, a fifth second-category data line Data35, a sixth second-category data line Data36, a seventh second-category data line Data37, an eighth second-category data line Data38, a ninth second-category data line Data39, a tenth second-category data line Data40, an eleventh second-category data line Data41, a twelfth second-category data line Data42, and a thirteenth second-category data line Data43. ta43, the fourteenth second-category data line Data44, the fifteenth second-category data line Data45, the sixteenth second-category data line Data46, the seventeenth second-category data line Data47, the eighteenth second-category data line Data48, the nineteenth second-category data line Data49, the twentieth second-category data line Data50, the twenty-first second-category data line Data51, the twenty-second second-category data line Data52, the twenty-third second-category data line Data53, and the twenty-fourth second-category data line Data54, and each second-category data line can be arranged and connected to a corresponding column of sub-pixel units.

[0057] Specifically, such as Figure 2As shown, the fan-out connection line FIAA includes a first fan-out connection line FIAA1, a second fan-out connection line FIAA2, a third fan-out connection line FIAA3, a fourth fan-out connection line FIAA4, a fifth fan-out connection line FIAA5, a sixth fan-out connection line FIAA6, a seventh fan-out connection line FIAA7, an eighth fan-out connection line FIAA8, a ninth fan-out connection line FIAA9, a tenth fan-out connection line FIAA10, an eleventh fan-out connection line FIAA11 and a twelfth fan-out connection line FIAA12, each fan-out connection line can be set corresponding to a corresponding column of sub-pixel units and connected to a first-type data line Data1.

[0058] Specifically, such as Figure 2 As shown, the first fan-out connection line FIAA1, the second fan-out connection line FIAA2, the third fan-out connection line FIAA3, the fourth fan-out connection line FIAA4, the fifth fan-out connection line FIAA5, the sixth fan-out connection line FIAA6, the seventh fan-out connection line FIAA7, the eighth fan-out connection line FIAA8, the ninth fan-out connection line FIAA9, the tenth fan-out connection line FIAA10, the eleventh fan-out connection line FIAA11 and the twelfth fan-out connection line FIAA12 are respectively connected to the tenth first-category data line Data20, the eleventh first-class data line Data21, the ninth first-class data line Data19, the eighth first-class data line Data18, the seventh first-class data line Data17, the twelfth first-class data line Data22, the fourth first-class data line Data14, the fifth first-class data line Data15, the third first-class data line Data13, the second first-class data line Data12, the first first-class data line Data11, and the sixth first-class data line Data16 are connected.

[0059] Specifically, such as Figure 5As shown, the first fan-out connection line FIAA1, the second fan-out connection line FIAA2, the third fan-out connection line FIAA3, the fourth fan-out connection line FIAA4, the fifth fan-out connection line FIAA5, the sixth fan-out connection line FIAA6, the seventh fan-out connection line FIAA7, the eighth fan-out connection line FIAA8, the ninth fan-out connection line FIAA9, the tenth fan-out connection line FIAA10, the eleventh fan-out connection line FIAA11 and the twelfth fan-out connection line FIAA12 are respectively connected to the eleventh first-category data Line Data21, the tenth first-category data line Data20, the ninth first-category data line Data19, the eighth first-category data line Data18, the seventh first-category data line Data17, the twelfth first-category data line Data22, the fifth first-category data line Data15, the fourth first-category data line Data14, the third first-category data line Data13, the second first-category data line Data12, the first first-category data line Data11, and the sixth first-category data line Data16 are connected.

[0060] In some embodiments, as Figure 2 、 Figure 3 As shown, in the first direction X, every three second-type data lines Data2 are connected to the red sub-pixel, the green sub-pixel and the blue sub-pixel in the pixel unit 11 respectively;

[0061] Among them, in the first direction X, within the six adjacent second-type data lines Data2 and the three fan-out connection lines FIAA, the three second-type data lines Data2 connected to one pixel unit 11, the two fan-out connection lines electrically connected to the red sub-pixel and the green sub-pixel respectively, the three second-type data lines Data2 connected to another pixel unit 11, and the fan-out connection line electrically connected to the blue sub-pixel are arranged in sequence;

[0062] The first-type control transistor T01 includes a first-subtype control transistor T1 and a second-subtype control transistor T3. The second-type control transistor T02 includes a third-subtype control transistor T2 and a fourth-subtype control transistor T4. The second-type data line Data2 connected to the red subpixel is electrically connected to the first-subtype control transistor T1, and the second-type data line Data2 connected to the green subpixel is electrically connected to the third-subtype control transistor T2. The fan-out connection line electrically connected to the red subpixel is electrically connected to the second-subtype control transistor T3, and the fan-out connection line electrically connected to the green subpixel is electrically connected to the fourth-subtype control transistor T4. By electrically connecting the fan-out connection line electrically connected to the red subpixel to the second-subtype control transistor T3, and the fan-out connection line electrically connected to the green subpixel to the fourth-subtype control transistor T4, the data line or fan-out connection line electrically connected to the red subpixel is controlled by the first signal control line, and the data line or fan-out connection line electrically connected to the green subpixel is electrically connected to the second signal control line, thereby improving display uniformity between the first subpixel unit 111 and the second subpixel unit 112.

[0063] In some embodiments, as Figure 2 、 Figure 3 As shown, part of the fan-out connection line FIAA electrically connected to the green sub-pixel and the second-type data line Data2 electrically connected to the red sub-pixel are arranged adjacent to each other, and part of the fan-out connection line FIAA electrically connected to the red sub-pixel and the second-type data line Data2 electrically connected to the red sub-pixel are arranged adjacent to each other.

[0064] Specifically, such as Figure 2 、 Figure 3 As shown, the second fan-out connection line FIAA2 is connected to the green sub-pixel through the eleventh first-class data line Data21, the second fan-out connection line FIAA2 is adjacent to the fourth second-class data line Data34 electrically connected to the red sub-pixel, the fifth fan-out connection line FIAA5 is connected to the red sub-pixel through the seventh first-class data line Data17, and the fifth fan-out connection line FIAA5 is adjacent to the tenth second-class data line Data40 electrically connected to the red sub-pixel.

[0065] In some embodiments, as Figure 2 、 Figure 3As shown, among the twelve adjacent second-type data lines Data12 and the six fan-out connection lines FIAA, the first fan-out connection line FIAA1 is electrically connected to a red sub-pixel, the second fan-out connection line FIAA2 is electrically connected to a green sub-pixel, the third fan-out connection line FIAA3 is electrically connected to a blue sub-pixel, the fourth fan-out connection line FIAA4 is electrically connected to another green sub-pixel, the fifth fan-out connection line FIAA5 is electrically connected to another red sub-pixel, and the sixth fan-out connection line FIAA6 is electrically connected to another blue sub-pixel;

[0066] The first fan-out connection line FIAA1, the second fan-out connection line FIAA2, the third fan-out connection line FIAA3, the fourth fan-out connection line FIAA4, the fifth fan-out connection line FIAA5, and the sixth fan-out connection line FIAA6 are sequentially arranged along the first direction X. Thus, the signal output sequence of the fan-out connection lines FIAA is consistent with the signal output mode of the driver chip, and there is no need to change the signal output mode of the driver chip.

[0067] Specifically, the above embodiment describes the connection relationship between the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 and the sub-pixel unit. It can be understood that the connection relationship between the seventh fan-out connection line FIAA7 to the twelfth fan-out connection line FIAA12 and the sub-pixel unit can refer to the connection relationship between the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 and the sub-pixel unit.

[0068] In some embodiments, the third fan-out connection line FIAA3 is connected to the second sub-class control transistor T3, and the sixth fan-out connection line FIAA6 is connected to the fourth sub-class control transistor T4;

[0069] Among them, among the twelve adjacent second-class data lines Data2 and six fan-out connection lines FIAA, among the four second-class data lines Data2 connected to the third sub-pixel unit 113, two adjacent second-class data lines Data2 are electrically connected to the first sub-class control transistor T1 and the third sub-class control transistor T2, respectively.

[0070] Specifically, in order to reduce the number of control lines, considering that the blue sub-pixel has a smaller impact on brightness and can be compensated by the driving chip, part of the data line or fan-out connection line connected to the blue sub-pixel can be electrically connected to the first signal control line, and the other part can be electrically connected to the second signal control line.

[0071] Specifically, such as Figure 2 、 Figure 3As shown in the figure, taking a total of 600 signal input lines, that is, a total of 1200 data lines as an example, the connection relationship between the first second-category data line Data31 to the tenth second-category data line Data42, the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6, the second-category data lines and the fan-out connection lines and the control transistors, signal control lines and signal input lines are explained. The connection relationship between other second-category data lines and fan-out connection lines and the control transistors, signal control lines and signal input lines can be referred to the following description.

[0072] Specifically, such as Figure 3 As shown, the first subclass control transistor T1 includes a first class first control transistor T11, a first class second control transistor T12, a first class third control transistor T13, a first class fourth control transistor T14, a first class fifth control transistor T15 and a first class sixth control transistor T16, the third subclass control transistor T2 includes a second class first control transistor T21, a second class second control transistor T22, a second class third control transistor T23, a second class fourth control transistor T24, a second class fifth control transistor T25, a second class sixth control transistor T26, and the second subclass control transistor T3 includes The third category first control transistor T31, the third category second control transistor T32 and the third category third control transistor T33, the fourth subcategory control transistor T4 includes the fourth category first control transistor T41, the fourth category second control transistor T42, the fourth category third control transistor T43; the signal input line SL includes the first signal input line S1, the second signal input line S2, the third signal input line S3, the fourth signal input line S4, the fifth signal input line S5, the sixth signal input line S6, the five-hundred-ninety-eighth signal input line S598, the five-hundred-ninety-ninth signal input line S599 and the six-hundredth signal input line S600.

[0073] like Figure 3 As shown, the high-potential power line VDD, the second-class data line Data2 and the fan-out connection line FIAA are alternately arranged, the first fan-out connection line FIAA1 and the second fan-out connection line FIAA2 are arranged between the third second-class data line Data33 and the fourth second-class data line Data34, the third fan-out connection line FIAA3 is arranged between the sixth second-class data line Data36 and the high-potential power line VDD, the fourth fan-out connection line FIAA4 and the fifth fan-out connection line FIAA5 are arranged between the ninth second-class data line Data39 and the tenth second-class data line Data40, and the sixth fan-out connection line FIAA6 is arranged behind the twelfth second-class data line Data42.

[0074] like Figure 3As shown, the first signal input line S1 is connected to one electrode of the first type first control transistor T11 and the second type first control transistor T21, and the other electrodes of the first type first control transistor T11 and the second type first control transistor T21 are respectively connected to the first second type data line Data31 and the second second type data line Data32; the second signal input line S2 is connected to one electrode of the first type second control transistor T12 and the second type second control transistor T22, and the other electrodes of the first type second control transistor T12 and the second type second control transistor T22 are respectively connected to the fourth second type data line Data34 and the third second type data line Data33.

[0075] like Figure 3 As shown, the third signal input line S3 is connected to one electrode of the first-type third control transistor T13 and the second-type third control transistor T23, and the other electrodes of the first-type third control transistor T13 and the second-type third control transistor T23 are respectively connected to the sixth-type second data line Data36 and the fifth-type second data line Data35; the fourth signal input line S4 is connected to one electrode of the first-type fourth control transistor T14 and the second-type fourth control transistor T24, and the other electrodes of the first-type fourth control transistor T14 and the second-type fourth control transistor T24 are respectively connected to the seventh-type second data line Data37 and the eighth-type second data line Data38.

[0076] like Figure 3 As shown, the fifth signal input line S5 is connected to one electrode of the first-class fifth control transistor T15 and the second-class fifth control transistor T25, and the other electrodes of the first-class fifth control transistor T15 and the second-class fifth control transistor T25 are respectively connected to the tenth second-class data line Data40 and the ninth second-class data line Data39; the sixth signal input line S6 is connected to one electrode of the first-class sixth control transistor T16 and the second-class sixth control transistor T26, and the other electrodes of the first-class sixth control transistor T16 and the second-class sixth control transistor T26 are respectively connected to the twelfth second-class data line Data42 and the eleventh second-class data line Data41.

[0077] like Figure 3As shown, the six hundredth signal input line S600 is connected to one electrode of the third type first control transistor T31 and the fourth type first control transistor T41, and the other electrode of the third type first control transistor T31 and the fourth type first control transistor T41 is respectively connected to the first fan-out connection line FIAA1 and the second fan-out connection line FIAA2; the five hundred and ninety-ninth signal input line S599 is connected to one electrode of the third type second control transistor T32 and the fourth type second control transistor T42, and the other electrode of the third type second control transistor T32 and the fourth type second control transistor T42 is respectively connected to the third fan-out connection line FIAA3 and the fourth fan-out connection line FIAA4; the five hundred and ninety-eighth signal input line S598 is connected to one electrode of the third type third control transistor T33 and the fourth type third control transistor T43, and the other electrode of the third type third control transistor T33 and the fourth type third control transistor T43 is respectively connected to the fifth fan-out connection line FIAA5 and the sixth fan-out connection line FIAA6.

[0078] In some embodiments, the fan-out connection line FIAA electrically connected to the red sub-pixel and the second-type data line Data2 electrically connected to the red sub-pixel are disposed adjacent to each other. By arranging the fan-out connection line FIAA electrically connected to the red sub-pixel and the second-type data line Data2 electrically connected to the red sub-pixel adjacent to each other, the second-type data line connected to each red sub-pixel is interfered with by the fan-out connection line controlled by the first signal control line. This results in similar or even consistent interference between the second-type data lines and the fan-out connection lines connected to each red sub-pixel, thereby improving display uniformity and preventing vertical streaks.

[0079] Specifically, compared with the embodiment that only improves the interference of the second type data line connected to the first sub-pixel unit with the adjacent second type data line, this embodiment further improves the interference of the second type data line connected to the first sub-pixel unit with the fan-out connection line, further improves the display uniformity, and improves the display effect.

[0080] In some embodiments, as Figure 4 、 Figure 5 As shown, among the twelve adjacently arranged second-type data lines Data2 and the six fan-out connection lines FIAA, the first fan-out connection line FIAA1 is electrically connected to a green sub-pixel, the second fan-out connection line FIAA2 is electrically connected to a red sub-pixel, the third fan-out connection line FIAA3 is electrically connected to a blue sub-pixel, the fourth fan-out connection line FIAA4 is electrically connected to another green sub-pixel, the fifth fan-out connection line FIAA5 is electrically connected to another red sub-pixel, and the sixth fan-out connection line FIAA6 is electrically connected to another blue sub-pixel;

[0081] The first fan-out connection line FIAA1, the second fan-out connection line FIAA2, the third fan-out connection line FIAA3, the fourth fan-out connection line FIAA4, the fifth fan-out connection line FIAA5, and the sixth fan-out connection line FIAA6 are sequentially arranged along the first direction X. Thus, the interference of the second-type data lines connected to the first sub-pixel units by the fan-out connection lines is similar or even consistent, thereby improving display uniformity and avoiding vertical stripes.

[0082] Specifically, it can be seen that the second fan-out connection line FIAA2 and the fifth fan-out connection line FIAA5 on the left side of the fourth second-category data line Data34 and the tenth second-category data line Data40 connected to the red sub-pixel are all controlled by the second signal control line Mux2, so that the second-category data lines connected to each red sub-pixel are subject to similar or even identical interference from the signal lines on the left, thereby improving display uniformity and avoiding display abnormalities.

[0083] Specifically, the above embodiment describes the connection relationship between the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 and the sub-pixel unit. It can be understood that the connection relationship between the seventh fan-out connection line FIAA7 to the twelfth fan-out connection line FIAA12 and the sub-pixel unit can refer to the connection relationship between the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 and the sub-pixel unit.

[0084] In some embodiments, the third fan-out connection line FIAA3 is connected to the second sub-class control transistor T3, and the sixth fan-out connection line FIAA6 is connected to the fourth sub-class control transistor T4;

[0085] Among them, among the twelve adjacent second-class data lines Data2 and the six fan-out connection lines FIAA, the four second-class data lines Data2 connected to the third sub-pixel unit 113 are respectively connected to a first sub-class control transistor T1, a third sub-class control transistor T2, another third sub-class control transistor T2 and another first sub-class control transistor T1.

[0086] Specifically, in order to reduce the number of control lines, considering that the blue sub-pixel has a smaller impact on brightness and can be compensated by the driving chip, part of the data line or fan-out connection line connected to the blue sub-pixel can be electrically connected to the first signal control line, and the other part can be electrically connected to the second signal control line.

[0087] Specifically, such as Figure 4 、 Figure 5As shown, still taking a total of 600 signal input lines, that is, a total of 1200 data lines as an example, the connection relationship between the second-category data lines and fan-out connection lines and the control transistors, signal control lines and signal input lines is explained by taking the first second-category data line Data31 to the tenth second-category data line Data42 and the first fan-out connection line FIAA1 to the sixth fan-out connection line FIAA6 as examples. The connection relationship between other second-category data lines and fan-out connection lines and the control transistors, signal control lines and signal input lines can be referred to the following description.

[0088] Specifically, for Figure 5 The connection relationship between each signal line and transistor in Figure 3 The same parts of the connection relationship between the signal lines and transistors in FIG are not repeated here. Figure 5 The connection relationship between each signal line and transistor in Figure 3 The differences in the connection relationship between the signal lines and transistors are as follows:

[0089] like Figure 5 As shown, the second signal input line S2 is connected to one electrode of the first-class second control transistor T12 and the second-class third control transistor T23, and the other electrodes of the first-class second control transistor T12 and the second-class third control transistor T23 are respectively connected to the third second-class data line Data33 and the sixth second-class data line Data36; the third signal input line S3 is connected to one electrode of the first-class third control transistor T13 and the second-class second control transistor T22, and the other electrodes of the first-class third control transistor T13 and the second-class second control transistor T22 are respectively connected to the fourth second-class data line Data34 and the fifth second-class data line Data35.

[0090] like Figure 5 As shown, the six hundredth signal input line S600 is connected to one electrode of the third type first control transistor T31 and the fourth type first control transistor T41, and the other electrode of the third type first control transistor T31 and the fourth type first control transistor T41 is respectively connected to the second fan-out connection line FIAA2 and the first fan-out connection line FIAA1; the five hundred and ninety-ninth signal input line S599 is connected to one electrode of the third type second control transistor T32 and the fourth type third control transistor T43, and the other electrode of the third type second control transistor T32 and the fourth type third control transistor T43 is respectively connected to the third fan-out connection line FIAA3 and the sixth fan-out connection line FIAA6; the five hundred and ninety-eighth signal input line S598 is connected to one electrode of the third type third control transistor T33 and the fourth type second control transistor T42, and the other electrode of the third type third control transistor T33 and the fourth type second control transistor T42 is respectively connected to the fifth fan-out connection line FIAA5 and the fourth fan-out connection line FIAA4.

[0091] In some embodiments, as Figure 3 、 Figure 5 As shown, the display panel 1 includes a repeating unit 21, and the repeating unit 21 includes twelve second-type data lines Data2 and six fan-out connection lines FIAA;

[0092] Each of the fan-out connection lines is connected to a first-type data line, and the twelve second-type data lines Data2 and the six fan-out connection lines FIAA are correspondingly arranged to the four columns of pixel units 11 .

[0093] Specifically, such as Figure 2 、 Figure 4 As shown, the twelve first-type data lines Data1 are arranged corresponding to the four columns of pixel units 11 .

[0094] Specifically, it is understood that one or more repeating units can be provided in the display panel, and the repeating units on both sides of the display panel can be symmetrically provided. It is understood that the arrangement of other second-type data lines and fan-out connection lines can be referred to. Figures 2 to 5 The arrangement of the repeating units in the first data line can be located at the edge of the display panel, and the connection relationship between other repeating units and the first data line can be seen in Figures 2 to 5 , specifically in Figure 2 、 Figure 4 Set other second-class data lines and fan-out connection lines on the right side of the repeating unit in Figure 2 、 Figure 4 Set other first-class data lines on the left side of the first-class data lines in the . Other first-class data lines and other fan-out connection lines can be Figure 2 、 Figure 4 Connect above the repeating unit in.

[0095] Specifically, for the thirteenth second-category data line Data43 , since a high-potential power line VDD is provided between it and the fan-out connection line, it is less disturbed or even not disturbed at all by the fan-out connection line, so that the display panel displays normally.

[0096] Specifically, such as Figure 3 、 Figure 5 As shown, the embodiment of the present application is described by taking the control transistor as a P-type transistor as an example, but the embodiment of the present application is not limited to this. The control transistor can be an N-type transistor, or partly a P-type transistor and partly an N-type transistor.

[0097] Specifically, the display panel may be an organic light emitting diode display panel.

[0098] Specifically, the above embodiments provide a detailed description of the display panel from aspects such as the pixel arrangement of the display panel and the connection relationship of the signal lines. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the display panel can be an organic light emitting diode display panel, and the light emitting colors of the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit can be red, green and blue, respectively.

[0099] At the same time, an embodiment of the present application provides a display device, which includes the display panel as described in any of the above embodiments.

[0100] Specifically, the display device may further include a control panel and a power supply.

[0101] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0102] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0103] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other unless there is any conflict.

[0104] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel units, each of the pixel units includes a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit of different luminous colors, and within each pixel unit, the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit are arranged in sequence along a first direction; the display panel includes: Multiple scan lines; a plurality of data lines, each of the data lines being connected to a sub-pixel unit of the same luminous color, and the plurality of data lines comprising a plurality of first-type data lines and a plurality of second-type data lines; a plurality of fan-out connection lines electrically connected to the first type of data lines, wherein the plurality of data lines and the plurality of fan-out connection lines are arranged at intervals along a first direction; a plurality of signal input lines, some of which are electrically connected to two second-type data lines, and some of which are electrically connected to two fan-out connection lines, and a first-type control transistor and a second-type control transistor are respectively provided between the signal input line and the corresponding two second-type data lines, a first-type control transistor and a second-type control transistor are respectively provided between the signal input line and the corresponding two fan-out connection lines, a gate of the first-type control transistor is connected to a first signal control line, and a gate of the second-type control transistor is connected to a second signal control line, an input time period of an effective level of the first signal control line does not overlap with an input time period of an effective level of the scan line, and an input time period of an effective level of the second signal control line overlaps with an input time period of an effective level of the scan line; The second-type data line connected to the first sub-pixel unit is electrically connected to the first-type control transistor, and the second-type data line connected to the second sub-pixel unit is electrically connected to the second-type control transistor.

2. The display panel according to claim 1, wherein: In the first direction, every three second-type data lines are respectively connected to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit in one pixel unit; Wherein, in the first direction, among the six adjacently arranged second-category data lines and the three fan-out connection lines, the three second-category data lines connected to one pixel unit, the two fan-out connection lines electrically connected to the first sub-pixel unit and the second sub-pixel unit respectively, the three second-category data lines connected to another pixel unit, and the fan-out connection line electrically connected to the third sub-pixel unit are arranged in sequence; The first type of control transistor includes a first sub-type control transistor and a second sub-type control transistor, the second type of control transistor includes a third sub-type control transistor and a fourth sub-type control transistor, the second type of data line connected to the first sub-pixel unit is electrically connected to the first sub-type control transistor, and the second type of data line connected to the second sub-pixel unit is electrically connected to the third sub-type control transistor; the fan-out connection line electrically connected to the first sub-pixel unit is electrically connected to the second sub-type control transistor, and the fan-out connection line electrically connected to the second sub-pixel unit is electrically connected to the fourth sub-type control transistor.

3. The display panel according to claim 2, wherein: Part of the fan-out connection line electrically connected to the second sub-pixel unit and the second-type data line electrically connected to the first sub-pixel unit are arranged adjacent to each other, and part of the fan-out connection line electrically connected to the first sub-pixel unit and the second-type data line electrically connected to the first sub-pixel unit are arranged adjacent to each other.

4. The display panel according to claim 3, wherein: Among the twelve adjacently arranged second-category data lines and the six fan-out connection lines, a first fan-out connection line is electrically connected to one of the first sub-pixel units, a second fan-out connection line is electrically connected to one of the second sub-pixel units, a third fan-out connection line is electrically connected to one of the third sub-pixel units, a fourth fan-out connection line is electrically connected to another of the second sub-pixel units, a fifth fan-out connection line is electrically connected to another of the first sub-pixel units, and a sixth fan-out connection line is electrically connected to another of the third sub-pixel units; A first fan-out connection line, a second fan-out connection line, a third fan-out connection line, a fourth fan-out connection line, a fifth fan-out connection line and a sixth fan-out connection line are sequentially arranged along the first direction.

5. The display panel according to claim 4, wherein: a third fan-out connection line connected to the second sub-type control transistor, and a sixth fan-out connection line connected to the fourth sub-type control transistor; Among the twelve adjacent second-category data lines and six fan-out connection lines, among the four second-category data lines connected to the third sub-pixel unit, two adjacent second-category data lines are electrically connected to the first sub-category control transistor and the third sub-category control transistor respectively.

6. The display panel according to claim 2, wherein: The fan-out connection line electrically connected to the first sub-pixel unit and the second-type data line electrically connected to the first sub-pixel unit are arranged adjacent to each other.

7. The display panel according to claim 6, wherein: Among the twelve adjacently arranged second-category data lines and six of the fan-out connection lines, a first fan-out connection line is electrically connected to a second sub-pixel unit, a second fan-out connection line is electrically connected to a first sub-pixel unit, a third fan-out connection line is electrically connected to a third sub-pixel unit, a fourth fan-out connection line is electrically connected to another second sub-pixel unit, a fifth fan-out connection line is electrically connected to another first sub-pixel unit, and a sixth fan-out connection line is electrically connected to another third sub-pixel unit; A first fan-out connection line, a second fan-out connection line, a third fan-out connection line, a fourth fan-out connection line, a fifth fan-out connection line and a sixth fan-out connection line are sequentially arranged along the first direction.

8. The display panel according to claim 7, wherein: a third fan-out connection line connected to the second sub-type control transistor, and a sixth fan-out connection line connected to the fourth sub-type control transistor; Among them, among the twelve adjacent second-class data lines and six fan-out connection lines, the four second-class data lines connecting the third sub-pixel unit are respectively connected to a first-subclass control transistor, a third-subclass control transistor, another third-subclass control transistor and another first-subclass control transistor.

9. The display panel according to any one of claims 1 to 8, characterized in that: The display panel includes a repeating unit, wherein the repeating unit includes twelve second-category data lines and six fan-out connection lines; Each of the fan-out connection lines is connected to a first-type data line, and twelve second-type data lines and six fan-out connection lines are arranged corresponding to four columns of pixel units.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

Images