Memory device configured to perform read operations of dummy channels

Abstract

The invention relates to a memory device configured to perform a read operation of a dummy channel. A memory device includes: an alignment data strobe signal generation circuit configured to generate an alignment data strobe signal from an internal clock signal when a read operation on a specific dummy channel of a specific Rank is performed based on a read identification signal and a read channel signal; and a core pipeline configured to receive the alignment data strobe signal and output core data output from the particular dummy channel based on the alignment data strobe signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from Korean Patent Application No. 10-2024-0022155, filed on February 15, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0002] Various embodiments of the present disclosure relate generally to memory devices, and more particularly, to memory devices associated with read operations of pseudo channels. Background Art

[0003] Stacked memory systems, such as high-bandwidth memory (HBM) devices, have recently gained widespread adoption due to their superior bandwidth and energy efficiency. Unlike existing memory systems that use parallel data buses, stacked memory systems include a stacked memory device consisting of a base die and multiple core dies interconnected by through-silicon vias (TSVs, hereinafter referred to as "vias"). During a read operation, when the base die receives core data output from the core die and transmits the core data to a controller, the stacked memory device can use a data strobe signal generated based on an internal clock signal to control the core data from the core die to be transmitted to and output from the base die. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a memory device may include: an alignment data select signal generation circuit, which is configured to generate an alignment data select signal from an internal clock signal when a read operation is performed on a specific pseudo channel of a specific Rank based on a read identification signal and a read channel signal; and a core pipeline, which is configured to receive the alignment data select signal and output core data output from the specific pseudo channel based on the alignment data select signal.

[0005] Furthermore, according to an embodiment of the present disclosure, a memory device may include multiple core dies stacked on a base die. In one embodiment, each of the multiple core dies may include an alignment data strobe signal generation circuit configured to receive an internal clock signal, a read identification signal, and a read channel signal from the base die to generate an alignment data strobe signal. In one embodiment, the alignment data strobe signal generation circuit may generate a latch identification signal and a latch channel signal from the read identification signal and the read channel signal in phase with the internal clock signal, generate an alignment data strobe signal based on the latch identification signal, the latch channel signal, and the core identification signal; generate an inverted latch identification signal and an inverted latch channel signal from the read identification signal and the read channel signal out of phase with the internal clock signal; and generate the alignment data strobe signal based on the inverted latch identification signal, the inverted latch channel signal, and the core identification signal.

[0006] Furthermore, according to an embodiment of the present disclosure, a memory device may include multiple core dies stacked on a base die. In one embodiment, each of the multiple core dies may include: an alignment data strobe signal generation circuit configured to receive an internal clock signal, a read identification signal, and a read channel signal from the base die to generate an alignment data strobe signal; and a read data strobe signal transmission circuit configured to generate a read data strobe signal based on the alignment data strobe signal and transmit the read data strobe signal to the base die. In one embodiment, the read data strobe signal generated by each core die forming the same Rank among the multiple core dies may be transmitted to the base die through the same through-hole array.

[0007] Furthermore, according to an embodiment of the present disclosure, a memory device may include multiple core dies stacked on a base die, each of the multiple core dies may include multiple channels, each of the multiple channels may include a first pseudo channel and a second pseudo channel, and the multiple channels may form a first rank and a second rank for setting bandwidth. In one embodiment, when a read operation is performed on a first pseudo channel of a first rank, the memory device may generate a first alignment data strobe signal from an internal clock signal based on a read identification signal and a read channel signal, and generate a first read data strobe signal from the first alignment data strobe signal during a first transfer period based on the first alignment data strobe signal; and when a read operation is performed on the first pseudo channel of a second rank, the memory device may generate a second alignment data strobe signal from an internal clock signal based on the read identification signal and the read channel signal, and generate a second read data strobe signal from the second alignment data strobe signal during a second transfer period based on the second alignment data strobe signal.

[0008] Furthermore, according to an embodiment of the present disclosure, a memory device may include multiple core dies stacked on a base die, each of the multiple core dies may include multiple channels, each of the multiple channels may include a first pseudo channel and a second pseudo channel, and the multiple channels may form a first rank and a second rank for setting bandwidth. In one embodiment, when a read operation is performed on a first pseudo channel of a first rank, the memory device may generate a first alignment data strobe signal from an internal clock signal based on a read identification signal and a read channel signal, generate a first read data strobe signal from the first alignment data strobe signal during a first transfer period based on the first alignment data strobe signal, and when a read operation is performed on a second pseudo channel of a second rank, the memory device may generate a second alignment data strobe signal from the internal clock signal based on the read identification signal and the read channel signal, and generate a second read data strobe signal from the second alignment data strobe signal during a second transfer period based on the second alignment data strobe signal.

[0009] Furthermore, according to an embodiment of the present disclosure, a memory device may include multiple core dies stacked on a base die, each of the multiple core dies may include multiple channels, each of the multiple channels may include a first pseudo channel and a second pseudo channel, and the multiple channels may form a rank for setting bandwidth. In one embodiment, when a read operation is performed on a first pseudo channel of the rank, the memory device may generate a first alignment data strobe signal from an internal clock signal based on a read identification signal and a read channel signal, and generate a first read data strobe signal from the first alignment data strobe signal during a first transfer period based on the first alignment data strobe signal; when a read operation is performed on a second pseudo channel of the rank, the memory device may generate a second alignment data strobe signal from an internal clock signal based on the read identification signal and the read channel signal, and generate a second read data strobe signal from the second alignment data strobe signal during a second transfer period based on the second alignment data strobe signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The configuration of a stacked memory device according to an embodiment of the present disclosure is shown.

[0011] Figure 2 Shown according to Figure 1 The configuration of an embodiment of a base die included in a stacked memory device is shown in FIG.

[0012] Figure 3 Shown in Figure 2 An embodiment of a read operation performed in the base die shown in FIG.

[0013] Figure 4Shown according to Figure 1 The configuration of an embodiment of a first core die included in a stacked memory device is shown.

[0014] Figure 5 The configuration according to an embodiment of each channel included in each core die is shown.

[0015] Figure 6 Shown according to Figure 5 An example configuration of the peripheral area is shown.

[0016] Figure 7 Shown according to Figure 6 The configuration of an embodiment of an alignment data strobe signal generating circuit included in the peripheral area is shown.

[0017] Figure 8 Shown according to Figure 7 The configuration of an embodiment of a latch signal generating circuit included in the alignment data strobe signal generating circuit is shown.

[0018] Figure 9 Shown according to Figure 7 The configuration of an embodiment of an internal clock signal alignment circuit included in an alignment data strobe signal generation circuit is shown.

[0019] Figure 10 Shown according to Figure 9 The circuit of an embodiment of the in-phase activation signal generating circuit is shown.

[0020] Figure 11 An example of a read identification signal that can indicate the Rank of a read operation performed is shown.

[0021] Figure 12 An example of a core identification signal that may indicate the core die and Rank on which a read operation is performed is shown.

[0022] Figure 13 An example of a latched channel signal that may indicate a dummy channel on which a read operation is performed is shown.

[0023] Figure 14 Shown according to Figure 9 The circuits of the embodiments of the out-of-phase activation signal generation circuits are shown.

[0024] Figure 15 and Figure 16 The operation of an embodiment of an alignment data strobe signal generation circuit is shown.

[0025] Figure 17 Shown according to Figure 5 Another example configuration of the peripheral area is shown.

[0026] Figure 18 Shown according to Figure 17 The configuration of an embodiment of a first read data strobe signal transmission circuit included in the peripheral area is shown.

[0027] Figure 19 Shown according to Figure 18 The circuit of an embodiment of the transmission activation signal generating circuit included in the first read data strobe signal transmission circuit is shown.

[0028] Figure 20 Shown Figure 18 The configuration of an embodiment of a read data strobe signal generating circuit included in the first read data strobe signal transmission circuit is shown.

[0029] Figure 21 Shown Figure 17 An example of a read operation performed in the peripheral region is shown.

[0030] Figure 22 A configuration of a stacked memory device according to another embodiment of the present disclosure is shown. Specific embodiments

[0031] In the following description of the embodiments, when a parameter is referred to as being "predetermined," it may be intended that the value of the parameter may be determined in advance when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the period during which the process or algorithm is executed.

[0032] It should be understood that although the terms "first," "second," "third," etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and are not intended to imply an order or quantity of the elements. Thus, the first element in some embodiments may be referred to as the second element in other embodiments without departing from the teachings of the present disclosure.

[0033] Furthermore, it should be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may exist. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements.

[0034] A logic "high" level and a logic "low" level can be used to describe the logic levels of electrical signals. A signal with a logic "high" level can be distinguished from a signal with a logic "low" level. For example, when a signal with a first voltage corresponds to a signal with a logic "high" level, a signal with a second voltage corresponds to a signal with a logic "low" level. In one embodiment, the logic "high" level can be set to a voltage level that is higher than the voltage level of the logic "low" level. At the same time, the logic levels of the signals can be set to different or opposite levels depending on the embodiment. For example, a signal with a logic "high" level in one embodiment can be set to a logic "low" level in another embodiment.

[0035] The term "logical bit group" may refer to a combination of logic levels of bits included in a signal. When the logic level of each bit included in the signal changes, the logical bit group of the signal may be set differently. For example, if the signal includes two bits, when the logic level of each of the two bits included in the signal is "logic low level, logic low level", the logical bit group of the signal may be set to a first logical bit group, and when the logic level of each of the two bits included in the signal is "logic low level and logic high level", the logical bit group of the signal may be set to a second logical bit group.

[0036] Hereinafter, various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0037] Figure 1 FIG. 1 shows a configuration of a stacked memory device 10 according to an embodiment of the present disclosure. Figure 1 As shown, the stacked memory device 10 may include a base die 100 and a plurality of core dies 111 , 112 , 113 , 114 , 115 , 116 , 117 , and 118 .

[0038] The base die 100 may control internal operations of each of the core dies 111, 112, 113, 114, 115, 116, 117, and 118, such as a write operation to store data and a read operation to output data, etc., according to control of a memory controller (not shown). The base die 100 may control each of the core dies 111, 112, 113, 114, 115, 116, 117, and 118 so that data is stored in each of the core dies 111, 112, 113, 114, 115, 116, 117, and 118 when a write operation to each of the core dies 111, 112, 113, 114, 115, 116, 117, and 118 is performed according to control of the memory controller (not shown). When a read operation is performed on each core die 111, 112, 113, 114, 115, 116, 117, and 118, the base die 100 may receive core data (eg, Figure 6 CDATA1 and CDATA2) to read data strobe signals (e.g., Figure 17 The core data is transferred to the memory controller (not shown) synchronously with the RDQS in the CPU.

[0039] Each of the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118 may be stacked on the base die 100. For example, core die 111 may be stacked on the base die 100, core die 112 may be stacked on the core die 111, core die 113 may be stacked on the core die 112, core die 114 may be stacked on the core die 113, core die 115 may be stacked on the core die 114, core die 116 may be stacked on the core die 115, core die 117 may be stacked on the core die 116, and core die 118 may be stacked on the core die 117.

[0040] Each of the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118 may include a plurality of channels. The core die 111 may include first to fourth channels CH0-CH3. As used herein, the tilde "~" indicates a range of components. For example, "CH0-CH3" indicates Figure 1, channels CH0, CH1, CH2, and CH3 are shown in FIG. Core die 112 may include fifth to eighth channels CH4-CH7. Core die 113 may include ninth to twelfth channels CH8-CH11. Core die 114 may include thirteenth to sixteenth channels CH12-CH15. Core die 115 may include first to fourth channels CH0-CH3. Core die 116 may include fifth to eighth channels CH4-CH7. Core die 117 may include ninth to twelfth channels CH8-CH11. Core die 118 may include thirteenth to sixteenth channels CH12-CH15. The first channel CH0 of core die 111 and the first channel CH0 of core die 115 may share at least one data path for input and output data. The second channel CH1 of core die 111 and the second channel CH1 of core die 115 may share at least one data path for input and output data. The third channel CH2 of core die 111 and the third channel CH2 of core die 115 can share at least one data path for input / output data. The fourth channel CH3 of core die 111 and the fourth channel CH3 of core die 115 can share at least one data path for input / output data. The fifth channel CH4 of core die 112 and the fifth channel CH4 of core die 116 can share at least one data path for input / output data. The sixth channel CH5 of core die 112 and the sixth channel CH5 of core die 116 can share at least one data path for input / output data. The seventh channel CH6 of core die 112 and the seventh channel CH6 of core die 116 can share at least one data path for input / output data. The eighth channel CH7 of core die 112 and the eighth channel CH7 of core die 116 can share at least one data path for input / output data. The ninth channel CH8 of core die 113 and the ninth channel CH8 of core die 117 can share at least one data path for input / output data. The tenth channel CH9 of the core die 113 and the tenth channel CH9 of the core die 117 can share at least one data path for input / output data. The eleventh channel CH10 of the core die 113 and the eleventh channel CH10 of the core die 117 can share at least one data path for input / output data. The twelfth channel CH11 of the core die 113 and the twelfth channel CH11 of the core die 117 can share at least one data path for input / output data. The thirteenth channel CH12 of the core die 114 and the thirteenth channel CH12 of the core die 118 can share at least one data path for input / output data. The fourteenth channel CH13 of the core die 114 and the fourteenth channel CH13 of the core die 118 can share at least one data path for input / output data.The fifteenth channel CH14 of core die 114 and the fifteenth channel CH14 of core die 118 can share at least one data path through which data is input and output. The sixteenth channel CH15 of core die 114 and the sixteenth channel CH15 of core die 118 can share at least one data path through which data is input and output. The first to fourth channels CH0-CH3 of core die 111, the fifth to eighth channels CH4-CH7 of core die 112, the ninth to twelfth channels CH8-CH11 of core die 113, and the thirteenth to sixteenth channels CH12-CH15 of core die 114 can form a first memory rank (Rank) RANK0 for setting bandwidth. The first to fourth channels CH0 - CH3 of core die 115 , the fifth to eighth channels CH4 - CH7 of core die 116 , the ninth to twelfth channels CH8 - CH11 of core die 117 , and the thirteenth to sixteenth channels CH12 - CH15 of core die 118 may form a second RankRANK1 for setting bandwidth.

[0041] Each of the first to fourth channels CH0-CH3 of the core die 111, each of the fifth to eighth channels CH4-CH7 of the core die 112, each of the ninth to twelfth channels CH8-CH11 of the core die 113, each of the thirteenth to sixteenth channels CH12-CH15 of the core die 114, each of the first to fourth channels CH0-CH3 of the core die 115, each of the fifth to eighth channels CH4-CH7 of the core die 116, each of the ninth to twelfth channels CH8-CH11 of the core die 117, and each of the thirteenth to sixteenth channels CH12-CH15 of the core die 118 may include a plurality of dummy channels (e.g., dummy channels) that operate independently. Figure 4 The first to sixteenth channels CH0~CH15 contain multiple pseudo channels (for example, Figure 4 Internal operations (such as write operations and read operations) of each pseudo channel in PC0 and PC1 can be performed independently.

[0042] Figure 2 Shown Figure 1 The configuration of the embodiment of the basic die 100 is shown. Figure 2 As shown, the base die 100 may include a command decoder (COM DEC) 101 , an internal clock signal generation circuit (ICLK GEN) 103 , and a read control circuit (RDCTR) 105 .

[0043] The command decoder 101 may generate a read command RDCMD, a channel signal PC, and an identification signal SID based on an external clock signal PCLK and an external command PCMD received from a memory controller (not shown). The command decoder 101 may decode the external command PCMD in synchronization with the external clock signal PCLK to generate the read command RDCMD, the channel signal PC, and the identification signal SID. The external command PCMD may indicate a specific pseudo channel (e.g., RANK0 or RANK1) included in a specific rank (e.g., RANK1). Figure 4 As an example, the command decoder 101 may generate a read command RDCMD with the binary bit “1” set, a channel signal PC with the binary bit “0” set, and an identification signal SID with the binary bit group “00” set to instruct a read operation on the first pseudo channel PC0 of the first Rank RANK0. For another example, the command decoder 101 may generate a read command RDCMD with the binary bit “1” set, a channel signal PC with the binary bit “1” set, and an identification signal SID with the binary bit group “01” set to instruct a read operation on the second pseudo channel PC1 of the second Rank RANK1.

[0044] The internal clock signal generation circuit 103 can generate an internal clock signal ICLK based on the external clock signal PCLK. The internal clock signal generation circuit 103 can divide the external clock signal PCLK to generate the internal clock signal ICLK. The internal clock signal ICLK can be provided as a plurality. As an example, the internal clock signal generation circuit 103 can divide the external clock signal PCLK by two to generate a first internal clock signal CLK1, a second internal clock signal CLK2, a first inverted internal clock signal CLK1B, and a second inverted internal clock signal CLK2B, each having a period twice that of the external clock signal PCLK. In this case, the second internal clock signal CLK2 can be generated half a period of the external clock signal PCLK later than the first internal clock signal CLK1, the first inverted internal clock signal CLK1B can be generated half a period of the external clock signal PCLK later than the second internal clock signal CLK2, and the second inverted internal clock signal CLK2B can be generated half a period of the external clock signal PCLK later than the first inverted internal clock signal CLK1B. Therefore, the first inverted internal clock signal CLK1B may be generated to be in an inverted phase with the first internal clock signal CLK1 , and the second inverted internal clock signal CLK2B may be generated to be in an inverted phase with the second internal clock signal CLK2 .

[0045] The read control circuit 105 may be electrically connected to the command decoder 101 to receive a read command RCMD, a channel signal PC, and an identification signal SID from the command decoder 101. The read control circuit 105 may execute a read command for a specific Rank (e.g., Figure 4 RANK0 or RANK1) in a specific pseudo channel (for example, Figure 4 When a read operation (PC0 or PC1 in the first pseudo channel) is performed, the read channel signal RPC and the read identification signal RSID are generated. As an example, when a read operation is performed on the first pseudo channel PC0 of the first Rank RANK0, the read control circuit 105 may generate the read channel signal RPC set to the binary bit group '01' and the read identification signal RSID set to the binary group '00'. As another example, when a read operation is performed on the second pseudo channel PC1 of the second Rank RANK1, the read control circuit 105 may generate the read channel signal RPC set to the binary bit group '10' and the read identification signal RSID set to the binary group '01'.

[0046] Figure 3 Shown in Figure 2 An embodiment of a read operation performed in base die 100A is shown.

[0047] like Figure 3As shown, at time point T11, when a read operation RDR1P0 is performed on the first pseudo channel PC0 of the first Rank RANK0, the command decoder 101 can decode the external command PCMD in synchronization with the external clock signal PCLK to generate a read command RDCMD set to a binary bit '1', a channel signal PC set to a binary bit '0', and an identification signal SID set to a binary bit group '00'. At time point T15, when the read control period RL-2 has passed since time point T11, the read control circuit 105 can generate a read channel signal RPC and a read identification signal RSID based on the read command RDCMD, the channel signal PC, and the identification signal SID. That is, when a read operation is performed on the first pseudo channel PC0 of the first Rank RANK0, the read control circuit 105 may receive a read command RDCMD set to binary bit '1', a channel signal PC set to binary bit '0', and an identification signal SID set to binary bit group '00' to generate a read channel signal RPC set to binary bit group '01' and a read identification signal RSID set to binary bit group '00'. The read control period RL-2 may be set to a period obtained by subtracting two cycles of the external clock signal PCLK from the read latency, but this is merely an example and the present disclosure is not limited thereto.

[0048] like Figure 3As shown, when a read operation RDR2P1 is performed on the second pseudo channel PC1 of the second Rank RANK1 at time point T12, the command decoder 101 can decode the external command PCMD in synchronization with the external clock signal PCLK to generate a read command RCMD set to binary bit '1', a channel signal PC set to binary bit '1', and an identification signal SID set to binary bit group '01' (i.e., SID[0] has binary bit '1' and SID[1] has binary bit '0'). At time point T16, when the read control period RL-2 has passed since time point T12, the read control circuit 105 can generate a read channel signal RPC and a read identification signal RSID based on the read command RDCMD, the channel signal PC, and the identification signal SID. That is, when a read operation on the second pseudo channel PC1 of the second Rank RANK1 is performed, the read control circuit 105 can receive a read command RCMD set to binary bit '1', a channel signal PC set to binary bit '1', and an identification signal SID set to binary bit group '01' to generate a read channel signal RPC set to binary bit group '10' (i.e., RPC[0] has binary bit '0', and RPC[1] has binary bit '1') and a read identification signal RSID set to binary bit group '01' (i.e., RSID[0] has binary bit '1', and RSID[1] has binary bit '0').

[0049] like Figure 3 As shown, when a no-operation (NOP) is executed at time point T13, command decoder 101 can decode external command PCMD in synchronization with external clock signal PCLK to generate a read command RDCMD set to binary bit '0' and a channel signal PC set to binary bit '0'. At time point T17, when a read control period RL-2 has elapsed since time point T13, read control circuit 105 can generate a read channel signal RPC and a read identification signal RSID based on the read command RDCMD and channel signal PC. That is, when a no-operation (NOP) is executed, read control circuit 105 can receive a read command RCMD set to binary bit '0' and a channel signal PC set to binary bit '0' to generate a read channel signal RPC set to binary bit group '00' and a read identification signal RSID set to binary bit group '00'.

[0050] like Figure 3As shown, when a read operation RDR1P1 is performed on the second pseudo channel PC1 of the first Rank RANK0 at time point T14, the command decoder 101 can decode the external command PCMD in synchronization with the external clock signal PCLK to generate a read command RDCMD set to binary bit '1', a channel signal PC set to binary bit '1', and an identification signal SID set to binary bit group '00'. At time point T18, when the read control period RL-2 has passed since time point T14, the read control circuit 105 can generate a read channel signal RPC and a read identification signal RSID based on the read command RDCMD, the channel signal PC, and the identification signal SID. That is, when the read operation RDR1P2 is performed on the second pseudo channel PC1 of the first Rank RANK0, the read control circuit 105 can receive the read command RCMD set to the binary bit '1', the channel signal PC set to the binary bit '1', and the identification signal SID set to the binary bit group '00' to generate the read channel signal RPC set to the binary bit group '10' and the read identification signal RSID set to the binary bit group '00'.

[0051] Figure 4 Shown Figure 1 The configuration of an example of a core die 111 included in a stacked memory device is shown. Figure 4 As shown, the first core die 111 may include first to fourth channels CH0-CH3. Each of the first to fourth channels CH0-CH3 may include a first pseudo channel PC0 and a second pseudo channel PC1 that operate independently to increase bandwidth. Internal operations (e.g., read operations and write operations) for each of the first pseudo channel PC0 and the second pseudo channel PC1 may be performed independently.

[0052] Figure 5 A configuration of the channel 121 according to an example of each of the first to sixteenth channels CH0 ˜ CH15 included in each of the core dies 111 , 112 , 113 , 114 , 115 , 116 , 117 , and 118 is shown.

[0053] like Figure 5 As shown, the channel 121 may include a first dummy core region (PC0 CORE) 123 - 1 , a second dummy core region (PC1 CORE) 123 - 2 , and a peripheral region (PERI) 125 .

[0054] The first dummy core area 123-1 may include a memory cell array in which data input when a write operation is performed for the first dummy channel PC0 is stored. The first dummy core area 123-1 may include a memory cell array in which data is output when a read operation is performed for the first dummy channel PC0.

[0055] The second dummy core area 123-2 may include a memory cell array in which data input when a write operation is performed on the second dummy channel PC1 is stored. The second dummy core area 123-2 may include a memory cell array in which data is output when a read operation is performed on the second dummy channel PC1.

[0056] The peripheral region 125 may include a logic circuit to control a write operation to the first dummy channel PC0 or the second dummy core region 123 - 2 . The peripheral region 125 may include a logic circuit to control a read operation to the first dummy channel PC0 or the second dummy core region 123 - 2 .

[0057] Figure 6 Shown according to Figure 5 The configuration of the peripheral region 125A of the example of the peripheral region 125 is shown in FIG.

[0058] like Figure 6 As shown, the peripheral area 125A may include control through-hole arrays (CTR TSV ARRAY (1) to CTR TSVARRAY (2)) 131-1 to 131-2, data through-hole arrays (DQ TSV ARRAY (1) to DQ TSV ARRAY (4)) 132-1 to 132-4, an alignment data strobe signal generation circuit (ADQS GEN) 133, a first core pipe (CORE PIPE1) 135-1, and a second core pipe (CORE PIPE2) 135-2.

[0059] Each of the control via arrays 131-1 and 131-2 may be formed on a base die ( Figure 1 The read identification signal RSID, the read channel signal RPC, and the internal clock signal ICLK generated in the base die 100 are transmitted to each of the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118 through the base die 100 and the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118. The control via array 131-1 may be located at the top center of the peripheral area 125A, and the control via array 131-2 may be located at the bottom center of the peripheral area 125A, but this is only an example and the present disclosure is not limited thereto.

[0060] Each of the data via arrays 132-1, 132-2, 132-3, and 132-4 may transmit the first core data CDATA1 and the second core data CDATA2 output from each of the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118 to the base die 100 through the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118. The data via array 132-1 may be located at the upper left portion of the peripheral area 125A, the data via array 132-2 may be located at the lower left portion of the peripheral area 125A, the data via array 132-3 may be located at the upper right portion of the peripheral area 125A, and the data via array 132-4 may be located at the lower right portion of the peripheral area 125A, but this is only an example and the present disclosure is not limited thereto.

[0061] Alignment data strobe signal generation circuit 133 may be connected to control via arrays 131-1 and 131-2 to receive read identification signal RSID, read channel signal RPC, and internal clock signal ICLK from control via arrays 131-1 and 131-2. Alignment data strobe signal generation circuit 133 may generate alignment data strobe signal ADQS based on read identification signal RSID, read channel signal RPC, and internal clock signal ICLK. Alignment data strobe signal generation circuit 133 may latch read identification signal RSID and read channel signal RPC in synchronization with internal clock signal ICLK. Based on the latched read identification signal RSID and read channel signal RPC, alignment data strobe signal ADQS may be generated to output first core data CDATA1 or second core data CDATA2 when performing a read operation for a specific pseudo channel (e.g., PC0 or PC1) of a specific rank (e.g., RANK0 or RANK1). When a read operation of the first pseudo channel PC0 for a specific Rank (e.g., RANK0 or RANK1) is performed, the first core data CDATA1 can be output from the first pseudo core area 123-1. When a read operation of the second pseudo channel PC1 for a specific Rank (e.g., RANK0 or RANK1) is performed, the second core data CDATA2 can be output from the second pseudo core area 123-2.

[0062] The first core pipe 135-1 may be electrically connected to the alignment data strobe signal generation circuit 133 to receive the alignment data strobe signal ADQS from the alignment data strobe signal generation circuit 133. The first core pipe 135-1 may output the first core data CDATA1 to the base die 100 through the data via arrays 132-1 and 132-2 based on the alignment data strobe signal ADQS. For example, when a read operation of the first pseudo channel PC0 for a specific rank (e.g., RANK0 or RANK1) is performed, the first core pipe 135-1 may output the first core data CDATA1 to the base die 100 through the data via arrays 132-1 and 132-2.

[0063] The second core pipe 135-2 may be electrically connected to the alignment data strobe signal generation circuit 133 to receive the alignment data strobe signal ADQS from the alignment data strobe signal generation circuit 133. The second core pipe 135-2 may output the second core data CDATA2 to the base die 100 through the data via arrays 132-3 and 132-4 based on the alignment data strobe signal ADQS. For example, when a read operation of the second dummy channel PC1 for a specific rank (e.g., RANK0 or RANK1) is performed, the second core pipe 135-2 may output the second core data CDATA2 to the base die 100 through the data via arrays 132-3 and 132-4.

[0064] Figure 7 Shown Figure 6 The configuration of the embodiment of the alignment data strobe signal generation circuit 133 is shown in FIG.

[0065] like Figure 7 As shown, the alignment data strobe signal generating circuit 133 may include a latch signal generating circuit (LATGEN) 141 and an internal clock signal alignment circuit (ICLK ALIGN) 143 .

[0066] The latch signal generation circuit 141 can generate a latch identification signal RSID-L, an inverted latch identification signal RSID-LB, a latch channel signal RPC-L, and an inverted latch channel signal RPC-LB based on the internal clock signal ICLK, the read identification signal RSID, and the read channel signal RPC. The latch signal generation circuit 141 can latch the read identification signal RSID and the read channel signal RPC synchronously with the internal clock signal ICLK to generate the latch identification signal RSID-L, the inverted latch identification signal RSID-LB, the latch channel signal RPC-L, and the inverted latch channel signal RPC-LB. For example, the latch signal generation circuit 141 can latch the read identification signal RSID and the read channel signal RPC in phase with the internal clock signal ICLK to generate the latch identification signal RSID-L and the latch channel signal RPC-L. When the internal clock signal ICLK includes the first internal clock signal ICLK1, the second internal clock signal ICLK2, the first inverted internal clock signal ICLK1B, and the second inverted internal clock signal ICLK2B, the same phase as the internal clock signal ICLK may be set to be synchronized with the first internal clock signal ICLK1. However, this is only an example and the present disclosure is not limited thereto.

[0067] In addition, the latch signal generating circuit 141 can latch the read identification signal RSID and the read channel signal RPC out of phase with the internal clock signal ICLK to generate the inverted latch identification signal RSID-LB and the inverted latch channel signal RPC-LB. The out-of-phase synchronization with the internal clock signal ICLK can be set to be synchronized with the first inverted internal clock signal ICLK1B, but this is only an example and the present disclosure is not limited thereto.

[0068] The internal clock signal alignment circuit 143 may be electrically connected to the latch signal generation circuit 141 to receive the latch identification signal RSID-L, the inverted latch identification signal RSID-LB, the latch channel signal RPC-L, and the inverted latch channel signal RPC-LB from the latch signal generation circuit 141. The internal clock signal alignment circuit 143 may generate the alignment data strobe signal ADQS based on the latch identification signal RSID-L, the inverted latch identification signal RSID-LB, the latch channel signal RPC-L, the inverted latch channel signal RPC-LB, the internal clock signal ICLK, and the core identification signal CID. When a read operation is performed on a specific pseudo channel (e.g., PC0 or PC1) included in a specific Rank (e.g., RANK0 or RANK1), the internal clock signal alignment circuit 143 may generate an alignment data strobe signal ADQS based on the latch identification signal RSID-L, the inverted latch identification signal RSID-LB, the latch channel signal RPC-L, the inverted latch channel signal RPC-LB, and the core identification signal CID in synchronization with the internal clock signal ICLK. For example, when a read operation is performed on a specific pseudo channel (e.g., PC0 or PC1) included in a specific Rank (e.g., RANK0 or RANK1), the internal clock signal alignment circuit 143 may generate an alignment data strobe signal ADQS based on the latch identification signal RSID-L, the latch channel signal RPC-L, and the core identification signal CID in phase with the internal clock signal ICLK. Furthermore, when a read operation is performed on a specific pseudo channel (e.g., PC0 or PC1) included in a specific rank (e.g., RANK0 or RANK1), the internal clock signal alignment circuit 143 can generate an alignment data strobe signal ADQS based on the inverted latch identification signal RSID-LB, the inverted latch channel signal RPC-LB, and the core identification signal CID in a phase-out synchronization with the internal clock signal ICLK. In one embodiment, the read identification signal RSID indicates the specific rank (e.g., RANK0 or RANK1) on which the read operation is performed. In one embodiment, the read channel signal RPC indicates the specific pseudo channel (e.g., PC0 or PC1) on which the read operation is performed.

[0069] Figure 8 Shown Figure 7 The configuration of the embodiment of the latch signal generating circuit 141 shown in FIG. Figure 8 As shown, the latch signal generating circuit 141 may include a first latch 145 - 1 and a second latch 145 - 2 .

[0070] The first latch 145-1 may latch the read identification signal RSID in synchronization with the first internal clock signal ICLK1 to generate a latch identification signal RSID-L. The first latch 145-1 may latch the read channel signal RPC in synchronization with the first internal clock signal ICLK1 to generate a latch channel signal RPC-L.

[0071] The second latch 145-2 may latch the read identification signal RSID in synchronization with the first inverted internal clock signal ICLK1B to generate an inverted latch identification signal RSID-LB. The second latch 145-2 may latch the read channel signal RPC in synchronization with the first inverted internal clock signal ICLK1B to generate an inverted latch channel signal RPC-LB.

[0072] Latch signal generation circuit 141A can latch read identification signal RSID and read channel signal RPC in synchronization with the in-phase phase of internal clock signal ICLK (i.e., first internal clock signal ICLK1) to generate latch identification signal RSID-L and latch channel signal RPC-L. Latch signal generation circuit 141A can latch read identification signal RSID and read channel signal RPC in synchronization with the out-of-phase phase of internal clock signal ICLK (i.e., first inverted internal clock signal ICLK1B) to generate inverted latch identification signal RSID-LB and inverted latch channel signal RPC-LB.

[0073] Figure 9 Shown Figure 7 The configuration of the embodiment of the internal clock signal alignment circuit 143 is shown. Figure 9 As shown, the internal clock signal alignment circuit 143 may include an in-phase activation signal generation circuit (IP-E GEN) 151, an out-of-phase activation signal generation circuit (OP-E GEN) 153, an in-phase data strobe signal generation circuit (DQS-IP GEN) 155, an out-of-phase data strobe signal generation circuit (DQS-OP GEN) 157 and a data strobe signal summing circuit (DQS SUM) 159.

[0074] The in-phase activation signal generation circuit 151 can generate an in-phase activation signal IP-E based on the latch identification signal RSID-L, the latch channel signal RPC-L, and the core identification signal CID. When the latch identification signal RSID-L and the core identification signal CID correspond to each other and the latch channel signal RPC-L is activated, the in-phase activation signal generation circuit 151 can generate an activated in-phase activation signal IP-E. The core identification signal CID can include information regarding the core die where the internal clock signal alignment circuit 143 is located and information regarding the Rank that includes the core die. When the Rank on which a read operation is being performed, indicated by the latch identification signal RSID-L, corresponds to the Rank that includes the core die indicated by the core identification signal CID and the latch channel signal RPC-L corresponding to the pseudo channel (e.g., PC0 or PC1) on which the read operation is being performed is activated, the in-phase activation signal generation circuit 151 can generate an activated in-phase activation signal IP-E.

[0075] The out-of-phase activation signal generation circuit 153 may generate an out-of-phase activation signal OP-E based on the inverted latch identification signal RSID-LB, the inverted latch channel signal RPC-LB, and the core identification signal CID. When the inverted latch identification signal RSID-LB and the core identification signal CID correspond to each other and the inverted latch channel signal RPC-LB is activated, the out-of-phase activation signal generation circuit 153 may generate an activated out-of-phase activation signal OP-E. When the Rank of the read operation performed, indicated by the inverted latch identification signal RSID-LB, corresponds to the Rank of the core die indicated by the core identification signal CID and the inverted latch channel signal RPC-LB corresponding to the dummy channel (e.g., PC0 or PC1) of the read operation is activated, the out-of-phase activation signal generation circuit 153 may generate an activated out-of-phase activation signal OP-E.

[0076] The in-phase data strobe signal generation circuit 155 can be electrically connected to the in-phase activation signal generation circuit 151 to receive the in-phase activation signal IP-E from the in-phase activation signal generation circuit 151. The in-phase data strobe signal generation circuit 155 can generate the in-phase data strobe signal DQS-IP from the internal clock signal ICLK based on the in-phase activation signal IP-E. When a read operation for a corresponding dummy channel included in a core die of a corresponding Rank is performed in phase with the internal clock signal ICLK and the in-phase activation signal IP-E is activated, the in-phase data strobe signal generation circuit 155 can generate the in-phase data strobe signal DQS-IP from the internal clock signal ICLK.

[0077] The out-of-phase data strobe signal generation circuit 157 can be electrically connected to the out-of-phase activation signal generation circuit 153 to receive the out-of-phase activation signal O-E from the out-of-phase activation signal generation circuit 153. The out-of-phase data strobe signal generation circuit 157 can generate the out-of-phase data strobe signal DQS-OP from the internal clock signal ICLK based on the out-of-phase activation signal O-E. When a read operation for a corresponding dummy channel included in a core die of a corresponding Rank is performed in synchronization with an out-of-phase of the internal clock signal ICLK and the out-of-phase activation signal O-E is activated, the out-of-phase data strobe signal generation circuit 157 can generate the out-of-phase data strobe signal DQS-OP from the internal clock signal ICLK.

[0078] The data strobe signal summing circuit 159 can be electrically connected to the in-phase data strobe signal generating circuit 155 and the out-of-phase data strobe signal generating circuit 157 to receive the in-phase data strobe signal DQS-IP from the in-phase data strobe signal generating circuit 155 or the out-of-phase data strobe signal DQS-OP from the out-of-phase data strobe signal generating circuit 157. The data strobe signal summing circuit 159 can sum the in-phase data strobe signal DQS-IP and the out-of-phase data strobe signal DQS-OP to generate the alignment data strobe signal ADQS. For example, when a read operation is performed on a corresponding dummy channel included in a core die of a corresponding Rank in synchronization with the internal clock signal ICLK and in phase, the data strobe signal summing circuit 159 can generate the in-phase data strobe signal DQS-IP generated in synchronization with the internal clock signal ICLK as the alignment data strobe signal ADQS. In addition, when the read operation of the corresponding pseudo channel included in the core die of the corresponding Rank is performed in synchronization with the internal clock signal ICLK and is out of phase, the data selection signal summing circuit 159 can generate the out-of-phase data selection signal DQS-OP generated in synchronization with the internal clock signal ICLK as the alignment data selection signal ADQS.

[0079] Figure 10 Shown Figure 9 10 , the in-phase activation signal generating circuit 151 may include XOR devices 161 - 1 and 161 - 2 , a NOR device 162 , a selector 163 , and an AND device 164 .

[0080] The XOR device 161-1 can receive the first bit RSID-L of the latch identification signal RSID-L. <0> and the third bit of the core identification signal CID <2> To perform an XOR operation. When the first bit RSID-L of the latch identification signal RSID-L <0> and the third bit of the core identification signal CID <2> When the first bit RSID-L of the latch identification signal RSID-L is the same as the first bit RSID-L of the latch identification signal RSID-L, the XOR device 161-1 can output a signal of a logic “low” level. <0> and the third bit of the core identification signal CID <2> When different from each other, the XOR device 161 - 1 may output a signal of a logic “high” level.

[0081] The XOR device 161-2 can receive the second bit RSID-L of the latch identification signal RSID-L. <1> and the fourth bit CID of the core identification signal CID <3> To perform an XOR operation. When the second bit RSID-L of the latch identification signal RSID-L <1> and the fourth bit CID of the core identification signal CID <3> When the second bit RSID-L of the latch identification signal RSID-L is the same as the first bit RSID-L of the latch identification signal RSID-L, the XOR device 161-2 can output a signal of a logic “low” level. <1> and the fourth bit CID of the core identification signal CID <3> When different from each other, the XOR device 161 - 2 may output a signal of a logic “high” level.

[0082] NOR device 162 may be electrically connected to XOR device 161-1 and XOR device 161-2 to receive the output signal of XOR device 161-1 and the output signal of XOR device 161-2 and perform a NOR operation. NOR device 162 may output a logic "high" level signal when the second bit and the first bit RSID-L<1:0> of latch identification signal RSID-L are identical to the fourth bit and the third bit CID<3:2> of core identification signal CID, and may output a logic "low" level signal when the second bit and the first bit RSID-L<1:0> of latch identification signal RSID-L are different from the fourth bit and the third bit CID<3:2> of core identification signal CID. Here, the second bit and the first bit RSID-L<1:0> of the latch identification signal RSID-L may indicate information about the Rank on which the read operation is performed, and the fourth bit and the third bit CID<3:2> of the core identification signal CID may indicate information about the Rank to which the core die including the in-phase activation signal generating circuit 151 belongs. However, the number and type of bits may be changed in various ways according to embodiments.

[0083] The selector 163 can selectively output one of the latch channel signal RPC-L and the write setting signal WT-RPC based on the write signal WT. The logic level of the write signal WT can be set according to whether a write operation is performed. For example, the write signal WT can be set to have a logic "high" level when a write operation is performed, and can be set to have a logic "low" level when a read operation is performed. The selector 163 can output the write setting signal WT-RPC when a write operation is performed, and can output the latch channel signal RPC-L when a read operation is performed. The logic level of the write signal WT and the signal selected by the selector 163 based on the write signal WT can be set in various ways according to the embodiment.

[0084] The AND device 164 may be electrically connected to the NOR device 162 and the selector 163 to receive the output signal of the NOR device 162 and the output signal of the selector 163. The AND device 164 may receive the output signal of the NOR device 162 and the output signal of the selector 163 to perform an AND operation and generate an in-phase activation signal IP-E.

[0085] When the Rank of the read operation performed indicated by the latch identification signal RSID-L corresponds to the Rank of the core die indicated by the core identification signal CID and the latch channel signal RPC-L corresponding to the pseudo channel (e.g., PC0 or PC1) on which the read operation is performed is activated, the in-phase activation signal generating circuit 151A can generate an activated in-phase activation signal IP-E.

[0086] Figure 11 An example of a read identification signal RSID that can indicate the Rank on which a read operation is performed is shown.

[0087] like Figure 11 As shown, when the second bit and the first bit RSID-L<1:0> of the latch identification signal RSID-L in the read operation are generated as the binary bit group '00', it can indicate that the read operation is performed on the first Rank RANK0. In addition, when the second bit and the first bit RSID-L<1:0> of the latch identification signal RSID-L in the read operation are generated as the binary bit group '01', it can indicate that the read operation is performed on the second Rank RANK1.

[0088] Figure 12 An example of a core identification signal CID that can indicate a core die and Rank on which a read operation is performed is shown.

[0089] like Figure 12As shown, when the fourth to first bits CID<3:0> of the core identification signal CID are generated as the binary bit group '0000', it can indicate that the read operation is performed in the first core die 111 of the first Rank RANK0; when the fourth to first bits CID<3:0> of the core identification signal CID are generated as the binary bit group '0001', it can indicate that the read operation is performed in the second core die 112 of the first Rank RANK0; when the fourth to first bits CID<3:0> of the core identification signal CID are generated as the binary bit group '0010', it can indicate that the read operation is performed in the third core die 113 of the first Rank RANK0; when the fourth to first bits CID<3:0> of the core identification signal CID are generated as the binary bit group '0011', it can indicate that the read operation is performed in the first Rank The fourth to first bits CID<3:0> of the core identification signal CID are generated as the binary bit group '0100', which may indicate that the read operation is performed in the fifth core die 115 of the second Rank RANK1; when the fourth to first bits CID<3:0> of the core identification signal CID are generated as the binary bit group '0101', which may indicate that the read operation is performed in the sixth core die 116 of the second Rank RANK1; when the fourth to first bits CID<3:0> of the core identification signal CID are generated as the binary bit group '0110', which may indicate that the read operation is performed in the seventh core die 117 of the second Rank RANK1; and when the fourth to first bits CID<3:0> of the core identification signal CID are generated as the binary bit group '0111', which may indicate that the read operation is performed in the eighth core die 118 of the second Rank RANK1.

[0090] Figure 13 An example of a latched channel signal RPC-L that may indicate a pseudo channel (eg, PC0 or PC1 ) on which a read operation is performed is shown.

[0091] like Figure 13 As shown, when the second bit and the first bit RPC-L<1:0> of the latch channel signal RPC-L are set to the binary bit group '01', it can indicate that the read operation is performed in the first pseudo channel PC0; and when the second bit and the first bit RPC-L<1:0> of the latch channel signal RPC-L are set to the binary bit group '10', it can indicate that the read operation is performed in the second pseudo channel PC1.

[0092] Figure 14 Shown Figure 9The circuit of the embodiment of the out-of-phase activation signal generating circuit 153 is shown. Figure 14 As shown, the out-of-phase activation signal generating circuit 153 may include XOR devices 165 - 1 and 165 - 2 , a NOR device 166 , a selector 167 , and an AND device 168 .

[0093] The XOR device 165-1 can receive the first bit RSID-LB of the inverted latch identification signal RSID-LB. <0> and the third bit of the core identification signal CID <2> The XOR device 165-1 can latch the first bit RSID-LB of the identification signal RSID-LB in the inverted state. <0> The third bit of the core identification signal CID <2> output a logic "low" level signal when they are the same as each other, and can invert the first bit RSID-LB of the latch identification signal RSID-LB. <0> The third bit of the core identification signal CID <2> Signals of a logic "high" level are not output simultaneously.

[0094] The XOR device 165-2 can receive the second bit RSID-LB of the inverted latch identification signal RSID-LB. <1> and the fourth bit CID of the core identification signal CID <3> The XOR device 165-2 can latch the second bit RSID-LB of the identification signal RSID-LB in the inverted state. <1> The fourth bit CID of the core identification signal CID <3> When the two bits are the same, the logic "low" level signal is output, and the second bit RSID-LB of the inverted latch identification signal RSID-LB is latched. <1> The fourth bit CID of the core identification signal CID <3> Signals of a logic "high" level are not output simultaneously.

[0095] The NOR device 166 can be electrically connected to the XOR device 165-1 and the XOR device 165-2 to receive the output signal of the XOR device 165-1 and the output signal of the XOR device 165-2 and perform a NOR operation. When the second bit and the first bit RSID-LB<1:0> of the inverted latch identification signal RSID-LB are the same as the fourth bit and the third bit CID<3:2> of the core identification signal CID, the NOR device 166 can output a signal of a logic "high" level, and when the second bit and the first bit RSID-LB<1:0> of the inverted latch identification signal RSID-LB are different from the fourth bit and the third bit CID<3:2> of the core identification signal CID, the NOR device 166 can output a signal of a logic "low" level. Here, the second bit and the first bit RSID-LB<1:0> of the inverted latch identification signal RSID-LB can indicate information about the Rank of the read operation being performed, but the number and type of bits can be changed in various ways according to the embodiment.

[0096] The selector 167 can selectively output either the inverted latch channel signal RPC-LB or the write setup signal WT-RPC based on the write signal WT. The selector 163 can output the write setup signal WT-RPC when a write operation is performed, and can output the inverted latch channel signal RPC-LB when a read operation is performed.

[0097] The AND device 168 may be electrically connected to the NOR device 166 and the selector 167 to receive the output signal of the NOR device 166 and the output signal of the selector 167. The AND device 168 may receive the output signal of the NOR device 166 and the output signal of the selector 167 to perform an AND operation and generate an out-of-phase activation signal O-E.

[0098] When the Rank of the read operation performed indicated by the inverted latch identification signal RSID-LB corresponds to the Rank of the core die indicated by the core identification signal CID and the inverted latch channel signal RPC-LB corresponding to the pseudo channel (e.g., PC0 or PC1) on which the read operation is performed is activated, the out-of-phase activation signal generation circuit 153A can generate an activated out-of-phase activation signal OP-E.

[0099] Figure 15 and Figure 16 Shown Figure 7 The operation of the embodiment of the alignment data strobe signal generation circuit 133A shown in FIG. The operation of the alignment data strobe signal generation circuit 133A when a read operation is performed on the first pseudo channel PC0 of the first Rank RANK0 and when a read operation is performed on the first pseudo channel PC0 of the second Rank RANK1 will be described separately. Here, assuming that the in-phase data strobe signal DQS-IP includes the first to sixth in-phase data strobe signals DQS-IP1 to DQS-IP6, and the alignment data strobe signal ADQS includes the first to sixth alignment data strobe signals ADQS1 to ADQS6, the operation can be described as follows.

[0100] like Figure 15As shown, at time point T21, when the second bit and the first bit RSID-L<1:0> of the latch identification signal RSID-L set to the binary bit group '00' are received and the second bit and the first bit RPC-L<1: 0> of the latch channel signal RPC-L set to the binary bit group '01' are received, and the read operation of the first pseudo channel PC0 of the first Rank RANK0 is performed, the in-phase activation signal generating circuit 151 can generate an activated in-phase activation signal IP-E at time point T22. From time point T23 onward, when one cycle of the first internal clock signal ICLK1 has elapsed since time point T21, the first to sixth in-phase data strobe signals DQS-IP1 to DQS-IP6 and the first to sixth alignment data strobe signals ADQS1 to ADQS6 can be generated from the first internal clock signal ICLK1, the second internal clock signal ICLK2, the first inverted internal clock signal ICLK1B, and the second inverted internal clock signal ICLK2B. For example, at time point T23, the in-phase data strobe signal generation circuit 155 can generate the first in-phase data strobe signal DQS-IP1 based on the first internal clock signal ICLK1, and the data strobe signal summing circuit 159 can generate the first alignment data strobe signal ADQS1 based on the first in-phase data strobe signal DQS-IP1. Furthermore, at time point T24, the in-phase data strobe signal generation circuit 155 can generate a second in-phase data strobe signal DQS-IP2 based on the second internal clock signal ICLK2, and the data strobe signal summing circuit 159 can generate a second alignment data strobe signal ADQS2 based on the second in-phase data strobe signal DQS-IP2. Furthermore, at time point T25, the in-phase data strobe signal generation circuit 155 can generate a third in-phase data strobe signal DQS-IP3 based on the first inverted internal clock signal ICLK1B, and the data strobe signal summing circuit 159 can generate a third alignment data strobe signal ADQS3 based on the third in-phase data strobe signal DQS-IP3. Furthermore, at time point T26, the in-phase data strobe signal generation circuit 155 may generate a fourth in-phase data strobe signal DQS-IP4 based on the second inverted internal clock signal ICLK2B, and the data strobe signal summing circuit 159 may generate a fourth alignment data strobe signal ADQS4 based on the fourth in-phase data strobe signal DQS-IP4. Furthermore, at time point T27, the in-phase data strobe signal generation circuit 155 may generate a fifth in-phase data strobe signal DQS-IP5 based on the first internal clock signal ICLK1, and the data strobe signal summing circuit 159 may generate a fifth alignment data strobe signal ADQS5 based on the fifth in-phase data strobe signal DQS-IP5.In addition, at time point T28, the in-phase data strobe signal generation circuit 155 can generate a sixth in-phase data strobe signal DQS-IP6 according to the second internal clock signal ICLK2, and the data strobe signal summing circuit 159 can generate a sixth alignment data strobe signal ADQS6 according to the sixth in-phase data strobe signal DQS-IP6.

[0101] like Figure 16As shown, at time point T31, when the second bit and the first bit RSID-L<1:0> of the latch identification signal RSID-L set to the binary bit group '01' are received and the second bit and the first bit RPC-L<1: 0> of the latch channel signal RPC-L set to the binary bit group '01' are received in synchronization with the out-of-phase of the internal clock signal ICLK (i.e., the first inverted internal clock signal ICLK1B), and the read operation of the first pseudo channel PC0 of the second Rank RANK1 is performed, the out-of-phase activation signal generating circuit 153 can generate an activated out-of-phase activation signal OP-E at time point T32. From time point T33 onward, when one cycle of the first inverted internal clock signal ICLK1B has elapsed since time point T31, the first to sixth out-of-phase data strobe signals DQS-OP1 to DQS-OP6 and the first to sixth alignment data strobe signals ADQS1 to ADQS6 can be generated from the first inverted internal clock signal ICLK1B, the second inverted internal clock signal ICLK2B, the first internal clock signal ICLK1, and the second internal clock signal ICLK2. For example, at time point T33, the out-of-phase data strobe signal generation circuit 157 can generate the first out-of-phase data strobe signal DQS-OP1 based on the first inverted internal clock signal ICLK1B, and the data strobe signal summing circuit 159 can generate the first alignment data strobe signal ADQS1 based on the first out-of-phase data strobe signal DQS-OP1. Furthermore, at time point T34, the out-of-phase data strobe signal generation circuit 157 may generate a second out-of-phase data strobe signal DQS-OP2 based on the second inverted internal clock signal ICLK2B, and the data strobe signal summing circuit 159 may generate a second alignment data strobe signal ADQS2 based on the second out-of-phase data strobe signal DQS-OP2. Furthermore, at time point T35, the out-of-phase data strobe signal generation circuit 157 may generate a third out-of-phase data strobe signal DQS-OP3 based on the first internal clock signal ICLK1, and the data strobe signal summing circuit 159 may generate a third alignment data strobe signal ADQS3 based on the third out-of-phase data strobe signal DQS-OP3. Furthermore, at time point T36, the out-of-phase data strobe signal generation circuit 157 may generate a fourth out-of-phase data strobe signal DQS-OP4 based on the second internal clock signal ICLK2, and the data strobe signal summing circuit 159 may generate a fourth alignment data strobe signal ADQS4 based on the fourth out-of-phase data strobe signal DQS-OP4. In addition, at time point T37, the out-of-phase data strobe signal generation circuit 157 can generate a fifth out-of-phase data strobe signal DQS-OP5 based on the first inverted internal clock signal ICLK1B, and the data strobe signal summing circuit 159 can generate a fifth alignment data strobe signal ADQS5 based on the fifth out-of-phase data strobe signal DQS-OP5.In addition, at time point T38, the out-of-phase data strobe signal generation circuit 157 can generate a sixth out-of-phase data strobe signal DQS-OP6 according to the second inverted internal clock signal ICLK2B, and the data strobe signal summing circuit 159 can generate a sixth alignment data strobe signal ADQS6 according to the sixth out-of-phase data strobe signal DQS-OP6.

[0102] Figure 17 Shown according to Figure 5 The configuration of the peripheral region 125B of another example of the peripheral region 125 is shown. Figure 17 As shown, the peripheral region 125B may include control via arrays (CTR TSV ARRAY (1) to CTR TSV ARRAY (2)) 171-1 to 171-2, data strobe via arrays (DQS TSV ARRAY (1) to DQS TSV ARRAY (2)) 172-1 to 172-2, an alignment data strobe signal generation circuit (ADQS GEN) 173, a first read data strobe signal transmission circuit (RDQS TX (1)) 175-1, and a second read data strobe signal transmission circuit (RDQS TX (2)) 175-2.

[0103] Each of the control via arrays 171-1 and 171-2 can connect the base die ( Figure 1 The read identification signal RSID, the read channel signal RPC, and the internal clock signal ICLK generated in the base die 100 are transmitted to each of the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118 through the base die 100 and the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118. The control via array 171-1 may be located at the top center of the peripheral area 125B, and the control via array 171-2 may be located at the bottom center of the peripheral area 125B, but this is only an example and the present disclosure is not limited thereto.

[0104] Each of the data strobe via arrays 172-1 and 172-2 may transmit a read data strobe signal RDQS output from each of the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118 to the base die 100 through the plurality of core dies 111, 112, 113, 114, 115, 116, 117, and 118. The data strobe via array 172-1 may be located at the upper left portion of the peripheral area 125A, and the data strobe via array 172-2 may be located at the upper right portion of the peripheral area 125A, but this is only an example and the present disclosure is not limited thereto.

[0105] Alignment data strobe signal generation circuit 173 can be electrically connected to control via arrays 171-1 and 171-2 to receive read identification signal RSID, read channel signal RPC, and internal clock signal ICLK from control via arrays 171-1 and 171-2. Alignment data strobe signal generation circuit 173 can generate alignment data strobe signal ADQS based on read identification signal RSID, read channel signal RPC, and internal clock signal ICLK. Alignment data strobe signal generation circuit 173 can latch read identification signal RSID and read channel signal RPC in synchronization with internal clock signal ICLK. Based on the latched read identification signal RSID and read channel signal RPC, alignment data strobe signal ADQS can be generated when a read operation is performed on a specific pseudo channel (e.g., PC0 or PC1) of a specific rank (e.g., RANK0 or RANK1) to transmit read data strobe signal RDQS to base die 100.

[0106] The first read data strobe signal transmission circuit 175-1 may be electrically connected to the alignment data strobe signal generation circuit 173 to receive the alignment data strobe signal ADQS from the alignment data strobe signal generation circuit 173. The first read data strobe signal transmission circuit 175-1 may output the read data strobe signal RDQS generated based on the alignment data strobe signal ADQS to the base die 100 through the data strobe via array 172-1. For example, when a read operation is performed on the first dummy channel PC0 of the corresponding Rank (e.g., RANK0 or RANK1), the first read data strobe signal transmission circuit 175-1 may generate the read data strobe signal RDQS based on the alignment data strobe signal ADQS and output the read data strobe signal RDQS to the base die 100 through the data strobe via array 172-1. In one embodiment, since the read data strobe signal RDQS is generated according to the alignment data strobe signal ADQS during the transfer period, the first read data strobe signal transmission circuit 175-1 can prevent or mitigate overlap of the read data strobe signals RDQS generated for each read operation when a read operation is performed on the first dummy channel PC0 and then a read operation is performed on another dummy channel (e.g., PC0 or PC1). The transfer period can be set to one cycle of the internal clock signal ICLK, but this is only an example and the present disclosure is not limited thereto.

[0107] The second read data strobe signal transmission circuit 175-2 may be electrically connected to the alignment data strobe signal generation circuit 173 to receive the alignment data strobe signal ADQS from the alignment data strobe signal generation circuit 173. The second read data strobe signal transmission circuit 175-2 may output the read data strobe signal RDQS generated based on the alignment data strobe signal ADQS to the base die 100 through the data strobe via array 172-2. For example, the second read data strobe signal transmission circuit 175-2 may generate the read data strobe signal RDQS based on the alignment data strobe signal ADQS and output the read data strobe signal RDQS to the base die 100 through the data strobe via array 172-2 when a read operation is performed on the second dummy channel PC1 of the corresponding Rank (e.g., RANK0 or RANK1). In one embodiment, since the read data strobe signal RDQS is generated according to the alignment data strobe signal ADQS during the transmission period, the second read data strobe signal transmission circuit 175-2 can prevent or alleviate the read data strobe signals RDQS generated for each read operation from overlapping each other when a read operation is performed on the second pseudo channel PC1 and then a read operation is performed on other pseudo channels (e.g., PC0 or PC1).

[0108] Figure 18 Shown Figure 17 The configuration of the example of the first read data strobe signal transmission circuit 175-1 is shown in FIG. Figure 18 As shown, the first read data strobe signal transmission circuit 175 - 1 may include a transmission activation signal generation circuit (TX-EN GEN) 181 and a read data strobe signal generation circuit (RDQS GEN) 183 .

[0109] The transmission activation signal generation circuit 181 can generate the transmission activation signal TX-EN based on the alignment data selection signal ADQS. The transmission activation signal generation circuit 181 can combine the bits included in the alignment data selection signal ADQS to generate the transmission activation signal TX-EN bits, which are activated during each preset transmission period. As an example, when the alignment data selection signal ADQS includes the first to sixth alignment data selection signals ADQS1~ADQS6, and the transmission activation signal TX-EN includes the first to fourth transmission activation signals TX-EN1~TX-EN4, the transmission activation signal generation circuit 181 can generate the first transmission activation signal TX-EN1 which is activated during the transmission period generated by the first alignment data selection signal ADQS1 and the third alignment data selection signal ADQS3, can generate the second transmission activation signal TX-EN2 which is activated during the transmission period generated by the second alignment data selection signal ADQS2 and the fourth alignment data selection signal ADQS4, can generate the third transmission activation signal TX-EN3 which is activated during the transmission period generated by the third alignment data selection signal ADQS3 and the fifth alignment data selection signal ADQS5, and can generate the fourth transmission activation signal TX-EN4 which is activated during the transmission period generated by the fourth alignment data selection signal ADQS4 and the sixth alignment data selection signal ADQS6.

[0110] The read data strobe signal generation circuit 183 may be electrically connected to the transmission activation signal generation circuit 181 to receive the transmission activation signal TX-EN from the transmission activation signal generation circuit 181. The read data strobe signal generation circuit 183 may generate a read data strobe signal RDQS based on the transmission activation signal TX-EN and the alignment data strobe signal ADQS. The read data strobe signal generation circuit 183 may generate the read data strobe signal RDQS according to the alignment data strobe signal ADQS during a transmission period in which the transmission activation signal TX-EN is activated. As an example, when the alignment data strobe signal ADQS includes the first to sixth alignment data strobe signals ADQS1 to ADQS6, the transmission activation signal TX-EN includes the first to fourth transmission activation signals TX-EN1 to TX-EN4, and the read data strobe signal RDQS includes the first to fourth read data strobe signals RDQS1 to RDQS4, the read data strobe signal generation circuit 183 may generate the first alignment data strobe signal ADQS1 as the first read data strobe signal during the transmission period in which the first transmission activation signal TX-EN1 is activated. RDQS1, the second alignment data selection signal ADQS2 can be generated as the second read data selection signal RDQS2 during the transmission period when the second transmission activation signal TX-EN2 is activated, the third alignment data selection signal ADQS3 can be generated as the third read data selection signal RDQS3 during the transmission period when the third transmission activation signal TX-EN3 is activated, and the fourth alignment data selection signal ADQS4 can be generated as the fourth read data selection signal RDQS4 during the transmission period when the fourth transmission activation signal TX-EN4 is activated.

[0111] Figure 19 Shown Figure 18 The circuit shown is an example of the transmission activation signal generating circuit 181.

[0112] like Figure 19As shown, the transmission activation signal generation circuit 181 may include OR devices 185-1 to 185-4. OR device 185-1 can receive the first alignment data strobe signal ADQS1 and the third alignment data strobe signal ADQS3 to perform an OR operation and generate a first transmission activation signal TX-EN1. OR device 185-2 can receive the second alignment data strobe signal ADQS2 and the fourth alignment data strobe signal ADQS4 to perform an OR operation and generate a second transmission activation signal TX-EN2. OR device 185-3 can receive the third alignment data strobe signal ADQS3 and the fifth alignment data strobe signal ADQS5 to perform an OR operation and generate a third transmission activation signal TX-EN3. OR device 185-4 can receive the fourth alignment data strobe signal ADQS4 and the sixth alignment data strobe signal ADQS6 to perform an OR operation and generate a fourth transmission activation signal TX-EN4.

[0113] The transmission activation signal generation circuit 181 may generate a first transmission activation signal TX-EN1 that is activated at a logic "high" level during a transmission period in which each of the first alignment data strobe signal ADQS1 and the third alignment data strobe signal ADQS3 is generated at a logic "high" level. The transmission activation signal generation circuit 181 may generate a second transmission activation signal TX-EN2 that is activated at a logic "high" level during a transmission period in which each of the second alignment data strobe signal ADQS2 and the fourth alignment data strobe signal ADQS4 is generated at a logic "high" level. The transmission activation signal generation circuit 181 may generate a third transmission activation signal TX-EN3 that is activated at a logic "high" level during a transmission period in which each of the third alignment data strobe signal ADQS3 and the fifth alignment data strobe signal ADQS5 is generated at a logic "high" level. The transmission activation signal generating circuit 181 may generate a fourth transmission activation signal TX-EN4 that is activated at a logic “high” level during a transmission period in which each of the fourth alignment data selection signal ADQS4 and the sixth alignment data selection signal ADQS6 is generated at a logic “high” level.

[0114] Figure 20 Shown Figure 18 The configuration of the embodiment of the read data strobe signal generating circuit 183 is shown in FIG. Figure 20As shown, the read data strobe signal generation circuit 183 may include a first read data strobe signal generation circuit (RDQS1GEN) 187-1, a second read data strobe signal generation circuit (RDQS2GEN) 187-2, a third read data strobe signal generation circuit (RDQS3GEN) 187-3, and a fourth read data strobe signal generation circuit (RDQS4GEN) 187-4.

[0115] The first read data strobe signal generation circuit 187-1 may generate a first read data strobe signal RDQS1 based on the first transmission activation signal TX-EN1 and the first alignment data strobe signal ADQS1. For example, the first read data strobe signal generation circuit 187-1 may generate the first alignment data strobe signal ADQS1 as the first read data strobe signal RDQS1 during a transmission period in which the first transmission activation signal TX-EN1 is activated.

[0116] The second read data strobe signal generation circuit 187-2 may generate a second read data strobe signal RDQS2 based on the second transmission activation signal TX-EN2 and the second alignment data strobe signal ADQS2. For example, the second read data strobe signal generation circuit 187-2 may generate the second alignment data strobe signal ADQS2 as the second read data strobe signal RDQS2 during a transmission period in which the second transmission activation signal TX-EN2 is activated.

[0117] The third read data strobe signal generation circuit 187-3 may generate a third read data strobe signal RDQS3 based on the third transmission activation signal TX-EN3 and the third alignment data strobe signal ADQS3. For example, the third read data strobe signal generation circuit 187-3 may generate the third alignment data strobe signal ADQS3 as the third read data strobe signal RDQS3 during a transmission period in which the third transmission activation signal TX-EN3 is activated.

[0118] The fourth read data strobe signal generation circuit 187-4 may generate a fourth read data strobe signal RDQS4 based on the fourth transfer activation signal TX-EN4 and the fourth alignment data strobe signal ADQS4. For example, the fourth read data strobe signal generation circuit 187-4 may generate the fourth alignment data strobe signal ADQS4 as the fourth read data strobe signal RDQS4 during a transfer period in which the fourth transfer activation signal TX-EN4 is activated.

[0119] Figure 21 Shown Figure 17 An embodiment of a read operation performed in the peripheral region 125B is shown. Figures 17 to 21, the read operations when the read operation is performed on the first dummy channel PC0 of the first Rank RANK0 and when the read operation is performed on the first dummy channel PC0 of the second Rank RANK1 can be respectively described as follows.

[0120] like Figure 17 and Figure 21 As shown, when a read operation is performed on the first pseudo channel PC0 of the first Rank RANK0, the alignment data selection signal generation circuit 173 can generate a first alignment data selection signal ADQS1 at time point T31, can generate a second alignment data selection signal ADQS2 at time point T32, can generate a third alignment data selection signal ADQS3 at time point T33, can generate a fourth alignment data selection signal ADQS4 at time point T34, can generate a fifth alignment data selection signal ADQS5 at time point T35, and can generate a sixth alignment data selection signal ADQS6 at time point T36.

[0121] like Figure 19 and Figure 21 As shown, the transmission activation signal generating circuit 181 can generate a first transmission activation signal TX-EN1 activated at a logic “high” level during a transmission period T31 to T35 in which the first alignment data selection signal ADQS1 and the third alignment data selection signal ADQS3 are generated at a logic “high” level, can generate a second transmission activation signal TX-EN2 activated at a logic “high” level during a transmission period T32 to T36 in which the second alignment data selection signal ADQS2 and the fourth alignment data selection signal ADQS4 are generated at a logic “high” level, can generate a third transmission activation signal TX-EN3 activated at a logic “high” level during a transmission period T33 to T41 in which the third alignment data selection signal ADQS3 and the fifth alignment data selection signal ADQS5 are generated at a logic “high” level, and can generate a fourth transmission activation signal TX-EN4 activated at a logic “high” level during a transmission period T34 to T42 in which the fourth alignment data selection signal ADQS4 and the sixth alignment data selection signal ADQS6 are generated at a logic “high” level.

[0122] like Figure 20 and 21As shown, the first read data selection signal generating circuit 187-1 can generate the first alignment data selection signal ADQS1 as the first read data selection signal RDQS1 during the transmission period T31~T35 when the first transmission activation signal TX-EN1 is activated, the second read data selection signal generating circuit 187-2 can generate the second alignment data selection signal ADQS2 as the second read data selection signal RDQS2 during the transmission period T32~T36 when the second transmission activation signal TX-EN2 is activated, the third read data selection signal generating circuit 187-3 can generate the third alignment data selection signal ADQS3 as the third read data selection signal RDQS3 during the transmission period T33~T41 when the third transmission activation signal TX-EN3 is activated, and the fourth read data selection signal generating circuit 187-4 can generate the fourth alignment data selection signal ADQS4 as the fourth read data selection signal RDQS4 during the transmission period T34~T36 when the fourth transmission activation signal TX-EN2 is activated.

[0123] like Figure 17 and Figure 21 As shown, when a read operation is performed on the first pseudo channel PC0 of the second Rank RANK1, the alignment data selection signal generation circuit 173 can generate a first alignment data selection signal ADQS1 at time point T41, can generate a second alignment data selection signal ADQS2 at time point T42, can generate a third alignment data selection signal ADQS3 at time point T43, can generate a fourth alignment data selection signal ADQS4 at time point T44, can generate a fifth alignment data selection signal ADQS5 at time point T45, and can generate a sixth alignment data selection signal ADQS6 at time point T46.

[0124] like Figure 19 and 21As shown, the transmission activation signal generating circuit 181 can generate a first transmission activation signal TX-EN1 activated at a logic “high” level during a transmission period T41 to T45 in which each of the first alignment data strobe signal ADQS1 and the third alignment data strobe signal ADQS3 is generated at a logic “high” level, and can generate a second transmission activation signal activated at a logic “high” level during a transmission period T42 to T46 in which each of the second alignment data strobe signal ADQS2 and the fourth alignment data strobe signal ADQS4 is generated at a logic “high” level. TX-EN2 can generate a third transmission activation signal TX-EN3 that is activated at a logic "high" level during a transmission period T43 to T47 in which each of the third alignment data selection signal ADQS3 and the fifth alignment data selection signal ADQS5 is generated at a logic "high" level, and can generate a fourth transmission activation signal TX-EN4 that is activated at a logic "high" level during a transmission period T44 to T48 in which each of the fourth alignment data selection signal ADQS4 and the sixth alignment data selection signal ADQS6 is generated at a logic "high" level.

[0125] like Figure 20 and 21 As shown, the first read data selection signal generating circuit 187-1 can generate the first alignment data selection signal ADQS1 as the first read data selection signal RDQS1 during the transmission period T41~T45 when the first transmission activation signal TX-EN1 is activated, the second read data selection signal generating circuit 187-2 can generate the second alignment data selection signal ADQS2 as the second read data selection signal RDQS2 during the transmission period T42~T46 when the second transmission activation signal TX-EN2 is activated, the third read data selection signal generating circuit 187-3 can generate the third alignment data selection signal ADQS3 as the third read data selection signal RDQS3 during the transmission period T43~T47 when the third transmission activation signal TX-EN3 is activated, and the fourth read data selection signal generating circuit 187-4 can generate the fourth alignment data selection signal ADQS4 as the fourth read data selection signal RDQS4 during the transmission period T44~T48 when the fourth transmission activation signal TX-EN4 is activated.

[0126] As described above, when the read operation on the first pseudo channel PC0 of the first Rank RANK0 and the read operation on the first pseudo channel PC0 of the second Rank RANK1 are sequentially performed, the first to fourth read data strobe signals RDQS1 to RDQS4 can be generated while ensuring the transmission period. Therefore, in one embodiment, the first to fourth read data strobe signals RDQS1 to RDQS4 generated in the read operation on the first pseudo channel PC0 of the first Rank RANK0 and the first to fourth read data strobe signals RDQS1 to RDQS4 generated in the read operation on the first pseudo channel PC0 of the second Rank RANK1 can be prevented from or mitigated from overlapping with each other.

[0127] In the foregoing description, although the read operation on the first pseudo channel PC0 of the first Rank RANK0 and the read operation on the first pseudo channel PC0 of the second Rank RANK1 are described as being performed in the same peripheral area 125B, this is only for comparison of the two read operations. In one embodiment, preferably, the read operation on the first pseudo channel PC0 of the first Rank RANK0 and the read operation on the first pseudo channel PC0 of the second Rank RANK1 are performed in the peripheral areas set for each. Therefore, in Figure 21 In one embodiment, preferably, the first to sixth alignment data select signals ADQS1~ADQS6, the first to fourth transmission activation signals TX-EN1~TX-EN4 and the first to fourth read data select signals RDQS1~RDQS4 are also generated separately for each pseudo channel of each Rank.

[0128] Figure 22 2 shows a configuration of a stacked memory device 20 according to another example of the present disclosure. Figure 22 As shown, the stacked memory device 20 may include a base die 200 and a plurality of core dies 211 ˜ 213 .

[0129] Each of the plurality of core dies 211-213 can be stacked on the base die 200. The plurality of core dies 211 and 213 illustrate some of the plurality of core dies stacked on the base die 200. The core die 211 can include a first channel CH0, which includes a first pseudo channel PC0. The core die 213 can include a first channel CH0, which includes a first pseudo channel PC0. The first channel CH0 of the core die 211 and the first channel CH0 of the core die 213 can share at least one data path through which data is input and output. The first channel CH0 of the core die 211 can be included in the first Rank RANK0, while the first channel CH0 of the core die 213 can be included in the second Rank RANK1.

[0130] When a read operation is performed on the first pseudo channel PC0 of the first Rank RANK0, the core die 211 may generate a read data strobe signal RDQS to transmit the read data strobe signal RDQS to the base die 200 through the via 221. When a read operation is performed on the first pseudo channel PC0 of the second Rank RANK1, the core die 213 may generate a read data strobe signal RDQS to transmit the read data strobe signal RDQS to the base die 200 through the via 221.

[0131] The base die 200 may include a data output circuit (DATA OUT) 201 and an interface circuit (PHY) 203. The data output circuit 201 may be electrically connected to a via 221 to receive a read data strobe signal RDQS from the via 221. The data output circuit 201 may align core data CDATA based on the read data strobe signal RDQS to transmit the core data CDATA to the interface circuit 203. For example, when a read operation is performed on the first pseudo channel PC0 of the first Rank RANK0, the data output circuit 201 may align the core data CDATA output from the core die 211 in synchronization with the read data strobe signal RDQS generated in the core die 211. Furthermore, when a read operation is performed on the first pseudo channel PC0 of the second Rank RANK1, the data output circuit 201 may align the core data CDATA output from the core die 213 in synchronization with the read data strobe signal RDQS generated in the core die 213. The interface circuit 203 may convert the aligned core data CDATA received from the electrically connected data output circuit 201 into transmission data TDATA to transmit the transmission data TDATA to a memory controller (not shown).

[0132] The above-mentioned stacked memory device 20 can transmit the read data select signal RDQS generated in the core die 211 when a read operation is performed on the first pseudo channel PC0 of the first Rank RANK0 and the read data select signal RDQS generated in the core die 213 when a read operation is performed on the first pseudo channel PC0 of the second Rank RANK1 to the base die 200 through the same through-hole 221, thereby reducing the number of through-holes used to transmit the read data select signal RDQS.

[0133] The concepts have been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictive, but rather illustrative. The scope of the concepts is not limited to the foregoing description, but is defined by the appended claims, and all distinguishing features within the scope of equivalents should be understood to be encompassed by the concepts.

Claims

1. A memory device comprising: an alignment data strobe signal generating circuit, which: receives a read identification signal, a read channel signal, and an internal clock signal; and generates an alignment data strobe signal from the internal clock signal when a read operation on a specific pseudo channel of a specific Rank is performed based on the read identification signal and the read channel signal; and A core pipeline receives the alignment data strobe signal and outputs core data output from the specific pseudo channel based on the alignment data strobe signal.

2. The memory device according to claim 1, wherein The read identification signal indicates the specific Rank.

3. The memory device according to claim 1, wherein The read channel signal indicates the specific pseudo channel. 4 . The memory device of claim 1 , further comprising a base die that: receives an external clock signal and an external command; and generates the read identification signal and the read channel signal based on the external clock signal and the external command.

5. The memory device according to claim 4, wherein The basic die includes: a command decoder that: decodes the external command in synchronization with the external clock signal received from the memory controller to generate a read command, a channel signal, and an identification signal; and A read control circuit generates the read identification signal and the read channel signal based on the read command, the channel signal and the identification signal. The memory device according to claim 5 , wherein: The base die further includes an internal clock signal generating circuit that divides the external clock signal to generate the internal clock signal.

7. The memory device of claim 4 , further comprising a plurality of core dies stacked on top of the base die, in, Each of the plurality of core dies includes a plurality of channels, and Each of the plurality of channels includes a plurality of dummy channels.

8. The memory device according to claim 7, wherein The channels included in the core die form at least one Rank for setting bandwidth.

9. The memory device according to claim 7, wherein: Each of the plurality of core dies includes the alignment data strobe signal generation circuit that receives the read identification signal and the read channel signal from the base die to generate the alignment data strobe signal.

10. The memory device according to claim 7, wherein Each of the plurality of core dies includes a core pipeline that outputs the core data to the base die.

11. The memory device according to claim 1, wherein The alignment data strobe signal generation circuit includes a latch signal generation circuit that generates a latch identification signal, an inverted latch identification signal, a latch channel signal, and an inverted latch channel signal based on the internal clock signal, the read identification signal, and the read channel signal.

12. The memory device according to claim 11, wherein The latch signal generating circuit: latching the read identification signal in phase with the internal clock signal to generate the latch identification signal, latching the read channel signal in phase with the internal clock signal to generate the latched channel signal, latching the read identification signal out of phase with the internal clock signal to generate the inverted latch identification signal, and The read channel signal is latched in out-of-phase synchronization with the internal clock signal to generate the inverted latched channel signal.

13. The memory device according to claim 11, wherein The alignment data selection signal generation circuit also includes an internal clock signal alignment circuit, which: receives a core identification signal; and generates an alignment data selection signal based on the latch identification signal, the inverted latch identification signal, the latch channel signal, the inverted latch channel signal, the internal clock signal and the core identification signal.

14. The memory device according to claim 13, wherein: The internal clock signal alignment circuit generates the alignment data strobe signal based on the latch identification signal, the latch channel signal, and the core identification signal that are in phase with the internal clock signal.

15. The memory device according to claim 13, wherein: The internal clock signal alignment circuit generates the alignment data select signal from the internal clock signal when the specific Rank indicated by the latch identification signal corresponds to the Rank of the core die indicated by the core identification signal and the latch channel signal corresponding to the specific pseudo channel is activated.

16. The memory device according to claim 15, wherein When the internal clock signal includes a first internal clock signal, a second internal clock signal, a first inverted internal clock signal, and a second inverted internal clock signal, the alignment data strobe signal includes a first alignment data strobe signal to a sixth alignment data strobe signal, and the latch identification signal and the latch channel signal are generated in synchronization with the first internal clock signal. The internal clock signal alignment circuit: generating the first alignment data strobe signal according to the first internal clock signal, generating the second alignment data strobe signal according to the second internal clock signal, generating the third alignment data strobe signal according to the first inverted internal clock signal, generating the fourth alignment data strobe signal according to the second inverted internal clock signal, generating the fifth alignment data strobe signal according to the first internal clock signal, and The sixth alignment data strobe signal is generated according to the second internal clock signal.

17. The memory device according to claim 13, wherein: The internal clock signal alignment circuit generates the alignment data strobe signal based on the inverted latch identification signal, the inverted latch channel signal, and the core identification signal that are out of phase with the internal clock signal.

18. The memory device according to claim 17, wherein: The internal clock signal alignment circuit generates the alignment data select signal from the internal clock signal when the specific Rank indicated by the inverted latch identification signal corresponds to the Rank of the core die indicated by the core identification signal and the inverted latch channel signal corresponding to the specific pseudo channel is activated.

19. The memory device according to claim 15, wherein: When the internal clock signal includes a first internal clock signal, a second internal clock signal, a first inverted internal clock signal, and a second inverted internal clock signal, the alignment data strobe signal includes a first alignment data strobe signal to a sixth alignment data strobe signal, and the inverted latch identification signal and the inverted latch channel signal are generated in synchronization with the first inverted internal clock signal. The internal clock signal alignment circuit: generating the first alignment data strobe signal according to the first inverted internal clock signal, generating the second alignment data strobe signal according to the second inverted internal clock signal, generating the third alignment data strobe signal according to the first internal clock signal, generating the fourth alignment data strobe signal according to the second internal clock signal, generating the fifth alignment data strobe signal according to the first inverted internal clock signal, and The sixth alignment data strobe signal is generated according to the second inverted internal clock signal.

20. The memory device of claim 13, wherein: The internal clock signal alignment circuit includes: an in-phase activation signal generating circuit, which generates an in-phase activation signal based on the latch identification signal, the latch channel signal and the core identification signal; an out-of-phase activation signal generating circuit, which generates an out-of-phase activation signal based on the inverted latch identification signal, the inverted latch channel signal and the core identification signal; an in-phase data strobe signal generating circuit that generates an in-phase data strobe signal from the internal clock signal based on the in-phase activation signal; an out-of-phase data strobe signal generating circuit that generates an out-of-phase data strobe signal from the internal clock signal based on the out-of-phase activation signal; and A data strobe signal summing circuit sums the in-phase data strobe signal and the out-of-phase data strobe signal to generate the aligned data strobe signal.

21. The memory device of claim 1 , further comprising: a control via array that transmits the read identification signal and the read channel signal received from a base die to the alignment data strobe signal generating circuit; as well as A data via array transmits the core data output from the core pipeline to the base die.

22. A memory device comprising: Multiple core dies stacked on top of a base die, Each of the plurality of core dies includes an alignment data strobe signal generation circuit, the alignment data strobe signal generation circuit receiving an internal clock signal, a read identification signal, and a read channel signal from the base die to generate an alignment data strobe signal, and Wherein, the alignment data strobe signal generating circuit: generating a latch identification signal and a latch channel signal from the read identification signal and the read channel signal in phase with the internal clock signal, and generating the alignment data strobe signal based on the latch identification signal, the latch channel signal and the core identification signal, and An inverted latch identification signal and an inverted latch channel signal are generated from the read identification signal and the read channel signal out of phase with the internal clock signal, and the alignment data strobe signal is generated based on the inverted latch identification signal, the inverted latch channel signal, and the core identification signal.

23. The memory device of claim 22, wherein: The read identification signal indicates a specific Rank on which a read operation is performed, and the read channel signal indicates a specific pseudo channel on which the read operation is performed.

24. The memory device of claim 22, wherein: When the internal clock signal includes a first internal clock signal, a second internal clock signal, a first inverted internal clock signal, and a second inverted internal clock signal, the alignment data strobe signal includes a first alignment data strobe signal to a sixth alignment data strobe signal, and the latch identification signal and the latch channel signal are generated in synchronization with the first internal clock signal. The alignment data strobe signal generating circuit: generating a first alignment data strobe signal according to the first internal clock signal, generating a second alignment data strobe signal according to the second internal clock signal, generating a third alignment data strobe signal according to the first inverted internal clock signal, generating a fourth alignment data strobe signal according to the second inverted internal clock signal, generating a fifth alignment data strobe signal according to the first internal clock signal, and A sixth alignment data strobe signal is generated according to the second internal clock signal.

25. The memory device of claim 22, wherein: When the internal clock signal includes a first internal clock signal, a second internal clock signal, a first inverted internal clock signal, and a second inverted internal clock signal, the alignment data strobe signal includes a first alignment data strobe signal to a sixth alignment data strobe signal, and the inverted latch identification signal and the inverted latch channel signal are generated in synchronization with the first inverted internal clock signal. The alignment data strobe signal generating circuit: generating a first alignment data strobe signal according to the first inverted internal clock signal, generating a second alignment data strobe signal according to the second inverted internal clock signal, generating a third alignment data strobe signal according to the first internal clock signal, generating a fourth alignment data strobe signal according to the second internal clock signal, generating a fifth alignment data strobe signal according to the first inverted internal clock signal, and A sixth alignment data strobe signal is generated according to the second inverted internal clock signal.

26. The memory device of claim 22, wherein: The basic bare chip receives an external clock signal and an external command; And generating the read identification signal and the read channel signal based on the external clock signal and the external command.

27. The memory device of claim 22, wherein: The alignment data strobe signal generating circuit comprises: a latch signal generating circuit that generates the latch identification signal, the inverted latch identification signal, the latch channel signal, and the inverted latch channel signal based on the internal clock signal, the read identification signal, and the read channel signal; and The internal clock signal alignment circuit generates the alignment data strobe signal based on the latch identification signal, the inverted latch identification signal, the latch channel signal, the inverted latch channel signal, the internal clock signal and the core identification signal. 28 . The memory device of claim 22 , further comprising a core pipeline that receives the alignment data strobe signal and outputs core data output from the dummy channel on which the read operation is performed based on the alignment data strobe signal.

29. The memory device of claim 28, further comprising: a control via array that transmits the read identification signal and the read channel signal received from a base die to the alignment data strobe signal generating circuit; as well as A data via array transmits the core data output from the core pipeline to the base die.

30. A memory device comprising: Multiple core dies stacked on top of a base die, Each of the plurality of core dies comprises: an alignment data strobe signal generating circuit, which: receives an internal clock signal, a read identification signal, and a read channel signal from the base die to generate an alignment data strobe signal; and a read data strobe signal transmission circuit, which generates a read data strobe signal based on the alignment data strobe signal, and transmits the read data strobe signal to the base die, The read data strobe signal generated from the core dies forming the same Rank among the plurality of core dies is transmitted to the base die through the same through-hole array.

31. The memory device of claim 30, wherein: The read data strobe signal transmission circuit includes: a transfer activation signal generating circuit that: generates a transfer activation signal activated during a transfer period based on the alignment data strobe signal; and A read data strobe signal generating circuit generates the read data strobe signal according to the alignment data strobe signal during the transfer period in which the transfer activation signal is activated.

32. The memory device of claim 31, wherein: When the alignment data strobe signal includes the first to sixth alignment data strobe signals, the transfer activation signal includes the first to fourth transfer activation signals, and the read data strobe signal includes the first to fourth read data strobe signals, The transmission activation signal generating circuit: generating the first transfer activation signal activated during a first transfer period in which the first alignment data strobe signal and the third alignment data strobe signal are generated, generating a second transfer activation signal activated during a second transfer period in which the second alignment data strobe signal and the fourth alignment data strobe signal are generated, generating the third transfer activation signal activated during a third transfer period in which the third alignment data strobe signal and the fifth alignment data strobe signal are generated, and The fourth transfer activation signal is generated to be activated during a fourth transfer period in which the fourth alignment data strobe signal and the sixth alignment data strobe signal are generated.

33. The memory device of claim 32, wherein: The read data strobe signal generating circuit: outputting the first alignment data strobe signal as the first read data strobe signal during the first transfer period, outputting the second alignment data strobe signal as the second read data strobe signal during the second transfer period, outputting the third alignment data strobe signal as the third read data strobe signal during the third transfer period, and The fourth alignment data strobe signal is output as the fourth read data strobe signal during the fourth transfer period.

34. A memory device comprising: Multiple core dies stacked on top of a base die, wherein each of the plurality of core dies comprises a plurality of channels, wherein each of the plurality of channels comprises a first dummy channel and a second dummy channel, and wherein the plurality of channels form a first Rank and a second Rank for setting bandwidth, and Wherein, the memory device: receiving an internal clock signal, a read identification signal, and a read channel signal to: generate a first alignment data strobe signal from the internal clock signal based on the read identification signal and the read channel signal when a read operation on the first dummy channel of the first Rank is performed, and generate a first read data strobe signal from the first alignment data strobe signal during a first transfer period based on the first alignment data strobe signal; and When a read operation on the first pseudo channel of the second Rank is performed, a second alignment data selection signal is generated from the internal clock signal based on the read identification signal and the read channel signal, and a second read data selection signal is generated from the second alignment data selection signal during a second transmission period based on the second alignment data selection signal.

35. A memory device comprising: Multiple core dies stacked on top of a base die, wherein each of the plurality of core dies comprises a plurality of channels, wherein each of the plurality of channels comprises a first dummy channel and a second dummy channel, and wherein the plurality of channels form a first Rank and a second Rank for setting bandwidth, and Wherein, the memory device: receiving an internal clock signal, a read identification signal, and a read channel signal to: generate a first alignment data strobe signal from the internal clock signal based on the read identification signal and the read channel signal when a read operation on the first dummy channel of the first Rank is performed, and generate a first read data strobe signal from the first alignment data strobe signal during a first transfer period based on the first alignment data strobe signal; and When a read operation on the second pseudo channel of the second Rank is performed, a second alignment data selection signal is generated from the internal clock signal based on the read identification signal and the read channel signal, and a second read data selection signal is generated from the second alignment data selection signal during a second transmission period based on the second alignment data selection signal.

36. A memory device comprising: Multiple core dies stacked on top of a base die, wherein each of the plurality of core dies comprises a plurality of channels, wherein each of the plurality of channels comprises a first dummy channel and a second dummy channel, wherein the plurality of channels form a Rank for setting bandwidth, and Wherein, the memory device: receiving an internal clock signal, a read identification signal, and a read channel signal to: generate a first alignment data strobe signal from the internal clock signal based on the read identification signal and the read channel signal when a read operation on the first dummy channel of the Rank is performed, and generate a first read data strobe signal from the first alignment data strobe signal during a first transfer period based on the first alignment data strobe signal, and When a read operation on the second pseudo channel of the Rank is performed, a second alignment data selection signal is generated from the internal clock signal based on the read identification signal and the read channel signal, and a second read data selection signal is generated from the second alignment data selection signal during a second transmission period based on the second alignment data selection signal.

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