Differential amplifier circuitry with coarse and fine gain trimming

Abstract

The invention relates to differential amplifier circuitry with coarse and fine gain trimming. An integrated circuit includes differential amplifier circuitry (430, Figure 4). The differential amplifier circuitry (430) includes first gain trim circuitry (470) having a first gain trim input (472), the first gain trim circuitry (470) including a first differential input transistor pair and a second differential input transistor pair. The differential amplifier circuitry (430) also includes second gain trim circuitry (474) having a second gain trim input (476), the second gain trim circuitry including a third differential input transistor pair and a fourth differential input transistor pair. The differential amplifier circuitry (430) also includes control logic (450) having a first gain trim output (458) and a second gain trim output (460). The first gain trim output (458) is coupled to the first gain trim input (472). The second gain trim output (460) is coupled to the second gain trim input (476).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 553,158, filed on February 14, 2024, entitled “CIRCUIT FOR AMPLIFIER WITH INTEGRATED DAC ENABLING COURSE AND FINE GAIN TUNING,” attorney docket number T104083US01, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to a differential amplifier circuit system with coarse and fine gain trimming. Background Art

[0004] Closed-loop amplifiers are typically used to amplify a differential input voltage with a fixed gain to produce an output voltage. Dynamic amplifier gain adjustment would extend compatibility with a range of input signals and reduce gain errors due to variations (e.g., temperature changes, component aging, etc.). The complexity, cost, and / or limited accuracy of dynamic amplifier gain adjustment circuitry are ongoing challenges. Summary of the Invention

[0005] In one example, an integrated circuit includes differential amplifier circuitry. The differential amplifier circuitry includes: first gain trim circuitry having a first gain trim input, the first gain trim circuitry including a first differential input transistor pair and a second differential input transistor pair; second gain trim circuitry having a second gain trim input, the second gain trim circuitry including a third differential input transistor pair and a fourth differential input transistor pair; and control logic having a first gain trim output and a second gain trim output. The first gain trim output is coupled to the first gain trim input. The second gain trim output is coupled to the second gain trim input.

[0006] In another example, a differential amplifier circuit includes: a first differential input transistor pair; a second differential input transistor pair; a resistor pair; a first selection circuit system having a first control input, the first selection circuit system coupled between the resistor pair and the first differential input transistor pair; a second selection circuit system having a second control input, the second selection circuit system coupled between the set of resistor pairs and the second differential input transistor pair; and control logic having a first gain trim output and a second gain trim output, the first gain trim output coupled to the first control input, and the second gain trim output coupled to the second control input.

[0007] In yet another example, an apparatus includes differential amplifier circuitry. The differential amplifier circuitry includes first gain trimming circuitry, second gain trimming circuitry, and control logic coupled to the coarse gain trimming circuitry and the fine gain trimming circuitry. The control logic is configured to receive a control input, determine a gain setting based on the control input, adjust a setting of the first gain trimming circuitry in response to the gain setting, and adjust a setting of the second gain trimming circuitry in response to the gain setting. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram illustrating an example system.

[0009] Figure 2 is a diagram illustrating another example system.

[0010] Figure 3A is a schematic diagram illustrating example differential amplifier circuitry.

[0011] Figure 3B is a schematic diagram showing other differential amplifier circuit systems.

[0012] Figure 4 is a block diagram illustrating example differential amplifier circuitry.

[0013] Figure 5 is a schematic diagram illustrating example gain trimming circuitry.

[0014] Figure 6 is a schematic diagram illustrating other example gain fine-tuning circuitry.

[0015] Figure 7 is a diagram illustrating example differential amplifier circuitry.

[0016] Figure 8 is a flow chart illustrating an example gain fine tuning control method. DETAILED DESCRIPTION

[0017] The same reference numerals or other reference signs are used in the drawings to designate the same or similar features. Such features may be the same or similar in function and / or structure.

[0018] Figure 1is a diagram illustrating an example system 100. In various examples, system 100 is part of an overvoltage protection system, a battery management system, a power telemetry system, a motor control system, or a solenoid control system. As shown, system 100 includes an electrical device 102, an integrated circuit (IC) 120, and a controller 140. In various examples, electrical device 102 may be a battery, a motor, a solenoid, a telemetry device, a power conditioning device, a sensor, or other electrical device. Figure 1 In the example of FIG, electrical device 102 has a first terminal 104, a second terminal 106, and a third terminal 108. If electrical device 102 is a sensor, third terminal 108 can be omitted. IC 120 has a first terminal 122, a second terminal 124, and a third terminal 126. Controller 140 has a first terminal 142 and a second terminal 144.

[0019] exist Figure 1 In the example of , IC 120 includes differential amplifier circuitry 130 having gain trimming circuitry 138. Differential amplifier circuitry 130 has a first terminal 132, a second terminal 134, and a third terminal 136. Figure 1 In the example of FIG. 1 , a first terminal 104 of an electrical device 102 is coupled to a first terminal 122 of an IC 120. A second terminal 106 of the electrical device 102 is coupled to a second terminal 124 of the IC 120. A third terminal 126 of the IC 120 is coupled to a first terminal 142 of a controller 140. A second terminal 144 of the controller 140 is coupled to a third terminal 108 of the electrical device 102. A first terminal 122 of the IC 120 is coupled to a first terminal 132 of a differential amplifier circuitry 130. A second terminal 124 of the IC 120 is coupled to a second terminal 134 of the differential amplifier circuitry 130. A third terminal 126 of the IC 120 is coupled to a third terminal 136 of the differential amplifier circuitry 130.

[0020] In some examples, electrical device 102 is configured to receive a control signal CS1 at third terminal 108 and perform an operation in response to control signal CS1. In other examples, electrical device 102 does not require control signal CS1 to perform an operation. During operation of electrical device 102, a voltage difference exists between first terminal 104 and second terminal 106 of electrical device 102. The voltage difference is received at first terminal 122 and second terminal 124 of IC 120 and at first terminal 132 and second terminal 134 of differential amplifier circuitry 130. Differential amplifier circuitry 130 is configured to receive a differential voltage across first terminal 132 and second terminal 134, apply a gain to the differential voltage, and provide a sense signal SNS1 at third terminal 136 in response to the differential voltage and the gain. In some examples, the gain of differential amplifier circuitry 130 can be adjusted using gain adjustment circuitry 138. In some examples, gain adjustment circuitry 138 provides a coarse gain adjustment level and a fine gain adjustment level. To improve accuracy, the gain trim circuitry 138 may include chopper amplifier components, which reduce the effects of temperature drift and noise.

[0021] The controller 140 is configured to receive a sense signal SNS1 at the first terminal 142 and adjust the control signal CS1 in response to the sense signal SNS1. In some examples, the process of monitoring the differential voltage, providing the sense signal SNS1 to the controller 140, and adjusting the control signal CS1 is repeated to provide continuous overvoltage protection, continuous battery management, continuous power telemetry, continuous motor control, continuous solenoid control, continuous power regulation, or other system operations. The control signal CS1 may be, for example, Figure 1 It is shown being provided to the electrical device 102, or may be provided to another electrical device.

[0022] The gain of differential amplifier circuitry 130 is adjustable using gain trimming circuitry 138. In some examples, gain trimming circuitry 138 is capable of both coarse and fine gain adjustments. Coarse gain adjustments can be used to cover a target range of gain values. Fine gain adjustments can be used to provide a target gain accuracy. In some examples, gain trimming circuitry 138 includes chopper circuitry. Using chopper circuitry reduces errors in differential amplifier circuitry 130. Such errors can be caused by offset voltage (e.g., due to component mismatch), temperature drift, gain drift, and noise (flicker noise). In some examples, gain trimming circuitry 138 includes control logic for selecting between different gain adjustment options and / or chopper options in response to user input and / or monitored parameters (e.g., input signal range, temperature, and / or other monitored parameters).

[0023] Figure 2 2 is a diagram illustrating another example system. In various examples, system 200 is part of an overvoltage protection system, a battery management system, a power telemetry system, a motor control system, or a solenoid control system. As shown, system 200 includes an electrical device 202, a sense resistor 210, an IC 220, and a controller 240. In various examples, electrical device 202 may be a battery, a motor, a solenoid, a telemetry device, a power conditioning device, a sensor, or other electrical device. Figure 2 In the example of FIG, electrical device 202 has a first terminal 204, a second terminal 206, and a third terminal 208. Sense resistor 210 has a first terminal 212 and a second terminal 214. IC 220 has a first terminal 222, a second terminal 224, and a third terminal 226. Controller 240 has a first terminal 242 and a second terminal 244.

[0024] exist Figure 2 In the example of , IC 220 includes differential amplifier circuitry 230 having gain trimming circuitry 238. Differential amplifier circuitry 230 has a first terminal 232, a second terminal 234, and a third terminal 236. Figure 2 In the example of FIG. 2 , a first terminal 204 of the electrical device 202 is coupled to a first terminal 212 of the sense resistor 210 and a first terminal 222 of the IC 220. A second terminal 206 of the electrical device 202 is coupled to a second terminal 214 of the sense resistor 210 and a second terminal 224 of the IC 220. A third terminal 226 of the IC 220 is coupled to a first terminal 242 of the controller 240. A second terminal 244 of the controller 240 is coupled to a third terminal 208 of the electrical device 202.

[0025] First terminal 222 of IC 220 is coupled to first terminal 232 of differential amplifier circuitry 230. Second terminal 224 of IC 220 is coupled to second terminal 234 of differential amplifier circuitry 230. Third terminal 226 of IC 220 is coupled to third terminal 236 of differential amplifier circuitry 230.

[0026] In some examples, the electrical device 202 is configured to: receive a control signal CS2 at the third terminal 208; and perform an operation in response to the control signal CS2. During operation of the electrical device 202, a current ISNS flows from the first terminal 204 and through the sense resistor 210. Figure 2In some examples, current ISNS flows back to second terminal 206 of electrical device 202. In other examples, current ISNS flows to a ground terminal. In either case, current ISNS is monitored by IC 220. In some examples, differential amplifier circuitry 230 monitors current ISNS by monitoring the voltage drop across sense resistor 210. In such examples, differential amplifier circuitry 230 is configured to receive a first voltage level at a first terminal 232, receive a second voltage level at a second terminal 234, and provide a current sense signal S2_ISNS at a third terminal 236 in response to the first and second voltage levels. Controller 240 is configured to receive current sense signal S2_ISNS at a first terminal 242 and adjust control signal CS2 in response to current sense signal S2_ISNS. In some examples, the process of monitoring current ISNS using sense resistor 210 and differential amplifier circuitry 230, providing current sense signal S2_ISNS to controller 240, and adjusting control signal CS2 for electrical device 202 is repeated to provide continuous overcurrent protection, continuous battery management, continuous power telemetry, continuous motor control, continuous solenoid control, continuous power regulation, or other system operations.

[0027] The gain of differential amplifier circuitry 230 is adjustable using gain adjustment circuitry 238. In some examples, gain adjustment circuitry 238 is capable of both coarse and fine gain adjustment. Alternatively, gain adjustment circuitry 238 includes chopper circuitry. In some examples, gain adjustment circuitry 238 includes control logic for selecting between different gain adjustment options and / or chopper options in response to user input and / or monitored parameters (e.g., input signal range, temperature, and / or other monitored parameters).

[0028] Figure 3A is a schematic diagram illustrating an example differential amplifier circuit system 300. The differential amplifier circuit system 300 is Figure 1 The differential amplifier circuit system 130 or Figure 2 In some examples, the differential amplifier circuit system 300 may have Figure 7 The chopper amplifier architecture in the differential amplifier circuit system 700 is shown in FIG. Figure 3A In the example of FIG, differential amplifier circuitry 300 has a first terminal 302, a second terminal 304, a third terminal 306, and a fourth terminal 308. Differential amplifier circuitry 300 includes an operational amplifier 309, a trimming controller 320, and resistors R1a, R1a_adj, R2a_adj, R2a, R1b, R1b_adj, R2b_adj, and R2b in the arrangement shown.

[0029] Trimming controller 320 has a first terminal 322, a second terminal 324, and a third terminal 326. Operational amplifier 309 has a first (inverting or "-") terminal 310, a second (non-inverting or "+") terminal 312, and a third terminal 314. Resistors R1a, R1a_adj, R2a_adj, R2a, R1b, R1b_adj, R2b_adj, and R2b each have a respective first terminal and a respective second terminal. Resistors R1a_adj and R2a_adj form a trimmable resistor controlled by control signal Ctadj_a. In some examples, the value of R1a_adj is inversely proportional to R2a_adj. In other words, when control signal Ctadj_a increases R1a_adj, R2a_adj decreases by the same amount, such that the total value of R1a_adj + R2a_adj remains constant. Similarly, when control signal Ctadj_a decreases R1a_adj, R2a_adj increases by the same amount, keeping the total value of R1a_adj + R2a_adj constant. Furthermore, resistors R1b_adj and R2b_adj form a trimmable resistor controlled by control signal Ctadj_b. The value of R1b_adj is inversely proportional to R2b_adj. In other words, when control signal Ctadj_b increases R1b_adj, R2b_adj decreases by the same amount, keeping the total value of R1b_adj + R2b_adj constant. Similarly, when control signal Ctadj_b decreases R1b_adj, R2b_adj increases by the same amount, keeping the total value of R1b_adj + R2b_adj constant.

[0030] exist Figure 3A In the example of FIG, a first terminal 302 of the differential amplifier circuitry 300 is coupled to a first terminal of a resistor R1a. A second terminal of the resistor R1a is coupled to a first terminal of a resistor R1a_adj. A second terminal of the resistor R1a_adj is coupled to a first terminal of a resistor R2a_adj and a first terminal 310 of an operational amplifier 309. A second terminal of the resistor R2a_adj is coupled to a first terminal of a resistor R2a. A second terminal of the resistor R2a is coupled to a third terminal 314 of the operational amplifier 309 and a third terminal 306 of the differential amplifier circuitry 300.

[0031] exist Figure 3AIn the example shown in FIG. 3 , second terminal 304 of differential amplifier circuitry 300 is coupled to a first terminal of resistor R1b. A second terminal of resistor R1b is coupled to a first terminal of resistor R1b_adj. A second terminal of resistor R1b_adj is coupled to a first terminal of resistor R2b_adj and a second terminal 312 of operational amplifier 309. A second terminal of resistor R2b_adj is coupled to a first terminal of resistor R2b. A second terminal of resistor R2b is coupled to a fourth terminal 308 of differential amplifier circuitry 300. A second terminal 324 of trim controller 320 is coupled to a control terminal of the trimmable resistors associated with resistors R1a_adj and R2a_adj. A third terminal 326 of trim controller 320 is coupled to a control terminal of the trimmable resistors associated with resistors R1b_adj and R2b_adj.

[0032] exist Figure 3A In the example of FIG, differential amplifier circuit system 300 is configured to receive a first input voltage VINA at a first terminal 302, a second input voltage VINb at a second terminal 304, and provide an output voltage VOUT at a third terminal 306 in response to the operation of an operational amplifier 309, a resistor network formed by resistors R1a, R1a_adj, R2a_adj, R2a, R1b, R1b_adj, R2b_adj, and R2b, and the operation of a trimming controller 320. In some examples, a reference voltage VREF is applied to a fourth terminal 308. Specifically, the resistor network formed by resistors R1a, R1a_adj, R2a_adj, R2a, R1b, R1b_adj, R2b_adj, and R2b determines the gain of differential amplifier circuit system 300, where the gain is adjustable by trimming controller 320 using control signals Ctadj_a and Ctadj_b. In some examples, the gain of the differential amplifier circuitry 300 is expressed as: Wherein R1=R1a or R1b, R2=R2a or R2b, R2S is R2a_adj+R2a or R2b_adj+R2b, and R1S is R1a+R1a_adj or R1b or R2b_adj.

[0033] Trim controller 320 is configured to receive an input parameter IN_P at a first terminal 322, provide a control signal Ctadj_a at a second terminal 324 in response to the input parameter IN_P, and provide a control signal Ctadj_b at a third terminal 326 in response to the input parameter IN_P. In some examples, input parameter IN_P includes a user input that sets the gain to a target value. In some examples, the gain is proportional to ((VOUT - VREF) / (VINb - VINa)) = ((R2 + R2_adj) / (R1 + R1_adj)) = R2S / R1S. In some examples, Ctadj_a and Ctadj_b can be used for coarse trimming and / or fine trimming adjustments by trim controller 320.

[0034] The gain of differential amplifier circuitry 300 is adjustable using trim controller 320. In some examples, trim controller 320 is capable of both coarse and fine gain adjustment. Alternatively, operational amplifier 309 may include chopper circuitry, and trim controller 320 may include chopper control circuitry. In some examples, trim controller 320 includes control logic for selecting between different gain adjustment options and / or chopper options in response to user input and / or monitored parameters (e.g., input signal range, temperature, and / or other monitored parameters).

[0035] Figure 3B is a schematic diagram showing another differential amplifier circuit system 350. The differential amplifier circuit system 350 is Figure 1 The differential amplifier circuit system 130, Figure 2 The differential amplifier circuit system 230 or Figure 3A In some examples, the differential amplifier circuit system 350 may have Figure 7 The chopper amplifier architecture in the differential amplifier circuit system 700 is shown in FIG. Figure 3B In the example of , the differential amplifier circuit system 350 has Figure 3A The first terminal 302, the second terminal 304, the third terminal 306, the fourth terminal 308 and the fine-tuning controller 320 described in FIG. Figure 3B In the example of FIG, first terminal 302 is an "n" (-) terminal that receives Vinn, and second terminal 304 is a "p" (+) terminal that receives Vinp. In the illustrated arrangement, differential amplifier circuitry 350 further includes operational amplifier 309A, a first resistor network 332, and a second resistor network 336. More specifically, first resistor network 332 is between first terminal 302 and third terminal 306. Second resistor network 336 is between second terminal 304 and fourth terminal 308.

[0036] Trimming controller 320 has a first terminal 322, a second terminal 324, and a third terminal 326. Operational amplifier 309A has first (inverting or "-") terminals 310A and 310B, second (non-inverting or "+") terminals 312A and 312B, and a third terminal 314. First resistor network 332 has a control terminal 334 and includes series resistors, including resistor R1a, resistor R2a, and other resistors. Second resistor network 336 has a control terminal 338 and includes series resistors, including resistor R1b, resistor R2b, and other resistors. First resistor network 332 couples one of its series resistor terminals to respective first terminals 310A and 310B of differential amplifier 309A in response to Ctadj_a. Second resistor network 336 couples one of its series resistor terminals to respective second terminals 312A and 312B of differential amplifier 309A in response to Ctadj_b.

[0037] exist Figure 3B In the example of FIG, differential amplifier circuit system 350 is configured to receive a first input voltage Vinn at first terminal 302; receive a second input voltage Vinp at second terminal 304; and provide an output voltage VOUT at third terminal 306 in response to the operation of operational amplifier 309A, a resistor network formed by first resistor network 332 and second resistor network 336, and trimming controller 320. In some examples, a reference voltage VREF is applied at fourth terminal 308. First resistor network 332 and second resistor network 336 determine the gain of differential amplifier circuit system 350, where the gain can be adjusted by trimming controller 320 using control signals Ctadj_a and Ctadj_b. In some examples, the gain of differential amplifier circuit system 350 is expressed as:

[0038] In some examples, fine-tuning controller 320 is configured to: receive an input parameter IN_P at a first terminal 322; provide a control signal Ctadj_a at a second terminal 324 in response to the input parameter IN_P; and provide a control signal Ctadj_b at a third terminal 326 in response to the input parameter IN_P. In some examples, the input parameter IN_P includes user input that sets the gain to a target value. In some examples, Ctadj_a and Ctadj_b can be used for coarse and / or fine tuning adjustments by fine-tuning controller 320.

[0039] The gain of differential amplifier circuitry 300 is adjustable using trim controller 320. In some examples, trim controller 320 is capable of both coarse and fine gain adjustment. Alternatively, operational amplifier 309 may include chopper circuitry, and trim controller 320 may include chopper control circuitry. In some examples, trim controller 320 includes control logic for selecting between different gain adjustment options and / or chopper options in response to user input and / or monitored parameters (e.g., input signal range, temperature, and / or other monitored parameters).

[0040] Figure 4 is a block diagram illustrating an example differential amplifier circuitry 430. The differential amplifier circuitry 430 is Figure 1 The differential amplifier circuit system 130, Figure 2 The differential amplifier circuit system 230 in Figure 3A The differential amplifier circuit system 300 or Figure 3B An example of the differential amplifier circuit system 350 in FIG. Figure 4 In the example of FIG4 , differential amplifier circuitry 430 has a first terminal 432, a second terminal 434, and a third terminal 436. Differential amplifier circuitry 430 includes gain trimming circuitry 438. Gain trimming circuitry 438 includes a trimming controller 450, a resistor network 464, a first differential input transistor pair control circuitry 470, a second differential input transistor pair control circuitry 474, and a chopper control circuitry 478.

[0041] exist Figure 4 In the example of FIG. 4 , trim controller 450 has a first terminal 452, a second terminal 454, a third terminal 456, a fourth terminal 458, a fifth terminal 460, and a sixth terminal 462. Resistor network 464 has a first terminal 466 and a second terminal 468. First differential input transistor pair control circuitry 470 has a terminal 472. Second differential input transistor pair control circuitry 474 has a terminal 476. Chopper control circuitry 478 has a terminal 480.

[0042] exist Figure 4In the example of FIG4 , second terminal 454 of trim controller 450 is coupled to first terminal 466 of resistor network 464. Third terminal 456 of trim controller 450 is coupled to second terminal 468 of resistor network 464. Fourth terminal 458 of trim controller 450 is coupled to terminal 472 of first differential input transistor pair control circuitry 470. Fifth terminal 460 of trim controller 450 is coupled to terminal 476 of second differential input transistor pair control circuitry 474. Sixth terminal 462 of trim controller 450 is coupled to terminal 480 of chopper control circuitry 478.

[0043] exist Figure 4 In the example, the fine-tuning controller 450 is used to: receive an input parameter IN_P at a first terminal 452; provide a control signal CS3 at a second terminal 454 in response to the input parameter IN_P; provide a control signal CS4 at a third terminal 456 in response to the input parameter IN_P; provide a control signal CS5 at a fourth terminal 458 in response to the input parameter IN_P; provide a control signal CS6 at a fifth terminal 460 in response to the input parameter IN_P; and provide a control signal CS7 at a sixth terminal 462 in response to the input parameter IN_P.

[0044] In some examples, the resistor network 464 is configured to receive a control signal CS3 at a first terminal 466, receive a control signal CS4 at a second terminal 468, and select a resistor pair in response to the control signals CS3 and CS4. In some examples, the resistor network 464 selects the values of the resistors R1a_adj, R2a_adj, R1b_adj, and R2b_adj in response to the control signals CS3 and CS4. In some examples, CS3 includes the control signal Ctadj_a described herein, and CS4 includes the control signal Ctadj_b described herein.

[0045] In some examples, the first differential input transistor pair control circuitry 470 is configured to receive a control signal CS5 at a terminal 472 and select a differential input transistor pair in the first differential input transistor pair in response to the control signal CS5. In some examples, the first differential input transistor pair control circuitry 470 selects a coarse gain adjustment for the differential amplifier circuitry 430 in response to the control signal CS5.

[0046] In some examples, the second differential input transistor pair control circuitry 474 is configured to receive a control signal CS6 at a terminal 476 and select a differential input transistor pair in the second differential input transistor pair in response to the control signal CS6. In some examples, the second differential input transistor pair control circuitry 474 selects fine gain adjustment for the differential amplifier circuitry 430 in response to the control signal CS6.

[0047] In some examples, the chopper control circuit system 478 is configured to: receive a control signal CS7 at a terminal 480; and direct chopper operation in response to the control signal CS7. In some examples, the control signal CS7 includes a first clock signal (e.g., Φ herein) and a shift clock signal (e.g., Φ+90 herein). In some examples, the chopper control circuit system 478 can control the cross-coupling switches (e.g., Figure 7 , a first cross-coupling switch 702, a second cross-coupling switch 712, and a third cross-coupling switch 740) and a notch filter (eg, Figure 7 A notch filter 750 is included in the circuit to reduce offset voltage, temperature drift, and noise.

[0048] Figure 5 is a schematic diagram illustrating an example gain fine tuning circuit system 500. Figure 5 In the example of FIG. 5 , the gain trimming circuit system 500 includes a first resistor network 502A, a second resistor network 502B, a first switch network 504A, a second switch network 504B, a first differential input transistor pair A1 / A2 to O1 / O2, and current sources CSA to CSO in the arrangement shown. The first resistor network 502A is Figure 3A The resistors R1a_adj and R2a_adj in Figure 3A The first resistor network 332 or Figure 4 The second resistor network 502B is an example of a portion of the resistor network 464 in FIG. Figure 3A The resistors R1b_adj and R2b_adj in Figure 3B The second resistor network 336 or Figure 4 4. The first switch network 504A and the second switch network 504B are Figure 4 4. The first differential input transistor pair A1 / A2 to O1 / O2 and current sources CSA to CSO are example components of the gain trimming circuitry (e.g., Figure 1 Components of the gain fine-tuning circuit system 138 in Figure 2 Components of the gain fine-tuning circuit system 238 or Figure 4 In some examples, gain trim circuitry components, such as gain trim circuitry 500, may include adjustable resistor network components, different differential input transistor pair options, and / or chopper components.

[0049] exist Figure 5In the example of FIG, first resistor network 502A receives a control signal Ctadj_a and selects a particular resistor in the series resistor chain in response to the control signal Ctadj_a. Second resistor network 502B receives a control signal Ctadj_b and selects a particular resistor in the series resistor chain in response to the control signal Ctadj_b. In some examples, control signals Ctadj_a and Ctadj_b are used to select the same relative resistor position. Once control signal Ctadj_a selects a resistor in the series resistor chain of first resistor network 502A, the resistor above the selected resistor forms R2a_adj, and the resistor below the selected resistor forms R1a_adj. Similarly, once control signal Ctadj_b selects a resistor in the series resistor chain of second resistor network 502B, the resistor above the selected resistor forms R2b_adj, and the resistor below the selected resistor forms R1b_adj.

[0050] exist Figure 5 In the example of the first switch network 504A and the second switch network 504B receive Figure 4 In response to control signal CS5, first switch network 504A and second switch network 504B couple a set of first differential input transistor pairs A1 / A2 through O1 / O2 to selected resistor pairs of first resistor network 502A and second resistor network 502B. Once connected, the voltage across the selected resistors of first resistor network 502A is the difference between Vinn1 and Vinn0. Simultaneously, the voltage across the selected resistors of second resistor network 502B is the difference between Vinp1 and Vinp0.

[0051] In some examples, each transistor in transistor pairs A1 / A2 through O1 / O2 is the same size (e.g., the width / length ratio of each transistor is the same for transistors A1 to O1 and A2 to O2). Additionally, each of differential input transistor pairs A1 / A2 through O1 / O2 is coupled to a corresponding current source in current sources CSA to CSO. In some examples, each of current sources CSA to CSO provides the same current level. In different examples, the number of resistors in the first resistor network 502A and the second resistor network 502B can vary. Additionally, the number of differential input transistor pairs of the gain trimming circuitry 500 can vary.

[0052] exist Figure 5 In some examples, resistors R_adj (R1a_adj and R2a_adj or R1b_adj and R2b_adj in this article) are tapped into the differential amplifier. In some examples, control signals Ctadj_a and Ctadj_b are used to select a plurality of resistor taps (e.g., 64=26 In some examples, additional gain steps are provided between resistor tap steps. In response to Ctadj_a and Ctadj_b, two identical adjacent taps are performed to achieve the target gain value, rather than moving 1 tap across resistor R_adj. For the "p" (+) side, the adjacent taps produce Vinp0 and Vinp1. For the "n" (-) side, the adjacent taps produce Vinn0 and Vinn1. Figure 5 In this example, the differential input transistor pairs of the amplifier are split into multiple parallel transistor pair options. To provide more gain steps, one of the taps is connected to one set of differential input transistor pairs, while the other tap is connected to the remaining differential input transistor pairs. Figure 5 In the example of FIG5 , there are 15 differential input transistor pairs, where the switch from each differential input transistor pair is coupled to a tap connected to a resistor. In some examples, the switches of the first switch network 504A and the second switch network 504B operate like a "thermometer." For example, for the lowest thermometer gain code (e.g., CS5=15'b000 0000 0000 0000), all differential pairs are connected to the lower Vinn0 tap. At the next code (e.g., CS5=15'b000 0000 00000001), one differential input transistor pair is connected to the higher Vinn1 tap, while the remaining 14 differential input transistor pairs remain connected to Vinn0. At the next code (e.g., CS5=15'b000 0000 0000 0011), two differential input transistor pairs are connected to Vinn1, while the remaining 13 differential input transistor pairs are connected to the Vinn0 tap. As the control code increases, more differential input transistor pairs are connected to the Vinn1 tap (like a thermometer) and the number of differential input transistor pairs connected to the Vinn0 tap is reduced until the last code (e.g., CS5=15'b111 1111 1111 1111) where all differential input transistor pairs are connected to the Vinn1 tap. Figure 5 The topology provides 16 additional gain step options for each resistor tap step.

[0053] In some instances, a coarse gain step adjustment can be performed by sliding both the Vinn0 and Vinn1 resistor taps by 1 step and resetting all differential pair connections so that they are all connected to Vinn0. However, this will cause glitches during this conversion. To avoid such glitches, the Vinn1 tap is kept at the same point and the Vinn0 tap is moved up 2 steps on the Vinn1 tap while keeping all differential input transistor pairs connected to the Vinn1 tap. This is effective because the Vinn0 tap has no differential input transistor pairs connected, while the Vinn1 tap has all differential input transistor pairs connected. In some instances, the same resistor tap is performed simultaneously for both the first resistor network 502A and the second resistor network 502B to avoid glitches during the resistor tap movement. This adjustment technique allows for glitch-free resistor tap conversion because all differential input transistor pairs are connected to the Vinn1 (or Vinn0) tap, and the Vinn0 (or Vinn1) tap moves one tap beyond the Vinn1 (or Vinn0) tap. When moving downward, a similar tap sliding technique is performed by moving the outer taps downward by 2 positions while keeping all differential input transistor pairs connected to the middle tap.

[0054] In some examples, combining the 16 differential input transistor pair options with the 64 gain steps of the resistor taps yields 64 x 16 = 1024 gain steps or codes. Using coarse trimming circuitry, the differential amplifier gain can cover a wider gain range with larger gain steps. For increased precision (e.g., 14-bit gain trimming), the differential amplifier circuitry can include fine gain trimming circuitry, which provides fine gain steps to reduce step size.

[0055] Figure 6 is a schematic diagram showing another example gain fine-tuning circuit system 600. Figure 6 In the example of FIG. 5 , the gain trimming circuit system 600 includes a first resistor network 502A, a second resistor network 502B, a third switch network 602A, a fourth switch network 602B, a second differential input transistor pair P1 / P2 to T1 / T2, and a current source CSP in the arrangement shown. The first resistor network 502A is Figure 3A The resistors R1a_adj and R2a_adj in Figure 3B The first resistor network 332 or Figure 4 The second resistor network 502B is an example of a portion of the resistor network 464 in FIG. Figure 3A The resistors R1b_adj and R2b_adj, the second resistor network 336 or Figure 4 The third switch network 602A and the fourth switch network 602B are examples of portions of the resistor network 464 in FIG. Figure 4 4. The second differential input transistor pair P1 / P2 to T1 / T2 and the current source CSP are example components of the gain trimming circuitry (e.g., Figure 1 Components of the gain fine-tuning circuit system 138 in Figure 2 Components of the gain fine-tuning circuit system 238 or Figure 4 In some examples, gain trim circuitry components, such as gain trim circuitry 600, may include adjustable resistor network components, different differential input transistor pair options, and / or chopper components.

[0056] exist Figure 6 In the example of FIG, first resistor network 502A receives control signal Ctadj_a and selects a particular resistor in the series resistor chain in response to control signal Ctadj_a. Second resistor network 502B receives control signal Ctadj_a and selects a particular resistor in the series resistor chain in response to control signal Ctadj_a. In some examples, control signals Ctadj_a and Ctadj_b are used to select the same relative resistor position. Once control signal Ctadj_a selects a resistor in the series resistor chain of first resistor network 502A, the resistor above the selected resistor forms R2a_adj, and the resistor below the selected resistor forms R1a_adj. Similarly, once control signal Ctadj_b selects a resistor in the series resistor chain of second resistor network 502B, the resistor above the selected resistor forms R2b_adj, and the resistor below the selected resistor forms R1b_adj.

[0057] exist Figure 6 In the example, the third switch network 602A and the fourth switch network 602B receive Figure 4 In response to the control signal CS6 described in the preceding text, the third switch network 602A and the fourth switch network 602B couple one of the second differential input transistor pairs P1 / P2 to T1 / T2 to the selected resistor pair in the first resistor network 502A and the second resistor network 502B. Once connected, the voltage across the selected resistor of the first resistor network 502A is the difference between Vinn1 and Vinn0. At the same time, the voltage across the selected resistor of the second resistor network 502B is the difference between Vinp1 and Vinp0. In some examples, each of the differential input transistor pairs P1 / P2 to T1 / T2 is a different size. Figure 6 In the example of , the size of each transistor in the differential input transistor pair P1 / P2 is Figure 5The size of each transistor in the differential input transistor pair A1 / A2 to O1 / O2 is 1 / 2. The size of each transistor in the differential input transistor pair Q1 / Q2 is Figure 5 The size of each transistor in the differential input transistor pair A1 / A2 to O1 / O2 is 1 / 4 of the size of each transistor in the differential input transistor pair R1 / R2. The size of each transistor in the differential input transistor pair S1 / S2 is 1 / 16 of the size of each transistor in the differential input transistor pair A1 / A2 to O1 / O2. The size of each transistor in the differential input transistor pair T1 / T2 is Figure 5 The gain adjustment circuitry 600 is configured to have a current source CSP that is 1 / 16 the size of each transistor in the differential input transistor pairs A1 / A2 through O1 / O2. In some examples, the current source CSP is shared by all differential input transistor pairs P1 / P2 through T1 / T2. In some examples, the number of differential input transistor pairs in the gain adjustment circuitry 600 can vary. In some examples, the gain adjustment circuitry 600 provides fine adjustment circuitry for a differential amplifier, where each of the differential input transistor pairs provides another fine adjustment option.

[0058] exist Figure 6 In some examples, five additional differential input transistor pairs are used to interpolate 16 additional gain fine-tuning steps. In some examples, the drains of the five additional differential input transistor pairs are connected to the same Figure 5 The coarse gain differential input transistor pair is connected to the same node as the coarse gain differential input transistor pair. In some examples, the fine gain differential input transistor pair shares the same current as the differential input transistor pair with corresponding W / L ratios to provide differential input transistor pair weights of 1 / 2, 1 / 4, 1 / 8, 1 / 16, and 1 / 16 of the coarse gain differential input transistor pair. In some examples, the sum of these W / L ratios is equal to the W / L ratio of the coarse gain differential input transistor pair. In some examples, Figure 6The control terminals of the differential input transistor pairs in are connected to the top tap (Vinn1 or Vinp1) and the bottom tap (Vinn0 or Vinp0) based on a selective binary counting system that produces equal gain steps between codes while minimizing glitches during code transitions. In some instances, the lowest selective binary code will be 5'd1 (e.g., CS6=00001), which results in the Vinn1 tap being connected to the T1 / T2 differential input transistor pair and resulting in a W / L weight of 1 / 16 that of the coarse differential input transistor pair. Simultaneously, the Vinn0 tap is connected to the S1 / S2, R1 / R2, Q1, Q2, and P1 / P2 differential input transistor pairs and resulting in a W / L weight of 15 / 16 that of the coarse differential input transistor pair. The next code is 5'd3 (e.g., CS6=00011), where A0 and A1 are connected to Vin1 and result in a weight of 2 / 16 of the coarse differential input transistor pair, resulting in Vin0 weighted at 14 / 16. The next code is 5'd5 (e.g., CS6=00101), resulting in the Vin1 tap being weighted at 3 / 16 of the coarse differential input transistor pair, and the Vin0 tap being weighted at 13 / 16 of the coarse differential input transistor pair.

[0059] In some examples, the selective binary code options include codes for 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 27, and 31. At code 5'd31 (e.g., CS6 = 11111), the Vinn0 tap has a weight of 0, and the Vinn1 tap is connected to all five differential input transistor pairs P1 / P2 to T1 / T2, resulting in a weight of 16 / 16, or 1, for the coarse differential input transistor pairs. Therefore, in some examples, each gain code increase in the fine gain trim adjustment increases the W / L weight by 1 / 16 relative to the coarse gain trim adjustment. In some examples, glitches can be prevented during the fine gain trim adjustment when sliding the resistor taps by moving the lower tap up by 2 steps and keeping the upper tap in the same position. To continue to achieve the same 1 / 16 W / L weight increment, the coarse gain trim step size can be decreased as the gain code increases. Similarly, the selective binary code can be decremented to avoid glitches. To obtain a weight change of 1 / 16 W / L at the resistor tap transition point, the selective binary code is changed from 5'31 (e.g., CS6 = 5'b11111) to 5'd30 (e.g., CS6 = 5'b11110). When counting down, the selective binary code options include 30, 28, 26, 24, 22, 20, 18, 16, 14, 12, 10, 8, 6, 4, 2, and 0. In some examples, the resistor tap position options, coarse gain trim control options, and fine gain trim control options are presented in Table 1.

[0060] Table 1

[0061]

[0062]

[0063] In the example of Table 1, 16,384 gain steps (e.g., the first column of Table 1) and associated gain codes are presented. Each gain step includes a resistor tap code (RTC) (the second column of Table 1), a first fine-tuning code (e.g., the third column of Table 1), and a second fine-tuning code (e.g., the fourth column of Table 1), where the first fine-tuning code is a coarse fine-tuning code and the second fine-tuning code is a fine fine-tuning code. Table 1 also shows the Vin0 tap position due to each resistor tap code (e.g., the fifth column of Table 1), the Vin0 tap weight due to each first fine-tuning code (e.g., the sixth column of Table 1), the Vin0 tap weight due to each second fine-tuning code (e.g., the seventh column of Table 1), and the total Vin0 tap weight due to the first and second fine-tuning codes (e.g., the eighth column of Table 1). Table 1 also shows the Vin1 tap position due to each resistor tap code (e.g., the ninth column in Table 1), the Vin1 tap weight due to each first trim code (e.g., the tenth column in Table 1), the Vin1 tap weight due to each second trim code (e.g., the eleventh column in Table 1), and the total Vin1 tap weight due to the first and second trim codes (e.g., the twelfth column in Table 1). Using the gain trimming technique associated with Table 1, a wide gain range and fine resolution are achieved. In the example of Table 1, there are 64 resistor tap options (representing a 6-bit gain trim option), 16 first trim code options (representing a 4-bit gain trim option), and 16 second trim code options (representing a 4-bit gain trim option), resulting in 64 x 16 x 16 = 16,384 gain steps or 14 bits of gain adjustment resolution. In other examples, the number of gain steps and / or gain adjustment resolution may vary.

[0064] Figure 7 is a diagram illustrating an example differential amplifier circuit system 700. Figure 7In the example of FIG, the differential amplifier circuit system 700 is a chopper amplifier. As shown in the figure, the differential amplifier circuit system 700 includes a first resistor network 502A, a second resistor network 502B, a first cross-coupling switch 702, a second cross-coupling switch 712, a first gain stage 722, a third cross-coupling switch 740, a notch filter 750, a second gain stage 760, a feedforward gain stage 780, a third gain stage 792, and capacitors C1 to C4 in the illustrated arrangement. Each of the capacitors C1 to C4 has a corresponding first terminal and a corresponding second terminal. The first cross-coupling switch 702 has a first terminal 704, a second terminal 706, a third terminal 708, a fourth terminal 710, and a fifth terminal 711. The second cross-coupling switch 712 has a first terminal 714, a second terminal 716, a third terminal 718, a fourth terminal 720, and a fifth terminal 721. The first gain stage 722 has a first terminal 724, a second terminal 726, a third terminal 728, a fourth terminal 730, a fifth terminal 732, a sixth terminal 734, and a seventh terminal 736. The first gain stage 722 includes a fine gain adjustment circuitry 738. In some examples, the fine gain adjustment circuitry 738 includes a coarse gain adjustment circuitry (e.g., Figure 5 5) and a fine gain adjustment circuit system (e.g., Figure 6 600 in the gain fine-tuning circuit system).

[0065] The third cross-coupling switch 740 has a first terminal 742, a second terminal 744, a third terminal 746, a fourth terminal 748, and a fifth terminal 749. The notch filter 750 has a first terminal 752, a second terminal 754, a third terminal 756, a fourth terminal 758, and a fifth terminal 759. The second gain stage 760 has a first terminal 762, a second terminal 764, a third terminal 766, and a fourth terminal 768. The third gain stage 792 has a first terminal 794, a second terminal 796, and a third terminal 798. The feed-forward gain stage 780 has a first terminal 781, a second terminal 782, a third terminal 783, a fourth terminal 784, a fifth terminal 785, a sixth terminal 786, and a seventh terminal 787. The feed-forward gain stage 780 includes gain fine adjustment circuitry 788. The control logic 790 has a first terminal 791A, a second terminal 791B, a third terminal 791C, and a fourth terminal 791D.

[0066] A first terminal 704 of the first cross-coupling switch 702 is coupled to the first resistor network 502A and receives Vinn1. A second terminal 706 of the first cross-coupling switch 702 is coupled to the second resistor network 502B and receives Vinp1. A third terminal 708 of the first cross-coupling switch 702 is coupled to a first terminal 724 of the first gain stage 722. A fourth terminal 710 of the first cross-coupling switch 702 is coupled to a second terminal 726 of the first gain stage 722. A fifth terminal 711 of the first cross-coupling switch 702 is coupled to a third terminal 791C of the control logic 790.

[0067] A first terminal 714 of the second cross-coupling switch 712 is coupled to the first resistor network 502A and receives Vinn0. A second terminal 716 of the second cross-coupling switch 712 is coupled to the second resistor network 502B and receives Vinp0. A third terminal 718 of the second cross-coupling switch 712 is coupled to a third terminal 728 of the first gain stage 722. A fourth terminal 720 of the second cross-coupling switch 712 is coupled to a fourth terminal 730 of the first gain stage 722. A fifth terminal 721 of the second cross-coupling switch 712 is coupled to a third terminal 791C of the control logic 790. A fifth terminal 732 of the first gain stage 722 is coupled to a first terminal 742 of the third cross-coupling switch 740. A sixth terminal 734 of the first gain stage 722 is coupled to a second terminal 744 of the third cross-coupling switch 740. A seventh terminal 736 of the first gain stage 722 is coupled to a first terminal 791A of the control logic 790. A third terminal 746 of the third cross-coupling switch 740 is coupled to a first terminal 752 of the notch filter 750 and a first terminal of the capacitor C1. A fourth terminal 748 of the third cross-coupling switch 740 is coupled to a second terminal 754 of the notch filter 750. A fifth terminal 749 of the third cross-coupling switch 740 is coupled to a third terminal 791C of the control logic 790.

[0068] A third terminal 756 of notch filter 750 is coupled to a first terminal 762 of second gain stage 760 and a first terminal of capacitor C2. A fourth terminal 758 of notch filter 750 is coupled to a second terminal 764 of second gain stage 760. A fifth terminal 759 of notch filter 750 is coupled to a fourth terminal 791D of control logic 790.

[0069] A first terminal 781 of the feed-forward gain stage 780 is coupled to the first resistor network 502A and receives Vinn1. A second terminal 782 of the feed-forward gain stage 780 is coupled to the second resistor network 502B and receives Vinp1. A third terminal 783 of the feed-forward gain stage 780 is coupled to the first resistor network 502A and receives Vinn0. A fourth terminal 784 of the feed-forward gain stage 780 is coupled to the second resistor network 502B and receives Vinp0. A fifth terminal 785 of the feed-forward gain stage 780 and the third terminal 766 of the second gain stage are coupled to a first terminal 794 of the third gain stage 792 and a first terminal of capacitor C3. A sixth terminal 786 of the feed-forward gain stage 780 and a fourth terminal 768 of the second gain stage 760 are coupled to a second terminal 796 of the third gain stage 792 and a first terminal of capacitor C4. A seventh terminal 787 of the feed-forward gain stage 780 is coupled to a first terminal 791A of the control logic 790. A second terminal 791B of the control logic 790 is coupled to the first and second resistor networks 502A and 502B. Second terminals of the capacitors C1 through C4 are coupled to a third terminal 798 of the third gain stage 792.

[0070] In some examples, differential amplifier circuitry 700 is configured to adjust Vinn1, Vinn0, Vinp1, and Vinp0 in response to control signals Ctadj_a and Ctadj_b, and to provide VOUT in response to a user- or system-applied VREF-set gain. In some examples, the gain is expressed as: Gain = ((VOUT - VREF) / (VINb - VINa)) = ((R2 + R2_adj) / (R1 + R1_adj)) = R2S / R1S. The operation of first cross-coupling switch 702, second cross-coupling switch 712, first gain stage 722, third cross-coupling switch 740, notch filter 750, second gain stage 760, feedforward gain stage 780, third gain stage 792, control logic 790, and capacitors C1 through C4 is configured to provide target gain accuracy while mitigating offset, offset temperature drift, and noise.

[0071] More specifically, first resistor network 502A is configured to adjust Vinn1 and Vinn0 in response to control signal Ctadj_a. Second resistor network 502B is configured to adjust Vinp1 and Vinp0 in response to control signal Ctadj_b. Control signals Ctadj_a and Ctadj_b are configured to select the same relative resistor positions. Once control signal Ctadj_a selects a resistor in the series resistor chain of first resistor network 502A, the resistor above the selected resistor forms R2a_adj, and the resistor below the selected resistor forms R1a_adj. Similarly, once control signal Ctadj_b selects a resistor in the series resistor chain of second resistor network 502B, the resistor above the selected resistor forms R2b_adj, and the resistor below the selected resistor forms R1b_adj.

[0072] The first cross-coupled switch 702 is configured to receive Vinn1 at a first terminal 704, receive Vinp1 at a second terminal 706, receive Φ at a fifth terminal 711, provide ainn1 at a third terminal 708 in response to Vinn1, Vinp1, and Φ, and provide ainp1 at a fourth terminal 710 in response to Vinn1, Vinp1, and Φ. When Φ is asserted, ainn1 = Vinn1 and ainp1 = Vinp1. When Φ is deasserted, ainn1 = Vinp1 and ainp1 = Vinn1.

[0073] The second cross-coupled switch 712 is configured to receive Vinn0 at a first terminal 714, receive Vinp0 at a second terminal 716, receive Φ at a fifth terminal 721, provide ainn0 at a third terminal 718 in response to Vinn0, Vinp0, and Φ, and provide ainp0 at a fourth terminal 720 in response to Vinn0, Vinp0, and Φ. When Φ is asserted, ainn0 = Vinn0 and ainp0 = Vinp0. When Φ is deasserted, ainn0 = Vinp0 and ainp0 = Vinn0.

[0074] The first gain stage 722 is used to: receive ainn1 at the first terminal 724; receive ainp1 at the second terminal 726; receive ainn0 at the third terminal 728; receive ainp0 at the fourth terminal 730; receive CS5 and CS6 at the seventh terminal 736; provide an output signal aoutn at the fifth terminal 732 in response to the operation of ainn1, ainn0, CS5, CS6 and the gain fine-tuning circuit system 738; and provide an output signal aoutp at the sixth terminal 734 in response to the operation of ainp1, ainp0, CS5, CS6 and the gain fine-tuning circuit system 738.

[0075] The third cross-coupled switch 740 is configured to receive aoutn at a first terminal 742, aoutp at a second terminal 744, Φ at a fifth terminal 749, provide a first output signal at a third terminal 746 in response to aoutp, aoutn, and Φ, and provide a second output signal at a fourth terminal 748 in response to aoutp, aoutn, and Φ. When Φ is asserted, the first output signal is equal to aoutn and the second output signal is equal to aoutp. When Φ is deasserted, the first output signal is equal to aoutp and the second output signal is equal to aoutn.

[0076] The notch filter 750 is configured to receive a first input signal from the third cross-coupled switch 740 at a first terminal 752, a second input signal from the third cross-coupled switch 740 at a second terminal 754, a clock Φ+90 at a fifth terminal 759, and provide a first filtered output at a third terminal 756 in response to the first and second input signals and the clock Φ+90, and provide a second filtered output at a fourth terminal 758 in response to the first and second input signals and the clock Φ+90. In summary, the notch filter 750 receives a differential input signal and provides a filtered differential output signal that reduces ripple in the signal.

[0077] The second gain stage 760 is configured to receive the first filtered output at a first terminal 762, receive the second filtered output at a second terminal 764, provide a first amplified output at a third terminal 766 in response to the first and second filtered differential outputs from the notch filter, and provide a second amplified output at a fourth terminal 768 in response to the first and second filtered differential outputs from the notch filter. The second gain stage 760 receives a differential input and provides an amplified differential output based on the differential input.

[0078] The feedforward gain stage 780 is used to: receive vinn1 at the first terminal 781; receive vinp1 at the second terminal 782; receive vinn0 at the third terminal 783; receive vinp0 at the fourth terminal 784; receive CS5 and CS6 at the seventh terminal 787; provide an output signal ffoutn at the fifth terminal 785 in response to the operation of vinn1, vinn0, CS5, CS6 and the gain fine-tuning circuit system 788; and provide an output signal ffoutp at the sixth terminal 786 in response to the operation of vinp1, vinp0, CS5, CS6 and the gain fine-tuning circuit system 788.

[0079] The third gain stage is configured to receive the first amplified output and the output signal ffoutn at the first terminal 794, receive the second amplified output and the output signal ffoutp at the second terminal 796, and provide VOUT in response to the first amplified output, the second amplified output, the output signal ffoutn, and the output signal ffoutp. Figure 7 In the example shown in Figure 1, capacitors C1 through C4 are used to compensate for the chopper amplifier operation. This compensation limits the bandwidth of the op amp to improve stability.

[0080] Using the gain trimming circuitry 738, the gain trimming circuitry 788, and the chopper components (e.g., the first cross-coupled switch 702, the second cross-coupled switch 712, the third cross-coupled switch 740, the notch filter 750, and the feed-forward gain stage 780), the differential amplifier circuitry 700 provides a coarse gain trimming option, a fine gain trimming option, improved accuracy and reduced offset, reduced offset temperature drift, and reduced noise.

[0081] Because the differential amplifier has an inherent offset due to transistor mismatch, the use of Figure 7 The chopper amplifier architecture shown (e.g., with an inline switched capacitor notch filter and a parallel feed-forward path) can reduce the offset. Using the chopper amplifier architecture, the differential inputs (Vinn and Vinp) are swapped every clock cycle. Figure 7 In the example of , the Vinn1 / Vinp1 terminals and the Vinn0 / Vinp0 terminals are swapped to the first gain stage 722 in the DC high gain path using the first cross-coupling switch 702 and the second cross-coupling switch 712 clock phase Φ. The output of the first gain stage 722 is also swapped (chopped) using the third cross-coupling switch 740 to maintain the polarity of the first gain stage. The notch filter 750 is connected at the output terminal of the first gain stage after the third cross-coupling switch 740 and is chopped using the clock phase Φ+90 to eliminate the ripple caused by the chopping. The second gain stage 760 is used to increase the gain of the DC path and further reduce the offset with the unchopped feedforward gain stage 780. In some examples, the first gain stage 722 and the feedforward gain stage 780 use a differential input transistor pair ( Figure 5 and 6 The third gain stage 792 is the output stage of the differential amplifier circuit system 700. Figure 7 In the example, gain adjustment is achieved using a combination of resistor tap selection, coarse gain trim selection, and fine gain trim selection integrated into the chopper amplifier. Figure 7In this example, gain adjustment may be possible over a wide range with high resolution, reducing gain error while also minimizing amplifier offset error, offset temperature drift, and reducing noise.

[0082] Figure 8 FIG. 8 is a flow chart illustrating an example gain fine-tuning control method 800. The gain fine-tuning control method 800 may be performed by Figure 1 The control logic of the gain fine-tuning circuit system 138, Figure 2 The control logic of the gain fine-tuning circuit system 238, Figure 3A and 3B Fine-tuning controller 320, Figure 4 Fine-tuning controller 450 or Figure 7 800 is performed by the control logic 790 in . As shown, the gain trim control method 800 includes receiving a control input at box 802. At box 804, a gain setting is determined based on the control input. At box 806, the setting of the coarse gain trim circuit system is adjusted in response to the gain setting. At box 808, the setting of the fine gain trim circuit system is adjusted in response to the gain setting. In some instances, the operation of box 808 may perform the operation of box 806. As another option, the operations of boxes 806 and 808 may be performed together or simultaneously. In some instances, the control input includes user input and / or gain settings based on programmed or monitored parameters (e.g., input signal range, temperature and / or other monitored parameters). In some instances, the differential amplifier circuit system is initially programmed based on a room temperature-based code to set the device to have a predetermined gain (e.g., 50) at room temperature (~30C). In some examples, the gain trim control method 800 can include selecting a particular resistor tap code, selecting a thermometer code for coarse gain trim adjustment, and selecting a binary code for fine gain trim adjustment. In some examples, the resistor tap code, thermometer code, and binary code are converted into corresponding switch control signals. In some examples, the gain trim operation is implemented to minimize disturbances at the output of the differential amplifier circuitry. Additionally, the gain trim operation is monotonic (each code has a defined output gain, and no two codes give the same gain).

[0083] In some examples, an integrated circuit includes differential amplifier circuitry (e.g., Figure 1 The differential amplifier circuit system 130 in Figure 2 The differential amplifier circuit system 230, Figure 3A The differential amplifier circuit system 300, Figure 3B The differential amplifier circuit system 350, Figure 4 The differential amplifier circuit system 430 or Figure 7The differential amplifier circuit system 700 in FIG. 1 includes a first gain fine-tuning circuit system (eg, Figure 4 The first input transistor pair in the control circuitry 470, or Figure 5 a first switch network 504A and a second switch network 504B in the circuit); and a second gain fine-tuning circuit system (eg, Figure 4 The second input transistor pair in the control circuitry 474, or Figure 5 The first gain trim circuit system has a first gain trim input (eg, Figure 4 Terminal 472 in, or Figure 5 ), and includes a first differential input transistor pair (e.g., Figure 5 One of the differential input transistor pairs A1 / A2 to O1 / O2 in FIG) and a second differential input transistor pair (eg, Figure 5 The second gain trim circuit system has a second gain trim input (e.g., Figure 4 Terminal 476 in, or Figure 6 ), and includes a third differential input transistor pair (e.g., Figure 6 One of the differential input transistor pairs P1 / P2 to T1 / T2 in FIG) and a fourth differential input transistor pair (eg, Figure 6 The differential amplifier circuitry also includes control logic (e.g., Figure 3A and 3B The fine-tuning controller 320 in Figure 4 Fine-tuning controller 450 or Figure 7 ), which has a first gain trim output (e.g., Figure 3A and 3B The second terminal 324, Figure 4 The fourth terminal 458, Figure 7 one of the first terminals 791A in the first embodiment) and a second gain trim output (e.g., Figure 3A and 3B The third terminal 326, Figure 4 The fifth terminal 460, Figure 7 The first gain trim output is coupled to the first gain trim input. The second gain trim output is coupled to the second gain trim input.

[0084] In some examples, each transistor in the first and second differential input transistor pairs has the same W / L ratio. In some examples, the differential amplifier circuitry includes a first current source (eg, Figure 5 one of the current sources CSA to CSO in the circuit) and a second current source (e.g., Figure 5 In such an example, a first current source is coupled to the first differential input transistor pair, a second current source is coupled to the second differential input transistor pair, and the first and second current sources are configured to provide the same current level.

[0085] In some examples, each transistor in the third differential input transistor pair has a first W / L ratio, and each transistor in the fourth differential input transistor pair has a second W / L ratio that is less than the first W / L ratio. In some examples, the differential amplifier circuitry includes a current source (e.g., Figure 6 The current source CSP in the

[0086] In some examples, the differential amplifier circuitry includes a resistor network (eg, Figure 3A Resistors in Figure 3B The first resistor network 332 and the second resistor network 336, Figure 4 The resistor network in 464, Figures 5 to 7 The first gain adjustment circuitry includes a first selection circuitry (eg, a first resistor network 502A and a second resistor network 502B) coupled between the resistor network and the first and second differential input transistor pairs. Figure 5 The second gain fine-tuning circuitry includes a second selection circuitry (eg, a first switching network 504A and a second switching network 504B) coupled between the resistor network and the third and fourth differential input transistor pairs. Figure 6 The first selection circuit system has a first control input (e.g., Figure 4 Terminal 472 in, or Figure 5 The second selection circuit system has a second control input (e.g., Figure 4 Terminal 476 in, or Figure 6 The first gain trim output is coupled to the first control input. The second gain trim output is coupled to the second control input.

[0087] In some examples, the differential amplifier circuitry includes a first gain stage (eg, Figure 7 ), cross-coupling switches before and after the first gain stage (e.g., Figure 7 , a first cross-coupling switch 702, a second cross-coupling switch 712, and a third cross-coupling switch 740) and a feed-forward gain stage (eg, Figure 7 The first gain stage includes a first gain fine-tuning circuit system and a second gain fine-tuning circuit system (e.g., Figure 7 The feedforward gain stage includes a third gain fine-tuning circuit system and a fourth gain fine-tuning circuit system (e.g., a first gain fine-tuning circuit system represented by the gain fine-tuning circuit system 738 in FIG. 1 ). Figure 7 788 in FIG. 1 ). The third gain trim circuitry has a third gain trim input (e.g., the same topology as described for the first gain trim circuitry). The fourth gain trim circuitry has a fourth gain trim input (e.g., the same topology as the second gain trim circuitry). The control logic has a third gain trim output and a fourth gain trim output (e.g., Figure 7 The third gain adjustment output is coupled to the third gain adjustment input. The fourth gain adjustment output is coupled to the fourth gain adjustment input.

[0088] In some examples, the first gain stage includes a first input terminal (eg, Figure 7 The first terminal 724 and the second terminal 726 in the second input terminal (eg, Figure 7 The cross-coupled switch includes a first output terminal (e.g., a third terminal 728 and a fourth terminal 730 in FIG. 1 ), and a first output terminal (e.g., a fifth terminal 732 and a sixth terminal 734). Figure 7 A first cross-coupled switch (eg, a third terminal 708 and a fourth terminal 710 in FIG. 1 ) Figure 7 , a first cross-coupled switch 702 in the embodiment of the present invention, and a third output terminal (eg, Figure 7 A second cross-coupled switch (eg, a third terminal 718 and a fourth terminal 720 in FIG. 1 ) Figure 7 ), and a second cross-coupled switch 712 in a circuit having a third input terminal (e.g., Figure 7 A third cross-coupled switch (eg, a first terminal 742 and a second terminal 744 in FIG. 1 ) Figure 7 7. In this example, the second output terminal of the first cross-coupling switch is coupled to the first input terminal of the first gain stage. The third output terminal of the second cross-coupling switch is coupled to the second input terminal of the first gain stage. The third input terminal of the third cross-coupling switch is coupled to the first output terminal of the first gain stage.

[0089] In some examples, the differential amplifier circuitry includes a notch filter (e.g., Figure 7 Notch filter 750 in the second gain stage (eg, Figure 7760) and a third gain stage (e.g., Figure 7 792 in the feedforward gain stage). In such an example, the notch filter is configured to filter the output signal from the third cross-coupled switch to produce a filtered signal. The second gain stage is configured to apply a gain to the filtered signal to produce an adjusted filtered result. The third gain stage is configured to apply a gain to a combination of the adjusted filtered result and the output of the feedforward gain stage.

[0090] In some examples, the control logic is configured to: obtain a first digital code (e.g., the first fine-tuning code in Table 1); obtain a second digital code (e.g., the second fine-tuning code in Table 1); generate a first control signal (e.g., control signal CS5 herein) at a first gain fine-tuning output in response to the first digital code; and generate a second control signal (e.g., control signal CS6 herein) at a second gain fine-tuning output in response to the second digital code.

[0091] In some examples, the differential amplifier circuitry (eg, Figure 1 The differential amplifier circuit system 130, Figure 2 The differential amplifier circuit system 230 in Figure 3A The differential amplifier circuit system 300, Figure 3B The differential amplifier circuit system 350, Figure 4 The differential amplifier circuit system 430 or Figure 7 The differential amplifier circuit system 700 in FIG. 7 includes: a first differential input transistor pair (eg, Figure 5 differential input transistor pairs A1 / A2 to O1 / O2); a second differential input transistor pair (e.g., Figure 6 The differential input transistor pair P1 / P2 to T1 / T2 in the resistor network (e.g. Figure 3A Resistors in Figure 3B The first resistor network 332 and the second resistor network 336, Figure 4 The resistor network in 464, Figures 5 to 7 The first resistor network 502A and the second resistor network 502B in the embodiment of the present invention); the first selection circuit system (for example, Figure 4 The first input transistor pair in the control circuitry 470, or Figure 5 , wherein the first switch network 504A and the second switch network 504B have a first control input (eg, Figure 4 Terminal 472 in, or Figure 5 The first selection circuit system is coupled between the resistor network and the first differential input transistor pair. The differential amplifier circuit system further includes a second selection circuit system (e.g., Figure 4The second input transistor pair control circuit system 474 in the embodiment of the present invention has a second control input (e.g., Figure 4 Terminal 476 in, or Figure 6 The second selection circuit system is coupled between the resistor network and the second differential input transistor pair. The differential amplifier circuit system also includes control logic (e.g., Figure 3A and 3B Fine-tuning controller 320, Figure 4 Fine-tuning controller 450 or Figure 7 The control logic 790 in FIG. 1 has a first gain trim output (eg, Figure 3A and 3B The second terminal 324, Figure 4 The fourth terminal 458, or Figure 7 one of the first terminals 791A in the first embodiment) and a second gain trim output (e.g., Figure 3A and 3B The third terminal 326, Figure 4 The fifth terminal 460, or Figure 7 The first gain trim output is coupled to the first control input. The second gain trim output is coupled to the second control input.

[0092] In some examples, the differential amplifier circuitry includes a respective current source coupled to each of the first differential input transistor pairs (eg, Figure 5 In such an example, each of the first differential input transistor pairs includes transistors having the same W / L ratio, and each corresponding current source is configured to provide the same current level.

[0093] In some examples, the differential amplifier circuitry includes a current source (eg, Figure 6 In such an example, each of the second differential input transistor pairs includes transistors having a different W / L ratio.

[0094] In some examples, the first differential input transistor pair, the second differential input transistor pair, the resistor network, the first selection circuitry, and the second selection circuitry are a first gain stage (eg, Figure 7 , the resistor network is a first resistor network, and the differential amplifier circuitry further includes a feedforward gain stage (eg, Figure 7 , which comprises a third differential input transistor pair (e.g., having Figure 51 / A2 to O1 / O2 in the topology); a fourth differential input transistor pair (e.g., having Figure 6 an additional differential input transistor pair of the same topology as the differential input transistor pair P1 / P2 to T1 / T2 in FIG; a second resistor network (e.g., having Figure 3A 、 3B and an additional resistor network of the same topology as the resistor or resistor network in 5 to 7); and a third selection circuit system (e.g., Figure 4 another first input transistor pair in the control circuitry 470, or Figure 5 The third selection circuitry has a third control input (e.g., Figure 4 The other terminal 472, or Figure 5 The third selection circuit system is coupled between the second resistor network and the third differential input transistor pair. The feedforward gain stage further includes a fourth selection circuit system (e.g., Figure 4 another second input transistor pair in the control circuitry 474, or Figure 6 The fourth selection circuitry has a fourth control input (e.g., an additional third switch network 602A and a fourth switch network 602B) coupled to the second gain trim output. Figure 4 The other terminal 476, or Figure 5 The fourth selection circuit system is coupled between the second resistor network and the fourth differential input transistor pair.

[0095] In some examples, the first gain stage includes a first input terminal (eg, Figure 7 The first terminal 724 and the second terminal 726 in the second input terminal (eg, Figure 7 In such an example, the differential amplifier circuit system includes a first output terminal (e.g., a third terminal 728 and a fourth terminal 730 in FIG. 1 ) and a first output terminal (e.g., a fifth terminal 732 and a sixth terminal 734). Figure 7 A first cross-coupled switch (eg, a third terminal 708 and a fourth terminal 710 in FIG. 1 ) Figure 7 , a first cross-coupled switch 702 in the embodiment of the present invention, and a third output terminal (eg, Figure 7 A second cross-coupled switch (eg, a third terminal 718 and a fourth terminal 720 in FIG. 1 ) Figure 7 ), and a second cross-coupled switch 712 in a circuit having a third input terminal (e.g., Figure 7 A third cross-coupled switch (eg, a first terminal 742 and a second terminal 744 in FIG. 1 ) Figure 7 740 in the differential amplifier circuitry. In such an example, the second output terminal of the first cross-coupling switch can be coupled to the first input terminal of the first gain stage. The third output terminal of the second cross-coupling switch can be coupled to the second input terminal of the first gain stage. The third input terminal of the third cross-coupling switch can be coupled to the first output terminal of the first gain stage. In some examples, the differential amplifier circuitry further includes a notch filter (e.g., Figure 7 Notch filter 750 in the second gain stage (eg, Figure 7 760) and a third gain stage (e.g., Figure 7 792 in the feedforward gain stage). In such an example, the notch filter is configured to filter the output signal from the third cross-coupled switch to produce a filtered signal. The second gain stage is configured to apply a gain to the filtered signal to produce an adjusted filtered result. The third gain stage is configured to apply a gain to a combination of the adjusted filtered result and the output of the feedforward gain stage.

[0096] In some instances, a device (e.g., Figure 1 System 100 in Figure 2 The system 200 in the present invention or the related IC 120 or 220 includes a differential amplifier circuit system (e.g., Figure 1 The differential amplifier circuit system 130 in Figure 2 The differential amplifier circuit system 230, Figure 3A The differential amplifier circuit system 300, Figure 3B The differential amplifier circuit system 350, Figure 4 The differential amplifier circuit system 430 or Figure 7 The differential amplifier circuit system 700 in FIG. 1 includes a first gain fine-tuning circuit system (eg, Figure 4 The first input transistor pair in the control circuitry 470, or Figure 5 a first switch network 504A and a second switch network 504B in the circuit); a second gain fine-tuning circuit system (eg, Figure 4 The second input transistor pair in the control circuitry 474, or Figure 5 and control logic coupled to the first gain trimming circuit system and the second gain trimming circuit system (eg, Figure 3A and 3B Fine-tuning controller 320, Figure 4 Fine-tuning controller 450 or Figure 7 The control logic 790 in FIG. 1 is configured to receive a control input (eg, Figure 3A 、3B or IN_P in 4); determining a gain setting based on a control input (e.g., one of the gain codes in Table 1); adjusting a setting of the first gain fine-tuning circuitry in response to the gain setting (e.g., by applying control signal CS5); and adjusting a setting of the second gain fine-tuning circuitry in response to the gain setting (e.g., by applying control signal CS6).

[0097] In some instances, the control input comprises a gain setting selected by a user. In some instances, the control input comprises a temperature. In some instances, the apparatus comprises: a device coupled to the differential amplifier circuitry (e.g., Figure 1 The device 102, or Figure 2 and a controller coupled to the differential amplifier circuitry and the device (e.g., Figure 1 The controller 140, or Figure 2 The device is configured to receive a control signal from the controller (e.g., Figure 1 The control signal CS1 in, or Figure 2 CS2 in the control signal); performing an operation in response to the control signal; and providing a sensing signal (eg, Figure 1 a voltage or current sense signal at the first terminal 104 and / or the second terminal 106 in the circuit, or Figure 2 The differential amplifier circuitry is configured to: receive the sense signal; and provide an amplified sense signal (e.g., a voltage or current sense signal at the first terminal 204 and / or the second terminal 206) in response to the settings of the first gain trimming circuitry and the second gain trimming circuitry. Figure 1 S1_ISNS in Figure 2 The controller is configured to: receive the amplified sense signal; and provide a control signal in response to the amplified sense signal. In various examples, the device of the apparatus may be a motor, a sensor, or another device.

[0098] As used herein, the term "coupled" may encompass any connection, communication, or signal path that supports a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, but the intermediate component C does not alter the functional relationship between devices A and B, such that device B is controlled by device A via the control signal generated by device A.

[0099] Additionally, throughout this specification, statements stating “based on” mean “based, at least in part, on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0100] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by the manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0101] As used herein, the terms "terminal," "node," "interconnect," "lead," and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components and / or conductors, or their terminations.

[0102] Circuits or devices described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacture, for example, by an end user and / or a third party.

[0103] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., NFETs or PFETs), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0104] In the claims, reference may be made to the control terminal of a transistor and its first and second terminals. In the context of a FET, the control terminal is the gate, and the first and second terminals are the drain and source. In the context of a BJT, the control terminal is the base, and the first and second terminals are the collector and emitter.

[0105] When a FET is "on" in this document, it is meant that the FET's conduction channel exists and drain current can flow through the FET. When a FET is "off" in this document, it is meant that the conduction channel does not exist, and therefore drain current does not flow through the FET. However, an "off" FET can have current flowing through the transistor's body diode.

[0106] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available before the components were replaced. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0107] Although some elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being external to the integrated circuit may be included in the integrated circuit, and / or some features described as being internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0108] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise indicated, the word "about," "substantially," or "substantially" preceding a parameter means within + / - 10% of the parameter, or if the parameter is zero, within a reasonable range of values about zero.

[0109] The described examples can be modified, and other examples are possible, within the scope of the claims.

Claims

1. An integrated circuit comprising: A differential amplifier circuit system comprising: a first gain trim circuitry having a first gain trim input, the first gain trim circuitry comprising a first differential input transistor pair and a second differential input transistor pair; a second gain trim circuitry having a second gain trim input, the second gain trim circuitry comprising a third differential input transistor pair and a fourth differential input transistor pair; as well as Control logic has a first gain trim output and a second gain trim output, the first gain trim output coupled to the first gain trim input, and the second gain trim output coupled to the second gain trim input. 2 . The integrated circuit of claim 1 , wherein each transistor in the first and second differential input transistor pairs has the same width-to-length (W / L) ratio.

3. The integrated circuit of claim 2 , wherein the differential amplifier circuitry comprises a first current source coupled to the first differential input transistor pair and a second current source coupled to the second differential input transistor pair, and wherein the first and second current sources are configured to provide the same current level.

4. The integrated circuit of claim 1 , wherein each transistor of the third differential input transistor pair has a first width-to-length (W / L) ratio, and each transistor of the fourth differential input transistor pair has a second W / L ratio that is smaller than the first W / L ratio.

5. The integrated circuit of claim 4, wherein the differential amplifier circuitry includes a current source coupled to the third differential input transistor pair and the fourth differential input transistor pair.

6. The integrated circuit of claim 4 , wherein the differential amplifier circuitry comprises a resistor network, the first gain trimming circuitry comprises a first selection circuitry coupled between the resistor network and the first and second differential input transistor pairs, the second gain trimming circuitry comprises a second selection circuitry coupled between the resistor network and the third and fourth differential input transistor pairs, the first selection circuitry having a first control input, the second selection circuitry having a second control input, the first gain trimming output coupled to the first control input, and the second gain trimming output coupled to the second control input.

7. The integrated circuit of claim 1 , wherein the differential amplifier circuitry comprises a first gain stage, cross-coupling switches before and after the first gain stage, and a feed-forward gain stage, the first gain stage comprising the first gain fine-tuning circuitry and the second gain fine-tuning circuitry, and the feed-forward gain stage comprising a third gain fine-tuning circuitry and a fourth gain fine-tuning circuitry, the third gain fine-tuning circuitry having a third gain fine-tuning input, the fourth gain fine-tuning circuitry having a fourth gain fine-tuning input, the control logic having a third gain fine-tuning output and a fourth gain fine-tuning output, the third gain fine-tuning output coupled to the third gain fine-tuning input, and the fourth gain fine-tuning output coupled to the fourth gain fine-tuning input.

8. The integrated circuit of claim 7 , wherein the first gain stage comprises a first input terminal, a second input terminal, and a first output terminal, the cross-coupling switches comprise a first cross-coupling switch having a second output terminal, a second cross-coupling switch having a third output terminal, and a third cross-coupling switch having a third input terminal, the second output terminal of the first cross-coupling switch is coupled to the first input terminal of the first gain stage, the third output terminal of the second cross-coupling switch is coupled to the second input terminal of the first gain stage, and the third input terminal of the third cross-coupling switch is coupled to the first output terminal of the first gain stage.

9. The integrated circuit of claim 8 , wherein the differential amplifier circuitry comprises a notch filter, a second gain stage, and a third gain stage, the notch filter configured to filter the output signal from the third cross-coupled switch to produce a filtered signal, the second gain stage configured to apply a gain to the filtered signal to produce an adjusted filtered result, and the third gain stage configured to apply a gain to a combination of the adjusted filtered result and an output of the feed-forward gain stage.

10. The integrated circuit of claim 8, wherein the control logic is configured to: Obtaining a first digital code; Obtain a second digital code; generating a first control signal at the first gain trim output in response to the first digital code; and A second control signal is generated at the second gain trim output in response to the second digital code.

11. A differential amplifier circuit comprising: a first differential input transistor pair; a second differential input transistor pair; Resistor network; first selection circuitry having a first control input, the first selection circuitry coupled between the resistive network and the first differential input transistor pair; second selection circuitry having a second control input, the second selection circuitry coupled between the resistive network and the second differential input transistor pair; as well as Control logic has a first gain trim output and a second gain trim output, the first gain trim output coupled to the first control input and the second gain trim output coupled to the second control input.

12. The differential amplifier circuit of claim 11 , further comprising a respective current source coupled to each of the first differential input transistor pairs, wherein each of the first differential input transistor pairs includes transistors having the same width-to-length (W / L) ratio, and each respective current source is configured to provide the same current level.

13. The differential amplifier circuit of claim 11 , further comprising a current source coupled to each of the second differential input transistor pairs, wherein each of the second differential input transistor pairs includes transistors having different width-to-length (W / L) ratios.

14. The differential amplifier circuit according to claim 11 , wherein the first differential input transistor pair, the The second differential input transistor pair, the resistor network, the first selection circuitry, and the second selection circuitry are part of a first gain stage, the resistor network is a first resistor network, and the differential amplifier circuit further includes a feed-forward gain stage comprising: a third differential input transistor pair; a fourth differential input transistor pair; a second resistor network; a third selection circuitry having a third control input coupled to the first gain trim output, the third selection circuitry coupled between the second resistor network and the third differential input transistor pair; as well as Fourth selection circuitry has a fourth control input coupled to the second gain trim output, the fourth selection circuitry coupled between the second resistor network and the fourth differential input transistor pair.

15. The differential amplifier circuit of claim 14 , wherein the first gain stage comprises a first input terminal, a second input terminal, and a first output terminal, the differential amplifier circuit further comprising a first cross-coupled switch having a second output terminal, a second cross-coupled switch having a third output terminal, and a third cross-coupled switch having a third input terminal, a notch filter, a second gain stage, and a third gain stage, the notch filter being configured to filter an output signal from the third cross-coupled switch to produce a filtered result, the second gain stage being configured to apply a gain to the second output signal to produce an adjusted filtered result, and the third gain stage being configured to apply a gain to a combination of the adjusted filtered result and an output of the feed-forward gain stage.

16. An apparatus comprising: A differential amplifier circuit system comprising: a first gain fine-tuning circuit system; a second gain fine-tuning circuit system; as well as control logic coupled to the first and second gain trim circuitry, the control logic configured to: receiving control inputs; determining a gain setting based on the control input; adjusting a setting of the first gain trim circuitry in response to the gain setting; and A setting of the second gain trim circuitry is adjusted in response to the gain setting.

17. The apparatus of claim 16, wherein the control input comprises a gain setting selected by a user.

18. The apparatus of claim 16, wherein the control input comprises temperature.

19. The apparatus of claim 16, further comprising: means coupled to the differential amplifier circuitry; as well as a controller coupled to the differential amplifier circuitry and the device, The apparatus is configured to: receiving a control signal from the controller; performing an operation in response to the control signal; and Providing a sensing signal, The differential amplifier circuitry is configured to: receiving the sensing signal; and providing an amplified sense signal in response to the settings of the first and second gain trim circuitry, and The controller is configured to: receiving the amplified sensing signal; and The control signal is provided in response to the amplified sense signal.

20. The apparatus of claim 19, wherein the device is a motor.

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