Multi-core polarization code continuous elimination bit flipping decoding method and device

Abstract

The invention provides a multi-core polarization code continuous elimination bit flipping decoding method and device, and the method comprises the steps: carrying out the continuous elimination decoding of a received channel signal, obtaining a decoding estimation value, carrying out the cyclic redundancy check, if the check is passed, the decoding is successful, or else, entering a bit flipping stage; constructing a key set of the multi-core polarization code, wherein the key set comprises an information bit position of which the first error probability is higher than a preset threshold value in continuous elimination decoding; sorting bit positions in the key set by adopting bit channel reliability estimation; and overturning the information bits in the key set for a predetermined number of times according to the sorting result, and re-executing the continuous elimination decoding and the cyclic redundancy check after each overturning until the cyclic redundancy check passes or reaches the upper limit of the predetermined number of overturning times. According to the invention, a reliable solution is provided for the application of the multi-core polarization code in an actual communication system.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to a method and device for continuously eliminating bit flipping decoding of multi-core polar codes. Background Art

[0002] Polar codes, as a coding scheme that achieves channel capacity, have been applied in 5G and other communications fields with low-complexity encoding and decoding modes. However, their initial construction uses a 2×2 core matrix, which results in limited code length flexibility. While methods such as puncturing and shortening can extend code length, they suffer from high design complexity, limited decoding performance, and a lengthy mother code tree structure. Multi-core polar codes, constructed by Kronecker products of kernel matrices of different sizes, offer a wide range of code lengths while combining low design complexity with superior decoding performance, and have become a research hotspot. However, the polarization effect of multi-core polar codes is insufficient under limited code lengths, leading to error propagation in the Successive Cancellation (SC) decoding algorithm, severely impacting decoding performance. Traditional SC bit-flipping decoding algorithms for polar codes use key sets to estimate the first error location to improve error propagation. However, their key set construction and sorting methods, designed based on the characteristics of the traditional 2×2 core matrix, present compatibility issues when directly applied to multi-core polar codes, making it difficult to effectively utilize the channel reliability information of multi-core polar codes. Therefore, developing a multi-core polar code continuous elimination bit flip decoding method and device that can effectively overcome the defects in the above-mentioned related technologies has become a technical problem that needs to be urgently solved in the industry. Summary of the Invention

[0003] In response to the above-mentioned problems existing in the prior art, embodiments of the present invention provide a method and device for decoding multi-core polar codes with continuous elimination of bit flipping.

[0004] In a first aspect, an embodiment of the present invention provides a method for continuous elimination bit flipping decoding of a multi-core polar code, comprising: performing continuous elimination decoding on a received channel signal to obtain a decoding estimate and perform a cyclic redundancy check; if the check passes, decoding is successful; otherwise, entering a bit flipping phase; constructing a key set of the multi-core polar code, the key set comprising the first information bit position with an error probability greater than a predetermined threshold in the continuous elimination decoding; sorting the bit positions in the key set using a bit channel reliability estimate; and flipping the information bits in the key set a predetermined number of times based on the sorting result, and re-performing continuous elimination decoding and a cyclic redundancy check after each flip until the cyclic redundancy check passes or a predetermined upper limit on the number of flips is reached.

[0005] Based on the content of the above method embodiments, the method for continuously eliminating bit-flipping in multi-core polar codes provided in the embodiments of the present invention, wherein constructing a key set for the multi-core polar code includes: generating a decoding tree diagram for the multi-core polar code, traversing the nodes in the tree diagram layer by layer, and if the current node is a Rate-1 node and the parent node of the Rate-1 node is a non-Rate-1 node, adding the information bit position corresponding to the current node to the key set; wherein the Rate-1 node is a node where the node itself or its descendant nodes are all information nodes.

[0006] Based on the content of the above method embodiments, in the multi-core polar code continuous bit flip elimination decoding method provided in the embodiments of the present invention, the use of bit channel reliability estimation to sort the bit positions in the key set includes: calculating the mean of the bit channels of each layer of the multi-core polar code through Gaussian approximation, sorting the bit channel means corresponding to the bit positions in the key set from small to large, and obtaining a bit flip order from low to high reliability.

[0007] Based on the content of the above method embodiment, the multi-core polar code continuous elimination bit flip decoding method provided in the embodiment of the present invention, the continuous elimination decoding of the received channel signal includes: traversing the decoding tree diagram of the received signal based on the generator matrix of the multi-core polar code until a decoding estimate is obtained; wherein the generator matrix is composed of a 2-core matrix The n1-th Kronecker product of the 3-core matrix The n2 Kronecker product construction.

[0008] Based on the content of the above method embodiment, the multi-core polar code continuous bit flipping elimination decoding method provided in the embodiment of the present invention, wherein the information bits in the key set are flipped a predetermined number of times according to the sorting result, including: the upper limit of the predetermined number of flips is the smaller value of the number of key set elements and the predetermined maximum number of flips, and each flipping is performed only on the unflipped bit with the highest current sorting priority until the cyclic redundancy check passes or the upper limit of the flipping number is reached.

[0009] Based on the content of the above method embodiment, the multi-core polar code continuous bit flip elimination decoding method provided in the embodiment of the present invention, wherein a decoding tree diagram for the multi-core polar code is generated, and the nodes in the tree diagram are traversed layer by layer, including: the nodes in the decoding tree diagram are identified as (ψ, t) by the layer number t and the subscript ψ, the traversal order is from top to bottom and from left to right, and the bit channel reliability corresponding to the node is characterized by the mean value calculated by Gaussian approximation.

[0010] Based on the content of the above method embodiment, the multi-core polar code continuous elimination bit flip decoding method provided in the embodiment of the present invention has a code length of Where n1 and n2 are the number of 2-core matrices and 3-core matrices respectively. K bits carrying information are concatenated with r cyclic redundancy check bits as the input vector u, the number of frozen bits is NKr, and the code rate of the multi-core polar code is

[0011] In a second aspect, an embodiment of the present invention provides a multi-core polar code continuous elimination bit flipping decoding apparatus, comprising: a first main module, configured to perform continuous elimination decoding on a received channel signal, obtain a decoding estimate, and perform a cyclic redundancy check. If the check passes, decoding is successful; otherwise, the bit flipping phase is entered; a second main module, configured to construct a key set for the multi-core polar code, the key set comprising the first information bit position in the continuous elimination decoding whose error probability is greater than a predetermined threshold; a third main module, configured to sort the bit positions within the key set using a bit channel reliability estimate; and a fourth main module, configured to flip the information bits within the key set a predetermined number of times based on the sorting result, and re-perform continuous elimination decoding and a cyclic redundancy check after each flip until the cyclic redundancy check passes or a predetermined upper limit on the number of flips is reached.

[0012] In a third aspect, an embodiment of the present invention provides an electronic device, including:

[0013] At least one processor, at least one memory and a communication interface; wherein,

[0014] The processor, memory and communication interface communicate with each other;

[0015] The memory stores program instructions executable by the processor, and the processor calls the program instructions to execute the multi-core polar code continuous elimination bit flip decoding method provided by any one of the various implementations of the first aspect.

[0016] In a fourth aspect, an embodiment of the present invention provides a non-transitory computer-readable storage medium, which stores computer instructions. The computer instructions enable a computer to execute the multi-core polar code continuous elimination bit flip decoding method provided by any one of the various implementations of the first aspect.

[0017] The method and device for decoding multi-core polar codes with continuous elimination of bit flips provided by the embodiments of the present invention accurately estimate the first error position in continuous elimination decoding by constructing a key set suitable for a multi-core structure, effectively improving the error propagation problem under limited code lengths. A key set sorting method based on bit channel reliability can further optimize decoding performance with the same number of flips. Compared with traditional continuous elimination decoding algorithms, this method can achieve a performance gain of approximately 0.7dB at a block error rate of 0.01 for multi-core polar codes with a code length of 384 and a code rate of 0.5, and a gain of approximately 0.85dB at a block error rate of 0.001 for codes with a code length of 576 and a code rate of 0.5. Furthermore, reliability sorting reduces invalid bit flips and lowers decoding latency, providing an efficient and reliable solution for the application of multi-core polar codes in practical communication systems and significantly improving the practicality of coding schemes. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A schematic diagram of a flow chart of a multi-core polar code continuous bit-flip elimination decoding method provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of the structure of a multi-core polar code continuous bit-flip elimination decoding device provided by an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of the physical structure of an electronic device provided by an embodiment of the present invention;

[0022] Figure 4 Schematic diagram of the key set distribution effect of the P(24,15) multi-core polar code provided in an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of a decoding tree for a multi-core polar code with N=12 provided in an embodiment of the present invention;

[0024] Figure 6 A schematic diagram showing a comparison of decoding performance of multi-core polar codes with a code length of 384 and a code rate of 0.5 provided in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram comparing the decoding performance of multi-core polar codes with a code length of 576 and a code rate of 0.5 provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be combined with each other arbitrarily to form a feasible technical solution. This combination is not subject to the constraints of the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be considered that this combination of technical solutions does not exist and is not within the scope of protection required by the present invention. If there are step numbers in the following embodiments, they are only set for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0027] The embodiment of the present invention provides a multi-core polar code continuous elimination bit flip decoding method, see Figure 1 The method includes: performing continuous elimination decoding on a received channel signal to obtain a decoding estimate and performing a cyclic redundancy check. If the check passes, the decoding is successful; otherwise, the method enters a bit flipping stage; constructing a key set of a multi-core polar code, the key set comprising the first information bit position with an error probability higher than a predetermined threshold in the continuous elimination decoding; sorting the bit positions in the key set using a bit channel reliability estimate; and flipping the information bits in the key set a predetermined number of times according to the sorting result, and re-performing continuous elimination decoding and a cyclic redundancy check after each flip until the cyclic redundancy check passes or a predetermined upper limit on the number of flips is reached.

[0028] Based on the content of the above method embodiment, as an optional embodiment, the multi-core polar code continuous bit flipping elimination decoding method provided in the embodiment of the present invention, the construction of the key set of the multi-core polar code includes: generating a decoding tree diagram of the multi-core polar code, traversing the nodes in the tree diagram layer by layer, and if the current node is a Rate-1 node and the parent node of the Rate-1 node is a non-Rate-1 node, adding the information bit position corresponding to the current node to the key set; wherein the Rate-1 node is a node whose itself or descendant nodes are all information nodes.

[0029] Generate a decoding tree diagram for the multi-core polar code. Traverse the nodes on the code tree layer by layer from top to bottom and from left to right to determine whether the current node is a Rate-1 node. If so, determine whether the parent node of the current node is a non-Rate-1 node. If so, add element c to the key set, where c is the length of the current node multiplied by the subscript of the current node. Otherwise, continue traversing. Figure 4 The figure shows a multi-core polar code for P(24,15). The nodes that meet the conditions are node (3,2), node (3,1), node (5,0), node (7,0), node (8,0), node (14,0), node (16,0), and node (17,0). The corresponding elements are 18, 9, 5, 7, 8, 14, 16, and 17, respectively.

[0030] Based on the content of the above method embodiment, as an optional embodiment, the multi-core polar code continuous bit flip elimination decoding method provided in the embodiment of the present invention, wherein the use of bit channel reliability estimation to sort the bit positions in the key set includes: calculating the mean of the bit channels of each layer of the multi-core polar code through Gaussian approximation, sorting the bit channel means corresponding to the bit positions in the key set from small to large, and obtaining a bit flip order from low to high reliability.

[0031] The mean of the bit channel in the last layer of the multi-core polar code is obtained through Gaussian approximation. The elements in the key set are associated with the bit channel means of the corresponding subscripts. The bit channel means are sorted from smallest to largest, and the corresponding elements are output. The principle of this method is that the bit channel means calculated through Gaussian approximation reveal the reliability of the subchannels. The lower the reliability of the selected channel, the higher the probability of flipping during the decoding process.

[0032] In the Gaussian approximation construction process of multi-core polar codes, in order to select the K most reliable channels to carry information, it is necessary to sort the reliability of N channels. Let the mean of the Additive White Gaussian Noise (AWGN) channel be 0 and the variance be σ 2 , then the mean of the channel output is as follows:

[0033]

[0034] In the above formula, represents the set of stored bit channel means, i represents the subscript corresponding to the calculated bit channel mean, and N is the size of the current set (here N is the code length of the multi-core polar code). R is the code rate of the multi-core polar code, E b is the energy per bit, and N0 is the power spectral density of the noise. In order to calculate the bit channel mean in the next stage, for the 2-core matrix T2, it can be calculated by the following formula:

[0035]

[0036] In the above formula, represents the upper layer channel mean value set, represents the calculated bit channel mean set. i represents the subscript corresponding to the calculated bit channel mean, and N is the size of the upper set. For the 3-core matrix T3, it can be calculated by the following formula:

[0037]

[0038]

[0039] In the above formula, represents the upper layer channel mean value set, represents the calculated bit channel mean set. i represents the subscript corresponding to the calculated bit channel mean, and N is the size of the upper layer set.

[0040] In addition, the φ function in all the above formulas can be calculated as follows:

[0041]

[0042] Where x is the independent variable and u is the integral variable. Using the above formula, the bit-channel mean of the multi-core polar code can be calculated layer by layer until the bit-channel mean of the final layer is obtained. This is then sorted for reliability and the channels carrying information are selected.

[0043] Based on the content of the above method embodiment, as an optional embodiment, the multi-core polar code continuous elimination bit flip decoding method provided in the embodiment of the present invention, the continuous elimination decoding of the received channel signal includes: traversing the decoding tree diagram of the received signal based on the generator matrix of the multi-core polar code until a decoding estimate is obtained; wherein the generator matrix is composed of a 2-core matrix Sub-Kronecker Product and 3-Core Matrix The n2 Kronecker product construction.

[0044] Successive Cancellation (SC) decoding of multi-core polar codes can be represented by a tree structure. Figure 5 The decoding tree for a multi-core polar code with a code length of 12 is shown. In this tree, black, white, and gray circles represent nodes that are information nodes (carrying information bits) or whose descendants are all information nodes, nodes that are frozen nodes (carrying frozen bits) or whose descendants are all frozen nodes, and other nodes, respectively. Let the level of the current node be t, and let its subscript at level t be ψ. Then, each node can be represented by (ψ, t).

[0045] SC decoding involves traversing the tree structure from top to bottom and from left to right. Let the log-likelihood ratio (LLR) vector in the decoding tree be y ψ,t , except for the root node receiving channel LLRs, the y corresponding to each node ψ,t All can be calculated from its parent node. For the T2 kernel matrix, the LLR calculation expression of its child node is as follows:

[0046]

[0047] Among them, the symbol The operation represented by l and r represent the left child node and the right child node respectively, k is the kth element in the vector set, is the kth codeword bit of the left child node. For the 3-core matrix T3, the LLR calculation expression of its child nodes is as follows:

[0048]

[0049] Among them, the symbol The operation represented by symbol The operation represented is modulo 2 addition. l, c, and r represent the left child node, the middle child node, and the right child node respectively. k is the kth element in the vector set. is the kth codeword bit of the left child node, is the kth codeword bit of the middle child node.

[0050] Based on the content of the above method embodiment, as an optional embodiment, the multi-core polar code continuous elimination bit flip decoding method provided in the embodiment of the present invention, wherein the information bits in the key set are flipped a predetermined number of times according to the sorting result, including: the upper limit of the predetermined number of flips is the smaller value of the number of key set elements and the predetermined maximum number of flips, and each flip only flips the unflipped bit with the highest current sorting priority until the cyclic redundancy check passes or the upper limit of the flip number is reached.

[0051] First, the channel received vector y passes through the SC decoder to output the decoded estimate Then to Perform CRC check. If the check passes, the decoding is considered successful. Otherwise, the bit flip operation is performed. At this time, the decoder will determine whether the bit flip exceeds the upper limit of the set flip number. If it exceeds, the decoding is considered to have failed. Otherwise, the SC decoding is performed again and the unreliable information bit u is flipped during the decoding process. i , and then the newly obtained decoding result Perform CRC check. Then, repeatedly perform bit flipping operation until Pass the CRC check (decoding successful) or reach the set upper limit of the number of flips (decoding failed).

[0052] Based on the content of the above method embodiment, as an optional embodiment, the multi-core polar code continuous bit flip elimination decoding method provided in the embodiment of the present invention, the generating of the decoding tree diagram of the multi-core polar code, and the traversal of the nodes in the tree diagram layer by layer, including: the nodes in the decoding tree diagram are identified as (ψ, t) by the layer number t and the subscript ψ, the traversal order is from top to bottom and from left to right, and the bit channel reliability corresponding to the node is characterized by the mean calculated by Gaussian approximation.

[0053] When the code length of a multi-core polar code is long, the number of elements in the key set becomes very large. This also means that during the SC bit-flip decoding process, a large number of unreliable bits must be flipped to achieve optimal decoding performance. However, this will result in extremely high decoding latency.

[0054] To address this issue, the simplest and most effective approach is to limit the number of flips, T. However, when the number of flips is limited, selecting the appropriate flipped bits within the key set becomes crucial. A reliability-based key set sorting method is proposed: Gaussian approximation is used to obtain the mean of the bit channel of the last layer of the multi-core polar code. The elements within the key set are associated with the bit channel mean of the corresponding subscript, sorted from small to large by the bit channel mean, and the corresponding elements are output. The principle behind this method is that the bit channel mean calculated using the Gaussian approximation reveals the reliability of the subchannel. Selecting a channel with lower reliability increases the probability of a flip during decoding.

[0055] Based on the content of the above method embodiment, as an optional embodiment, the multi-core polar code continuous elimination bit flip decoding method provided in the embodiment of the present invention has a code length of Where n1 and n2 are the number of 2-core matrices and 3-core matrices respectively. K bits carrying information are concatenated with r cyclic redundancy check bits as the input vector u, the number of frozen bits is NKr, and the code rate of the multi-core polar code is

[0056] The multi-core polar code continuous elimination bit flip decoding method provided by the embodiment of the present invention accurately estimates the first error position in continuous elimination decoding by constructing a key set suitable for the multi-core structure, effectively improving the error propagation problem under limited code length. The key set sorting method based on the bit channel reliability can further optimize the decoding performance with the same number of flips. Compared with the traditional continuous elimination decoding algorithm, this method can achieve a performance gain of approximately 0.7dB at a block error rate of 0.01 for a multi-core polar code with a code length of 384 and a code rate of 0.5, and a gain of approximately 0.85dB at a block error rate of 0.001 for a code with a code length of 576 and a code rate of 0.5. At the same time, reliability sorting reduces invalid bit flips and reduces decoding latency, providing an efficient and reliable solution for the application of multi-core polar codes in practical communication systems and significantly improving the practicality of the coding scheme.

[0057] All multi-core polar codes are constructed using the Gaussian approximation method under the condition of SNR = 0. The coded codewords are modulated using Binary Phase Shift Keying (BPSK) and transmitted through an AWGN channel. The CRC polynomial used is 0x07. Figure 6 The decoding results of the multi-core polar code with a code length of 384 and a code rate of 0.5 are shown. In the figure, SC represents SC decoding, and SC-Flip represents the bit flip decoding algorithm that flips all elements (58) in the key set. -2 At the position of 10, the SC bit flipping decoding algorithm brings about 0.7dB decoding performance gain for multi-core polar codes. -3 , resulting in a decoding performance gain of approximately 0.9 dB. It can be seen that the algorithm greatly improves the decoding performance of multi-core polar code SC decoding. In addition, a comparison of the decoding performance of the key set sorted by order (SC-Flip-A) and the key set sorted by reliability (SC-Flip-B) at flip times T = 20 and T = 40 shows that the proposed method of sorting the key set by reliability significantly outperforms the key set sorted by order. The decoding performance of the key set sorted by order at T = 20 is similar to that of the original SC decoding. This is because the use of CRC check "loses" some code rate, and the CRC bits do not carry information.

[0058] Figure 7 The decoding results of the multi-core polar code with a code length of 576 and a code rate of 0.5 are shown. In the figure, SC represents SC decoding, and SC-Flip represents the bit flip decoding algorithm that flips all elements (84) in the key set. -2 At the position of 10, the SC bit flipping decoding algorithm brings about 0.7dB decoding performance gain for multi-core polar codes. -3, resulting in a decoding performance gain of approximately 0.85dB. This shows that the algorithm significantly improves the decoding performance of multi-core polar code SC decoding. Furthermore, a comparison of the decoding performance of the key set sorted by order (SC-Flip-A) and the key set sorted by reliability (SC-Flip-B) at flip times T = 30 and T = 50 shows that the proposed method of sorting the key set by reliability significantly outperforms the key set sorted by order. The reason why the decoding performance of the key set sorted by order at T = 30 is similar to that of the original SC decoding is that the use of CRC check "loses" some bit rate, and the CRC bits do not carry information.

[0059] The implementation basis of each embodiment of the present invention is achieved through programmed processing by a device with processor functions. Therefore, in engineering practice, the technical solutions and functions of each embodiment of the present invention can be encapsulated into various modules. Based on this reality, on the basis of the above embodiments, an embodiment of the present invention provides a multi-core polar code continuous elimination bit flip decoding device, which is used to execute the multi-core polar code continuous elimination bit flip decoding method in the above method embodiment. Figure 2 The device includes: a first main module, configured to implement continuous elimination decoding of a received channel signal, obtain a decoding estimate, and perform a cyclic redundancy check. If the check passes, the decoding is successful; otherwise, the bit flipping phase is entered; a second main module, configured to implement construction of a key set for a multi-core polar code, wherein the key set includes the first information bit position with an error probability higher than a predetermined threshold in the continuous elimination decoding; a third main module, configured to implement sorting of the bit positions in the key set using a bit channel reliability estimate; and a fourth main module, configured to implement flipping of the information bits in the key set a predetermined number of times according to the sorting result, and re-performing continuous elimination decoding and a cyclic redundancy check after each flip until the cyclic redundancy check passes or the predetermined upper limit of the flipping number is reached.

[0060] The multi-core polar code continuous elimination bit flip decoding device provided by the embodiment of the present invention adopts Figure 2 By constructing key sets suitable for multi-core structures, several modules in the algorithm accurately estimate the first error position in continuous elimination decoding, effectively improving the error propagation problem under limited code lengths. A key set sorting method based on bit channel reliability can further optimize decoding performance with the same number of flips. Compared with traditional continuous elimination decoding algorithms, this method can achieve a performance gain of approximately 0.7dB at a block error rate of 0.01 for multi-core polar codes with a code length of 384 and a code rate of 0.5, and a gain of approximately 0.85dB at a block error rate of 0.001 for codes with a code length of 576 and a code rate of 0.5. Furthermore, reliability sorting reduces invalid bit flips and lowers decoding latency, providing an efficient and reliable solution for the application of multi-core polar codes in practical communication systems and significantly improving the practicality of the coding scheme.

[0061] It should be noted that the device in the device embodiment provided by the present invention can be used to implement the method in the above-mentioned method embodiment as well as the method in other method embodiments provided by the present invention. The only difference is that the corresponding functional modules are set. The principle is basically the same as the principle of the above-mentioned device embodiment provided by the present invention. As long as those skilled in the art refer to the specific technical solutions in other method embodiments on the basis of the above-mentioned device embodiment, obtain the corresponding technical means and the technical solutions composed of these technical means by combining technical features, and ensure the practicality of the technical solutions, they can improve the device in the above-mentioned device embodiment to obtain the corresponding device class embodiment, thereby obtaining the corresponding device class embodiment for implementing the methods in other method class embodiments. For example:

[0062] Based on the content of the above-mentioned device embodiment, as an optional embodiment, the multi-core polar code continuous bit flipping elimination decoding device provided in the embodiment of the present invention further includes: a first submodule, used to implement the key set of constructing the multi-core polar code, including: generating a decoding tree diagram of the multi-core polar code, traversing the nodes in the tree diagram layer by layer, and if the current node is a Rate-1 node and the parent node of the Rate-1 node is a non-Rate-1 node, adding the information bit position corresponding to the current node to the key set; wherein the Rate-1 node is a node whose itself or descendant nodes are all information nodes.

[0063] Based on the content of the above-mentioned device embodiment, as an optional embodiment, the multi-core polar code continuous bit flip elimination decoding device provided in the embodiment of the present invention further includes: a second submodule, configured to implement the use of bit channel reliability estimation to sort the bit positions in the key set, including: calculating the mean of the bit channels of each layer of the multi-core polar code through Gaussian approximation, sorting the bit channel means corresponding to the bit positions in the key set from small to large, and obtaining a bit flip order from low to high reliability.

[0064] Based on the content of the above-mentioned device embodiment, as an optional embodiment, the multi-core polar code continuous elimination bit flip decoding device provided in the embodiment of the present invention further includes: a third submodule for realizing the continuous elimination decoding of the received channel signal, including: traversing the decoding tree diagram of the received signal based on the generator matrix of the multi-core polar code until a decoding estimate is obtained; wherein the generator matrix is composed of a 2-core matrix The n1-th Kronecker product of the 3-core matrix The n2 Kronecker product construction.

[0065] Based on the content of the above-mentioned device embodiment, as an optional embodiment, the multi-core polar code continuous elimination bit flip decoding device provided in the embodiment of the present invention further includes: a fourth submodule, configured to implement the predetermined number of flipping of the information bits in the key set according to the sorting result, including: the upper limit of the predetermined number of flipping is the smaller value of the number of key set elements and the predetermined maximum number of flipping, and each time the flipping is performed, only the unflipped bit with the highest priority in the current sorting is flipped until the cyclic redundancy check passes or the upper limit of the flipping number is reached.

[0066] Based on the content of the above-mentioned device embodiment, as an optional embodiment, the multi-core polar code continuous bit flipping elimination decoding device provided in the embodiment of the present invention further includes: a fifth submodule, which is used to implement the decoding tree diagram for generating the multi-core polar code, and traverse the nodes in the tree diagram layer by layer, including: the nodes in the decoding tree diagram are identified as (ψ, t) by the layer number t and the subscript ψ, the traversal order is from top to bottom and from left to right, and the bit channel reliability corresponding to the node is characterized by the mean calculated by Gaussian approximation.

[0067] Based on the content of the above device embodiment, as an optional embodiment, the multi-core polar code continuous elimination bit flip decoding device provided in the embodiment of the present invention further includes: a sixth submodule for realizing the code length of the multi-core polar code Where n1 and n2 are the number of 2-core matrices and 3-core matrices respectively. K bits carrying information are concatenated with r cyclic redundancy check bits as the input vector u, the number of frozen bits is NKr, and the code rate of the multi-core polar code is

[0068] The method of the embodiment of the present invention is implemented by electronic devices, so it is necessary to introduce the relevant electronic devices. Based on this purpose, the embodiment of the present invention provides an electronic device, such as Figure 3 As shown, the electronic device includes: at least one processor, a communications interface, at least one memory, and a communications bus, wherein the at least one processor, the communications interface, and the at least one memory communicate with each other via the communications bus. The at least one processor can call logic instructions in the at least one memory to execute all or part of the steps of the methods provided in the aforementioned method embodiments.

[0069] In addition, the logic instructions in the at least one memory mentioned above can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each method embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0070] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0071] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

[0072] The flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present invention. Based on this understanding, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or sometimes in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0073] It should be noted that the terms "include", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements. Any "predetermined threshold", "preset threshold" or similar expressions that do not indicate a specific value can be determined by a person of ordinary skill in the art through simple experiments or corresponding debugging.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A multi-core polar code continuous elimination bit flip decoding method, characterized in that: include: Performing continuous elimination decoding on the received channel signal to obtain a decoding estimate and performing a cyclic redundancy check. If the check passes, the decoding is successful; otherwise, the bit flipping phase is entered. Constructing a key set of a multi-core polar code, the key set comprising the first information bit position in the continuous elimination decoding with an error probability higher than a predetermined threshold. The bit positions in the key set are sorted using a bit channel reliability estimate; the information bits in the key set are flipped a predetermined number of times according to the sorting result, and continuous elimination decoding and cyclic redundancy check are re-executed after each flip until the cyclic redundancy check passes or a predetermined upper limit on the number of flips is reached.

2. The multi-core polar code continuous bit flip elimination decoding method according to claim 1, characterized in that: Constructing a key set for a multi-core polar code includes generating a decoding tree diagram for the multi-core polar code, traversing nodes in the tree diagram layer by layer, and adding an information bit position corresponding to the current node to the key set if the current node is a Rate-1 node and the parent node of the Rate-1 node is a non-Rate-1 node. The Rate-1 node is a node where the node itself or its descendant nodes are all information nodes.

3. The multi-core polar code continuous bit-flip elimination decoding method according to claim 2, characterized in that: The sorting of the bit positions in the key set using bit channel reliability estimation includes: calculating the mean of the bit channels of each layer of the multi-core polar code through Gaussian approximation, sorting the bit channel means corresponding to the bit positions in the key set from small to large, and obtaining a bit flipping order from low to high reliability.

4. The multi-core polar code continuous bit flip elimination decoding method according to claim 3, characterized in that: The continuous elimination decoding of the received channel signal includes: traversing the decoding tree diagram of the received signal based on the generator matrix of the multi-core polarization code until a decoding estimate value is obtained; wherein the generator matrix is composed of a 2-core matrix The n1-th Kronecker product of the 3-core matrix The n2 Kronecker product construction.

5. The multi-core polar code continuous bit flip elimination decoding method according to claim 4, characterized in that: The information bits in the key set are flipped a predetermined number of times according to the sorting result, including: the upper limit of the predetermined number of flips is the smaller value of the number of key set elements and the predetermined maximum number of flips, and each flip only flips the unflipped bit with the highest current sorting priority until the cyclic redundancy check passes or the upper limit of the flip number is reached.

6. The multi-core polar code continuous bit flip elimination decoding method according to claim 5, characterized in that: The step of generating a decoding tree diagram for a multi-core polar code and traversing nodes in the tree diagram layer by layer includes: identifying nodes in the decoding tree diagram as (ψ, t) by a layer number t and a subscript ψ, traversing the tree diagram in a top-to-bottom and left-to-right order, and characterizing bit channel reliabilities corresponding to the nodes by a mean value calculated by Gaussian approximation.

7. The multi-core polar code continuous bit flip elimination decoding method according to claim 6, characterized in that: The code length of the multi-core polar code Where n1 and n2 are the number of 2-core matrices and 3-core matrices respectively. K bits carrying information are concatenated with r cyclic redundancy check bits as the input vector u, the number of frozen bits is NKr, and the code rate of the multi-core polar code is 8. A multi-core polar code continuous elimination bit flip decoding device, characterized in that: include: The first main module is used to implement continuous elimination decoding of the received channel signal, obtain a decoding estimate, and perform a cyclic redundancy check. If the check passes, the decoding is successful; otherwise, the bit flipping stage begins. The second main module is used to construct a key set for the multi-core polar code, which contains the first information bit position with an error probability higher than a predetermined threshold in the continuous elimination decoding. The third main module is used to sort the bit positions in the key set using bit channel reliability estimation. The fourth main module is used to flip the information bits in the key set a predetermined number of times based on the sorting result, and re-execute continuous elimination decoding and cyclic redundancy check after each flip until the cyclic redundancy check passes or the predetermined upper limit of the flipping number is reached.

9. An electronic device, characterized in that: include: At least one processor, at least one memory and a communication interface; wherein, The processor, memory and communication interface communicate with each other; The memory stores program instructions that can be executed by the processor, and the processor calls the program instructions to execute the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores computer instructions, which cause a computer to execute the method of any one of claims 1 to 7.

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