Data acquisition system based on HPLC (High Performance Liquid Chromatography) chip

Abstract

The invention relates to a data acquisition system based on an HPLC (High Performance Liquid Chromatography) chip, and belongs to the technical field of power line carrier communication. According to the invention, the off-chip memory is arranged outside the HPLC chip, the memory control unit for controlling the off-chip memory is arranged in the HPLC chip, and the address and the control signal of the off-chip memory are generated by using the memory control unit, so that the ADC data provided by the analog front end are directly written into the off-chip memory, and when the ADC data needs to be processed, the ADC data can be directly written into the off-chip memory. And the memory control unit reads the corresponding ADC data from the off-chip memory based on the bus to be processed by a PC (Personal Computer). Therefore, the ADC data provided by the analog front end is directly written into the off-chip memory under the control of the memory control unit, and the ADC data of the HPLC can be directly stored by the off-chip memory without too many pins of the HPLC chip; the problem that an existing HPLC chip cannot be directly subjected to off-chip storage due to the fact that the number of pins is limited is solved.

Description

Technical Field

[0001] The invention relates to a data acquisition system based on an HPLC chip, and belongs to the technical field of power line carrier communication. Background Art

[0002] The HPLC (power carrier communication) chip has a certain amount of SRAM and FLASH inside as memory and program storage space. The ADC sampling data collected by the analog front end needs to be stored before subsequent processing, but the memory storage space is limited. Especially when the ADC sampling data needs to be stored and provided to the algorithm and software for simultaneous analysis, the memory cannot meet the demand. If the collected data is placed in the memory, the software program needs to be rewritten to reserve space for storing the OFDM data of the preamble, FC, and PB. In this way, only a small amount of data can be stored, not the complete frame, which has a great limitation on subsequent analysis problems.

[0003] In order not to affect the operation of the upper-layer software, it is necessary to expand the memory outside the HPLC chip (off-chip memory) to store the ADC sampling data in the off-chip memory. When the ADC sampling data is stored in the off-chip memory, the HPLC chip needs to be controlled. Due to the limited number of pins of the HPLC chip, and the SRAM interface is used as a debugging interface when data is collected and is not used normally, some peripheral interfaces can be reused and used when a debugging board is needed. If it is to be used as a necessary function, the package can also be made larger and all the interfaces can be brought out. The pins of the SRAM controller (the controller that controls the reading and writing of the off-chip memory) are all reused from the pins of other peripherals, so if you want to use the off-chip memory to store ADC data, you need to develop a separate test board, which increases the complexity of the solution and is also relatively costly. Summary of the Invention

[0004] The purpose of the present invention is to provide a data acquisition system based on HPLC chip to solve the problem that the current HPLC chip cannot directly perform off-chip storage due to the limited number of pins.

[0005] To solve the above-mentioned technical problems, the present invention provides a data acquisition system based on an HPLC chip, comprising a processor and an analog front end arranged in the HPLC chip, an off-chip memory arranged outside the HPLC chip, and a memory control unit arranged within the HPLC chip. The memory control unit is configured to generate an address and a control signal for the off-chip memory when it is necessary to write ADC data provided by the analog front end into the off-chip memory, and to directly write the ADC data provided by the analog front end into the off-chip memory using the generated address and control signal for the off-chip memory. When it is necessary to process the ADC data, the memory control unit reads the corresponding ADC data from the off-chip memory based on a bus for processing by a PC.

[0006] Furthermore, the memory control unit includes an ahb_mem_ctrl module and a sram_timing_gen module. The ahb_mem_ctrl module is used to obtain the ADC data to be written and generate the address and control signal of the off-chip memory to the sram_timing_gen module; the sram_timing_gen module is used to generate the timing of writing to the off-chip memory according to the received address and control signal of the external memory, and write the ADC data to be written into the off-chip memory according to the timing.

[0007] Furthermore, the memory control unit also includes an ahb_mux module, which is used to obtain instructions for reading / writing off-chip memory from the bus and send the bus address and control signal to the ahb_mem_ctrl module. The ahb_mem_ctrl module is used to convert the bus address and control signal into the address and control signal of the off-chip memory, and send the address and control signal of the off-chip memory to the sram_timing_gen module. The sram_timing_gen module generates corresponding read / write timing based on the configuration information and the address and control signal of the off-chip memory, and performs read / write operations on the off-chip memory according to the timing.

[0008] Furthermore, the configuration information is obtained by the ahb_cfg_reg module.

[0009] Furthermore, the configuration information includes write pulse width, number of clock cycles to maintain the address or data on the bus, number of clock cycles for address setup time, read cycle time, and number of clock cycles between read-to-write, write-to-read, and read-to-read of the static memory.

[0010] Furthermore, the HPLC chip further includes a synchronization module, and the synchronization module is used to synchronously process the ADC data to be written into the off-chip memory.

[0011] Furthermore, the memory control unit is used to perform initialization operations when an abnormality occurs in the HPLC, enable ADC write enable, store the data to be collected in the off-chip memory, turn off ADC write enable, and read the data written by the ADC into the off-chip memory and send it to the PC to determine whether there is a problem with the received frame.

[0012] Furthermore, the off-chip memory is SRAM.

[0013] The present invention has the following beneficial effects: As an improved invention, the present invention provides an off-chip memory outside the HPLC chip and a memory control unit for controlling the off-chip memory within the HPLC chip. The memory control unit generates the address and control signals of the off-chip memory to directly write the ADC data provided by the analog front end into the off-chip memory. When the ADC data needs to be processed, the memory control unit reads the corresponding ADC data from the off-chip memory via a bus for processing by the PC. Therefore, the present invention, through the control of the memory control unit, can directly write the ADC data provided by the analog front end into the off-chip memory. This eliminates the need for excessive pin count on the HPLC chip and allows the HPLC ADC data to be directly stored in the off-chip memory. This solves the problem that current HPLC chips cannot directly perform off-chip storage due to the limited number of pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a functional block diagram of the HPLC chip of the present invention;

[0015] Figure 2 This is a block diagram of the implementation of the memory control unit SRAM_CTRL provided in the HPLC chip of the present invention;

[0016] Figure 3 The present invention is a flowchart of the high-speed data acquisition system based on HPLC chip. DETAILED DESCRIPTION

[0017] The specific embodiments of the present invention are further described below with reference to the accompanying drawings. In currently used chips, the sram_ctrl interface is often multiplexed with other peripheral interfaces or test interfaces to meet requirements. The present invention provides an off-chip memory outside the HPLC chip and a memory control unit within the HPLC chip. The memory control unit generates the address and control signals for the off-chip memory, allowing the ADC data provided by the analog front end to be directly written into the off-chip memory. The present invention eliminates the need for an excessive number of pins on the HPLC chip and allows the off-chip memory to be used to store the HPLC ADC data. This solves the problem that current HPLC chips cannot directly perform off-chip storage due to the limited number of pins.

[0018] An embodiment of a data acquisition system based on HPLC chip

[0019] like Figure 1As shown, the high-speed data acquisition system based on the HPLC chip of the present invention includes a processor, a bus, an analog front end and a memory control unit arranged in the HPLC chip, wherein the analog front end AFE is used to obtain ADC data, and the memory control unit is used to generate an address and control signal of the off-chip memory when it is necessary to write the ADC data provided by the analog front end into the off-chip memory, and use the generated off-chip memory address and control signal to directly write the ADC data provided by the analog front end into the off-chip memory. When it is necessary to process the ADC data, the memory control unit reads the corresponding ADC data from the off-chip memory based on the bus for PC processing.

[0020] Since the off-chip memory in this embodiment is SRAM, the memory control unit is the SRAM_CTRL module, such as Figure 2 As shown, it includes an ahb_mem_ctrl module and a sram_timing_gen module. The ahb_mem_ctrl module is used to obtain the ADC data to be written and generate the address and control signal of the off-chip memory to the sram_timing_gen module. The sram_timing_gen module generates the timing for writing to the off-chip memory based on the received address and control signal of the external memory, and writes the ADC data to be written into the off-chip memory according to the timing. Sram has a base address in the system. When the CPU accesses Sram, it will send a bus command to the base address + offset address. Ahb_mem_ctrl calculates the location of the data in Sram based on the offset address, that is, the chip select and address of Sram. The specific calculation method is related to the data bit width of Sram. For example, to access 32-bit data with an offset address of 4 in the system, the second and third data of the 16-bit Sram must be accessed.

[0021] In addition to implementing the write function, it is also necessary to be able to read the ADC sampled data written to the off-chip memory and send it to the external PC, which then calls the relevant algorithm to process the ADC sampled data. The SRAM_CTRL module also includes the ahb_mux module. The ahb_mux module is used to obtain the read / write instruction of the off-chip memory from the bus. The instruction is issued by the master on the AHB matrix, such as the CPU or DMA, and sends the bus address and control signal to the ahb_mem_ctrl module. The ahb_mem_ctrl module is used to convert the bus address and control signal into the address and control signal of the off-chip memory, and send the address and control signal of the off-chip memory to the sram_timing_gen module. The sram_timing_gen module generates the corresponding read / write timing based on the configuration information and the address and control signal of the off-chip memory, and performs read / write operations on the off-chip memory according to the timing.

[0022] Specifically, if Figure 2 As shown, ahb_mux is the AHB module, adc_data_sync: ADC is the data synchronization module, ahb_cfg_reg is the AHB configuration register module, ahb_mem_ctrl is the AHB to MEM interface module, sram_timing_gen is the SRAM timing generation module, sram_addr is the SRAM address, sram_cs is the SRAM chip select valid, sram_lb indicates the SRAM low 8 bits are valid, sram_ub indicates the SRAM high 8 bits are valid, sram_oe indicates the SRAM output is valid, which is used to control the top-level IO data bus and input and output switching, sram_we is the SRAM write enable, sram_in_data indicates the SRAM input data, sram_out_data indicates the SRAM output data, ahb_bus is the AHB bus, adc_vld indicates the ADC input data is valid, and adc_data_in indicates the ADC sampling data. The SRAM_CTRL module also supports CPU read and write access, supports direct output of ADC sampling data, and supports external asynchronous SRAM interface. The external SRAM supports two speeds: 200MHz / 2 and 200MHz / 3. The address width is 24 bits (for a maximum of 16MB of SRAM) and the data width is 16 bits. The (fixed) AHB bus is aligned to 32 bits, with a data width of 16 bits. Therefore, each bus access requires two external SRAM accesses. The AHB master supports read and write access to the SRAM via the bus. Regarding performance, if the AHB bus clock is 200MHz, ADC data writes are supported at up to 200 / 3MHz, meeting the 50MHz ADC sampling data system requirement in HPLC.

[0023] The AHB bus accesses external SRAM as follows: The AHB bus initiates a 32-bit read or write instruction, which is sent to the ahb_mem_ctrl module via the ahb_mux. The ahb_mem_ctrl module converts the received AHB bus address and control signals into the SRAM address and control signals, and then sends one or two read or write operations to the sram_timing_gen module. The sram_timing_gen module is responsible for generating the timing for the corresponding SRAM device based on the configuration. Timing-related parameters include: tbta refers to the number of clock cycles between read-to-write, write-to-read, and read-to-read of the static memory; twp refers to the write pulse width; twr refers to the number of clock cycles to maintain the address or data on the bus; tas refers to the number of clock cycles for the address setup time; and trc refers to the read cycle time.

[0024] The process for writing ADC data directly into SRAM is as follows: ADC input data passes through the data synchronization module and is written to the ahb_mem_ctrl module. Then, the data is written sequentially according to the size of the external memory. Once the data is full, it restarts at address 0. The SRAM address and control signals are then sent to the sram_timing_gen module to generate the timing for the external SRAM. The ADC path only supports writing. Reading ADC data can be done via the AHB bus path.

[0025] Figure 3 This is the software usage process. When HPLC performance anomalies require data collection and reporting to the algorithm, SRAM_CTRL is initialized first. Then, ADC write is enabled based on the HPLC interrupt. After the required data collection is completed, the ADC write is disabled. The software reads the data written to SRAM by the ADC and sends it to the UART interface, which then sends it to the PC to determine if there is any problem with the received frame.

Claims

1. A data acquisition system based on an HPLC chip, comprising a processor and an analog front end arranged in the HPLC chip, characterized in that: It also includes an off-chip memory arranged outside the HPLC chip and a memory control unit arranged inside the HPLC chip. The memory control unit is used to generate an address and control signal of the off-chip memory when the ADC data provided by the analog front end needs to be written into the off-chip memory, and use the generated off-chip memory address and control signal to directly write the ADC data provided by the analog front end into the off-chip memory. When the ADC data needs to be processed, the memory control unit reads the corresponding ADC data from the off-chip memory based on the bus for PC processing.

2. The data acquisition system based on HPLC chip according to claim 1, characterized in that, The memory control unit includes an ahb_mem_ctrl module and a sram_timing_gen module. The ahb_mem_ctrl module is used to obtain the ADC data to be written and generate the address and control signal of the off-chip memory to the sram_timing_gen module; the sram_timing_gen module is used to generate the timing of writing to the off-chip memory according to the received address and control signal of the external memory, and write the ADC data to be written into the off-chip memory according to the timing.

3. The data acquisition system based on HPLC chip according to claim 2, characterized in that, The memory control unit also includes an ahb_mux module, which is used to obtain instructions for reading / writing off-chip memory from the bus and send the bus address and control signal to the ahb_mem_ctrl module. The ahb_mem_ctrl module is used to convert the bus address and control signal into the address and control signal of the off-chip memory, and send the address and control signal of the off-chip memory to the sram_timing_gen module. The sram_timing_gen module generates a corresponding read / write timing based on the configuration information and the address and control signal of the off-chip memory, and performs read / write operations on the off-chip memory according to the timing.

4. The data acquisition system based on HPLC chip according to claim 3, characterized in that, The configuration information is obtained by the ahb_cfg_reg module.

5. The data acquisition system based on HPLC chip according to claim 3, characterized in that, The configuration information includes write pulse width, clock cycles for maintaining the address or data on the bus, clock cycles for address setup time, read cycle time, and clock cycles between read-to-write, write-to-read, and read-to-read of the static memory.

6. The data acquisition system based on HPLC chip according to claim 1, characterized in that, The HPLC chip further comprises a synchronization module, which is used for synchronously processing the ADC data to be written into the off-chip memory.

7. The data acquisition system based on HPLC chip according to claim 1, characterized in that, The memory control unit is used to perform initialization operations when an abnormality occurs in the HPLC, enable ADC write enable, store the data to be collected in the off-chip memory, turn off ADC write enable, and read the data written by the ADC into the off-chip memory and send it to the PC to determine whether there is a problem with the received frame.

8. The data acquisition system based on HPLC chip according to claim 1, characterized in that, The off-chip memory is SRAM.

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