Solar cell and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a solar cell and a photovoltaic module, and the solar cell comprises a substrate which is provided with a first surface and a second surface which are opposite to each other in a first direction; the dielectric layer is located on at least one of the first surface and the second surface, the dielectric layer comprises a plurality of pores, and at least part of the pores penetrate through the dielectric layer in the first direction; the doping layer is located on the side, away from the substrate, of the dielectric layer; wherein the transmission path of the current carrier passing through the substrate, the dielectric layer and the doping layer along the first direction is a reference transmission path, and the transmission resistance corresponding to the reference transmission path in at least part of the solar cell rises along with the rise of the temperature of the solar cell. According to the embodiment of the invention, the method at least facilitates the higher transmission efficiency of the carriers at a lower temperature, and facilitates the reduction of the thermal runaway risk of the solar cell through the inhibition of the transmission efficiency of the carriers at a higher temperature.

Description

Technical Field

[0001] The present application relates to the field of photovoltaics, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells are becoming increasingly popular as a sustainable, clean energy source. A solar cell utilizes the photovoltaic principle to generate charge carriers, converting sunlight into electricity. Grid lines are typically used in solar cells to extract these charge carriers, effectively utilizing the electrical energy. Current mainstream solar cell types include BC cells (back contact), TOPCON (tunnel oxide passive contact), PERC cells (passivated emitter and real cell), and heterojunction cells.

[0003] However, in the current passivation contact structure of solar cells that includes a tunneling layer, the carrier transmission mechanism in the tunneling layer is mainly quantum tunneling transmission. Therefore, when preparing the tunneling layer, its thickness and uniformity are required to be extremely high, which poses great challenges to the process and equipment. Summary of the Invention

[0004] The embodiments of the present application provide a solar cell and a photovoltaic module, which are at least beneficial for achieving higher carrier transmission efficiency at lower temperatures, and are beneficial for reducing the risk of thermal runaway of the solar cell by leveraging the characteristic that the carrier transmission efficiency is suppressed at higher temperatures.

[0005] According to some embodiments of the present application, on one hand, the embodiments of the present application provide a solar cell, comprising: a substrate, the substrate having a first surface and a second surface opposite to each other along a first direction; a dielectric layer, located on at least one of the first surface and the second surface, the dielectric layer comprising a plurality of pores, at least a portion of the pores penetrating the dielectric layer along the first direction; a doping layer, located on a side of the dielectric layer away from the substrate; wherein a transmission path of carriers along the first direction through the substrate, the dielectric layer and the doping layer is a reference transmission path, and the transmission resistance corresponding to the reference transmission path in at least part of the solar cell increases with an increase in the temperature of the solar cell.

[0006] In some embodiments, the dielectric layer includes a first dielectric layer, the doping layer includes a first doping layer located on a side of the first dielectric layer away from the substrate; the first doping layer and the substrate contain doping elements with different conductivity types; the transmission path of the carrier along the first direction in the substrate, the first dielectric layer and the first doping layer is one of the reference transmission paths.

[0007] In some embodiments, the dielectric layer includes a second dielectric layer; the doping layer includes a second doping layer located on a side of the second dielectric layer away from the substrate, and the second doping layer and the substrate have doping elements of the same conductivity type; the transmission path of the carrier along the first direction in the substrate, the second dielectric layer and the second doping layer is one of the reference transmission paths.

[0008] In some embodiments, at least one of the first surface and the second surface of the substrate has a first region and a second region alternately arranged along a second direction; the second dielectric layer and the second doped layer are located in the first region; or, the second dielectric layer and the second doped layer are located in the first region and the second region at the same time.

[0009] In some embodiments, a diffusion layer is further provided between the substrate and the dielectric layer, and the diffusion layer and the doping layer contain doping elements of the same conductivity type.

[0010] In some embodiments, the doping concentration of the doping element in the diffusion layer is 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 .

[0011] In some embodiments, the first surface or the second surface is a back surface, and the back surface has a first field region and a second field region arranged alternately along the second direction; wherein, the dielectric layer includes a third dielectric layer located on the first field region, the doping layer includes a third doping layer located on the first field region, the third doping layer and the substrate have doping elements of the same conductivity type, and the transmission path of the carriers along the first direction in the substrate, the third dielectric layer and the third doping layer is one of the reference transmission paths; and / or, the dielectric layer includes a fourth dielectric layer located on the second field region, the doping layer includes a fourth doping layer located on the second field region, the fourth doping layer and the substrate have doping elements of different conductivity types, and the transmission path of the carriers along the first direction in the substrate, the fourth dielectric layer and the fourth doping layer is one of the reference transmission paths.

[0012] In some embodiments, an isolation region is provided between the first field region and the second field region.

[0013] In some embodiments, the material of the dielectric layer includes one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; and / or, the material of the dielectric layer includes one or more of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0014] In some embodiments, the pores in the dielectric layer are formed by heat treatment, the process temperature used in the heat treatment is 800° C. to 1100° C., and the treatment time of the heat treatment is 20 min to 60 min.

[0015] In some embodiments, the dielectric layer includes a first portion and a second portion alternately and irregularly arranged along a direction perpendicular to the first direction, the pores are located in the first portion, and the current density in the first portion is greater than the current density in the second portion.

[0016] In some embodiments, a ratio of the current density in the first portion to the current density in the second portion is greater than or equal to 10.

[0017] In some embodiments, the arrangement density of the pores in the dielectric layer is 1×10 6 pieces / cm 2 ~1×10 8 pieces / cm 2 .

[0018] In some embodiments, the reference transmission path includes a first reference transmission path and a second reference transmission path, wherein the transmission path of the carriers through the substrate, the first portion and the doping layer is the first reference transmission path; and / or, the transmission path of the carriers through the substrate, the second portion and the doping layer is the second reference transmission path.

[0019] In some embodiments, the transmission resistance corresponding to the first reference transmission path increases as the temperature of the solar cell increases; and / or the transmission resistance corresponding to the second reference transmission path decreases as the temperature of the solar cell increases.

[0020] In some embodiments, the impedance corresponding to the reference transmission path is 0.05 mΩ·cm 2 ~1.4mΩ·cm 2 .

[0021] In some embodiments, at least a portion of the pores accommodate the substrate and / or the doping layer; and / or at least a portion of the pores have air gaps therein.

[0022] In some embodiments, the temperature range of the dielectric layer is -50°C to 150°C.

[0023] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a solar cell, comprising: a substrate, the substrate having a first surface and a second surface opposite to each other along a first direction; a dielectric layer, located on at least one of the first surface and the second surface, the dielectric layer comprising a plurality of pores, at least a portion of the pores penetrating the dielectric layer along the first direction; a doping layer, located on a side of the dielectric layer away from the substrate; wherein, carriers are transmitted along the first direction through the substrate and the dielectric layer to the doping layer, and the transmission efficiency of the carriers in at least a portion of the dielectric layer decreases as the temperature of the dielectric layer increases.

[0024] In some embodiments, the dielectric layer includes a first dielectric layer, and the doping layer includes a first doping layer located on a side of the first dielectric layer away from the substrate; the first doping layer and the substrate have doping elements with different conductivity types; and minority carriers among the carriers are transmitted along the first direction through the substrate and the first dielectric layer to the first doping layer.

[0025] In some embodiments, the dielectric layer includes a second dielectric layer; the doping layer includes a second doping layer located on a side of the second dielectric layer away from the substrate, and the second doping layer and the substrate have doping elements of the same conductivity type; the majority carriers among the carriers are transmitted along the first direction through the substrate and the second dielectric layer to the second doping layer.

[0026] In some embodiments, at least one of the first surface and the second surface has a first region and a second region alternately arranged along a second direction; the second dielectric layer and the second doped layer are located on the first region; or, the second dielectric layer and the second doped layer are located in the first region and the second region at the same time.

[0027] In some embodiments, a diffusion layer is further provided between the substrate and the dielectric layer, and the diffusion layer and the doping layer contain doping elements of the same conductivity type.

[0028] In some embodiments, the doping concentration of the doping element in the diffusion layer is 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 .

[0029] In some embodiments, the first surface or the second surface is a back surface, and the back surface has a first field region and a second field region arranged alternately along the second direction; wherein the dielectric layer includes a third dielectric layer located on the first field region, the doping layer includes a third doping layer located on the first field region, the third doping layer and the substrate have doping elements of the same conductivity type, and the majority carriers of the carriers are transmitted to the third doping layer along the first direction via the substrate and the third dielectric layer; and / or, the dielectric layer includes a fourth dielectric layer located on the second field region, the doping layer includes a fourth doping layer located on the second field region, the fourth doping layer and the substrate have doping elements of different conductivity types, and the minority carriers of the carriers are transmitted to the fourth doping layer along the first direction via the substrate and the fourth dielectric layer.

[0030] In some embodiments, an isolation region is provided between the first field region and the second field region.

[0031] In some embodiments, the material of the dielectric layer includes one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; and / or, the material of the dielectric layer includes one or more of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0032] In some embodiments, the pores in the dielectric layer are formed by heat treatment, the process temperature used in the heat treatment is 800° C. to 1100° C., and the treatment time of the heat treatment is 20 min to 60 min.

[0033] In some embodiments, the dielectric layer includes a first portion and a second portion alternately and irregularly arranged along a direction perpendicular to the first direction, and in the first portion of the pore, a current density in the first portion is greater than a current density in the second portion.

[0034] In some embodiments, a ratio of the current density in the first portion to the current density in the second portion is greater than or equal to 10.

[0035] In some embodiments, the arrangement density of the pores in the dielectric layer is 1×10 6 pieces / cm 2 ~1×10 8 pieces / cm 2 .

[0036] In some embodiments, the transmission path of the carrier along the first direction through the substrate, the dielectric layer and the doping layer is a reference transmission path, and the impedance corresponding to the reference transmission path is 0.05 mΩ·cm 2 ~1.4mΩ·cm 2 .

[0037] In some embodiments, the transmission path of the carriers along the first direction through the substrate, the dielectric layer and the doping layer is a reference transmission path, and the reference transmission path includes a first reference transmission path and a second reference transmission path, wherein the transmission path of the carriers through the substrate, the first portion and the doping layer is the first reference transmission path; and / or, the transmission path of the carriers through the substrate, the second portion and the doping layer is the second reference transmission path.

[0038] In some embodiments, the transmission resistance corresponding to the first reference transmission path increases as the temperature of the solar cell increases; and / or the transmission resistance corresponding to the second reference transmission path decreases as the temperature of the solar cell increases.

[0039] In some embodiments, at least a portion of the pores accommodate the substrate and / or the doping layer; and / or at least a portion of the pores have air gaps therein.

[0040] In some embodiments, at least one of the first surface and the second surface has a first region and a second region alternately arranged along a second direction; and the dielectric layer and the doping layer are located on the first region.

[0041] In some embodiments, the temperature range of the dielectric layer is -50°C to 150°C.

[0042] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a photovoltaic assembly, comprising: a cell string, formed by connecting a plurality of solar cells as described in any one of the above items; a packaging film, used to cover the surface of the cell string; and a cover plate, used to cover the surface of the packaging film facing away from the cell string.

[0043] The technical solution provided by the embodiments of the present application has at least the following advantages: The dielectric layer is designed to include a plurality of pores, with at least some of the pores extending through the dielectric layer in a first direction. This improves the carrier transport mechanism in the dielectric layer, so that the carrier transport mechanism in the dielectric layer is primarily achieved through the pores. This helps reduce the reliance of carriers on the quantum tunneling effect during transport in the dielectric layer, thereby reducing the requirements for the thickness of the dielectric layer and thereby increasing the thickness fluctuation range of the dielectric layer. Furthermore, the majority of the dielectric layer without pores ensures that the dielectric layer has good passivation properties relative to the substrate.

[0044] Furthermore, the transmission resistance corresponding to the reference transmission path in at least some solar cells increases as the temperature of the solar cell increases. Thus, on the one hand, even if the temperature of the dielectric layer is low, the transmission resistance corresponding to the reference transmission path is also low, that is, the carriers have a high transmission efficiency in the dielectric layer, which helps ensure that the solar cell has a high photoelectric conversion efficiency even at low temperatures. On the other hand, if the temperature of the dielectric layer increases, the transmission resistance corresponding to the reference transmission path increases, that is, the carrier transmission efficiency is suppressed at high temperatures, which can reduce the current in the local area of the solar cell, thereby helping to reduce the risk of thermal runaway of the solar cell. On the other hand, if the temperature of a local area of the solar cell increases, resulting in an increase in the transmission resistance corresponding to the reference transmission path in the local area, that is, resulting in a decrease in the carrier transmission efficiency in the local area, the carriers in the local area tend to be transmitted laterally to other areas with lower temperatures, and then transmitted to the doped layer through the dielectric layer. This helps to reduce the number of carriers concentrated in the local high-temperature area of the solar cell. By leveraging the temperature difference and the increase in the transmission resistance corresponding to the reference transmission path in the high-temperature area of the solar cell, the uniform distribution of current in the solar cell is promoted, further reducing the risk of thermal runaway of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A first cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 2 A partially enlarged cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 3 A schematic top view of a dielectric layer in a solar cell provided in one embodiment of the present application; Figure 4 A comparison chart of dielectric layer-related properties in three different solar cells provided in an embodiment of the present application; Figure 5 A second cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 6Another partially enlarged cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 7 A schematic partial enlarged cross-sectional view of another embodiment of the solar cell provided in the present application; Figure 8 A third cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 9 A fourth cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 10 A fifth cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 11 A partial top view schematic diagram of a test structure obtained by cutting from a solar cell according to an embodiment of the present application; Figure 12 A sixth cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 13 A seventh cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 14 A line graph showing the change in transfer resistance versus temperature in two different solar cells provided in an embodiment of the present application; Figure 15 This is an eighth cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 16 A ninth cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 17 A schematic cross-sectional view of a substrate in a method for manufacturing a solar cell provided in another embodiment of the present application; Figure 18 An enlarged cross-sectional schematic diagram of a method for manufacturing a solar cell provided by another embodiment of the present application after an initial dielectric layer and an initial doping layer are formed on the first surface; Figure 19 Another enlarged cross-sectional schematic diagram after forming an initial dielectric layer and an initial doping layer on the first surface in the method for manufacturing a solar cell provided by another embodiment of the present application; Figure 20 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in another embodiment of the present application; Figure 21 A partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present application.

[0047] Description of reference numerals: 100, substrate; 100a, first surface; 100b, second surface; 110, first part; 120, second part; 130, first metal area; 140, first non-metal area; 150, second metal area; 160, second non-metal area; 35, first area; 46, second area; 101, dielectric layer; 111, pores; 121, initial dielectric layer; 102, doping layer; 112, initial doping layer; 103, diffusion layer; 104, electrode; 40, solar cell; 41, encapsulation film; 42, cover; 43, conductive tape. DETAILED DESCRIPTION

[0048] As known from the background art, the carrier transport mechanism in the dielectric layer needs to be improved.

[0049] Analysis revealed that, given that the primary mechanism of carrier transmission in the dielectric layer is quantum tunneling, the thickness of the dielectric layer significantly influences the efficiency of carrier transmission within the dielectric layer. Specifically, excessively thick dielectric layers can reduce the probability of carrier tunneling within the dielectric layer, leading to poor contact between the dielectric layer and the substrate. Excessively thin dielectric layers can lead to imperfect passivation of the dielectric layer at its interface with the substrate, imperfecting the dielectric layer's passivation performance. Generally, to achieve optimal passivation contact performance, the dielectric layer's thickness must be kept within a range of 0.2 nm, posing significant challenges to both process and equipment.

[0050] Furthermore, since the carrier transmission mechanism in the dielectric layer is primarily quantum tunneling, the probability of carrier tunneling in the dielectric layer increases with the temperature of the dielectric layer. In other words, the transmission resistance corresponding to carrier transmission in the dielectric layer decreases as the temperature of the dielectric layer increases. As the temperature of the dielectric layer rises, the transmission resistance corresponding to carrier transmission in the dielectric layer decreases, making it easier for carriers to pass through the dielectric layer to other film layers via quantum tunneling.

[0051] It is understandable that as the temperature of the dielectric layer increases, the number of carriers passing through the dielectric layer through the quantum tunneling transmission mechanism per unit time increases, which will increase the current in the local area of the solar cell. As the temperature and current increase simultaneously, the risk of thermal runaway of the solar cell will increase.

[0052] An embodiment of the present application provides a solar cell and a photovoltaic module. In the solar cell, a dielectric layer is designed to include multiple pores, and at least a portion of the pores penetrate the dielectric layer along a first direction. In this way, the carrier transmission mechanism in the dielectric layer can be improved, so that the carrier transmission mechanism in the dielectric layer is mainly achieved by transmission through the pores, which is beneficial to reducing the dependence of carriers on the quantum tunneling effect when transmitting in the dielectric layer, thereby reducing the requirements for the thickness of the dielectric layer, and thus facilitating an increase in the thickness fluctuation range of the dielectric layer. At the same time, the majority of the portion of the dielectric layer where pores are not formed can ensure that the dielectric layer has good passivation performance with respect to the substrate. Furthermore, the transmission resistance corresponding to the reference transmission path in at least some solar cells increases as the temperature of the solar cell increases. Thus, on the one hand, even if the temperature of the dielectric layer is low, the transmission resistance corresponding to the reference transmission path is also low, that is, the carriers have a high transmission efficiency in the dielectric layer, which helps ensure that the solar cell has a high photoelectric conversion efficiency even at low temperatures. On the other hand, if the temperature of the dielectric layer increases, the transmission resistance corresponding to the reference transmission path increases, that is, the carrier transmission efficiency is suppressed at high temperatures, which can reduce the current in the local area of the solar cell, thereby helping to reduce the risk of thermal runaway of the solar cell. On the other hand, if the temperature of a local area of the solar cell increases, resulting in an increase in the transmission resistance corresponding to the reference transmission path in the local area, that is, when the carrier transmission efficiency in the local area decreases, the carriers in the local area tend to be transmitted laterally to other areas with lower temperatures, and then transmitted to the doped layer through the dielectric layer. This helps to reduce the number of carriers concentrated in the local high-temperature area of the solar cell. By leveraging the temperature difference and the increase in the transmission resistance corresponding to the reference transmission path in the high-temperature area of the solar cell, the uniform distribution of current in the solar cell is promoted, further reducing the risk of thermal runaway of the solar cell.

[0053] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0054] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0055] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0056] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0057] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0058] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0059] In the accompanying drawings corresponding to the embodiments of the present application, the thickness and area of the layers are exaggerated for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) as being on or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. Conversely, when describing a component as being on the surface of another component, or when describing a component as being formed or disposed on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0060] In the description of the embodiments of this application, when a component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them) or another component can be present between them. In addition, when a component such as a layer, film, region, or plate is "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located between them.

[0061] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0062] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to help readers better understand the embodiments of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present application can still be implemented.

[0063] An embodiment of the present application provides a solar cell, which will be described in detail below with reference to the accompanying drawings.

[0064] refer to Figures 1 to 3 The solar cell includes: a substrate 100 having a first surface 100a and a second surface 100b opposite to each other along a first direction X; a dielectric layer 101 located on at least one of the first surface 100a and the second surface 100b, the dielectric layer 101 including a plurality of pores 111, at least some of the pores 111 penetrating the dielectric layer 101 along the first direction X; and a doped layer 102 located on a side of the dielectric layer 101 away from the substrate 100. A carrier transmission path along the first direction X through the substrate 100, the dielectric layer 101, and the doped layer 102 is a reference transmission path, and a transmission resistance corresponding to the reference transmission path in at least some solar cells increases as the temperature of the solar cell increases.

[0065] in, Figure 1 A first cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 2 A partially enlarged cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 3A schematic top view of a dielectric layer in a solar cell provided in one embodiment of the present application.

[0066] It should be noted that Figure 1 In the example, the dielectric layer 101 is located on both the first surface 100a and the second surface 100b. In actual applications, the dielectric layer can be located only on the first surface or only on the second surface. Various situations will be described in detail later. Figure 3 In the figure, the first portion 110 and the second portion 120 in the dielectric layer 101 are divided by dashed boxes of different shapes.

[0067] It is worth noting that, first, the dielectric layer 101 is designed to include a plurality of pores 111, with at least a portion of the pores 111 penetrating the dielectric layer 101 along the first direction X. This improves the carrier transport mechanism in the dielectric layer. Specifically, the carrier transport mechanism in the dielectric layer 101 is primarily based on transport via the pores 111. In other words, most carriers are transported to the doped layer 102 via the substrate 100 and the portion of the dielectric layer 101 having the pores 111. For example, carriers can be directly transported to the doped layer 102 via the pores 111, while some carriers are transported to the doped layer 102 via the portion of the dielectric layer 101 not having the pores 111 via quantum tunneling. The portion of the dielectric layer 101 having the pores 111 is the first portion 110, which will be described in detail later.

[0068] Furthermore, the transmission resistance corresponding to the reference transmission path in at least some solar cells increases as the temperature of the solar cells increases, which will cause the transmission efficiency of the carriers in the dielectric layer 101 to decrease as the temperature of the dielectric layer 101 increases. In this way, on the one hand, even if the temperature of the dielectric layer 101 is low, the transmission resistance corresponding to the reference transmission path is also low, that is, the carriers have a high transmission efficiency in the dielectric layer 101, which is conducive to ensuring that the solar cell has a high photoelectric conversion efficiency at a low temperature; on the other hand, if the temperature of the dielectric layer 101 increases, the transmission resistance corresponding to the reference transmission path increases, that is, the characteristic that the transmission efficiency of the carriers is suppressed at a higher temperature, which can reduce the transmission efficiency of the carriers transmitted from the dielectric layer 101 to the doping layer 101 per unit time. 2, thereby reducing the current in some areas of the solar cell, thereby helping to reduce the risk of thermal runaway of the solar cell. On the other hand, if the temperature of a local area of the solar cell rises, causing the transmission resistance corresponding to the reference transmission path in the local area to increase, that is, causing the carrier transmission efficiency in the local area to decrease, the carriers in the local area will tend to be transmitted laterally to other areas with lower temperatures, and then transmitted to the doping layer 102 through the dielectric layer 101. This helps to reduce the number of carriers concentrated in the local high-temperature area of the solar cell. By leveraging the temperature difference and the increase in the transmission resistance corresponding to the reference transmission path in the high-temperature area of the solar cell, the current in the solar cell is uniformly distributed, thereby further reducing the risk of thermal runaway of the solar cell. Therefore, it is beneficial to ensure that the solar cell has a high photoelectric conversion efficiency at a lower temperature while reducing the risk of thermal runaway of the solar cell, thereby avoiding performance degradation of the solar cell due to local overheating.

[0069] Furthermore, since the carrier transport mechanism in the dielectric layer 101 is primarily achieved through the pores 111, the carrier transport in the dielectric layer 101 is less dependent on the quantum tunneling effect, which helps reduce the thickness requirements for the dielectric layer 101. In other words, the change in the transmission resistance corresponding to the reference transmission path is less affected by the quantum tunneling effect. That is, the carrier transmission efficiency in the dielectric layer 101 is less affected by the quantum tunneling effect, and its sensitivity to the thickness of the dielectric layer 101 is reduced. Even if the dielectric layer 101 is thick, the carriers can still reduce the transmission resistance corresponding to the reference transmission path by virtue of the pores 111. That is, the carriers have good transmission efficiency in the dielectric layer 101, which helps increase the thickness fluctuation range of the dielectric layer 101, that is, expand the process window for manufacturing the dielectric layer 101. Moreover, the majority of the dielectric layer 101 without the pores 111, namely the second portion 120 (described in detail later), ensures that the dielectric layer 101 has good passivation properties with respect to the substrate 100.

[0070] It should be noted that, in practical applications, the temperature of a solar cell is generally the temperature of the dielectric layer 101 in the solar cell. Furthermore, a detailed description will be provided later on the carrier transmission mechanism in the dielectric layer 101, which primarily utilizes the pores 111 for transmission. The description will also include the fact that the transmission resistance corresponding to the reference transmission path in at least some solar cells increases with increasing solar cell temperature, i.e., that the carrier transmission efficiency in the dielectric layer 101 decreases with increasing temperature of the dielectric layer 101.

[0071] It is worth noting that the reference Figures 1 to 3 The carrier transmission path along the first direction X through the substrate 100, the dielectric layer 101, and the doped layer 102 is a reference transmission path. In the carrier transmission path along the first direction X through the substrate 100, the dielectric layer 101, and the doped layer 102, due to the insulation properties of the dielectric layer 101, the carrier transmission is primarily hindered by the dielectric layer 101. On this basis, the carrier transmission efficiency in the dielectric layer 101 decreases as the temperature of the dielectric layer 101 increases. As the temperature increases, the carriers encounter greater resistance in the reference transmission path, resulting in a greater transmission resistance corresponding to the reference transmission path. Consequently, the transmission resistance corresponding to the reference transmission path increases as the temperature of the solar cell increases. In other words, the transmission efficiency of carriers in the dielectric layer 101 decreases as the temperature of the dielectric layer 101 increases, and the transmission resistance corresponding to the reference transmission path increases as the temperature of the solar cell increases; vice versa, the transmission efficiency of carriers in the dielectric layer 101 increases as the temperature of the dielectric layer 101 decreases, and the transmission resistance corresponding to the reference transmission path decreases as the temperature of the solar cell decreases.

[0072] In some embodiments, the temperature range of the dielectric layer 101, that is, the temperature of the solar cell, can be -50°C to 150°C. For example, it can be -45°C, -40°C, -35°C, -30°C, -25°C, -20°C, -15°C, -10°C, -5°C, 0°C, 5°C, 10°C, 15°C, 20°C, 25°C, 30°C, 35°C, 40°C, 45°C, 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C, 85°C, 90°C, 95°C, 100°C, 105°C, 110°C, 115°C, 120°C, 125°C, 130°C, 135°C, 140°C or 145°C, etc.

[0073] The positional relationship between the pores 111 , the substrate 100 , and the doping layer 102 will be described in detail below.

[0074] In some embodiments, reference Figure 6 or Figure 7At least a portion of the pores 111 accommodates the substrate 100 and / or the doping layer 102 .

[0075] in, Figure 6 Another partially enlarged cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 7 This is another enlarged cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application. In some examples, reference Figure 6 or Figure 7 One pore 111 can contain the substrate 100 and be completely filled with it; another pore 111 can contain the doped layer 102 and be completely filled with it; and yet another pore 111 can be completely filled with both the substrate 100 and the doped layer 102. As a result, the doped layer 102 in the areas where these pores 111 are located can be in contact with the substrate 100. Therefore, carriers are more likely to gather in the areas where the pores 111 are located, where the impedance is relatively low, than in the areas with the dielectric layer 101. In other words, the pores 111 provide a new transmission path for carriers besides quantum tunneling.

[0076] It should be noted that the filling conditions of the substrate 100 and the doping layer 102 in different pores 111 in the same dielectric layer 101 may be the same or different.

[0077] In other embodiments, reference Figure 2 、 Figure 6 or Figure 7 , there may also be air gaps in at least a portion of the pores 111. In other words, there are spaces in at least a portion of the pores 111 that are not filled by the substrate 100 or the doping layer 102.

[0078] In some embodiments, reference Figure 3 The dielectric layer 101 includes first portions 110 and second portions 120 that are alternately and irregularly arranged along a direction perpendicular to the first direction X. The pores 111 are located in the first portions 110. During carrier transmission, the current density in the first portions 110 is greater than the current density in the second portions 120. In other words, the dielectric layer 101 includes a plurality of first portions 110 that are arranged at intervals. The second portions 120 wrap around the outer wall of each first portion 110 that extends along the first direction X. The arrangement of the plurality of first portions 110 along the direction perpendicular to the first direction X can be irregular, with random intervals.

[0079] It should be noted that Figure 3 In the figure, the dielectric layer 101 is divided into a first portion 110 and a second portion 120 by a dotted line.

[0080] It is worth noting that for the pores 111 that penetrate the dielectric layer 101 along the first direction X and are filled with the substrate 100 and / or the doped layer 102, carriers can be directly transmitted from the substrate 100 through the pores 111 in the first portion 110 through the dielectric layer 101 to the doped layer 102 without relying on the quantum tunneling effect. For the pores 111 that do not penetrate the dielectric layer 101 along the first direction X, the pores 111 are generally filled with the substrate 100 or the doped layer 102. Moreover, the portion of the dielectric layer 101 that directly faces the pores 111 along the first direction X is thinner than other portions of the dielectric layer 101. Therefore, carriers are more likely to pass through the thinner portion of the dielectric layer 101 based on the quantum tunneling effect and ultimately be transmitted to the doped layer 102. Moreover, due to the thinning of the thickness, the electric field strength constructed in the portion of the dielectric layer 101 near the pores 111 is higher, which has a stronger driving effect on the tunneling of carriers. Therefore, based on the coordination of various aspects, compared with the portion of the dielectric layer 101 without the pore 111, that is, the second portion 120, the portion of the first portion 110 located near the pore 111 has a smaller obstruction effect on the transmission of carriers along the first direction X, which can improve the efficiency of carriers passing through the dielectric layer 101. That is, more carriers can pass through the dielectric layer 101 per unit time, which is conducive to allowing more carriers to gather on the substrate 100 and pass through the dielectric layer 101 with the help of the pore 111.

[0081] Based on this, in the solar cell, the reference transmission path includes a first reference transmission path and a second reference transmission path. Among them, the transmission path of the carriers through the substrate 100, the first part 110 and the doping layer 102 is the first reference transmission path, and the transmission path of the carriers through the substrate 100, the second part 120 and the doping layer 102 is the second reference transmission path. Since the pores 111 are located in the first part 110 of the dielectric layer 101, most of the carriers pass through the dielectric layer 101 directly through the pores 111 that penetrate the dielectric layer 101. In other words, since the pores 111 that penetrate the dielectric layer 101 are filled with the substrate 100 and / or the doping layer 102, the carriers do not need to pass through the dielectric layer 101 for quantum tunneling, and can be directly transmitted between the substrate 100 and the doping layer 102. Of course, for some of the pores 111 that do not penetrate the dielectric layer 101, due to their thin thickness, carriers can still be transmitted through the quantum tunneling effect. In other words, the first reference transmission path primarily transmits carriers through the pores 111. However, due to the structural differences between the different pores 111, the first reference transmission path includes at least two carrier transmission modes. Compared with the quantum tunneling effect transmission mode, the primary carrier transmission mode is transmission through the pores 111 that penetrate the dielectric layer 101. Therefore, the transmission resistance corresponding to the first reference transmission path increases with the temperature of the solar cell. In contrast, the second portion 120 does not have pores. Although a large number of carriers will accumulate in the first portion 110, some carriers will still pass through the dielectric layer 101 through the quantum tunneling effect. In other words, the carrier transmission mode of the second reference transmission path is quantum tunneling transmission. Therefore, the transmission resistance corresponding to the second reference transmission path decreases with the temperature of the solar cell. Because the majority of carriers accumulate in the first portion, the pore transmission mode has a greater impact on the carriers than the quantum tunneling effect.

[0082] In some cases, a ratio of the current density in first portion 110 to the current density in second portion 120 may be greater than or equal to 10.

[0083] It is worth noting that, based on the effect of the pores 111 in the dielectric layer 101 on improving the efficiency of carriers passing through the dielectric layer 101, not only will the photogenerated carriers located in the corresponding area of the first part 110 be gathered at the pores 111, but the photogenerated carriers located in the corresponding area of the second part 120 and close to the first part 110 will also be first transmitted laterally along the second direction Y to the corresponding area of the first part 110, and finally transmitted with the help of the pores 111. Some carriers will still gather in the corresponding area of the second part 120 and pass through the dielectric layer 101 with the help of the quantum tunneling effect, so that the current density in the first part 110 and the current density in the second part 120 have a large difference, and generally the ratio of the two will be greater than or equal to 10.

[0084] In some embodiments, reference Figures 1 to 3 The arrangement density of the pores 111 in the dielectric layer 101 can be 1×10 6 pieces / cm 2 ~1×10 8 pieces / cm 2 , for example, it can be 2×10 6 pieces / cm 2 , 3×10 6 pieces / cm 2 , 4×10 6 pieces / cm 2 , 5×10 6 pieces / cm 2 , 6×10 6 pieces / cm 2 , 7×10 6 pieces / cm 2 , 8×10 6 pieces / cm 2 , 9×10 6 pieces / cm 2 , 1×10 7 pieces / cm 2 , 2×10 7 pieces / cm 2 , 3×10 7 pieces / cm 2 , 4×10 7 pieces / cm 2 , 5×10 7 pieces / cm 2 , 6×10 7 pieces / cm 2 , 7×10 7 pieces / cm 2 , 8×10 7 pieces / cm 2 or 9×10 7 pieces / cm 2 wait.

[0085] It is worth noting that, combined with reference Figure 4 As shown in Table 1, if the arrangement density of the pores 111 in the dielectric layer 101 is less than 1×10 6 pieces / cm 2 The number of pores 111 arranged per unit area in the dielectric layer 101 is small, and the effect of improving the transmission efficiency of carriers in the dielectric layer 101 is general. For example, based on the sparse arrangement of the pores 111, a large number of carriers still pass through the dielectric layer 101 by means of the quantum tunneling effect, which easily leads to a decrease in the filling factor of the solar cell. If the arrangement density of the pores 111 in the dielectric layer 101 is greater than 1×10 8 pieces / cm 2The number of pores 111 arranged per unit area in the dielectric layer 101 is large, which will reduce the passivation effect of the dielectric layer 101 on the substrate 100. Although the fill factor of the solar cell is improved, the open circuit voltage of the solar cell will be reduced. Therefore, the arrangement density of the pores 111 in the dielectric layer 101 is designed to be 1×10 6 pieces / cm 2 ~1×10 8 pieces / cm 2 It is not only beneficial to improve the carrier transmission efficiency in the dielectric layer 101 by means of the pores 111 with appropriate arrangement density, thereby improving the fill factor of the solar cell, but also beneficial to ensure that the dielectric layer 101 has a good passivation effect on the substrate 100, thereby reducing the defect state density at the contact point between the substrate 100 and the dielectric layer 101, thereby ensuring that the solar cell has a higher open circuit voltage, thereby maintaining the photoelectric conversion efficiency of the solar cell at a higher level.

[0086] Table 1: Fill factors of three different solar cells

[0087] It should be noted that Figure 4 This is a comparison diagram of the dielectric layer related characteristics of three different solar cells provided in an embodiment of the present application. Figure 4 The three pictures in the figure correspond to the etching pit traces caused by pores in the dielectric layer of three different solar cells. Figure 4 The box plots below the three images correspond to the impedance values of the reference transmission paths in three different solar cells. Specifically, Figure 4 The three pictures respectively illustrate etching of three different solar cells. When etching to the dielectric layer 101, the etching pits caused by the pores 111 can be used to characterize the arrangement density of the pores 111 in the dielectric layer 101. Figure 4 The three box plots corresponding to the three different solar cells can respectively illustrate the impedance values corresponding to the reference transmission paths, and thus can represent the efficiency of carrier transmission in the dielectric layer 101. In addition, Table 1 shows the fill factors corresponding to the three different solar cells.

[0088] In some cases, the solar cell may be firstly subjected to acid etching, for example, using hydrofluoric acid to remove other dielectric layers, such as the silicon nitride layer, located on the surface of the dielectric layer 101; and then the solar cell may be subjected to alkaline etching to expose the pores 111 in the dielectric layer 101, so as to finally observe the pores 111 under a microscope. Figure 3 or Figure 4 The etch pit traces caused by the pores 111 are shown.

[0089] In some embodiments, reference Figures 1 to 3 The transmission path of the carriers along the first direction X sequentially passing through the substrate 100, the dielectric layer 101 and the doping layer 102 is a reference transmission path. The impedance corresponding to the reference transmission path can be 0.05 mΩ·cm 2 ~1.4mΩ·cm 2 , more preferably 0.1 mΩ·cm 2 ~1.3mΩ·cm 2 , for example, it can be 0.05 mΩ·cm 2 , 0.1mΩ·cm 2 , 0.15mΩ·cm 2 , 0.2mΩ·cm 2 , 0.25mΩ·cm 2 , 0.3mΩ·cm 2 , 0.35mΩ·cm 2 , 0.4mΩ·cm 2 , 0.45mΩ·cm 2 , 0.5mΩ·cm 2 , 0.55mΩ·cm 2 , 0.6mΩ·cm 2 , 0.65mΩ·cm 2 , 0.7mΩ·cm 2 , 0.75mΩ·cm 2 , 0.8mΩ·cm 2 , 0.85mΩ·cm 2 , 0.9mΩ·cm 2 , 0.95mΩ·cm 2 , 1mΩ·cm 2 , 1.05mΩ·cm 2 , 1.1mΩ·cm 2 , 1.15mΩ·cm 2 , 1.2mΩ·cm 2 , 1.25mΩ·cm 2 , 1.3mΩ·cm 2 , 1.35mΩ·cm 2 or 1.4 mΩ·cm 2 wait.

[0090] It is worth noting that the density of the pores 111 in the dielectric layer 101 also affects the impedance of the reference transmission path. If the impedance of the reference transmission path is less than 0.05 mΩ·cm 2, the number of pores 111 arranged per unit area in the dielectric layer 101 is required to be large. Although the fill factor of the solar cell is improved, the passivation effect of the dielectric layer 101 on the substrate 100 will be reduced, thereby reducing the open circuit voltage of the solar cell. If the impedance corresponding to the reference transmission path is greater than 1.4 mΩ·cm 2 , the number of pores 111 arranged per unit area in the dielectric layer 101 is small, and the dielectric layer 101 has a general effect on improving the transmission efficiency of carriers in the dielectric layer 101. Therefore, the impedance corresponding to the design reference transmission path is 0.05mΩ·cm 2 ~1.4mΩ·cm 2 This is not only beneficial for improving the carrier transmission efficiency in the dielectric layer 101 by relying on the low impedance corresponding to the reference transmission path, thereby improving the fill factor of the solar cell, but also beneficial for ensuring that the dielectric layer 101 has a good passivation effect on the substrate 100, thereby reducing the defect state density at the contact point between the substrate 100 and the dielectric layer 101, thereby ensuring that the solar cell has a higher open circuit voltage, thereby maintaining the photoelectric conversion efficiency of the solar cell at a higher level.

[0091] The following describes in detail the carrier transport mechanism in the dielectric layer 101 , mainly focusing on the transport achieved via the pores 111 .

[0092] refer to Figure 4 Compared with the three solar cells corresponding to Group 1, Group 2 and Group 3, the greater the arrangement density of the pores 111 in the dielectric layer 101, the smaller the impedance corresponding to the reference transmission path, the less obstruction the carriers encounter when transmitting in the reference transmission path, and the more conducive to improving the carrier transmission efficiency in the dielectric layer 101. Therefore, it can be indirectly explained that the carrier transmission mechanism in the dielectric layer 101 is mainly achieved by means of the pores 111.

[0093] In some embodiments, reference Figure 5 , Figure 5 This is a second cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application. The solar cell may further include: a diffusion layer 103, located between the substrate 100 and the dielectric layer 101, wherein the diffusion layer 103 and the doping layer 102 are doped with a doping element of the same conductivity type. It is worth noting that the introduction of the doping element in the diffusion layer 103 can saturate the dangling bonds on the side of the dielectric layer 101 away from the doping layer 102, and reduce the transmission resistance of the diffusion layer 103 itself, thereby facilitating the reduction of the obstruction to the lateral transmission of carriers along the second direction Y, making it easier for carriers to converge at the pores 111, increasing the current density in the first portion 110, and allowing more carriers to pass through the dielectric layer 101 per unit time.

[0094] It should be noted that the morphology of the diffusion layer 103 includes at least the following two situations: In some cases, continue to refer to Figure 5 After forming the dielectric layer 101 with the pores 111 on the substrate 100, during the process of preparing the doping layer 102, a small amount of doping elements in the doping layer 102 will pass through the pores 111 (refer to Figure 3 ) diffuses into the substrate 100, so that the portion of the substrate 100 in contact with the dielectric layer 101 is transformed into a diffusion layer 103 doped with the doping element. In other words, the diffusion layer 103 can be regarded as a substrate doped with the doping element.

[0095] In other cases, a doping layer is first formed on a substrate, and then a dielectric layer with pores and a doping layer are sequentially formed on a side of the doping layer away from the substrate. In other words, the doping layer is not transformed from a substrate doped with doping elements.

[0096] In some examples, the doping concentration of the doping element in the diffusion layer 103 may be 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 , for example, it can be 2×10 18 atom / cm 3 , 3×10 18 atom / cm 3 , 4×10 18 atom / cm 3 , 5×10 18 atom / cm 3 , 6×10 18 atom / cm 3 , 7×10 18 atom / cm 3 , 8×10 18 atom / cm 3 or 9×10 18 atom / cm 3 wait.

[0097] It is worth noting that if the doping concentration of the doping element in the diffusion layer 103 is less than 1×10 18 atom / cm 3 , the effect of reducing the transmission resistance of the diffusion layer 103 itself is limited; if the doping concentration of the doping element in the diffusion layer 103 is greater than 1×10 19 atom / cm 3Too much doping element in the diffusion layer 103 will cause more defect states inside the diffusion layer 103, which will increase the recombination probability of carriers in the diffusion layer 103. Therefore, the doping concentration of the doping element in the diffusion layer 103 is designed to be 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 , which is beneficial to reduce the obstacles encountered by carriers in the lateral transmission along the second direction Y by taking advantage of the small transmission resistance of the diffusion layer 103 itself, and at the same time avoid having a large number of defect states inside the diffusion layer 103, so as to avoid carriers from being recombined in the diffusion layer 103 in advance, and ensure that the carriers are gathered at the pores 111.

[0098] The following describes in detail the arrangement of the dielectric layer 101 and the doping layer 102 on the substrate 100 in combination with the types of solar cells.

[0099] In some embodiments, reference Figure 1 、 Figure 5 or Figure 8 The dielectric layer 101 includes a first dielectric layer, and the doped layer 102 includes a first doped layer located on a side of the first dielectric layer away from the substrate 100. The first doped layer and the substrate 100 contain doping elements of different conductivity types. Minority carriers are transmitted along the first direction X through the substrate 100 and the first dielectric layer to the first doped layer. Conversely, majority carriers are transmitted along the first direction X through the first doped layer and the first dielectric layer to the substrate 100. Based on this, it can be seen that the carrier transmission path along the first direction X through the substrate 100, the first dielectric layer, and the first doped layer is a reference transmission path.

[0100] In other embodiments, reference Figure 1 、 Figure 5 or Figure 9 The dielectric layer 101 includes a second dielectric layer; the doped layer 102 includes a second doped layer located on a side of the second dielectric layer away from the substrate 100, and the second doped layer and the substrate 100 contain doping elements of the same conductivity type; majority carriers are transmitted along the first direction X through the substrate 100 and the second dielectric layer to the second doped layer; conversely, minority carriers are transmitted along the first direction X through the second doped layer and the second dielectric layer to the substrate. Therefore, the carrier transmission path along the first direction X through the substrate 100, the first dielectric layer, and the first doped layer is a reference transmission path.

[0101] It should be noted that Figure 1 、 Figure 5 or Figure 9The second surface 100b shown can be considered the back side of the solar cell. In addition, the first dielectric layer and the second dielectric layer can be present simultaneously in a solar cell, or one of them can be present in a solar cell selectively, and the first dielectric layer is provided with a first doped layer on the side away from the substrate, and the second dielectric layer is provided with a second doped layer on the side away from the substrate. Furthermore, the first dielectric layer and / or the second dielectric layer can fully cover the surface of one of the first and second surfaces of the solar cell, or can partially cover the surface of one of the first and second surfaces of the solar cell.

[0102] It should be noted that in solar cells of different types and structures, there may be slight differences in the carrier transmission paths. Therefore, the carrier transmission direction and carrier transmission path shown in one embodiment of the present application are only examples of one or more of them and are not limited to this.

[0103] In some other embodiments, reference Figure 8 or Figure 9 The first surface 100a or the second surface 100b is the back surface, and the back surface has first field areas and second field areas alternately arranged along the second direction Y. An isolation area may be set between the first field areas and the second field areas, or may not be set.

[0104] In some cases, the dielectric layer 101 includes a third dielectric layer located on the first field region, the doped layer 102 includes a third doped layer located on the first field region, the third doped layer and the substrate 100 are doped with doping elements of the same conductivity type, majority carriers are transmitted along the first direction X through the substrate 100 and the third dielectric layer to the third doped layer, and minority carriers are transmitted along the first direction X through the third doped layer and the third dielectric layer to the substrate 100. In other words, the transmission path of carriers along the first direction X through the substrate 100, the third dielectric layer, and the third doped layer is one type of reference transmission path.

[0105] In some cases, the dielectric layer 101 includes a fourth dielectric layer located on the second field region, the doped layer 102 includes a fourth doped layer located on the second field region, the fourth doped layer and the substrate 100 include doping elements of different conductivity types, and minority carriers among the carriers are transmitted along the first direction X through the substrate 100 and the fourth dielectric layer to the fourth doped layer; and minority carriers among the carriers are transmitted along the first direction X through the fourth doped layer and the fourth dielectric layer to the substrate 100. In other words, the transmission path of the carriers along the first direction X through the substrate 100, the fourth dielectric layer, and the fourth doped layer is one type of reference transmission path.

[0106] It should be noted that the above two situations may exist simultaneously in one solar cell, or may exist selectively in one solar cell.

[0107] In the above two embodiments, the doping element in the substrate 100 can be a first doping element, and a doping element with a conductivity type different from that of the first doping element can be a second doping element; one of the first doping element and the second doping element is an N-type doping element, and the other is a P-type doping element.

[0108] In some examples, the N-type doping element may be at least one of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As); the P-type semiconductor substrate is doped with a P-type element, and the P-type doping element may be at least one of Group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0109] The area distribution on the first surface 100 a or the second surface 100 b is described in detail below.

[0110] In some embodiments, reference Figure 5 、 Figure 8 or Figure 9 , at least one of the first surface 100a and the second surface 100b has first regions 35 and second regions 46 alternately arranged along the second direction Y; the dielectric layer 101 and the doping layer 102 may be located only on the first region 35. In other embodiments, referring to Figure 1 The second dielectric layer and the second doping layer may also be located in the first region 35 and the second region 46 at the same time.

[0111] In some cases, the solar cell is a solar cell having electrodes on one side or both sides, for example, a single-sided or double-sided TOPCON cell. Figure 1 、 Figure 5 、 Figure 8 or Figure 9 The first surface 100a of the substrate 100 can be the front side, and the first surface 100a has a first metal area 130 and a first non-metal area 140 arranged alternately along the second direction Y; the second surface 100b of the substrate 100 can be the back side, and the second surface 100b has a second metal area 150 and a second non-metal area 160 arranged alternately along the second direction Y.

[0112] In some examples, reference Figure 1 or Figure 5 , both the first surface 100a and the second surface 100b have first regions 35 and second regions 46 alternately arranged along the second direction Y. The first regions 35 include a first metal region 130 and a second metal region 150, and the second regions 46 include a first non-metal region 140 and a second non-metal region 160. On this basis, the stacked structure formed by the dielectric layer 101 and the doped layer 102 can be located only on the first metal region 130 or the second metal region 150, or can be located on both the first metal region 130 and the second metal region 150.

[0113] In other examples, reference Figure 8 , Figure 8 This is a third cross-sectional schematic diagram of a solar cell provided in an embodiment of the present application. Only the first surface 100a has first regions 35 and second regions 46 alternately arranged along the second direction Y. The first regions 35 include first metal regions 130, and the second regions 46 include first non-metal regions 140. Based on this, the stacked structure consisting of the dielectric layer 101 and the doped layer 102 can be located only on the first metal region 130. In practical applications, the stacked structure consisting of the dielectric layer and the doped layer can also be located on both the first metal region and the first non-metal region.

[0114] In some other examples, reference Figure 9 , Figure 9 This is a fourth cross-sectional schematic diagram of a solar cell provided in an embodiment of the present application. Only the second surface 100b has first regions 35 and second regions 46 alternately arranged along the second direction Y. The first regions 35 include second metal regions 150, and the second regions 46 include second non-metal regions 160. Based on this, the stacked structure consisting of the dielectric layer 101 and the doped layer 102 can be located only on the second metal region 150. In practical applications, the stacked structure consisting of the dielectric layer and the doped layer can also be located on both the second metal region and the second non-metal region.

[0115] In other cases, the solar cell is a solar cell having an electrode on one side, such as a BC cell. Figure 8 or Figure 9 The first surface 100a or the second surface 100b of the substrate 100 may be the back surface, with only the back surface having first regions 35 and second regions 46 arranged alternately along the second direction Y. The first regions 35 may include first and second field regions, which are arranged alternately along the second direction Y. The doped layer 102 located on the first field region is a third doped layer, and the doped layer 102 located on the second field region is a fourth doped layer. The third doped layer and the substrate 100 are doped with a doping element of the same conductivity type, and the fourth doped layer is doped with a second doping element of a different conductivity type from the first doping element. Furthermore, the second region 46 may be considered an isolation region between adjacent first and second field regions. In practical applications, an isolation region may not be provided between the first and second field regions.

[0116] It is worth noting that the dielectric layer 101 and the doping layer 102 are only located on the first region 35, and the second region 46 is not covered by the doping layer 102. This helps to avoid the second region 46 being affected by the parasitic absorption of light by the doping layer 102, thereby allowing more light to be incident on the second region 46 and absorbed by the substrate 100 for utilization.

[0117] In some embodiments, reference Figure 10 , Figure 10 This is a fifth cross-sectional schematic diagram of a solar cell provided in an embodiment of the present application. The solar cell further includes an electrode 104 in contact with the doped layer 102, and the electrode 104 is located at least on a side of the doped layer 102 away from the substrate 100. It is worth noting that after carriers in the substrate 100 are transferred to the doped layer 102 via the dielectric layer 101 having the pores 111, they are further transferred to the electrode 104 in contact with the doped layer 102 to be collected by the electrode 104.

[0118] The following describes in detail, in conjunction with a specific solar cell, how the transmission efficiency of carriers in the dielectric layer 101 decreases as the temperature of the dielectric layer 101 increases, that is, how the transmission resistance of the reference transmission path of carriers in at least part of the solar cell increases as the temperature of the solar cell increases.

[0119] Combined with reference Figure 5 、 Figure 8 and Figure 11 , Figure 5 For a bifacial cell, the dielectric layer 101 and the doping layer 102 are only provided in the first area 35, i.e., the metal area, on both the front and back sides; Figure 8 For a single-sided cell, the dielectric layer 101 and the doping layer 102 are also provided only in the first region 35 , ie, the metal region, on the front or back side. Figure 11 This is a partial top view of a test structure obtained by cutting from a solar cell according to an embodiment of the present application. The transmission resistance corresponding to a reference transmission path is measured using the Transmission Line Model (TLM) method. The reference transmission path is the transmission path of carriers along the first direction X through the substrate 100, the dielectric layer 101, and the doped layer 102. In other words, the reference transmission path is the transmission path corresponding to carriers transmitted along the first direction X through the substrate 100 and the dielectric layer 101 to the doped layer 102.

[0120] Among them, continue to refer to Figure 11 A typical TLM structure is obtained by cutting from a solar cell. A single TLM structure includes a plurality of electrodes 104 spaced apart along the second direction Y. By measuring the resistance between different electrodes 104, the transmission resistance can be fitted. The transmission resistance is the transmission resistance corresponding to the aforementioned reference transmission path, which can characterize the carrier flow in the doped layer 102 (reference) along the first direction X. Figure 1 ), the transmission resistance moving in the dielectric layer and the substrate 100.

[0121] It should be noted that Figure 11 4 examples of testing the resistance between different electrodes 104 are shown in FIG. Figure 11, along the second direction Y, the plurality of electrodes 104 are sequentially used as the first electrode, the second electrode, the third electrode, the fourth electrode and the fifth electrode, based on Figure 11 The two probes shown in Case 1 measure the resistance between the first electrode and the second electrode. Figure 11 The two probes shown in Case 2 measure the resistance between the first electrode and the third electrode. Figure 11 The two probes shown in Case 3 measure the resistance value between the first electrode and the fourth electrode and the resistance value between the first electrode and the fourth electrode based on the Figure 11 The two probes shown in Case 4 measure the resistance between the first electrode and the fifth electrode. Based on the test methods shown in Cases 1, 2, 3, and 4, an IV curve (current-voltage curve) can be obtained. The slope of each curve corresponds to the resistance between two different electrodes 104.

[0122] In some cases, the resistance between two electrodes 104 and the resistance between another two electrodes 104, for example, Figure 12 The resistance value between the first electrode and the second electrode corresponding to Case 1 is shown as Figure 13 In the resistance value between the first electrode and the third electrode corresponding to Case 2 shown, the carriers are all transmitted in sequence along the first direction X through the substrate 100 and the dielectric layer 101 to the doping layer 102, and further transmitted to the electrode 104 in contact with the doping layer 102 to be collected by the electrode 104. The difference between the resistance value between the two electrodes 104 and the resistance value between the other two electrodes 104 is mainly reflected in the length of the transmission path of the carriers along the second direction Y in the substrate 100.

[0123] In other words, reference Figure 12 and Figure 13 , the transmission path of carriers transmitted along the first direction X through the substrate 100 and the dielectric layer 101 to the doped layer 102 is taken as the reference transmission path, and the transmission resistance corresponding to the reference transmission path can be regarded as the first longitudinal resistance R1; the transmission path of carriers transmitted along the second direction Y from the portion of the substrate 100 facing one electrode 104 to the portion facing another electrode 104 is taken as the first transverse transmission path, and the transmission resistance corresponding to the first transverse transmission path is the first transverse resistance R2. Figure 12 and Figure 13The resistance between any two electrodes 104 measured in the example shown mainly includes a first longitudinal resistance R1 and a first transverse resistance R2. The resistance value between the two electrodes 104 is consistent with the resistance value between the other two electrodes 104, that is, the difference is very small and can be almost ignored. The first transverse resistance R2 increases linearly with the increase of the distance between the two electrodes 104 in the second direction Y. Therefore, the first longitudinal resistance R1 can be fitted by the change of the resistance value between multiple different electrodes 104. For example, the first longitudinal resistance R1 can be fitted based on the change of the resistance value measured corresponding to Case 1, Case 2, Case 3 and Case 4.

[0124] It can be understood that, in the resistance value between the two electrodes 104 and the resistance value between the other two electrodes 104, the difference in the first longitudinal resistance R1 corresponding to the reference transmission path is very small and almost negligible, and the length of the first transverse transmission path has obvious difference, then the first transverse resistance R2 corresponding to each of the two first transverse transmission paths has obvious difference, which leads to the difference in the resistance value between the two electrodes 104 and the resistance value between the other two electrodes 104.

[0125] In one example, compared to reference Figure 12 and Figure 13 , the transmission path of carriers from the portion directly opposite the first electrode to the portion directly opposite the second electrode in the substrate 100 along the second direction Y is taken as the first sub-transverse transmission path, and the transmission path of carriers from the portion directly opposite the first electrode to the portion directly opposite the third electrode in the substrate 100 along the second direction Y is taken as the second sub-transverse transmission path. The length of the second sub-transverse transmission path is significantly longer than the length of the first sub-transverse transmission path. The first electrode, the second electrode, and the third electrode each have no significant difference from the reference transmission path corresponding to the substrate 100. The difference in resistance between the first electrode and the second electrode and the resistance between the first electrode and the third electrode is mainly caused by the difference in length of the first sub-transverse transmission path and the second sub-transverse transmission path. Based on this, the transmission resistance corresponding to the reference transmission path is a stable value, and the transmission resistance can be fitted by measuring the resistance values between different electrodes 104.

[0126] It should be noted that Figure 12 A sixth cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 13 This is a seventh cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application. Figure 12 and Figure 13 In the figure, the first longitudinal resistor R1 and the first transverse resistor R2 are roughly indicated by thick dashed boxes, and the positional relationship between the probe and the electrode 104 is indicated by white filled arrows.

[0127] For further reference, Figure 14 , Figure 14 This is a line graph showing the change in transmission resistance of two different solar cells with temperature, provided in one embodiment of the present application. By changing the temperature of the solar cell, i.e. Figure 14 The test temperature is shown, and the transmission line model (TLM) method is used to measure the transmission resistance corresponding to the reference transmission path in the solar cell at different temperatures, so that Figure 14 The transmission resistance corresponding to the reference transmission path shown in the figure increases with the temperature of the solar cell. It is worth noting that the transmission resistance corresponding to the reference transmission path in the solar cell at different temperatures can reflect the carrier in the dielectric layer 101 (reference Figure 1 ), wherein the increase in the transmission resistance corresponding to the reference transmission path can reflect the decrease in the transmission efficiency of the carriers in the dielectric layer 101. Based on this, Figure 14 The transmission resistance corresponding to the reference transmission path shown increases with the increase in the temperature of the solar cell, which can reflect that the transmission efficiency of carriers in the dielectric layer 101 decreases with the increase in the temperature of the dielectric layer 101.

[0128] It should be noted that Figure 14 The middle orange broken line, that is, battery-1 corresponds to the TBC battery (TOPCon BackContact, referring to the cross-passivated back contact battery), and the dark blue broken line, that is, battery-2 corresponds to the TOPCON battery.

[0129] It is worth noting that in actual situations, Figure 12 and Figure 13 The first longitudinal resistance R1 shown includes not only the transmission resistance corresponding to the reference transmission path, but also the contact resistance at the contact point between the electrode 104 and the doped layer 102. Furthermore, similar to the transmission resistance corresponding to the reference transmission path, the contact resistance at the contact point between the electrode 104 and the doped layer 102 has the same resistance value as the contact resistance between the other two electrodes 104, i.e., the difference is very small and can be almost ignored.

[0130] In order to further improve the accuracy of the transmission resistance corresponding to the fitted reference transmission path, the following method can be used to obtain the resistance value of the contact resistance at the contact point between the electrode 104 and the doping layer 102, and then subtract the contact resistance from the first longitudinal resistance R1 fitted in the above-described method, which can be regarded as the transmission resistance corresponding to the reference transmission path.

[0131] refer to Figure 15 and Figure 16, the transmission path of carriers from the doped layer 102 to the electrode 104 along the first direction X is regarded as the longitudinal transmission path, and the transmission resistance corresponding to the longitudinal transmission path is the second longitudinal resistance R3; the transmission path of carriers from the portion facing one electrode 104 to the portion facing another electrode 104 in the doped layer 102 along the second direction Y is regarded as the second transverse transmission path, and the transmission resistance corresponding to the second transverse transmission path is the second transverse resistance R4. Figure 15 and Figure 16 The resistance between any two electrodes 104 measured in the example shown mainly includes a second longitudinal resistance R3 and a second transverse resistance R4. The second longitudinal resistance R3 is consistent with the resistance between the two electrodes 104 and the resistance between the other two electrodes 104, that is, the difference is very small and can be almost ignored. The second transverse resistance R4 increases linearly with the increase of the distance between the two electrodes 104 in the second direction Y. Therefore, the second longitudinal resistance R3 can be fitted by changing the resistance between multiple different electrodes 104. For example, based on Figure 11 The second longitudinal resistance R3 is fitted by measuring the changes in resistance values corresponding to Cases 1, 2, 3, and 4. The second longitudinal resistance R3 can be regarded as the contact resistance at the contact point between the electrode 104 and the doping layer 102 .

[0132] It should be noted that Figure 15 This is an eighth cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application; Figure 16 This is a ninth cross-sectional schematic diagram of a solar cell provided in one embodiment of the present application. Figure 15 and Figure 16 The second longitudinal resistor R3 and the second transverse resistor R4 are roughly indicated by thick dashed boxes, and the positional relationship between the probe and the electrode 104 is indicated by white filled arrows.

[0133] In addition, the transmission path of the carriers along the first direction X through the substrate 100, the dielectric layer 101 and the doping layer 102 is a reference transmission path. Figure 15 、 Figure 16 and Figure 1 The reference transmission path in the solar cell shown corresponds to the transmission resistance, not the Figure 15 and Figure 16 The second longitudinal resistance R3 shown in Figure 15 、 Figure 16 and Figure 1 The sample of the solar cell shown in FIG. 1 is first subjected to selective etching to remove the dielectric layer and the doping layer located on the second region, leaving only the dielectric layer and the doping layer located on the first region. Figure 15 、 Figure 16 and Figure 1The solar cell etching process shown is as follows Figure 12 or Figure 13 Then, the selectively etched sample was cut to obtain Figure 11 The typical TLM structure shown in the figure is based on the above Figure 12 and Figure 13 The method described in "fitting the transmission resistance corresponding to the reference transmission path by measuring the resistance values between different electrodes 104" is used to obtain Figure 15 、 Figure 16 and Figure 1 The transmission resistance corresponding to the reference transmission path in the solar cell is shown, and the fitting test of the transmission resistance is not described in detail here.

[0134] Moreover, it can be based on Figure 15 、 Figure 16 and Figure 1 The solar cell shown first obtains the contact resistance between the electrode 104 and the doping layer 102, and then Figure 15 、 Figure 16 and Figure 1 The solar cell shown is subjected to selective etching to fit the transmission resistance corresponding to the reference transmission path, and the contact resistance is subtracted from the fitted transmission resistance.

[0135] In some embodiments, reference Figures 1 to 10 The material of the dielectric layer 101 may include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; in other embodiments, Figures 1 to 10 The material of the dielectric layer 101 may include one or more of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0136] In some embodiments, reference Figures 1 to 10 , the material of the doping layer 102 may include polysilicon doped with doping elements.

[0137] In some embodiments, reference Figures 1 to 10 The doping concentration of the doping element in different regions of the doping layer 102 can be substantially consistent, that is, the doping element is uniformly doped in the doping layer 102. In other embodiments, the doping concentration of the doping element in the doping layer 102 can vary gradually, for example, gradually increasing or decreasing, along the direction from the dielectric layer 101 to the doping layer 102. It should be noted that the doping layer 102 can have a single film layer structure or a multi-layer stacked structure.

[0138] In some embodiments, reference Figures 1 to 10 The pores 111 in the dielectric layer 101 may be formed by heat treatment. The process temperature of the heat treatment may be 800° C. to 1100° C., and the treatment time of the heat treatment may be 20 min to 60 min.

[0139] It is worth noting that the thermal treatment results in the presence of pores 111 in the dielectric layer 101, thereby diversifying the carrier transmission paths in the dielectric layer 101. This allows carriers to be transmitted through the dielectric layer 101 either through quantum tunneling or through the pores 111, thereby improving the carrier transmission efficiency in the dielectric layer 101. Compared to the prior art method of transmitting carriers solely through the quantum tunneling effect, the presence of pores 111 causes carriers to preferentially gather in the pore 111 region, thereby lengthening the carrier transmission path from the substrate to the electrode in the solar cell, further improving carrier transmission efficiency.

[0140] In some cases, the process temperature used for heat treatment can be 800℃~890℃, for example, it can be 805℃, 815℃, 820℃, 825℃, 830℃, 835℃, 840℃, 845℃, 850℃, 855℃, 860℃, 865℃, 870℃, 875℃, 880℃ or 885℃, etc.

[0141] In other cases, the process temperature used for heat treatment can be 900℃~950℃ or 890℃~930℃, for example, it can be 890℃, 895℃, 900℃, 905℃, 910℃, 915℃, 920℃, 925℃, 930℃, 935℃, 940℃ or 945℃, etc.

[0142] It is worth noting that the reference Figure 4 , compared with Figure 4 The arrangement density of the pores 111 in the dielectric layer 101 in the solar cell corresponding to Group 3 shown in the figure is such that if the process temperature used for the heat treatment is greater than 930°C or 950°C, the arrangement density of the pores in the dielectric layer in the resulting solar cell will be greater, and the impedance corresponding to the reference transmission path will be easier to be greater than 0.1 mΩ·cm. 2 Even lower, for example, than 0.05mΩ·cm 2 The fill factor of the solar cell is improved, but the passivation effect of the dielectric layer on the substrate is reduced, thereby reducing the open circuit voltage of the solar cell.

[0143] Compared with Figure 4 The arrangement density of the pores 111 in the dielectric layer 101 in the solar cell corresponding to Group 1 shown in the figure is smaller than 900°C or 890°C in the process temperature of the heat treatment, or smaller than 900°C or 890°C in the dielectric layer. Figure 4The arrangement of the pores 111 in the solar cell corresponding to Group 1 is as sparse as that shown, so the impedance corresponding to the reference transmission path is easy to be 1.4 mΩ·cm 2 Higher, for example, equal to Figure 4 1.46 mΩ·cm shown 2 , thereby reducing the effect of the dielectric layer 101 on improving the transmission efficiency of carriers in the dielectric layer 101 .

[0144] Thus, the process temperature used in the heat treatment is designed to be 900°C~950°C or 890°C~930°C, which is conducive to controlling the arrangement density of the pores 111 in the dielectric layer 101 to be moderate, thereby controlling the impedance corresponding to the reference transmission path to be 0.1mΩ·cm 2 ~1.3mΩ·cm 2 , so as to improve the transmission efficiency of carriers in the dielectric layer 101 by relying on the low impedance corresponding to the reference transmission path, while ensuring that the dielectric layer 101 has a good passivation effect on the substrate 100.

[0145] In some other cases, the process temperature used for the heat treatment can be 950℃~1100℃, for example, it can be 955℃, 960℃, 965℃, 970℃, 975℃, 980℃, 985℃, 990℃, 995℃, 1000℃, 1005℃, 1010℃, 1015℃, 1020℃, 1025℃, 1030℃, 1035℃, 1040℃, 1045℃, 1050℃, 1055℃, 1060℃, 1065℃, 1070℃, 1075℃, 1080℃, 1085℃, 1090℃ or 1095℃, etc.

[0146] In summary, the dielectric layer 101 is designed to include a plurality of pores 111, with at least a portion of the pores 111 extending through the dielectric layer 101 along the first direction X. This improves the carrier transport mechanism in the dielectric layer. Specifically, the carrier transport mechanism in the dielectric layer 101 is primarily achieved through the pores 111, which helps reduce the reliance of carriers on the quantum tunneling effect during transport in the dielectric layer 101 and reduces the thickness requirements for the dielectric layer 101. This helps increase the thickness fluctuation range of the dielectric layer 101, i.e., increases the process window for fabricating the dielectric layer 101. Furthermore, the majority of the dielectric layer 101 without the pores 111 ensures that the dielectric layer 101 has good passivation properties with respect to the substrate 100.

[0147] Furthermore, the transmission resistance corresponding to the reference transmission path in at least some solar cells increases as the temperature of the solar cells increases, that is, the transmission efficiency of carriers in the dielectric layer 101 decreases as the temperature of the dielectric layer 101 increases. Thus, on the one hand, even when the temperature of the dielectric layer 101 is low, the transmission resistance corresponding to the reference transmission path is also low, that is, the carriers have a high transmission efficiency in the dielectric layer 101, which helps ensure that the solar cell has a high photoelectric conversion efficiency even at low temperatures. On the other hand, if the temperature of the dielectric layer 101 increases, the transmission resistance corresponding to the reference transmission path increases, that is, the carrier transmission efficiency is suppressed at high temperatures, which can reduce the current in the local area of the solar cell, thereby helping to reduce the risk of thermal runaway of the solar cell. On the other hand, if the temperature of a local area of the solar cell rises, causing the transmission resistance corresponding to the reference transmission path in the local area to increase, that is, causing the carrier transmission efficiency in the local area to decrease, the carriers in the local area will tend to transmit laterally to other areas with lower temperatures, and then transmit to the doped layer 102 through the dielectric layer 101. This helps to reduce the number of carriers concentrated in the local high-temperature area of the solar cell. By leveraging the temperature difference and the increase in the transmission resistance corresponding to the reference transmission path in the high-temperature area of the solar cell, or the decrease in the carrier transmission efficiency in the high-temperature area of the solar cell, the current in the solar cell is promoted to be uniformly distributed, further reducing the risk of thermal runaway of the solar cell.

[0148] Another embodiment of the present application also provides a method for manufacturing a solar cell, which is used to form the solar cell provided in the aforementioned embodiment. The following detailed description of the method for manufacturing a solar cell provided in another embodiment of the present application is provided in conjunction with the accompanying drawings. It should be noted that parts that are identical or corresponding to the aforementioned embodiments are not repeated here.

[0149] refer to Figures 17 to 19 ,as well as Figure 2 、 Figure 3 、 Figure 5 and Figure 6 , the manufacturing method of the solar cell comprises at least the following steps: Figure 17 , providing a substrate 100, the substrate 100 having a first surface 100a and a second surface 100b opposite to each other along a first direction X; Figures 17 to 19 ,as well as Figure 2 、 Figure 3 、 Figure 5 and Figure 6A dielectric layer 101 and a doped layer 102 are sequentially formed on at least one of the first surface 100a and the second surface 100b; wherein the dielectric layer 101 includes a plurality of pores 111, and at least a portion of the pores 111 penetrate the dielectric layer 101 along the first direction X. Carriers in the substrate 100 are transmitted to the doped layer 102 via the dielectric layer 101 along the first direction X, and the transmission efficiency of carriers in the dielectric layer 101 decreases as the temperature of the dielectric layer 101 increases.

[0150] in, Figure 17 A schematic cross-sectional view of a substrate in a method for manufacturing a solar cell provided in another embodiment of the present application; Figure 18 An enlarged cross-sectional schematic diagram of a method for manufacturing a solar cell provided by another embodiment of the present application after an initial dielectric layer and an initial doping layer are formed on the first surface; Figure 19 Another enlarged cross-sectional schematic diagram is provided in the method for manufacturing a solar cell according to another embodiment of the present application after an initial dielectric layer and an initial doping layer are formed on the first surface.

[0151] It is worth noting that in the solar cell formed by the solar cell manufacturing method provided by another embodiment of the present application, the dielectric layer 101 includes a plurality of pores 111, and at least a portion of the pores 111 penetrate the dielectric layer 101 along the first direction X, so that the carrier transmission mechanism in the dielectric layer 101 is mainly based on the transmission through the pores 111, which is beneficial to increase the thickness fluctuation range of the dielectric layer 101, that is, increase the process window when preparing the dielectric layer 101. At the same time, the majority of the portions of the dielectric layer 101 where the pores 111 are not formed can ensure that the dielectric layer 101 has good passivation performance with respect to the substrate 100. Furthermore, the transmission resistance corresponding to the reference transmission path in at least some solar cells increases as the temperature of the solar cells increases, that is, the transmission efficiency of carriers in the dielectric layer 101 decreases as the temperature of the dielectric layer 101 increases. This, on the one hand, is conducive to ensuring that the solar cells have a higher photoelectric conversion efficiency even at lower temperatures; on the other hand, if the temperature of the dielectric layer 101 increases, the transmission resistance corresponding to the reference transmission path increases, that is, the characteristic that the carrier transmission efficiency is suppressed at higher temperatures, which can reduce the current in the local area of the solar cell, thereby helping to reduce the risk of thermal runaway of the solar cell; on the other hand, by taking advantage of the temperature difference and the characteristic that the transmission resistance corresponding to the reference transmission path in the high-temperature area of the solar cell increases, or by taking advantage of the characteristic that the carrier transmission efficiency in the high-temperature area of the solar cell decreases, it can promote the uniform distribution of current in the solar cell, thereby further reducing the risk of thermal runaway of the solar cell.

[0152] In some embodiments, the steps of forming the dielectric layer 101 and the doping layer 102 include: Figure 18 or Figure 19 , forming an initial dielectric layer 121 on at least one of the first surface 100a and the second surface 100b; Figure 18 or Figure 19 , an initial doping layer 112 is formed on the side of the initial dielectric layer 121 away from the substrate 100, and the initial doping layer 112 can be amorphous silicon doped with doping elements; Figure 18 、 Figure 19 、 Figure 2 and Figure 3 , or in combination with reference Figure 18 、 Figure 19 、 Figure 5 and Figure 6 The semi-finished solar cell having the initial doping layer 112 is subjected to a heat treatment to promote crystallization of the initial doping layer 112, thereby transforming the initial doping layer 112 into polycrystalline silicon doped with doping elements, i.e., the doping layer 102. Moreover, during the heat treatment step, pores 111 are formed in the initial dielectric layer 121, thereby transforming the initial dielectric layer 121 into the dielectric layer 101 having a plurality of pores 111.

[0153] It should be noted that, in practical applications, a dielectric layer with pores may be formed on the substrate first, and then the doping layer may be formed directly on the dielectric layer.

[0154] In some cases, the process temperature used for the heat treatment is 800° C. to 1100° C. Preferably, the process temperature used for the heat treatment may be 900° C. to 950° C. or 890° C. to 930° C., for example, 895° C., 900° C., 905° C., 910° C., 915° C., 920° C., 925° C., 930° C., 935° C., 940° C., or 945° C.

[0155] It is worth noting that the reference Figure 4 , compared with Figure 4 The arrangement density of the pores 111 in the dielectric layer 101 in the solar cell corresponding to Group 3 shown in the figure is such that if the process temperature used for the heat treatment is greater than 930°C or 950°C, the arrangement density of the pores in the dielectric layer in the resulting solar cell will be greater, and the impedance corresponding to the reference transmission path will be easier to be greater than 0.1 mΩ·cm. 2 Even lower, for example, than 0.05mΩ·cm 2 The fill factor of the solar cell is improved, but the passivation effect of the dielectric layer on the substrate is reduced, thereby reducing the open circuit voltage of the solar cell.

[0156] Compared with Figure 4The arrangement density of the pores 111 in the dielectric layer 101 in the solar cell corresponding to Group 1 shown in the figure is smaller than 900°C or 890°C in the process temperature of the heat treatment, or smaller than 900°C or 890°C in the dielectric layer. Figure 4 The arrangement of the pores 111 in the solar cell corresponding to Group 1 is as sparse as that shown, so the impedance corresponding to the reference transmission path is easy to be 1.4 mΩ·cm 2 Higher, for example, equal to Figure 4 1.46 mΩ·cm shown 2 , thereby reducing the effect of the dielectric layer 101 on improving the transmission efficiency of carriers in the dielectric layer 101 .

[0157] Thus, the process temperature used in the heat treatment is designed to be 900°C~950°C or 890°C~930°C, which is conducive to controlling the arrangement density of the pores 111 in the dielectric layer 101 to be moderate, thereby controlling the impedance corresponding to the reference transmission path to be 0.1mΩ·cm 2 ~1.3mΩ·cm 2 , so as to improve the transmission efficiency of carriers in the dielectric layer 101 by relying on the low impedance corresponding to the reference transmission path, while ensuring that the dielectric layer 101 has a good passivation effect on the substrate 100.

[0158] In some cases, the treatment time of the heat treatment can be 20min~60min, for example, it can be 21min, 22min, 23min, 24min, 25min, 26min, 27min, 28min, 29min, 30min, 31min, 32min, 33min, 34min, 35min, 36min, 37min, 38min, 39min, 40min, 41min, 42min, 43min, 44min, 45min, 46min, 47min, 48min, 49min, 50min, 51min, 52min, 53min, 54min, 55min, 56min, 57min, 58min or 59min, etc.

[0159] In some cases, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process can be used to form the initial dielectric layer 121. In some examples, the thickness of the initial dielectric layer 121 along the first direction X can be 1 nm to 3 nm, for example, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, or 2.9 nm.

[0160] In some cases, the initial doping layer 112 may be formed using a deposition process.

[0161] In some examples, the deposition process for forming the initial doping layer 112 may be a PECVD process, a LPCVD (Low Pressure Chemical Vapor Deposition) process, or an ALD (Atomic Layer Deposition) process.

[0162] In some examples, the thickness of the initial doping layer 112 may be less than or equal to 150 nm along the first direction X. Preferably, the thickness of the initial doping layer 112 may be 60 nm to 100 nm, for example, 62 nm, 65 nm, 67 nm, 70 nm, 72 nm, 75 nm, 78 nm, 80 nm, 83 nm, 85 nm, 88 nm, 90 nm, 93 nm, 95 nm, or 98 nm.

[0163] The following describes in detail the preparation method of the dielectric layer 101 and the doping layer 102 by taking the finally formed solar cell as a TOPCON cell.

[0164] On this basis, combined with reference Figure 9 and Figure 17The second surface 100b has first regions 35 and second regions 46 alternately arranged along the second direction Y. Taking the dielectric layer 101 including the second dielectric layer located on the second surface 100b and the doping layer 102 including the second doping layer located on the second surface 100b as an example, the method for forming the second dielectric layer and the second doping layer includes at least the following steps: forming a second dielectric film covering the second surface 100b; forming a second doped semiconductor film on a side of the second dielectric film away from the second surface 100b; forming a first mask on a side of the second doped semiconductor film away from the second surface 100b; performing a heat treatment so that the second doped semiconductor film is transformed into The first mask is laser treated to remove the first mask located on the second region 46; a chain hydrofluoric acid etching process is performed on the first surface 100a to remove the edge-plated first mask on a single side; an alkaline etching process is then performed to remove the initial second doped layer located on the second region 46 and not protected by the first mask; and finally, a hydrofluoric acid etching solution is used to remove the remaining first mask located in the first region 35 and the exposed second dielectric film located in the second region 46. The remaining second dielectric film located in the first region 35 serves as the second dielectric layer, and the remaining initial second doped layer located in the first region 35 serves as the second doped layer. It should be noted that the above-mentioned heat treatment is the heat treatment described above.

[0165] In some cases, the relevant parameters used in laser processing are as follows: the laser power can be 40w~60w, for example, 45w, 50w or 55w, etc.; the laser scanning speed can be 50000mm / s~55000mm / s, for example, 51000mm / s, 52000mm / s, 53000mm / s or 54000mm / s, etc.; the laser frequency can be 400KHz~600KHz, for example, 450KHz, 500KHz or 550KHz, etc.

[0166] In some embodiments, before forming the dielectric layer 101 and the doping layer 102 , providing the substrate 100 may further include the following steps: An initial substrate is provided, wherein the initial substrate is doped with a first doping element. In some examples, the resistivity of the initial substrate may be 0.3 Ω·cm to 7 Ω·cm.

[0167] The initial substrate is double-sided textured to form a pyramid texture surface. In some examples, the size of the pyramids can be 0.5 μm to 3 μm.

[0168] An emitter is formed on the front side of the initial substrate. In some examples, the initial substrate is doped with an N-type dopant element, and the emitter is a P+ emitter, i.e., a boron-doped emitter. The doping concentration of the boron element in the P+ emitter can be 1×10 18 atom / cm 3 ~1×1019 atom / cm 3 ; The square resistance of the P+ emitter can be 300Ω / sq~500Ω / sq, preferably, the square resistance of the P+ emitter can be 350Ω / sq~450Ω / sq.

[0169] The back side of the initial substrate is polished. In some examples, silicon oxide is formed on the back side of the initial substrate during the aforementioned process. A single-sided inline device is first used to remove the back side silicon oxide using hydrofluoric acid. The back side is then subjected to alkaline polishing to remove edge knots and back side plating, and finally cleaned.

[0170] In some embodiments, before forming the dielectric layer 101 and the doping layer 102, the method for manufacturing a solar cell may further include the following steps: An aluminum oxide passivation layer is deposited on the first surface 100a and the second surface 100b using an ALD process in a single-drop manner. The aluminum oxide passivation layer on the second surface 100b is not only located on the side of the second doped layer away from the substrate 100, but also located on the second region 46, thereby passivating the substrate 100 located in the second region 46. In some examples, the thickness of the aluminum oxide passivation layer can be 2 nm to 7 nm, preferably 3 nm to 6 nm.

[0171] Anti-reflection layers are deposited on the first surface 100a and the second surface 100b using a PECVD process. In some examples, the anti-reflection layer can be a single layer or a stacked layer comprising one or more of silicon nitride, silicon oxynitride, and silicon oxide, and can have a thickness of 60 nm to 130 nm.

[0172] Electrode paste is formed on the first area 35 of the first surface 100 a and the second surface 100 b respectively by screen printing, and then the electrode paste is sintered and subjected to light injection or electrical injection to form electrodes in ohmic contact with the doping layer 102 .

[0173] Finally, the manufactured solar cells are tested, sorted and stored.

[0174] Another embodiment of the present application further provides a photovoltaic module for converting received light energy into electrical energy. The photovoltaic module provided in another embodiment of the present application is described in detail below with reference to the accompanying drawings. It should be noted that portions identical or corresponding to the preceding embodiments are not described in detail here.

[0175] Combined with reference Figure 20 and Figure 21 ,as well as Figures 1 to 19The photovoltaic module includes: a cell string, which is formed by connecting multiple solar cells 40 provided by the aforementioned embodiments, or by connecting multiple solar cells 40 formed by the solar cell manufacturing method provided by the aforementioned embodiments; an encapsulation film 41, which is used to cover the surface of the cell string; and a cover plate 42, which is used to cover the surface of the encapsulation film 41 facing away from the cell string.

[0176] in, Figure 20 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in another embodiment of the present application; Figure 21 A partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present application.

[0177] In some embodiments, the solar cell 40 is electrically connected in a whole cell or multiple slices to form multiple cell strings, and the multiple cell strings are electrically connected in series and / or parallel. The solar cell 40 can be a whole cell or a sliced cell. A sliced cell refers to a cell formed by cutting a complete whole cell.

[0178] In some embodiments, in conjunction with reference Figure 20 and Figure 21 , multiple solar cells 40 can be electrically connected through conductive ribbons 43. Figure 20 and Figure 21 Only one positional relationship between the solar cells 40 is illustrated, i.e., the grid lines of the same polarity of the solar cells 40 are arranged in the same direction, or the grid lines of each solar cell 40 with positive polarity are arranged toward the same side, so that the conductive ribbons 43 connect different sides of two adjacent solar cells 40. In other embodiments, the solar cells may also be arranged with electrodes of different polarities facing the same side, i.e., the electrodes of multiple adjacent solar cells are arranged in the order of first polarity, second polarity, and first polarity, respectively, so that the conductive ribbon connects two adjacent solar cells on the same side.

[0179] In some embodiments, the encapsulation film 41 includes a first encapsulation layer and a second encapsulation layer. The first encapsulation layer covers one of the front and back surfaces of the solar cell 40, and the second encapsulation layer covers the other of the front and back surfaces of the solar cell 40. Specifically, at least one of the first encapsulation layer and the second encapsulation layer can be an organic encapsulation film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene co-elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first encapsulation layer and the second encapsulation layer can be an EP film, an EPE film, or a PVP film. The EP film refers to a coextruded film composed of stacked EVA and POE films, the EPE film refers to a coextruded film formed by stacking EVA film, POE film, and EVA film in sequence, and the PVP film refers to a coextruded film composed of stacked POE film, EVA film, and POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another already manufactured film during the film processing process, or by bonding different types of already manufactured films together.

[0180] In some cases, there is a boundary line between the first encapsulation layer and the second encapsulation layer before lamination. After the lamination process, the photovoltaic module is formed and there is no longer the concept of the first encapsulation layer and the second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0181] In some embodiments, the cover plate 42 may be a light-transmitting cover plate such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 42 facing the encapsulation film 41 may have a concave-convex surface or a velvet surface including multiple raised structures, thereby increasing the utilization of incident light. The cover plate 42 includes a first cover plate and a second cover plate. The first cover plate faces the first encapsulation layer, and the second cover plate faces the second encapsulation layer.

[0182] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, the scope of protection of the embodiments of the present application shall be based on the scope defined in the claims.

Claims

1. A solar cell, characterized in that: include: a substrate having a first surface and a second surface opposite to each other in a first direction; a dielectric layer located on at least one of the first surface and the second surface, the dielectric layer comprising a plurality of pores, at least some of the pores penetrating the dielectric layer along the first direction; a doping layer, located on a side of the dielectric layer away from the substrate; A transmission path of carriers along the first direction through the substrate, the dielectric layer, and the doping layer is a reference transmission path, and a transmission resistance corresponding to the reference transmission path in at least part of the solar cells increases with an increase in the temperature of the solar cells.

2. The solar cell according to claim 1, wherein The dielectric layer includes a first dielectric layer, and the doping layer includes a first doping layer located on a side of the first dielectric layer away from the substrate; the first doping layer and the substrate contain doping elements with different conductivity types; and the transmission path of the carrier along the first direction in the substrate, the first dielectric layer, and the first doping layer is one of the reference transmission paths.

3. The solar cell according to claim 1, wherein The dielectric layer includes a second dielectric layer; the doping layer includes a second doping layer located on a side of the second dielectric layer away from the substrate, and the second doping layer and the substrate have doping elements of the same conductivity type; the transmission path of the carrier along the first direction in the substrate, the second dielectric layer and the second doping layer is one of the reference transmission paths.

4. The solar cell according to claim 3, characterized in that At least one of the first surface and the second surface of the substrate has a first area and a second area alternately arranged along a second direction; the second dielectric layer and the second doped layer are located in the first area; or, the second dielectric layer and the second doped layer are located in the first area and the second area at the same time.

5. The solar cell according to claim 1, wherein A diffusion layer is further provided between the substrate and the dielectric layer, and the diffusion layer and the doping layer contain doping elements of the same conductivity type.

6. The solar cell according to claim 5, characterized in that The doping concentration of the doping element in the diffusion layer is 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 .

7. The solar cell according to claim 1, wherein The first surface or the second surface is a back surface, and the back surface has first fields and second fields alternately arranged along a second direction; wherein, The dielectric layer includes a third dielectric layer located on the first field region, the doped layer includes a third doped layer located on the first field region, the third doped layer and the substrate have doping elements of the same conductivity type, and a transmission path of the carriers along the first direction among the substrate, the third dielectric layer, and the third doped layer is one of the reference transmission paths; and / or, The dielectric layer includes a fourth dielectric layer located on the second field region, the doped layer includes a fourth doped layer located on the second field region, the fourth doped layer and the substrate have doping elements with different conductivity types, and the transmission path of the carrier along the first direction in the substrate, the fourth dielectric layer and the fourth doped layer is one of the reference transmission paths.

8. The solar cell according to claim 7, characterized in that An isolation area is provided between the first area and the second area.

9. The solar cell according to claim 1, wherein The material of the dielectric layer includes one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; and / or, the material of the dielectric layer includes one or more of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

10. The solar cell according to claim 1, wherein The pores in the dielectric layer are formed by heat treatment, the process temperature adopted in the heat treatment is 800° C. to 1100° C., and the treatment time of the heat treatment is 20 min to 60 min.

11. The solar cell according to claim 1, wherein The dielectric layer includes a first portion and a second portion alternately and irregularly arranged along a direction perpendicular to the first direction. The pores are located in the first portion. The current density in the first portion is greater than the current density in the second portion.

12. The solar cell according to claim 11, characterized in that A ratio of a current density in the first portion to a current density in the second portion is greater than or equal to 10.

13. The solar cell according to claim 1 or 11, characterized in that The arrangement density of the pores in the dielectric layer is 1×10 6 pieces / cm 2 ~1×10 8 pieces / cm 2 .

14. The solar cell according to claim 11, wherein The reference transmission path includes a first reference transmission path and a second reference transmission path, wherein the transmission path of the carriers through the substrate, the first portion and the doping layer is the first reference transmission path; and / or, the transmission path of the carriers through the substrate, the second portion and the doping layer is the second reference transmission path.

15. The solar cell according to claim 14, characterized in that The transmission resistance corresponding to the first reference transmission path increases as the temperature of the solar cell increases; and / or the transmission resistance corresponding to the second reference transmission path decreases as the temperature of the solar cell increases.

16. The solar cell according to claim 1, wherein The impedance corresponding to the reference transmission path is 0.05 mΩ·cm 2 ~1.4mΩ·cm 2 .

17. The solar cell according to claim 1, wherein At least a portion of the pores accommodates the substrate and / or the doping layer; and / or at least a portion of the pores has air gaps therein.

18. The solar cell according to claim 1, wherein The temperature range of the dielectric layer is -50°C to 150°C.

19. A solar cell, characterized in that: include: a substrate having a first surface and a second surface opposite to each other in a first direction; a dielectric layer located on at least one of the first surface and the second surface, the dielectric layer comprising a plurality of pores, at least some of the pores penetrating the dielectric layer along the first direction; a doping layer, located on a side of the dielectric layer away from the substrate; The carriers are transported along the first direction through the substrate and the dielectric layer to the doping layer, and the transport efficiency of the carriers in at least a portion of the dielectric layer decreases as the temperature of the dielectric layer increases.

20. The solar cell according to claim 19, characterized in that The dielectric layer includes a first dielectric layer, and the doping layer includes a first doping layer located on a side of the first dielectric layer away from the substrate; the first doping layer and the substrate contain doping elements of different conductivity types; minority carriers among the carriers are transmitted to the first doping layer along the first direction through the substrate and the first dielectric layer.

21. The solar cell according to claim 19, wherein The dielectric layer includes a second dielectric layer; the doping layer includes a second doping layer located on a side of the second dielectric layer away from the substrate, and the second doping layer and the substrate have doping elements of the same conductivity type; majority carriers among the carriers are transmitted along the first direction through the substrate and the second dielectric layer to the second doping layer.

22. The solar cell according to claim 21, characterized in that At least one of the first surface and the second surface has a first region and a second region alternately arranged along a second direction; the second dielectric layer and the second doped layer are located on the first region; or, the second dielectric layer and the second doped layer are located in both the first region and the second region.

23. The solar cell according to claim 19, wherein A diffusion layer is further provided between the substrate and the dielectric layer, and the diffusion layer and the doping layer contain doping elements of the same conductivity type.

24. The solar cell according to claim 23, characterized in that The doping concentration of the doping element in the diffusion layer is 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 .

25. The solar cell according to claim 19, wherein The first surface or the second surface is a back surface, and the back surface has first fields and second fields alternately arranged along a second direction; wherein, The dielectric layer includes a third dielectric layer located on the first field region, the doped layer includes a third doped layer located on the first field region, the third doped layer and the substrate have doping elements of the same conductivity type, and majority carriers among the carriers are transmitted to the third doped layer via the substrate and the third dielectric layer along the first direction; and / or, The dielectric layer includes a fourth dielectric layer located on the second field region, the doped layer includes a fourth doped layer located on the second field region, the fourth doped layer and the substrate have doping elements with different conductivity types, and minority carriers among the carriers are transmitted to the fourth doped layer along the first direction through the substrate and the fourth dielectric layer.

26. The solar cell according to claim 25, characterized in that An isolation area is provided between the first area and the second area.

27. The solar cell according to claim 19, wherein The material of the dielectric layer includes one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; and / or, the material of the dielectric layer includes one or more of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

28. The solar cell according to claim 19, wherein The pores in the dielectric layer are formed by heat treatment, the process temperature adopted in the heat treatment is 800° C. to 1100° C., and the treatment time of the heat treatment is 20 min to 60 min.

29. The solar cell according to claim 19, wherein The dielectric layer includes a first portion and a second portion alternately and irregularly arranged along a direction perpendicular to the first direction. The pores are located in the first portion. The current density in the first portion is greater than the current density in the second portion.

30. The solar cell according to claim 29, characterized in that A ratio of a current density in the first portion to a current density in the second portion is greater than or equal to 10.

31. The solar cell according to claim 19 or 29, characterized in that The arrangement density of the pores in the dielectric layer is 1×10 6 pieces / cm 2 ~1×10 8 pieces / cm 2 .

32. The solar cell according to claim 19, wherein The transmission path of the carriers along the first direction through the substrate, the dielectric layer and the doping layer is a reference transmission path, and the impedance corresponding to the reference transmission path is 0.05 mΩ·cm 2 ~1.4mΩ·cm 2 .

33. The solar cell according to claim 29, wherein The transmission path of the carriers along the first direction through the substrate, the dielectric layer and the doped layer is a reference transmission path, and the reference transmission path includes a first reference transmission path and a second reference transmission path, wherein the transmission path of the carriers through the substrate, the first portion and the doped layer is the first reference transmission path; and / or, the transmission path of the carriers through the substrate, the second portion and the doped layer is the second reference transmission path.

34. The solar cell according to claim 33, characterized in that The transmission resistance corresponding to the first reference transmission path increases as the temperature of the solar cell increases; and / or the transmission resistance corresponding to the second reference transmission path decreases as the temperature of the solar cell increases.

35. The solar cell according to claim 19, wherein At least a portion of the pores accommodates the substrate and / or the doping layer; and / or at least a portion of the pores has air gaps therein.

36. The solar cell according to claim 19, wherein The temperature range of the dielectric layer is -50°C to 150°C.

37. A photovoltaic module, characterized in that: include: A cell string formed by connecting a plurality of solar cells according to any one of claims 1 to 18, or a plurality of solar cells according to any one of claims 19 to 36; A packaging film, used to cover the surface of the battery string; A cover plate is used to cover the surface of the packaging film facing away from the battery string.

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