Infrared detector

Abstract

The embodiment of the invention provides an infrared detector. The infrared detector comprises a signal processing integrated circuit and a storage integrated circuit, the signal processing integrated circuit is in communication connection with the storage integrated circuit; the signal processing integrated circuit comprises a reading module and a correction module; the reading module is used for acquiring an analog electric signal converted by external infrared radiation, converting the analog electric signal into an original digital image signal, and outputting the original digital image signal to the correction module; the correction module is used for correcting the original digital image signal based on the correction configuration data to obtain a corrected digital image signal; the storage integrated circuit is used for storing correction configuration data. The correction module is manufactured in the signal processing integrated circuit, and then the signal processing integrated circuit and the storage integrated circuit are integrated, so that the occupied space of the infrared sensing system can be reduced.

Description

Technical Field

[0001] The present application relates to the field of infrared sensing technology, and in particular to an infrared detector. Background Art

[0002] In existing uncooled infrared focal plane array (IRFPAA) sensor technology, the non-uniformity correction circuit features multiple modules, a complex structure, long computation time, and large storage requirements. This circuit primarily relies on an external image processor and external memory to perform the correction. Specifically, the uncooled IRFPAA sensor transmits the image signal to the non-uniformity correction circuit (which the external image processor includes) via a high-speed signal interface, while simultaneously relying on large-capacity external memory to perform the complex correction. The correction configuration data stored in the external memory is sent to the external image processor via another set of high-speed signal interfaces. The external image processor converts the correction configuration data and outputs it to the sensor. The non-uniformity correction circuit calculates the corrected image signal based on the acquired image signal and the correction configuration data, and outputs the corrected image signal via an image output interface. This results in a separate architecture for the uncooled IRFPAA sensor, image processor, and memory, resulting in a low level of integration and a large footprint for the infrared sensing system.

[0003] In order to improve the above-mentioned problems, the related art usually adopts the method of stacking multiple integrated circuits for integration. However, since the communication connection point and the photosensitive surface of the uncooled infrared focal plane array sensor are on the same side, and the size difference between the sensor and the correction circuit is large, it is difficult to integrate the uncooled infrared focal plane array sensor and the correction circuit in a stacked manner, or the cost of stacking integration is high. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide an infrared detector to reduce the space occupied by the infrared sensing system. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides an infrared detector, comprising:

[0006] A signal processing integrated circuit and a memory integrated circuit; the signal processing integrated circuit is communicatively connected to the memory integrated circuit;

[0007] The signal processing integrated circuit includes a readout module and a correction module; the readout module is used to obtain the analog electrical signal converted from external infrared radiation, convert the analog electrical signal into an original digital image signal, and output the original digital image signal to the correction module; the correction module is used to correct the original digital image signal based on correction configuration data to obtain a corrected digital image signal; the storage integrated circuit is used to store the correction configuration data.

[0008] In a possible implementation, the signal processing integrated circuit further includes a control module, a storage control module, and a clock reset control module;

[0009] The control module, the readout module, the storage control module, the correction module, and the clock reset control module are all communicatively connected to a first bus of the signal processing integrated circuit, and the readout module, the correction module, and the storage control module are all communicatively connected to a second bus of the signal processing integrated circuit;

[0010] The control module is used to control each module in the signal processing integrated circuit;

[0011] The storage control module is used to read and write the correction configuration data in the correction module and the storage integrated circuit;

[0012] The clock reset control module is used to provide a timing reference for the signal processing integrated circuit.

[0013] In one possible embodiment, the correction module is specifically configured to receive the original digital image signal output by the readout module and the correction configuration data read by the storage control module, calculate a corrected digital image signal based on the original digital image signal and the correction configuration data through its own correction sub-modules, encode and output the corrected digital image signal through its own encoding output sub-module, and obtain updated correction configuration data based on the corrected digital image signal and the original digital image signal.

[0014] In one possible implementation, the correction module includes an encoding output submodule and N correction submodules; wherein N is an integer not less than 1;

[0015] The i-th correction submodule is communicatively connected to the i-1-th correction submodule, and the N-th correction submodule is communicatively connected to the encoding output submodule; wherein i∈N, and i is an integer not less than 2;

[0016] The i-1th correction submodule outputs its own processed correction result to the i-th correction submodule with minimum delay.

[0017] In a possible implementation, the N correction submodules include a multiplicative correction submodule, an additive correction submodule, and a time domain filtering submodule;

[0018] The multiplicative correction submodule is communicatively connected to the additive correction submodule, the additive correction submodule is communicatively connected to the time domain filtering submodule, and the time domain filtering submodule is communicatively connected to the encoding output submodule;

[0019] The multiplicative correction submodule outputs the correction result after its own processing to the additive correction submodule through minimum delay, and the additive correction submodule outputs the correction result after its own processing to the time domain filtering submodule through minimum delay.

[0020] In a possible implementation, the infrared detector further includes a substrate;

[0021] The signal processing integrated circuit is arranged on the substrate, and the memory integrated circuit is arranged on a side of the signal processing integrated circuit away from the substrate;

[0022] or,

[0023] The signal processing integrated circuit and the memory integrated circuit are both disposed on the substrate, and an orthographic projection of the memory integrated circuit on the substrate and an orthographic projection of the signal processing integrated circuit on the substrate have a first preset distance therebetween.

[0024] In a possible implementation, the storage integrated circuit is provided with a first communication connection point, and a second communication connection point is provided on a side of the signal processing integrated circuit away from the substrate, and the first communication connection point is connected to the second communication connection point.

[0025] In a possible implementation, the infrared detector further includes a MEMS pixel array;

[0026] The MEMS pixel array and the second communication connection point are arranged on the same side of the signal processing integrated circuit;

[0027] The MEMS pixel array is communicatively connected to a readout module of the signal processing integrated circuit;

[0028] The MEMS pixel array is used to convert external infrared radiation into analog electrical signals.

[0029] In one possible implementation, the MEMS pixel array and the memory integrated circuit have no overlapping orthographic projections on the substrate, and there is a second preset distance between the orthographic projection of the memory integrated circuit on the substrate and the orthographic projection of the MEMS pixel array on the substrate.

[0030] In a possible implementation, the infrared detector further includes a cover structure;

[0031] The cover structure is disposed on the substrate, a cavity is formed between the cover structure and the substrate, and the signal processing integrated circuit, the MEMS pixel array and the memory integrated circuit are located in the cavity;

[0032] The cover structure includes an infrared light-transmitting surface and an annular protrusion, and the annular protrusion of the cover structure is connected to the base plate;

[0033] or,

[0034] The cover structure is arranged on a side of the signal processing integrated circuit away from the substrate, a cavity is formed between the cover structure and the signal processing integrated circuit, and the MEMS pixel array is located in the cavity;

[0035] The cover structure includes an infrared light-transmitting surface and an annular protrusion, and the annular protrusion of the cover structure is connected to the signal processing integrated circuit.

[0036] In a possible implementation manner, the second preset distance is not less than 1.5 times the thickness of the memory integrated circuit.

[0037] In a possible implementation, when the memory integrated circuit is disposed on a side of the signal processing integrated circuit away from the substrate, the side of the signal processing integrated circuit away from the substrate has a thermal conductive material deposition area;

[0038] The MEMS pixel array has no overlapping portion with the orthographic projection of the thermal conductive material deposition area on the substrate, and the orthographic projection of the memory integrated circuit on the substrate is included in the orthographic projection of the thermal conductive material deposition area on the substrate.

[0039] Beneficial effects of the embodiments of the present application:

[0040] An infrared detector provided in an embodiment of the present application includes: a signal processing integrated circuit and a storage integrated circuit; the signal processing integrated circuit is communicatively connected to the storage integrated circuit; the signal processing integrated circuit includes a readout module and a correction module; the readout module is used to obtain an analog electrical signal converted from external infrared radiation, convert the analog electrical signal into an original digital image signal, and output the original digital image signal to the correction module; the correction module is used to correct the original digital image signal based on correction configuration data to obtain a corrected digital image signal; and the storage integrated circuit is used to store the correction configuration data. By fabricating the correction module in the signal processing integrated circuit and then integrating the signal processing integrated circuit with the storage integrated circuit, the space occupied by the infrared sensing system can be reduced.

[0041] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0043] Figure 1 A schematic diagram of the first structure of the infrared detector provided in an embodiment of the present application;

[0044] Figure 2 A schematic top view of a signal processing integrated circuit for an infrared detector provided in an embodiment of the present application;

[0045] Figure 3 A schematic diagram of the second structure of the infrared detector provided in an embodiment of the present application;

[0046] Figure 4 A schematic diagram of a business slice table and a priority table corresponding to the business slice table;

[0047] Figure 5 A schematic diagram of a workflow of a signal processing integrated circuit for an infrared detector provided in an embodiment of the present application;

[0048] Figure 6 A schematic diagram of the arbitration logic of the read / write instruction arbitration unit;

[0049] Figure 7 A schematic diagram of the third structure of the infrared detector provided in an embodiment of the present application (stacked structure);

[0050] Figure 8 A schematic diagram of the fourth structure of the infrared detector provided in an embodiment of the present application (stacked structure);

[0051] Figure 9 A schematic diagram of the fifth structure (stacked structure) of the infrared detector provided in an embodiment of the present application;

[0052] Figure 10 This is a schematic diagram of the sixth structure (stacked structure) of the infrared detector provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0054] In existing uncooled infrared focal plane array (IRFPAA) sensor technology, the non-uniformity correction circuit features multiple modules, a complex structure, long computation time, and large storage requirements. This circuit primarily relies on an external image processor and external memory to perform the correction. Specifically, the uncooled IRFPAA sensor transmits the image signal to the non-uniformity correction circuit (which the external image processor includes) via a high-speed signal interface, while simultaneously relying on large-capacity external memory to perform the complex correction. The correction configuration data stored in the external memory is sent to the external image processor via another set of high-speed signal interfaces. The external image processor converts the correction configuration data and outputs it to the sensor. The non-uniformity correction circuit calculates the corrected image signal based on the acquired image signal and the correction configuration data, and outputs the corrected image signal via an image output interface. This results in a separate architecture for the uncooled IRFPAA sensor, image processor, and memory, resulting in a low level of integration and a large footprint for the infrared sensing system.

[0055] In order to improve the above-mentioned problems, the related art usually adopts the method of stacking multiple integrated circuits for integration. However, since the communication connection point and the photosensitive surface of the uncooled infrared focal plane array sensor are on the same side, and the size difference between the sensor and the correction circuit is large, it is difficult to integrate the uncooled infrared focal plane array sensor and the correction circuit in a stacked manner, or the cost of stacking integration is high.

[0056] In order to improve at least one of the above problems, an embodiment of the present application provides an infrared detector.

[0057] First, the professional terms that may be used in the embodiments of this application are explained:

[0058] Uncooled infrared focal plane (IRFP) sensitive pixels, also known as sensitive microbolometers, absorb external infrared radiation, causing the pixel itself to heat up, which in turn changes the resistance of the heat-sensitive material within the pixel. Given these performance characteristics, the pixel's output signal (usually a voltage) is read. The change in resistance of the heat-sensitive material within the pixel is then calculated based on the relationship between the output signal and the change in resistance. The amount of infrared radiation absorbed by the pixel is then determined based on the relationship between the change in resistance and the amount of absorbed external infrared radiation. Uncooled IRFP sensitive pixels generally utilize a cantilever microbridge structure fabricated using micromachining technology. A layer of heat-sensitive material with a high temperature coefficient of resistance is deposited on the bridge deck. The bridge deck is supported by two mechanically sound legs coated with a conductive material. The contact points between the legs and the substrate serve as bridge piers, which are electrically connected to a readout circuit. Through the legs and piers, the heat-sensitive material is connected to the readout circuit's electrical path, forming a temperature-sensitive pixel unit that is also connected to the readout circuit.

[0059] Uncooled infrared focal plane pixel array: includes multiple uncooled infrared focal plane sensitive pixels arranged orthogonally in rows and columns and bias circuits corresponding to each sensitive pixel.

[0060] Uncooled infrared focal plane array readout circuitry is used to extract, integrate, sample / hold, and perform analog-to-digital conversion on the weak electrical signals generated by the uncooled infrared focal plane pixel array, and then output them. Its typical structure includes a bias circuit, current mirror circuit, column integrator amplifier circuit, sample-and-hold circuit, multiplexer, timing control circuit, and analog-to-digital conversion circuit. The signal current generated by infrared thermal radiation is very small, so noise control in the circuit itself is crucial. Input stage zero offset, analog-to-digital conversion nonlinearity, and differences in charge transfer efficiency all contribute to nonuniformity in the readout circuit.

[0061] Non-uniformity in uncooled infrared focal plane arrays (IFPAs) refers to the phenomenon of inconsistent response output across pixels in an array under uniform infrared radiation input, manifesting as fixed pattern noise (FPN). Its primary causes include factors such as detector materials, manufacturing process quality, readout circuit non-uniformity, ambient temperature variations, and the infrared optical system. Specific forms of non-uniformity include fringe or grid noise, multiplicative and additive noise, and temperature-dependent noise. Non-uniformity poses significant challenges to image quality, radiometric measurement errors, and system stability.

[0062] Next, the infrared detector 1 provided in the embodiment of the present application is described in detail. Figure 1 , the infrared detector 1 includes:

[0063] A signal processing integrated circuit 11 and a memory integrated circuit 12; the signal processing integrated circuit 11 is communicatively connected to the memory integrated circuit 12;

[0064] The signal processing integrated circuit 11 includes a readout module 111 and a correction module 112; the readout module 111 is used to obtain the analog electrical signal converted from external infrared radiation, convert the analog electrical signal into an original digital image signal, and output the original digital image signal to the correction module 112; the correction module 112 is used to correct the original digital image signal based on the correction configuration data to obtain a corrected digital image signal; the storage integrated circuit 12 is used to store the correction configuration data.

[0065] The readout module 111 is used to output the original digital image signal to the correction module 112, and the storage control module 114 of the signal processing integrated circuit 11 is used to read the correction configuration data stored in the storage integrated circuit 12 to the correction module 112. The correction module 112 calculates the corrected digital image signal based on the acquired original digital image signal and the correction configuration data, and outputs the corrected digital image signal to the outside of the infrared detector 1 through its own image output interface, which can be directly used by the user.

[0066] In the embodiment of the present application, the correction module 112 is fabricated in the signal processing integrated circuit 11 (non-stacked integration), and the signal processing integrated circuit 11 is then integrated with the storage integrated circuit 12, thereby realizing the integration of infrared sensing, correction calculation, and storage, thereby improving the integration of the infrared sensing system and reducing the occupied space of the infrared sensing system. Moreover, on the basis of realizing the integration of sensing, calculation, and storage, the complexity of the circuit design is reduced, and the circuit design cost is reduced.

[0067] In one possible implementation, see Figure 1 and Figure 2 , the signal processing integrated circuit 11 further includes a control module 113, a storage control module 114, and a clock reset control module 115;

[0068] The control module 113, the readout module 111, the storage control module 114, the correction module 112, and the clock reset control module 115 are all communicatively connected to the first bus of the signal processing integrated circuit 11, and the readout module 111, the correction module 112, and the storage control module 114 are all communicatively connected to the second bus of the signal processing integrated circuit 11;

[0069] The control module 113 is used to control each module in the signal processing integrated circuit 11;

[0070] The storage control module 114 is used to read and write the correction configuration data in the correction module 112 and the storage integrated circuit 12;

[0071] The clock reset control module 115 is used to provide a timing reference for the signal processing integrated circuit 11 .

[0072] The bias circuit, multiplexer circuit, etc. inside the readout module 111 are controlled by the control module 113 via the first bus.

[0073] The storage control module 114 is controlled by the control module 113 via the first bus.

[0074] The clock reset control module 115 is used to generate the operating frequency and reset release control of each circuit of the infrared detector 1 . The clock reset control module 115 is controlled by the control module 113 through the first bus.

[0075] Correction module 112 is used to correct the non-uniformity of the original digital image signal and encode the corrected digital image signal into an image format such as BT1120 (a video coding standard for high-definition television studio signal digital interfaces), BT656 (a parallel hardware interface standard primarily used for transmitting standard-definition digital video streams), MIPI (Mobile Industry Processor Interface, a low-voltage differential signaling interface for high-speed, interference-resistant video data transmission), or DVP (Digital Video Port, a parallel transmission interface designed as a low-speed bus). The signal is then output to the outside of infrared detector 1 via a third bus for direct user use. Non-uniformity correction can include resistance correction, bias correction, two-point correction and temperature drift suppression, blanking correction, horizontal and vertical stripe removal, bad pixel removal, pothole removal, time-domain filtering and noise reduction, motion compensation, edge enhancement, wide dynamic range mapping, and image data encoding. The above-mentioned correction processes can be interconnected step by step to achieve successive correction. According to the needs of the scene, the parameter configuration of the control module 113 can be controlled by the first bus, and the correction cascade order (pipeline series order) can be adjusted in real time to an appropriate cascade order for different causes and types of non-uniformity.

[0076] The control module 113 is the core control module. It exchanges commands and data with components external to the infrared detector 1 via the fourth bus. It also relies on its internal central control unit to control the various modules within the signal processing integrated circuit 11 and the coordination between these modules via the first bus, achieving overall control of the infrared detector 1. The control module 113 is the scheduling core of the entire infrared detector 1. During the calibration phase (which involves collecting response data under known conditions, generating compensation parameters, and storing them through a preset standardized process), the control module 113 controls the modules within the signal processing integrated circuit 11 to complete the calibration according to the calibration process and stores the calibrated template data (corrected configuration data) in the storage integrated circuit 12. During normal operation, the control module 113 schedules the modules within the signal processing integrated circuit 11 based on the actual configuration and operating scenario, performing tasks such as timing control to ensure that the readout timing and calculated digital image signals meet design requirements. Furthermore, the control module 113 is required to monitor internal and external interruptions or other abnormal events in real time throughout the operation of the infrared detector 1 and handle these events to ensure that the infrared detector 1 operates as expected.

[0077] The storage control module 114 drives and reads and writes the storage integrated circuit 12 via the fifth bus according to the interface timing of the storage integrated circuit 12, and provides sufficient storage bandwidth for the infrared detector 1 via the second bus. It is necessary to reasonably select the storage integrated circuit 12 based on the requirements for storage capacity and bandwidth, and design the bus interface of the fifth bus based on the type of storage integrated circuit 12 and the interface protocol timing.

[0078] The second bus may be an AHB (Advanced High-performance Bus) or an AXI (Advanced Extensible Interface) bus, or other similar custom buses.

[0079] The fourth bus may be a SPI (Serial Peripheral Interface) or a USB (Universal Serial Bus) bus, or other similar custom buses.

[0080] The first bus may be an Advanced Peripheral Bus (APB) or an AHB bus, or other similar custom buses.

[0081] The third bus may be a BT656, MIPI or DVP bus, or other similar custom bus.

[0082] It can be understood that the first bus and the second bus are internal buses of the signal processing integrated circuit 11 , the third bus and the fourth bus are external buses, and the fifth bus is a bus between the signal processing integrated circuit 11 and the memory integrated circuit 12 .

[0083] By adopting a dual bus design (a first bus and a second bus) inside the signal processing integrated circuit 11, the first bus is used to transmit control signals, and the second bus is used to transmit data signals (the data signals mainly include the original digital image signals transmitted from the readout module 111 to the correction module 112, and the correction configuration data transmitted between the correction module 112 and the storage control module 114), the control flow and the data flow are separated, which can effectively improve the bandwidth congestion problem.

[0084] The storage control module 114 dynamically schedules the fifth bus and the second bus to match real-time storage requirements.

[0085] The storage control module 114 allocates storage bandwidth on demand. During the calibration phase, the control module 113 writes correction configuration data to the storage integrated circuit 12. During the working phase, the correction module 112 processes the original digital image signal in real time according to the configured pipeline sequence.

[0086] In order to more clearly understand the solution of the present application, the embodiment of the present application provides a simple schematic diagram of the position arrangement of each module in the signal processing integrated circuit 11, see Figure 2 (Top view diagram), of course Figure 2 The positions shown in the figure are for reference only and do not represent the actual position arrangement in actual application. In actual design, the positions of the modules need to be arranged reasonably according to the different resolutions and the power consumption and heat generation of each module to avoid affecting the temperature uniformity of the signal processing integrated circuit 11.

[0087] It is understandable that Figure 2 The position of the MEMS (Micro-Electro-Mechanical System) pixel array 15 provided on the signal processing integrated circuit 11 is also illustrated.

[0088] In an embodiment of the present application, a dual-bus design is adopted inside the signal processing integrated circuit 11, where the first bus is used to transmit control signals and the second bus is used to transmit data signals, thereby isolating the control flow from the data flow, thereby effectively improving the bandwidth congestion problem. Compared with the related art of data interaction between different integrated circuits, data interaction is carried out through the second bus, and transmission power consumption is reduced by about 70%. For different causes and types of non-uniformity, the control module 113 dynamically adjusts the correction cascade sequence (pipeline series sequence) to adapt to the needs of multiple scenarios and improve the configurability of the system. For non-essential correction types, the control module 113 can bypass them to ensure the flexibility of the system and further reduce power consumption.

[0089] In one possible implementation, see Figure 3 The control module 113 includes a central control unit 11131, a readout control unit 11132, a correction control unit 11133, and a memory control unit 11134;

[0090] The central control unit 11131 is respectively connected to the readout control unit 11132, the correction control unit 11133, and the memory control unit 11134; the readout control unit 11132 is connected to the readout module 111; the correction control unit 11133 is connected to the correction module 112; and the memory control unit 11134 is respectively connected to the readout module 111, the correction module 112, and the storage control module 114;

[0091] The central control unit 11131 is configured to obtain a target operating mode of the infrared detector 1 and activate its own pixel counter and row counter based on the target operating mode; the row counter counts the number of pixel rows in a frame of image, and the pixel counter counts the number of pixels in a row of pixels in a frame of image; generates a synchronization pulse, and utilizes the synchronization pulse to align the operations of the readout control unit 11132, the correction control unit 11133, and the memory control unit 11134;

[0092] The readout control unit 11132 is configured to generate a row cycle timing and a frame cycle timing for the readout module 111 based on the synchronization pulse and the target operating mode;

[0093] The correction control unit 11133 is configured to determine the pipeline series connection order of each correction submodule 1122 in the correction module 112 based on the synchronization pulse and the target working mode, and control each correction submodule 1122 to start working;

[0094] The memory control unit 11134 is used to generate a business slice table and a priority table for the readout module 111, the correction module 112, and the storage control module 114 based on the synchronization pulse and the target working mode; wherein the business slice table is the business demand determined based on the pipeline series order of the correction control unit 11133, and the priority table is the priority corresponding to each business slice in the business slice table.

[0095] The central control unit 11131, as the core unit of the control module 113, acts as the brain. After power-on initialization, the central control unit 11131 adaptively adjusts the working mode by sensing the working environment (such as temperature, posture, external environment, etc.). The central control unit 11131 will set the maximum value of the pixel counter and the row counter and the counting mode according to the working mode, and start counting. At the same time, the linkage coordination circuit within the central control unit 11131 generates a synchronization pulse to align the actions of the three units: the readout control unit 11132, the correction control unit 11133, and the memory control unit 11134. The synchronization pulse can achieve pixel-level alignment to achieve the purpose of efficient coordination.

[0096] In one example, the operating mode may be an HDR (High Dynamic Range) mode. In another example, the operating mode may be a real-time single-frame mode.

[0097] The readout control unit 11132 starts its own timing generation circuit based on the synchronization pulse and working mode, generates row cycle timing and frame cycle timing for the readout module 111, guides the operation of each circuit in the readout module 111, and applies different biases to each sensitive pixel row by row and point by point.

[0098] Based on the synchronization pulse and the operating mode, the correction control unit 11133 adjusts the pipeline series order of the N correction submodules 1122 and starts each correction submodule 1122. For different operating modes, the correction control unit 11133 can adjust the pipeline series order of each row in a fine-grained manner.

[0099] Based on the synchronization pulses and operating mode, the memory control unit 11134 generates a service slice table for the readout module 111 and the correction module 112, as well as a variable priority table to guide the operation of the read / write instruction channel and the read / write data channel of the storage control module 114. The memory control unit 11134 can fine-tune the service slices and priorities of the read / write services within each row. This dynamic scheduling mechanism ensures optimal memory requirements under different operating modes. The business slices are divided into read business R1, R2...Rn and write business W1, W2...Wn. The business slice table is the business demand determined based on the pipeline series sequence of the correction control unit 11133. For example, the pipeline series sequence is {second correction submodule, third correction submodule, first correction submodule}, where the second correction submodule requires 2 writes, the third correction submodule requires 1 write and 1 read, and the first correction submodule requires 1 write. Then the generated business slice is {R3, W2, W2, W3, W1}. The priority table is the priority corresponding to each business slice in the business slice table, with 1 being the highest and 5 being the lowest. The schematic diagram is shown as follows: Figure 4 As shown, the service slice table can be R3, W2, W2, W3, W1, and the corresponding priority table can be 1, 3, 3, 4, 4.

[0100] In an embodiment of the present application, the readout control unit 11132, the correction control unit 11133, and the memory control unit 11134 in the control module 113 tightly combine the originally independent readout module 111, the correction module 112, and the storage control module 114, and manage them in a unified manner, so that each module can achieve pixel-level alignment based on the working mode, reducing the management difficulty and time complexity of each module.

[0101] In order to more clearly understand the solution of the present application, a brief description of the working process of the signal processing integrated circuit 11 is given. Figure 5 , including the following steps:

[0102] Step 1: The signal processing integrated circuit 11 is initialized; Step 2: The central control unit 11131 obtains the working mode; Step 3: The central control unit 11131 starts the pixel counter and the row counter, and generates a synchronization pulse; Step 4: The readout control unit 11132 starts the timing generation, generates the row cycle timing and the frame cycle timing; Step 5: The correction control unit 11133 determines the pipeline series sequence of each correction submodule 1122 in the correction module 112, and controls each correction submodule 1122 to start the working state; Step 6: The memory control unit 11134 generates a business slice table and a priority table; Step 7: The readout module 111 outputs the original digital image signal of a sensitive pixel; Step 8: The storage control module 114 reads the Correction configuration data of the sensitive pixel should be obtained; Step 9, each correction submodule 1122 of the correction module 112 performs calculation based on the original digital image signal of the sensitive pixel and the correction configuration data to obtain a corrected digital image signal; Step 10, the encoding output submodule 1121 of the correction module 112 outputs the corrected digital image signal; Step 11, the storage control module 114 writes the updated correction configuration data into the storage integrated circuit 12; Step 12, whether the pixel counter reaches the number of pixels in one row, if not, return to execute steps 7 and 8, if yes, execute step 13, determine whether the row counter reaches the number of rows in one frame, if not, return to execute steps 4, 5, and 6, if yes, execute step 14, and one frame processing is completed.

[0103] In one possible implementation, see Figure 3 The storage control module 114 includes a read / write data transceiver unit 11141, a read / write data arbitration unit 11142, a read / write instruction generation unit 11143, a read / write instruction arbitration unit 11144, and a particle control unit 11145;

[0104] The read / write data transceiver unit 11141 is communicatively connected to the read / write data arbitration unit 11142, and the read / write data arbitration unit 11142 is communicatively connected to the particle control unit 11145; the read / write instruction generation unit 11143 is communicatively connected to the read / write instruction arbitration unit 11144, and the read / write instruction arbitration unit 11144 is communicatively connected to the read / write data arbitration unit 11142 and the particle control unit 11145 respectively; the particle control unit 11145 is communicatively connected to the storage integrated circuit 12;

[0105] The read / write instruction generating unit 11143 is configured to generate corresponding read / write instructions based on the service slice table of the control module 113;

[0106] The read / write instruction arbitration unit 11144 is configured to sort the read / write instructions based on the priority table of the control module 113;

[0107] The read / write data transceiver unit 11141 is configured to read the correction configuration data in the storage integrated circuit 12 to the correction module 112 , or write the correction configuration data in the correction module 112 to the storage integrated circuit 12 ;

[0108] The read / write data arbitration unit 11142 is used to control the transmission timing of the correction configuration data;

[0109] The particle control unit 11145 is used to convert the read and write instructions and the correction configuration data into signals recognized by the storage integrated circuit 12.

[0110] The read and write instruction generation unit 11143 of the storage control module 114 is used to generate corresponding read and write instructions based on the business slice table; the read and write instruction arbitration unit 11144 is used to arbitrate the read and write instructions sent by the read and write instruction generation unit 11143 according to the priority; the particle control unit 11145 is used to convert the read and write instructions and the correction configuration data into the external bus timing of the memory integrated circuit 12 interface to complete the corresponding read and write work.

[0111] The read / write instruction arbitration unit 11144 is the core unit of the storage control module 114. Its main task is to ensure that all services corresponding to the service slice table are completed within a synchronization pulse cycle. Its core mechanism is to reorder the read / write instructions according to the priority table, obtain the arbitration results, and send them out one by one. The arbitration logic diagram of the read / write instruction arbitration unit 11144 can be seen in Figure 6 , the read and write instructions can be C1, C2, C3, C4, C5, C6, and the corresponding priorities are 1, 3, 3, 2, 2, 2 respectively. The arbitration results are C1, C4, C5, C2, C6, C3.

[0112] In one possible embodiment, the correction module 112 is specifically used to receive the original digital image signal output by the readout module 111 and the correction configuration data read by the storage control module 114, and based on the original digital image signal and the correction configuration data, calculate a corrected digital image signal through its own correction sub-modules 1122, encode the corrected digital image signal through its own encoding output sub-module 1121 and output it, and obtain updated correction configuration data based on the corrected digital image signal and the original digital image signal, and write the updated correction configuration data into the storage integrated circuit 12 through the storage control module 114.

[0113] The cascade order of each correction submodule 1122 is controlled by the correction control unit 11133. This order can be adjusted in real time based on the operating mode to accommodate various operational scenarios. Once the cascade order is determined, each correction submodule 1122 sequentially inputs the correction results of the previous correction submodule to the next correction submodule in a pipelined manner with minimal latency, minimizing latency (in the microsecond range) and improving computational speed.

[0114] The updated correction configuration data is obtained based on the corrected digital image signal and the original digital image signal to ensure continuous optimization of the image processing effect and meet dynamically changing processing requirements (during the image processing process, conditions may change in real time, and the correction configuration data needs to be dynamically adjusted to adapt to the new situation. In addition, multi-step processing may accumulate errors. Updating the correction configuration data can eliminate these errors and improve accuracy).

[0115] In one possible implementation, see Figure 3 , the correction module 112 includes an encoding output submodule 1121 and N correction submodules 1122; wherein N is an integer not less than 1;

[0116] The i-th correction submodule 1122 is communicatively connected to the i-1-th correction submodule 1122, and the N-th correction submodule 1122 is communicatively connected to the encoding output submodule 1121; wherein i∈N, and i is an integer not less than 2;

[0117] The (i-1)th correction submodule 1122 outputs the correction result processed by itself to the (i)th correction submodule 1122 with minimum delay.

[0118] In the embodiment of the present application, the (i-1)th correction submodule 1122 outputs the correction result processed by itself to the (i)th correction submodule 1122 with minimum delay, so as to achieve minimum delay and improve operation speed.

[0119] In a possible implementation, the N correction submodules include a multiplicative correction submodule, an additive correction submodule, and a time domain filtering submodule;

[0120] The multiplicative correction submodule is communicatively connected to the additive correction submodule, the additive correction submodule is communicatively connected to the time domain filtering submodule, and the time domain filtering submodule is communicatively connected to the encoding output submodule 1121;

[0121] The multiplicative correction submodule outputs its own processed correction result to the additive correction submodule with minimum delay, and the additive correction submodule outputs its own processed correction result to the time domain filtering submodule with minimum delay to achieve minimum delay and improve operation speed.

[0122] The multiplicative correction submodule, the additive correction submodule, and the time domain filtering submodule all have built-in parameter caches (stored in the storage integrated circuit 12) to support parallel processing.

[0123] In a possible implementation, the infrared detector 1 further includes a substrate 13;

[0124] See also Figure 7 and Figure 8 , the signal processing integrated circuit 11 is arranged on the substrate 13, and the memory integrated circuit 12 is arranged on a side of the signal processing integrated circuit 11 away from the substrate 13;

[0125] or,

[0126] See Figure 9 and Figure 10 The signal processing integrated circuit 11 and the storage integrated circuit 12 are both arranged on the substrate 13, and there is a first preset distance between the orthographic projection of the storage integrated circuit 12 on the substrate 13 and the orthographic projection of the signal processing integrated circuit 11 on the substrate 13.

[0127] In one possible implementation, the memory integrated circuit 12 is provided with a first communication connection point, and the signal processing integrated circuit 11 is provided with a second communication connection point on a side away from the substrate 13, and the first communication connection point is connected to the second communication connection point. The memory integrated circuit 12 is communicatively connected to the signal processing integrated circuit 11 via the first and second communication connection points.

[0128] The first communication connection point can be set on a side of the storage integrated circuit 12 away from the substrate 13, or on a side of the storage integrated circuit 12 close to the substrate 13, or at other locations on the storage integrated circuit 12. This application does not make specific restrictions on this.

[0129] A third communication connection point is also provided on the substrate 13 , and the third communication connection point is connected to the second communication connection point. The signal processing integrated circuit 11 and the memory integrated circuit 12 communicate with external signals through the substrate 13 .

[0130] In one possible implementation, see Figure 7 、 Figure 8 、 Figure 9 and Figure 10 , the infrared detector 1 also includes a MEMS pixel array 15;

[0131] The MEMS pixel array 15 is arranged on a side of the signal processing integrated circuit 11 away from the substrate 13 (the MEMS pixel array 15 and the second communication connection point are arranged on the same side of the signal processing integrated circuit 11);

[0132] The MEMS pixel array 15 is communicatively connected to the readout module 111 of the signal processing integrated circuit 11;

[0133] The MEMS pixel array 15 is used to convert external infrared radiation into analog electrical signals.

[0134] The MEMS pixel array 15 can be a bridge-shaped pixel array, including a bridge deck and two edge supporting bridge legs. The edge supporting bridge legs can be communicatively connected to the readout module 111 of the signal processing integrated circuit 11. The MEMS pixel array 15 can also be a pixel array of other structures, which is not specifically limited in this application.

[0135] The bias circuit corresponding to each sensitive pixel in the MEMS pixel array 15 can be controlled by the control module 113 of the signal processing integrated circuit 11 via the first bus.

[0136] It is understandable that Figure 7 、 Figure 8 、 Figure 9 and Figure 10 The MEMS pixel array 15 is only shown schematically and does not represent its actual structure.

[0137] In one possible embodiment, the MEMS pixel array 15 and the memory integrated circuit 12 have no overlapping parts in their orthographic projections on the substrate 13, and there is a second preset distance between the orthographic projection of the memory integrated circuit 12 on the substrate 13 and the orthographic projection of the MEMS pixel array 15 on the substrate 13.

[0138] In a possible implementation manner, the second preset distance is not less than 1.5 times the thickness of the memory integrated circuit 12 .

[0139] See also Figure 7 When cover structure 14 is disposed on substrate 13 and memory integrated circuit 12 is disposed on a side of signal processing integrated circuit 11 away from substrate 13, the orthographic projections of MEMS pixel array 15 and memory integrated circuit 12 on substrate 13 do not overlap, and a second predetermined distance exists between the orthographic projections of memory integrated circuit 12 and MEMS pixel array 15 on substrate 13. This ensures that the projection of memory integrated circuit 12 avoids MEMS pixel array 15 and does not obstruct the optical path. In one example, in a 640×512 array with an 8-micron pixel pitch, zero obstruction can be achieved when the thickness of memory integrated circuit 12 is ≤200 microns.

[0140] In a possible embodiment, the infrared detector 1 further includes a cover structure 14, which can be seen in FIG. Figure 7 and Figure 10The cover structure 14 is disposed on the substrate 13, a cavity is formed between the cover structure 14 and the substrate 13, and the signal processing integrated circuit 11, the MEMS pixel array 15 and the storage integrated circuit 12 are located in the cavity;

[0141] The cover structure 14 includes an infrared light-transmitting surface 141 and an annular protrusion 142 , and the annular protrusion 142 of the cover structure 14 is connected to the base plate 13 ;

[0142] Alternatively, see Figure 8 and Figure 9 The cover structure 14 is provided on a side of the signal processing integrated circuit 11 away from the substrate 13 , a cavity is formed between the cover structure 14 and the signal processing integrated circuit 11 , and the MEMS pixel array 15 is located in the cavity;

[0143] The cover structure 14 includes an infrared light-transmitting surface 141 and an annular protrusion 142 . The annular protrusion 142 of the cover structure 14 is connected to the signal processing integrated circuit 11 .

[0144] The memory integrated circuit 12 comprises one or more volatile or non-volatile memory chips, used to store calibration data, perform correction calculations, and operate the central control unit 11131. The memory integrated circuit 12 must consume appropriate power to avoid temperature non-uniformity. The memory integrated circuit 12 communicates with the storage control module 114 of the signal processing integrated circuit 11 via a fifth bus to perform data access.

[0145] The signal processing integrated circuit 11 and the memory integrated circuit 12 are sealed in the same package through advanced packaging technology. The signal processing integrated circuit 11 and the memory integrated circuit 12 are connected to each other through wires to realize internal signal communication and to realize external signal communication through the substrate 13. The memory integrated circuit 12 can be stacked on the signal processing integrated circuit 11, such as Figure 7 and Figure 8 As shown, Figure 7 The memory integrated circuit 12 is at an appropriate distance from the MEMS pixel array 15 to avoid blocking the light path; if the side of the signal processing integrated circuit 11 away from the substrate 13 is not large enough to stack the memory integrated circuit 12, the memory integrated circuit 12 can be placed directly on the substrate 13, such as Figure 9 and Figure 10 The cover structure 14 includes an infrared light-transmitting surface 141 and an annular protrusion 142, so that the infrared detector 1 forms a vacuum cavity, thereby forming an infrared detector 1 that integrates sensing, computing and storage.

[0146] Annular protrusion 142 can be either an annular light-shielding protrusion or an annular light-transmitting protrusion, which is not specifically limited in this application. When annular protrusion 142 is an annular light-shielding protrusion, the material of the light-shielding protrusion can be metal, ceramic, or wafer-level. The light-shielding protrusion can serve the following functions: physically protecting the fragile infrared light-transmitting surface 141, isolating the integrated circuit from environmental dust and moisture, and preventing side light leakage that may cause signal crosstalk.

[0147] Figure 7 and Figure 10 The cavity formed by the infrared detector 1 shown in FIG can protect the exposed pads at the wire connection, thereby improving the reliability and safety of the infrared detector. Figure 7 and Figure 10 The infrared detector 1 shown in Figure 8 Zhongyu Figure 9 The infrared detector 1 shown in the figure is lighter and can be lightweight.

[0148] By adopting a dual integrated circuit package architecture, that is, the signal processing integrated circuit 11 and the storage integrated circuit 12 are integrated into the same package through advanced packaging technology, and the bus inside the same integrated circuit replaces the high-speed communication between different circuits, compared with the traditional separate architecture, high-speed communication between different circuits is eliminated, EMI (Electromagnetic Interference) risk is reduced, and PCB (Printed Circuit Board) design is simplified. The size after packaging is reduced by about 50% compared with the separate architecture, and through vacuum packaging and module layout optimization, thermal crosstalk is reduced and thermal stability is improved.

[0149] In one possible implementation, Figure 7 and Figure 8 In the infrared detector 1 shown, that is, when the memory integrated circuit 12 is arranged on a side of the signal processing integrated circuit 11 away from the substrate 13, the side of the signal processing integrated circuit 11 away from the substrate 13 has a heat conductive material deposition area;

[0150] The MEMS pixel array 15 has no overlapping portion with the orthographic projection of the thermal conductive material deposition area on the substrate 13 , and the orthographic projection of the storage integrated circuit 12 on the substrate 13 is included in the orthographic projection of the thermal conductive material deposition area on the substrate 13 .

[0151] By depositing a thermally conductive material on the side of the signal processing integrated circuit 11 away from the substrate 13, the heat generated by the memory integrated circuit 12 during operation is quickly transferred from the signal processing integrated circuit 11 to the substrate 13, thereby increasing the allowable power consumption of the memory integrated circuit 12 to 50 mW (milliwatts). In one example, the thermally conductive material can be aluminum nitride (AlN).

[0152] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0153] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0154] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. An infrared detector, characterized in that: The infrared detector comprises: A signal processing integrated circuit and a memory integrated circuit; the signal processing integrated circuit is communicatively connected to the memory integrated circuit; The signal processing integrated circuit includes a readout module and a correction module; the readout module is used to obtain the analog electrical signal converted from external infrared radiation, convert the analog electrical signal into an original digital image signal, and output the original digital image signal to the correction module; the correction module is used to correct the original digital image signal based on correction configuration data to obtain a corrected digital image signal; the storage integrated circuit is used to store the correction configuration data.

2. The infrared detector according to claim 1, characterized in that: The signal processing integrated circuit further includes a control module, a storage control module, and a clock reset control module; The control module, the readout module, the storage control module, the correction module, and the clock reset control module are all communicatively connected to a first bus of the signal processing integrated circuit, and the readout module, the correction module, and the storage control module are all communicatively connected to a second bus of the signal processing integrated circuit; The control module is used to control each module in the signal processing integrated circuit; The storage control module is used to read and write the correction configuration data in the correction module and the storage integrated circuit; The clock reset control module is used to provide a timing reference for the signal processing integrated circuit.

3. The infrared detector according to claim 1, characterized in that: The correction module is specifically configured to receive the original digital image signal output by the readout module and the correction configuration data read by the storage control module, calculate a corrected digital image signal based on the original digital image signal and the correction configuration data through its own correction submodules, encode and output the corrected digital image signal through its own encoding output submodule, and obtain updated correction configuration data based on the corrected digital image signal and the original digital image signal.

4. The infrared detector according to claim 3, characterized in that: The correction module includes an encoding output submodule and N correction submodules; wherein N is an integer not less than 1; The i-th correction submodule is communicatively connected to the i-1-th correction submodule, and the N-th correction submodule is communicatively connected to the encoding output submodule; wherein i∈N, and i is an integer not less than 2; The i-1th correction submodule outputs its own processed correction result to the i-th correction submodule with minimum delay.

5. The infrared detector according to claim 4, characterized in that: The N correction submodules include a multiplicative correction submodule, an additive correction submodule, and a time domain filtering submodule; The multiplicative correction submodule is communicatively connected to the additive correction submodule, the additive correction submodule is communicatively connected to the time domain filtering submodule, and the time domain filtering submodule is communicatively connected to the encoding output submodule; The multiplicative correction submodule outputs the correction result after its own processing to the additive correction submodule through minimum delay, and the additive correction submodule outputs the correction result after its own processing to the time domain filtering submodule through minimum delay.

6. The infrared detector according to claim 1, characterized in that: The infrared detector further includes a substrate; The signal processing integrated circuit is arranged on the substrate, and the memory integrated circuit is arranged on a side of the signal processing integrated circuit away from the substrate; or, The signal processing integrated circuit and the memory integrated circuit are both disposed on the substrate, and an orthographic projection of the memory integrated circuit on the substrate and an orthographic projection of the signal processing integrated circuit on the substrate have a first preset distance therebetween.

7. The infrared detector according to claim 1, characterized in that: The memory integrated circuit is provided with a first communication connection point, and a second communication connection point is provided on a side of the signal processing integrated circuit away from the substrate, and the first communication connection point is connected to the second communication connection point.

8. The infrared detector according to claim 7, characterized in that: The infrared detector also includes a MEMS pixel array; The MEMS pixel array and the second communication connection point are arranged on the same side of the signal processing integrated circuit; The MEMS pixel array is communicatively connected to a readout module of the signal processing integrated circuit; The MEMS pixel array is used to convert external infrared radiation into analog electrical signals.

9. The infrared detector according to claim 8, characterized in that: The orthographic projections of the MEMS pixel array and the memory integrated circuit on the substrate have no overlapping parts, and there is a second preset distance between the orthographic projection of the memory integrated circuit on the substrate and the orthographic projection of the MEMS pixel array on the substrate.

10. The infrared detector according to claim 6, characterized in that: The infrared detector further includes a cover structure; The cover structure is disposed on the substrate, a cavity is formed between the cover structure and the substrate, and the signal processing integrated circuit, the MEMS pixel array and the memory integrated circuit are located in the cavity; The cover structure includes an infrared light-transmitting surface and an annular protrusion, and the annular protrusion of the cover structure is connected to the base plate; or, The cover structure is arranged on a side of the signal processing integrated circuit away from the substrate, a cavity is formed between the cover structure and the signal processing integrated circuit, and the MEMS pixel array is located in the cavity; The cover structure includes an infrared light-transmitting surface and an annular protrusion, and the annular protrusion of the cover structure is connected to the signal processing integrated circuit.

11. The infrared detector according to claim 9, characterized in that: The second preset distance is not less than 1.5 times the thickness of the memory integrated circuit.

12. The infrared detector according to claim 6, characterized in that: When the memory integrated circuit is arranged on a side of the signal processing integrated circuit away from the substrate, the side of the signal processing integrated circuit away from the substrate has a heat conductive material deposition area; The MEMS pixel array has no overlapping portion with the orthographic projection of the thermal conductive material deposition area on the substrate, and the orthographic projection of the memory integrated circuit on the substrate is included in the orthographic projection of the thermal conductive material deposition area on the substrate.

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