A method, system and medium for testing vehicle chip performance under multiple temperature conditions

Abstract

The present application provides a method, system and medium for testing the performance of on-board chips under multiple temperature conditions. By setting a high and low temperature shock box, a control device and a clock source, the on-board chip to be tested is set in the high and low temperature shock box, and the clock source and the control device are placed outside the high and low temperature shock box; the internal temperature of the high and low temperature shock box is controlled; an excitation signal is sent to the on-board chip to be tested and the sending time is recorded; a completion signal sent by the on-board chip to be tested is received and the completion time is recorded; the execution time of the on-board chip to be tested to perform key operations is calculated; based on the execution time of the key operations performed at multiple internal temperatures, the performance test results of the on-board chip to be tested are determined; that is, the temperature control of the on-board chip to be tested is realized by using the high and low temperature shock box, and the control device and the clock source are set outside the high and low temperature shock box to avoid the influence of temperature changes in the high and low temperature shock box on the control device and the clock source, thereby improving the test accuracy.

Description

Technical Field

[0001] The present application relates to the technical field of vehicle-mounted chip performance testing, and specifically to a method, system, and medium for testing vehicle-mounted chip performance under multiple temperature conditions. Background Art

[0002] As intelligent driving and new energy vehicles increase their adaptability to a wider range of climate environments, automotive-grade chips must maintain consistent performance in critical operations under harsh temperature fluctuations. The execution time consistency of key chip operations (such as startup response, control feedback, communication transactions, and encryption authentication) directly impacts vehicle control safety and user experience, making it a key test metric for automotive-grade chip certification.

[0003] Existing testing techniques often place the test equipment and the chip under test in the same test environment, without considering the impact of temperature drift on the internal timers or software timing of the test equipment and the chip under test. This leads to insufficient test accuracy under varying temperature conditions. Therefore, a system and method that can accurately test the performance of automotive chips under multiple temperature conditions is urgently needed. Summary of the Invention

[0004] In order to solve the above technical problems, the present application is proposed. The embodiments of the present application provide a method, system and medium for testing the performance of an on-board chip under multiple temperature conditions.

[0005] According to one aspect of the present application, a method for testing the performance of an on-board chip under multiple temperature conditions is provided, which is applied to a system for testing the performance of an on-board chip under multiple temperature conditions. The system for testing the performance of an on-board chip under multiple temperature conditions includes a high and low temperature shock box, a control device and a clock source. The on-board chip to be tested is arranged in the high and low temperature shock box, the control device is connected to the high and low temperature shock box and the on-board chip to be tested, the clock source is connected to the control device, and the clock source and the control device are placed outside the high and low temperature shock box; the method for testing the performance of an on-board chip under multiple temperature conditions includes: controlling the internal temperature of the high and low temperature shock box according to test requirements; sending an excitation to the on-board chip to be tested signal to trigger the on-board chip to be tested to perform the corresponding key operation, and use the clock source to record the sending time of sending the excitation signal; wherein, the key operation represents the specific functional operation of the on-board chip to be tested; receive the completion signal sent by the on-board chip to be tested after completing the key operation, and use the clock source to record the completion time of sending the completion signal; based on the sending time and the completion time, calculate the execution time of the on-board chip to be tested to perform the key operation at the internal temperature; based on the execution time of the on-board chip to be tested to perform the key operation at multiple internal temperatures, determine the performance test result of the on-board chip to be tested.

[0006] In one embodiment, controlling the internal temperature of the high and low temperature shock box according to the test requirements includes: controlling the internal temperature of the high and low temperature shock box to adjust to a set temperature value according to the test requirements.

[0007] In one embodiment, controlling the internal temperature of the high and low temperature shock box according to test requirements also includes: collecting the actual temperature of the high and low temperature shock box; calculating a first difference between a preset temperature value and the actual temperature; and further adjusting the internal temperature of the high and low temperature shock box based on the first difference.

[0008] In one embodiment, controlling the internal temperature of the high and low temperature shock box according to the test requirements includes: controlling the internal temperature of the high and low temperature shock box to dynamically adjust according to a preset temperature change slope according to the test requirements.

[0009] In one embodiment, controlling the internal temperature of the high and low temperature shock box according to test requirements also includes: collecting the actual temperature of the high and low temperature shock box; calculating the actual temperature change rate of the high and low temperature shock box based on the actual temperature; calculating the second difference between the preset temperature change slope and the actual temperature change rate; and further adjusting the internal temperature of the high and low temperature shock box based on the second difference.

[0010] In one embodiment, determining the performance test result of the vehicle chip to be tested based on the execution time of the vehicle chip to be tested performing the key operation at multiple internal temperatures includes: calculating multiple performance indicators of the vehicle chip to be tested based on the execution time of the vehicle chip to be tested performing the key operation at multiple internal temperatures; and determining the performance test result of the vehicle chip to be tested based on the multiple performance indicators.

[0011] In one embodiment, the calculation of multiple performance indicators of the vehicle chip to be tested based on the execution time of the vehicle chip to be tested performing the key operation at multiple internal temperatures includes: calculating the execution time trend indicator, stability indicator, and sensitivity indicator of the vehicle chip to be tested based on the execution time of the vehicle chip to be tested performing the key operation at multiple internal temperatures; wherein the execution time trend indicator represents the overall time for the vehicle chip to be tested to perform the key operation, the stability index represents the time difference for the vehicle chip to be tested to perform the key operation at different temperatures, and the sensitivity index represents the degree of change in the execution time of the vehicle chip to be tested to perform the key operation at each temperature.

[0012] In one embodiment, the method for testing the performance of on-board chips under multiple temperature conditions also includes: determining a temperature drift correction function of the control device based on the ambient temperature of the control device; wherein the temperature drift correction function represents the delay amount of the control device under different ambient temperatures; calculating a temperature drift correction value based on the internal temperature of the control device and the temperature drift correction function; correcting the execution time based on the temperature drift correction value to obtain a corrected time; determining the performance test result of the on-board chip to be tested based on the execution time of the on-board chip to be tested performing the key operation at multiple internal temperatures includes: determining the performance test result of the on-board chip to be tested based on the corrected time of the on-board chip to be tested performing the key operation at multiple internal temperatures.

[0013] According to another aspect of the present application, a vehicle-mounted chip performance testing system under multiple temperature conditions is provided, including: a high and low temperature shock box, in which the vehicle-mounted chip to be tested is arranged; a control device, which is connected to the high and low temperature shock box and the vehicle-mounted chip to be tested; a clock source, which is connected to the control device; wherein the clock source and the control device are placed outside the high and low temperature shock box, and the control device is used to execute the vehicle-mounted chip performance testing method under multiple temperature conditions described in any one of the above items.

[0014] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute any of the above methods.

[0015] The present application provides a method, system and medium for testing the performance of an on-board chip under multiple temperature conditions. By setting a high and low temperature shock box, a control device and a clock source, the on-board chip to be tested is set in the high and low temperature shock box, the control device is connected to the high and low temperature shock box and the on-board chip to be tested, and the clock source is connected to the control device; wherein the clock source and the control device are placed outside the high and low temperature shock box; and according to the test requirements, the internal temperature of the high and low temperature shock box is controlled; an excitation signal is sent to the on-board chip to be tested to trigger the on-board chip to perform the corresponding key operation, and the clock source is used to record the sending time of the excitation signal; the on-board chip to be tested is received The chip sends a completion signal after completing the key operation, and uses a clock source to record the completion time of sending the completion signal; based on the sending time and completion time, calculate the execution time of the key operation performed by the on-board chip to be tested at the internal temperature; based on the execution time of the key operation performed by the on-board chip to be tested at multiple internal temperatures, determine the performance test results of the on-board chip to be tested; that is, use a high and low temperature shock box to achieve temperature control of the on-board chip to be tested, and set a control device and a clock source outside the high and low temperature shock box to avoid the influence of temperature changes in the high and low temperature shock box on the control device and the clock source, thereby improving the test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other purposes, features, and advantages of the present application will become more apparent through a more detailed description of the embodiments of the present application in conjunction with the accompanying drawings. The accompanying drawings are intended to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0017] Figure 1 This is a structural diagram of a vehicle-mounted chip performance testing system under multiple temperature conditions provided by an exemplary embodiment of the present application.

[0018] Figure 2 This is a flow chart of a method for testing the performance of an on-board chip under multiple temperature conditions provided by an exemplary embodiment of the present application.

[0019] Figure 3 It is a structural diagram of an electronic device provided by an exemplary embodiment of the present application.

[0020] Explanation of the accompanying symbols: 1. High and low temperature shock box; 2. Control equipment; 3. Clock source; 4. On-board chip to be tested. DETAILED DESCRIPTION

[0021] Below, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described herein.

[0022] Figure 1 This is a schematic diagram of the structure of a vehicle chip performance test system under multiple temperature conditions provided by an exemplary embodiment of the present application. Figure 1As shown, the system for testing the performance of an on-board chip under multiple temperature conditions includes a high-temperature shock chamber 1, a control device 2, and a clock source 3. The on-board chip 4 to be tested is disposed within the high-temperature shock chamber 1, the control device 2 is connected to the high-temperature shock chamber 1 and the on-board chip 4 to be tested, and the clock source 3 is connected to the control device 2. The clock source 3 and the control device 2 are disposed outside the high-temperature shock chamber 1. By disposing the high-temperature shock chamber 1, the temperature inside the high-temperature shock chamber 1 can be dynamically set and adjusted (e.g., -40°C to 125°C), thereby enabling performance testing of the on-board chip 4 to be tested under different ambient temperatures. Furthermore, by disposing the control device 2 outside the high-temperature shock chamber 1, the control device 2 is used to simultaneously control the temperature inside the high-temperature shock chamber 1 and the performance testing of the on-board chip 4 to be tested, thereby preventing changes in the temperature environment from affecting the control device 2, thereby improving test accuracy. Furthermore, by disposing the clock source 3 outside the high-temperature shock chamber 1, the system further improves test accuracy by preventing changes in the temperature environment from affecting the internal timer of the on-board chip 4 to be tested. The control device 2 can be a field-programmable gate array (FPGA), and the interfaces of the onboard chip to be tested 4 can include GPIO, SPI, I2C, LIN, CAN, UART, etc. Using this multi-temperature onboard chip performance testing system, the test resolution can reach 24.7 picoseconds, and the temperature drift coefficient can be as low as 0.0338 picoseconds / degree Celsius, fully meeting high-precision testing requirements. Optionally, this application can also include a data acquisition and analysis terminal (e.g., a PC) to obtain relevant data during the test and generate a test report.

[0023] The present application provides a vehicle-mounted chip performance testing system under multiple temperature conditions. By setting a high and low temperature shock box, a control device and a clock source, the vehicle-mounted chip to be tested is set in the high and low temperature shock box, the control device is connected to the high and low temperature shock box and the vehicle-mounted chip to be tested, and the clock source is connected to the control device; wherein the clock source and the control device are placed outside the high and low temperature shock box; the high and low temperature shock box is used to realize the temperature control of the vehicle-mounted chip to be tested, and the control device and the clock source are set outside the high and low temperature shock box to avoid the influence of temperature changes in the high and low temperature shock box on the control device and the clock source, thereby improving the test accuracy.

[0024] Figure 2 This is a flow chart of a method for testing the performance of an onboard chip under multiple temperature conditions provided by an exemplary embodiment of the present application. The method for testing the performance of an onboard chip under multiple temperature conditions is applied to the above-mentioned onboard chip performance testing system under multiple temperature conditions; Figure 2 As shown, the vehicle-mounted chip performance testing method under multiple temperature conditions includes the following steps:

[0025] Step 210: Control the internal temperature of the high and low temperature shock chamber according to test requirements.

[0026] After building the above-mentioned test system, this application sends temperature control instructions to the high and low temperature shock box through the control device to control the internal temperature of the high and low temperature shock box to meet the test requirements, thereby realizing the test of the on-board chip to be tested in a specific temperature environment.

[0027] Step 220: Send an excitation signal to the onboard chip to be tested to trigger the onboard chip to be tested to perform a corresponding key operation, and use a clock source to record the sending time of the excitation signal.

[0028] After controlling the internal temperature of the high and low temperature shock box, this application sends an excitation signal to the on-board chip to be tested to trigger the on-board chip to be tested to perform corresponding key operations (such as specific functional operations of the on-board chip to be tested), and uses a clock source to record the sending time of the excitation signal.

[0029] Step 230: Receive a completion signal sent by the on-board chip to be tested after completing the key operation, and use a clock source to record the completion time of sending the completion signal.

[0030] After sending the stimulus signal, the on-board chip to be tested will send a signal indicating that the operation is completed (i.e., a completion signal) after completing the key operation. After receiving the completion signal, the control device controls the clock source to record the time of the completion signal (i.e., the completion time).

[0031] Step 240: Calculate the execution time of the onboard chip to be tested to perform the key operation at the internal temperature based on the sending time and the completion time.

[0032] Based on the sending time and completion time, the execution time of the tested vehicle chip to perform the key operation at the internal temperature is calculated. That is, based on the time from the tested vehicle chip receiving the excitation signal to the completion of the corresponding operation, the execution time of the key operation is calculated. Specifically, execution time = completion time - sending time.

[0033] Step 250 : Determine a performance test result of the onboard chip to be tested based on the execution time of the onboard chip to be tested performing key operations at multiple internal temperatures.

[0034] This application controls the temperature changes of high and low temperature shock boxes to achieve performance testing of the on-board chip to be tested under different temperature conditions, and determines the performance test results of the on-board chip to be tested by combining the execution time of key operations at multiple internal temperatures.

[0035] The present application provides a method for testing the performance of an on-board chip under multiple temperature conditions, which comprises setting a high and low temperature shock chamber, a control device and a clock source, wherein the on-board chip to be tested is set in the high and low temperature shock chamber, the control device is connected to the high and low temperature shock chamber and the on-board chip to be tested, and the clock source is connected to the control device; wherein the clock source and the control device are placed outside the high and low temperature shock chamber; and according to the test requirements, the internal temperature of the high and low temperature shock chamber is controlled; an excitation signal is sent to the on-board chip to be tested to trigger the on-board chip to perform a corresponding key operation, and the clock source is used to record the sending time of the excitation signal; a completion signal is received after the on-board chip to be tested completes the key operation, and the clock source is used to record the completion time of the sending of the completion signal; based on the sending time and the completion time, the execution time of the on-board chip to be tested performing the key operation at the internal temperature is calculated; based on the execution time of the on-board chip to be tested performing the key operation at multiple internal temperatures, the performance test result of the on-board chip to be tested is determined; that is, the temperature of the on-board chip to be tested is controlled by using the high and low temperature shock chamber, and the control device and the clock source are set outside the high and low temperature shock chamber to avoid the influence of temperature changes in the high and low temperature shock chamber on the control device and the clock source, thereby improving the test accuracy.

[0036] In one embodiment, the specific implementation of the above step 210 may be: according to the test requirements, the internal temperature of the high and low temperature shock box is controlled to be adjusted to a set temperature value.

[0037] This application can set the high and low temperature shock box to a high temperature zone, a room temperature zone, and a low temperature zone, and perform temperature control on different partitions to ensure that the temperature in the corresponding partition reaches the set temperature value or temperature range, so as to realize the performance test of the on-board chip to be tested at a static temperature.

[0038] In one embodiment, the specific implementation method of the above step 210 can be: collecting the actual temperature of the high and low temperature shock box; calculating the first difference between the preset temperature value and the actual temperature; and further adjusting the internal temperature of the high and low temperature shock box based on the first difference.

[0039] In the process of adjusting the internal temperature of the high and low temperature shock box, the present application collects the actual temperature inside the high and low temperature shock box in real time (using temperature sensors and other equipment to collect), and calculates the difference between the preset temperature value (i.e., the target value) and the actual temperature, and based on the difference, corrects the temperature control amount of the high and low temperature shock box to adjust the internal temperature of the high and low temperature shock box to the preset temperature value, thereby improving the accuracy of temperature control.

[0040] In one embodiment, the specific implementation of the above step 210 may be: according to the test requirements, the internal temperature of the high and low temperature shock box is controlled to be dynamically adjusted according to a preset temperature change slope.

[0041] The present application can also set a temperature control curve (for example, setting the rate of temperature rise or fall, i.e., the temperature change rate) to control the internal temperature of the high and low temperature shock box to change according to the temperature control curve, thereby realizing the performance test of the on-board chip to be tested in a dynamically changing temperature environment.

[0042] Correspondingly, the present application can use a set period or a set temperature interval to send an excitation signal and receive a completion signal to test the performance of the on-board chip to be tested under different temperature conditions.

[0043] In one embodiment, the specific implementation method of the above-mentioned step 210 can be: collecting the actual temperature of the high and low temperature shock box; calculating the actual temperature change rate of the high and low temperature shock box based on the actual temperature; calculating the second difference between the preset temperature change slope and the actual temperature change rate; and further adjusting the internal temperature of the high and low temperature shock box based on the second difference.

[0044] In the process of adjusting the internal temperature of the high and low temperature shock box, the present application collects the actual temperature inside the high and low temperature shock box in real time (using temperature sensors and other equipment for collection), and calculates the actual temperature change rate of the high and low temperature shock box based on the actual temperature, calculates the difference between the preset temperature change slope (i.e., the target temperature change rate) and the actual temperature change rate, and corrects the temperature control amount of the high and low temperature shock box based on the difference to adjust the internal temperature change rate of the high and low temperature shock box to the preset temperature change rate, thereby improving the accuracy of dynamic temperature control.

[0045] In one embodiment, the specific implementation method of the above-mentioned step 250 can be: calculating multiple performance indicators of the vehicle-mounted chip to be tested based on the execution time of the vehicle-mounted chip to be tested performing key operations at multiple internal temperatures; and determining the performance test results of the vehicle-mounted chip to be tested based on the multiple performance indicators.

[0046] This application tests the execution time of key operations of the vehicle-mounted chip to be tested at multiple internal temperatures, calculates multiple performance indicators of the vehicle-mounted chip to be tested in multiple dimensions, and comprehensively evaluates the performance of the vehicle-mounted chip to be tested by combining multiple performance indicators.

[0047] In one embodiment, the specific implementation method of the above-mentioned step 210 can be: based on the execution time of the vehicle-mounted chip to be tested to perform key operations at multiple internal temperatures, calculate the execution time trend index, stability index, and sensitivity index of the vehicle-mounted chip to be tested; wherein, the execution time trend index represents the overall time for the vehicle-mounted chip to be tested to perform key operations, the stability index represents the time difference for the vehicle-mounted chip to be tested to perform key operations at different temperatures, and the sensitivity index represents the degree of change in the execution time of the vehicle-mounted chip to be tested to perform key operations at various temperatures.

[0048] This application calculates the execution time trend index, stability index, and sensitivity index of the vehicle-mounted chip to be tested to determine the overall time for the vehicle-mounted chip to be tested to perform key operations, the time difference for the vehicle-mounted chip to be tested to perform key operations at different temperatures, and the degree of change in the execution time of the vehicle-mounted chip to be tested to perform key operations at various temperatures, thereby comprehensively evaluating the performance of the vehicle-mounted chip to be tested from multiple dimensions.

[0049] Among them, the specific calculation method of the execution time trend indicator can be: calculating the average value (that is, the average value within a fixed window) of multiple adjacent target points during the test process (which can be multiple time points in static testing or multiple temperature points in dynamic testing), thereby obtaining multiple average points representing the average values ​​of each window, and connecting multiple average points to obtain a curve, which represents the overall time trend of the key operations performed by the on-board chip to be tested.

[0050] The specific calculation method of the stability index can be: calculate the standard deviation of multiple adjacent target points during the test process (which can be multiple time points in static testing or multiple temperature points in dynamic testing) as the stability index. The smaller the standard deviation, the more similar the time it takes for the on-board chip to perform key operations at each temperature, and the more stable its performance.

[0051] The specific calculation method of the sensitivity index can be: calculate the slope between two adjacent target points during the test process (that is, the time difference divided by the temperature difference) as the sensitivity index of the on-board chip to be tested at the corresponding temperature. The larger the absolute value of the slope, the more sensitive the on-board chip to be tested is to the temperature.

[0052] Optionally, when performing static testing, the present application may also set a threshold. For example, if the standard deviation of the on-board chip under test is greater than a preset standard deviation threshold or the time increment exceeds a set ratio (e.g., 20%) within a short set time, the on-board chip under test is judged to have poor performance or to be more sensitive at a specific temperature. For another example, if the absolute rate of change (i.e., temperature drift coefficient) of the time taken by the on-board chip under test to perform key operations suddenly increases (greater than a set value) or there is a large difference between the execution time of a single target point and the execution time of adjacent target points, the on-board chip under test is judged to have poor performance or to be more sensitive at a specific temperature.

[0053] Optionally, when conducting dynamic testing, the present application can also set a slope attenuation factor, that is, when the on-board chip to be tested reaches the above-mentioned threshold, the slope attenuation is triggered. At this time, the rising or falling slope of the temperature curve is controlled to be multiplied by the slope attenuation factor (for example, 50% or 25%), that is, the rising or falling slope of the temperature curve is slowed down to achieve a fine scan of the sensitive temperature range and obtain as many target points as possible.

[0054] In one embodiment, the above-mentioned method for testing the performance of on-board chips under multiple temperature conditions may further include: determining a temperature drift correction function of the control device based on the ambient temperature of the control device; wherein the temperature drift correction function represents the delay amount of the control device under different ambient temperatures; calculating a temperature drift correction value based on the internal temperature of the control device and the temperature drift correction function; correcting the execution time based on the temperature drift correction value to obtain a corrected time; correspondingly, the specific implementation method of the above-mentioned step 250 may be: determining the performance test result of the on-board chip to be tested based on the corrected time of the on-board chip to be tested performing key operations at multiple internal temperatures.

[0055] Since the control device itself may have a certain temperature drift, which may cause a certain deviation in the test results, this application conducts a temperature drift test on the control device before the test. The specific test process is: place the control device in a temperature chamber that can slowly change the ambient temperature, and at multiple temperature points (for example, from 15°C to 35°C, with a point set every 1°C), record two data at the same time: the temperature read by the temperature sensor inside the control device and the temperature reading of the temperature sensor. and the measured value of the reference delay chain inside the control device (the input of the reference delay chain is a fixed and known delay generated by dividing a stable clock source inside the control device) , the actual delay of the known reference delay chain should be constant , at different temperatures Next, the measured value Drift will occur, thus, calculating at each temperature point The measurement error , these The data points are fitted to obtain a temperature drift correction function or lookup table. In the actual test process, this application reads the internal temperature of the control device ,according to , calculate the internal temperature through the temperature drift correction function or lookup table Under this condition, the inherent measurement error of the control device itself is controlled, and the inherent measurement error of the device itself is recorded as , subtract this error from the original measurement value to obtain the final, temperature drift compensated, true and accurate operation time, that is: ,in, For the final, temperature drift compensated, true and accurate operating time, is the original measurement value.

[0056] Below, reference Figure 3 The electronic device according to the embodiment of the present application is described. The electronic device may be either or both of the first device and the second device, or a standalone device independent of them, and the standalone device may communicate with the first device and the second device to receive collected input signals from them.

[0057] Figure 3 The figure shows a block diagram of an electronic device according to an embodiment of the present application.

[0058] like Figure 3 As shown, the electronic device 10 includes one or more processors 11 and a memory 12 .

[0059] The processor 11 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0060] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 11 may execute the program instructions to implement the methods of the various embodiments of the present application described above and / or other desired functions. Various contents such as input signals, signal components, and noise components may also be stored in the computer-readable storage medium.

[0061] In one example, the electronic device 10 may further include an input device 13 and an output device 14 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0062] When the electronic device is a stand-alone device, the input device 13 may be a communication network connector, configured to receive collected input signals from the first device and the second device.

[0063] In addition, the input device 13 may also include, for example, a keyboard, a mouse, and the like.

[0064] The output device 14 can output various information to the outside, including determined distance information, direction information, etc. The output device 14 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0065] Of course, to simplify, Figure 3 Only some of the components related to the present application in the electronic device 10 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, the electronic device 10 may further include any other appropriate components according to specific application scenarios.

[0066] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method according to various embodiments of the present application described in the above-mentioned "Exemplary Method" section of this specification.

[0067] The computer program product may be written in any combination of one or more programming languages ​​to implement the program code for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0068] In addition, an embodiment of the present application may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enable the processor to execute the steps of the method according to various embodiments of the present application described in the above "Exemplary Method" section of this specification.

[0069] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0070] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this application are merely illustrative and not restrictive, and it should not be assumed that these advantages, strengths, and effects are required of each embodiment of this application. In addition, the specific details disclosed above are merely illustrative and facilitating understanding, and are not restrictive. The above details do not limit this application to necessarily being implemented using the above specific details.

[0071] The block diagrams of the devices, devices, equipment, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0072] It should also be noted that in the apparatus, device, and method of the present application, each component or each step can be decomposed and / or recombined, and such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0073] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0074] The above description has been provided for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for testing the performance of an on-board chip under multiple temperature conditions, characterized in that: The system is applied to a vehicle-mounted chip performance test system under multiple temperature conditions, comprising a high-low temperature shock chamber, a control device, and a clock source. The vehicle-mounted chip to be tested is arranged in the high-low temperature shock chamber, the control device is connected to the high-low temperature shock chamber and the vehicle-mounted chip to be tested, the clock source is connected to the control device, and the clock source and the control device are placed outside the high-low temperature shock chamber. The vehicle-mounted chip performance testing method under multiple temperature conditions includes: Controlling the internal temperature of the high and low temperature shock box according to test requirements; Sending an excitation signal to the onboard chip to be tested to trigger the onboard chip to be tested to perform a corresponding key operation, and using the clock source to record the sending time of the excitation signal; wherein the key operation represents a specific functional operation of the onboard chip to be tested; receiving a completion signal sent by the on-board chip to be tested after completing the key operation, and using the clock source to record the completion time of sending the completion signal; Calculating, based on the sending time and the completion time, an execution time for the on-board chip to be tested to perform the key operation at the internal temperature; Determining a performance test result of the on-board chip to be tested based on the execution time of the key operation performed by the on-board chip to be tested at the multiple internal temperatures; Determining the performance test result of the onboard chip to be tested based on the execution time of the key operation performed by the onboard chip to be tested at the plurality of internal temperatures includes: Calculating a plurality of performance indicators of the on-board chip to be tested based on the execution time of the on-board chip to be tested performing the key operation at the plurality of internal temperatures; Determining a performance test result of the on-board chip to be tested based on the multiple performance indicators; The calculating of the multiple performance indicators of the onboard chip to be tested based on the execution time of the key operation performed by the onboard chip to be tested at the multiple internal temperatures includes: Based on the execution time of the vehicle-mounted chip to be tested to perform the key operation at multiple internal temperatures, the execution time trend index, stability index, and sensitivity index of the vehicle-mounted chip to be tested are calculated; wherein, the execution time trend index represents the overall time for the vehicle-mounted chip to be tested to perform the key operation, the stability index represents the time difference for the vehicle-mounted chip to be tested to perform the key operation at different temperatures, and the sensitivity index represents the degree of change in the execution time of the vehicle-mounted chip to be tested to perform the key operation at various temperatures.

2. The method for testing the performance of an on-board chip under multiple temperature conditions according to claim 1, characterized in that: According to the test requirements, controlling the internal temperature of the high and low temperature shock box includes: According to the test requirements, the internal temperature of the high and low temperature shock box is controlled to be adjusted to the set temperature value.

3. The method for testing the performance of an on-board chip under multiple temperature conditions according to claim 2, characterized in that: According to the test requirements, controlling the internal temperature of the high and low temperature shock box also includes: Collecting the actual temperature of the high and low temperature shock box; calculating a first difference between a preset temperature value and the actual temperature; The internal temperature of the high and low temperature shock box is further adjusted based on the first difference.

4. The method for testing the performance of an on-board chip under multiple temperature conditions according to claim 1, characterized in that: According to the test requirements, controlling the internal temperature of the high and low temperature shock box includes: According to the test requirements, the internal temperature of the high and low temperature shock box is controlled to be dynamically adjusted according to the preset temperature change slope.

5. The method for testing the performance of an on-board chip under multiple temperature conditions according to claim 4, characterized in that: According to the test requirements, controlling the internal temperature of the high and low temperature shock box also includes: Collecting the actual temperature of the high and low temperature shock box; Calculating an actual temperature change rate of the high and low temperature shock box based on the actual temperature; calculating a second difference between the preset temperature change slope and the actual temperature change rate; The internal temperature of the high and low temperature shock box is further adjusted based on the second difference.

6. The method for testing the performance of an on-board chip under multiple temperature conditions according to claim 1, characterized in that: The vehicle-mounted chip performance testing method under multiple temperature conditions also includes: Determining a temperature drift correction function of the control device based on the ambient temperature of the control device; wherein the temperature drift correction function represents the delay amount of the control device at different ambient temperatures; calculating a temperature drift correction value based on the internal temperature of the control device and the temperature drift correction function; Correcting the execution time based on the temperature drift correction value to obtain a corrected time; Determining the performance test result of the onboard chip to be tested based on the execution time of the key operation performed by the onboard chip to be tested at the plurality of internal temperatures includes: The performance test result of the onboard chip to be tested is determined based on the corrected time of the onboard chip to be tested performing the key operation at the multiple internal temperatures.

7. A vehicle-mounted chip performance testing system under multiple temperature conditions, characterized in that: include: A high and low temperature shock box, in which the onboard chip to be tested is placed; A control device connected to the high and low temperature shock box and the on-board chip to be tested; a clock source, the clock source being connected to the control device; Wherein, the clock source and the control device are placed outside the high and low temperature shock box, and the control device is used to execute the vehicle chip performance testing method under multiple temperature conditions according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and the computer program is used to execute the method according to any one of claims 1 to 6.

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