SET-resistant high-transient off-chip capacitor-free LDO circuit and chip

Abstract

The invention relates to the technical field of integrated circuit design, in particular to an anti-SET high transient LDO circuit without an off-chip capacitor and a chip. A dynamic bias sub-circuit and two reinforcing sub-circuits are additionally arranged on an LDO sub-circuit without an off-chip capacitor; wherein the dynamic bias sub-circuit can dynamically improve the loop bandwidth, improve the response speed and improve the transient response; wherein one reinforcing sub-circuit dissipates charges generated by particle bombardment to realize a reinforcing effect on the sensitive node V2; and the other reinforcing sub-circuit not only has a reinforcing effect on the sensitive node Vg, but also can enhance the slew rate of the Vg so as to improve the transient response. The LDO circuit solves the problems that the output stability of an existing LDO circuit without an off-chip capacitor is greatly influenced by transient change of an output load and SET, and the LDO circuit is difficult to work normally in specific environments such as a radiation environment and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and more specifically to: 1. a high-transient, no-off-chip-capacitor LDO (low-dropout linear regulator) circuit that is resistant to SET (single-event transient effect); and 2. a high-transient, no-off-chip-capacitor LDO chip that is resistant to SET. Background Art

[0002] Traditional LDO topologies require at least one external capacitor and a dedicated output pin for each LDO. This necessitates numerous bulky external components, consumes more PCB space, and increases the IC pin count. This runs counter to the trend of higher integration and smaller size in consumer portable electronics.

[0003] However, considering the role of off-chip capacitors, the design of LDO without off-chip capacitors will face greater challenges in transient response, loop frequency compensation and power supply rejection ratio performance.

[0004] Existing capacitor-free LDOs are highly sensitive to transient effects. When chips containing capacitor-free LDO circuits enter the space environment, the complex cosmic ray radiation present there, including single-event effects (such as single-event upsets and single-event transients) and total dose effects, can cause integrated circuit performance degradation, functional abnormalities, or even permanent damage. When heavy ions strike sensitive nodes in the LDO circuit, they generate SET perturbations along their propagation path, ultimately producing transient pulses in the output DC level. This can affect subsequent circuits and systems, leading to errors and even global functional interruptions. Therefore, designing highly transient, capacitor-free LDO circuits that are resistant to SET is of great significance and necessity. Summary of the Invention

[0005] Based on this, in order to address the problem that the output stability of existing LDO circuits without external capacitors is greatly affected by transient changes in the output load and SET, and is difficult to work normally in specific environments such as radiation environments, the present invention provides a high transient SET-resistant LDO circuit and chip without external capacitors.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] In a first aspect, the present invention provides a SET-resistant high transient LDO circuit without external capacitors, comprising: an LDO subcircuit without external capacitors, a dynamic bias subcircuit, a first reinforcement subcircuit, and a second reinforcement subcircuit.

[0008] The LDO sub-circuit without external capacitors has two sensitive nodes V2 and Vg, two bias control nodes V1 and Va, one op amp control node V5, one feedback node Vfb, and one output terminal Vout.

[0009] The dynamic bias subcircuit is connected to V5 to ensure that Vout maintains a stable output when the load transient changes.

[0010] The reinforcement sub-circuit 1 is connected to V2 and is used to reinforce V2.

[0011] The second reinforcement sub-circuit is used to reinforce Vg and enhance the Vg slew rate to improve transient response.

[0012] Among them, the reinforcement sub-circuit 2 includes: 4 PMOS transistors P9-P12, 4 NMOS transistors N9-N12, and 1 capacitor Ct. The sources of P9-P12 are connected to the power supply VDD; the drain of P9 is connected to Vg, and the gate is connected to the drain of P12 and the drain of N12; the drain of P10 is connected to the gate of N9 and the drain of N10; the gate of P10 and the gate of P11 are connected to V1; the drain of P11 is connected to the gate of N11, the drain of N11, the gate of N10, the gate of P12, and the positive electrode of Ct; the negative electrode of Ct is connected to Vfb; the sources of N9-N12 are grounded GND; the gate of N12 is connected to Va.

[0013] The implementation of such a SET-resistant, high-transient, and off-chip capacitor-free LDO circuit is based on a method or process according to an embodiment of the present disclosure.

[0014] In a second aspect, the present invention discloses a SET-resistant, high-transient, and no-external-capacitor LDO chip, which adopts the layout of a SET-resistant, high-transient, and no-external-capacitor LDO circuit disclosed in the first aspect.

[0015] The implementation of such a SET-resistant high transient LDO chip without external capacitors is based on the method or process of an embodiment of the present disclosure.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. The present invention adds a dynamic bias subcircuit and two reinforcement subcircuits to an LDO subcircuit without off-chip capacitors. The dynamic bias subcircuit can dynamically increase the loop bandwidth, improve the response speed, and enhance the transient response. One reinforcement subcircuit dissipates the charge generated by particle bombardment, thereby reinforcing the sensitive node V2. The other reinforcement subcircuit not only reinforces the sensitive node Vg, but also enhances the Vg slew rate to improve the transient response of the entire loop.

[0018] 2. Compared with the traditional circuit, the present invention not only effectively suppresses SET impact, but also improves transient performance, maintains a small area overhead, and avoids excessive increase in circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A circuit structure diagram of a SET-resistant, high-transient, and off-chip capacitor-free LDO circuit provided in Example 1 of the present invention;

[0021] Figure 2 The circuit structure diagram of an existing LDO circuit without external capacitors and without SET reinforcement is shown in FIG.

[0022] Figure 3 This is a graph showing the stability test results provided in Example 3 of the present invention;

[0023] Figure 4 Single particle bombardment test results provided by Example 3 of the present invention Figure 1 ;

[0024] Figure 5 Single particle bombardment test results provided by Example 3 of the present invention Figure 2 ;

[0025] Figure 6 Single particle bombardment test results provided by Example 3 of the present invention Figure 3 ;

[0026] Figure 7 This is a load transient jump test result diagram provided by Example 3 of the present invention;

[0027] Figure 8 The adjustment rate test results provided by Example 3 of the present invention Figure 1 ;

[0028] Figure 9 The adjustment rate test results provided by Example 3 of the present invention Figure 2 ;

[0029] Figure 10 This is a graph showing the output stability test results provided by Example 3 of the present invention;

[0030] Figure 11 This is a diagram of power consumption test results provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0032] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] Example 1

[0035] See Figure 1 , provides a high transient SET-resistant LDO circuit without external capacitors for this embodiment 1. This circuit is improved based on the existing LDO circuit without external capacitors that has not been reinforced for SET resistance.

[0036] First, this embodiment 1 provides a specific example of an existing LDO circuit without external capacitors that is not hardened against SET. The circuit includes: seven PMOS transistors P1, P13, P3-P6, and Ppower; eight NMOS transistors N1-N6, N13-N14; four resistors Rt, Rf1, Rf2, and Rload; two capacitors CL and Cc; and one current source Ibias.

[0037] Among them, P1, P3~P6, N1~N6 constitute the operational amplifier part (among which, P1, P3, P4, N1~N4 constitute the first-stage operational amplifier; P5~P6, N5~N6 constitute the second-stage operational amplifier), and are connected to the reference voltage Vref; P13, N13, N14, Ibias constitute the bias part; Ppower serves as the power tube and forms the output end Vout; Rf1 and Rf2 serve as the feedback part; Cc and Rt constitute the Miller compensation part; CL and Rload constitute the load part.

[0038] Specifically:

[0039] 1. For the op amp part, the source of P1, the source of P5, and the source of P6 are connected to the power supply VDD; the gate of P4 is connected to Vref; the drain of P4 is connected to the gate of N2, the drain of N3, the gate of N4, and the gate of N5 (and form node V3); the gate of P5 is connected to the drain of P5, the drain of N5, and the gate of P6; the sources of N1 to N6 are grounded GND; the drain of N1, the gate of N1, the drain of N2, the gate of N3, the drain of P3, and the gate of N6 are connected to the sensitive node V2; the drain of P1, the drain of P3, and the source of P4 are connected to the op amp control node V5.

[0040] 2. For the bias section, the source of P13 and the input of Ibias are connected to the power supply VDD; the sources of N13 and N14 are connected to the ground GND; the output of Ibias, the gate of N13, the drain of N13, and the gate of N14 are connected to the bias control node Va; the drain of P13, the source of P13, and the drain of N14 are connected to the bias control node V1.

[0041] 3. For the power transistor, the source of Ppower is connected to the power supply VDD, and the drain is used as Vout; the gate of Ppower, the drain of P6, and the drain of N6 are connected to the sensitive node Vg.

[0042] It should be noted that, when in use, Vout will be connected to an external load as an output load (not shown in the figure).

[0043] 4. For the feedback part, Miller compensation part, and load part, the first end of Rf1, the positive electrode of CL, and the first end of Rload are connected to Vout; the second end of Rf2, the negative electrode of CL, and the second end of Rload are grounded GND; the first end of Rt is connected to the first end of Rf1, and the second end is connected to the negative electrode of Cc (and forms node V4); the positive electrode of Cc is connected to the drain of N4 (and forms node V3); the second end of Rf1, the first end of Rf2, and the gate of P3 are connected to the feedback node Vfb.

[0044] Then, P13, P1 and N13, N14 provide tail current to the op amp through a current mirror image; N1-N4 serve as the load of the first-stage op amp, making the current flowing through P3 and P4 the same, thereby making the voltages of V2 and V3 the same; Rf1 and Rf2 use resistor voltage division to ensure that the voltages of Vfb and Vout satisfy: Vfb = (Rf2 / (Rf1+Rf2))*Vout; P5 and P6 are the same size and serve as the load of the second-stage op amp, thereby making the voltages of V4 and Vg the same; Cc forms frequency compensation to achieve separation of primary and secondary poles; at the same time, Rt can add a zero point to ensure sufficient phase margin and bandwidth, so that the LDO sub-circuit without external capacitors remains stable in both heavy and light load states.

[0045] It should be noted that the existing LDO circuit without external capacitors that has not been hardened against SET can also adopt other circuit designs, but it must meet the following requirements: it has two sensitive nodes V2 and Vg, two bias control nodes V1 and Va, one op amp control node V5, one feedback node Vfb, and one output terminal Vout.

[0046] Existing LDO circuits without external capacitors that haven't been reinforced for SET resistance suffer from the issues mentioned in the background technology: output stability is significantly affected by transient changes in the output load and SET, making it difficult to operate normally in radiation environments and certain specific environments. Therefore, this circuit is upgraded to a circuit with high transient response and SET resistance by using it as an LDO subcircuit without external capacitors and adding a dynamic bias subcircuit and two reinforcement subcircuits (including reinforcement subcircuit 1 and reinforcement subcircuit 2). This allows the output voltage to quickly recover and stabilize during transient load changes, and accelerates the dissipation and compensation of the large amount of excess charge generated by single-particle bombardment, allowing the Vout voltage to recover quickly.

[0047] Ⅰ. The dynamic bias subcircuit is connected to V5 to ensure that Vout maintains a stable output during load transients.

[0048] In this embodiment 1, the dynamic bias sub-circuit can be designed to include: a PMOS transistor P2; the drain of P2 is connected to V5, the gate is connected to Vg, and the source is connected to the power supply VDD.

[0049] After adding the P2 tube, the tail current of the first-stage op amp can be dynamically changed:

[0050] When all tubes of the first-stage op amp are in normal working condition, when the output load jumps from light load to heavy load, the Vg voltage decreases. At this time, the tail current of the first-stage op amp also increases, which increases the current of the two branches of the first-stage op amp (i.e., P3 and P4), thereby reducing the output impedance of the first-stage op amp, thereby increasing the loop bandwidth, improving the response speed, and achieving the effect of assisting in improving transient response.

[0051] II. Reinforcement sub-circuit 1 is connected to V2 and is used to reinforce V2.

[0052] In this embodiment 1, the reinforcement sub-circuit 1 can be designed to include: 3 NMOS transistors N7-N8, N15, and 2 PMOS transistors P7-P8;

[0053] The source of N7, the source of N8, and the source of N15 are grounded GND; the gate of N7, the gate of P7, and the drain of N15 are connected to V2; the drain of N7 is connected to the gate of N8, the drain of P7, and the drain of P8 (and form node V9); the drain of N8 is connected to the drain of P8 and the gate of N15 (and form node V10); the sources of P7~P8 are connected to the power supply VDD.

[0054] Among them, P7 and N7 form the first-stage inverter, and P8 and N8 form the second-stage inverter. In other words, the drain voltage of P3, the input voltage of the first-stage inverter, and the drain voltage of N15 are the same (all the voltage of V2).

[0055] Once V2 is bombarded by radiation, it generates a large number of electrons, causing the gate voltages of P7 to N7 to rise and the gate voltages of P8 and N8 to drop. The two-stage inverter outputs a high level, turning on N15 and discharging the drain of P3. Therefore, choosing the right size for N15 accelerates the dissipation of V2's excess electrons through N15, thereby shortening the pulse width generated at the output of the circuit due to radiation.

[0056] Specifically, as shown above, V2 is connected to the gate of N1, the drain of N2, the gate of N3, the drain of P3, and the gate of N6. By bombarding these electrodes, it was found that the drain of P3 caused V2 to be the sensitive end of the sensitive node.

[0057] The first reinforcement sub-circuit can reinforce V2. When the circuit is working normally, the voltage of V2 serves as the input of the two-stage inverter, and the voltage of V10 is low, which turns off N15 and has no effect on the circuit. When the drain of P3 is bombarded by a single particle, the voltage of V3 becomes high. V3 passes through the two-stage inverter to make the voltage of V10 become high. N15 is turned on, and V2 dissipates charge, which has an anti-SET effect.

[0058] III. The second reinforcement sub-circuit is used to reinforce Vg and enhance the Vg slew rate to improve transient response.

[0059] In this embodiment 1, the second reinforcement subcircuit is designed to include: four PMOS transistors P9-P12, four NMOS transistors N9-N12, and one capacitor Ct. The sources of P9-P12 are connected to the power supply VDD; the drain of P9 is connected to Vg, and the gate is connected to the drain of P12 and the drain of N12; the drain of P10 is connected to the gate of N9 and the drain of N10; the gate of P10 and the gate of P11 are connected to V1; the drain of P11 is connected to the gate of N11, the drain of N11, the gate of N10, the gate of P12, and the positive electrode of Ct; the negative electrode of Ct is connected to Vfb; the sources of N9-N12 are connected to ground GND; and the gate of N12 is connected to Va.

[0060] Among them, P10 and N10 form a common-source amplifier; P12 and N12 form another common-source amplifier.

[0061] As shown above, Vg is connected to the gate of Ppower, the drain of P6, and the drain of N6. Through bombardment testing of these electrodes, it was found that the drain of P6 and the drain of N6 make Vg a sensitive end of the sensitive node.

[0062] The second reinforcement sub-circuit can reinforce Vg. When the drain of P6 is bombarded by a single particle, Vg will generate an upward pulse, Vout will generate a downward pulse, and the voltage of Vfb will also change accordingly. V6 will generate an undershoot voltage through Ct coupling. The common-source amplifier composed of P10 and N10 amplifies the undershoot voltage of V6 to the overshoot voltage of V7, thereby turning on N9 and connecting Vg to a pull-down discharge path, thereby quickly dissipating the charge generated by the drain of P6. Vg then decreases rapidly and reduces the undershoot voltage of Vout, achieving single-particle transient reinforcement. Similarly, when the drain of N6 is bombarded by a single particle, Vg will generate a downward pulse, Vout will generate an upward pulse, the voltage of Vfb will also change, and V6 will generate an overshoot voltage through Ct coupling; the common-source amplifier composed of P12 and N12 amplifies the overshoot voltage of V6 to the undershoot voltage of V8, thereby turning on P9 and connecting Vg to a pull-up charging path, thereby compensating the charge generated by the drain of N6, and Vg will quickly increase and reduce the overshoot voltage of Vout, realizing single-particle transient reinforcement.

[0063] It's important to emphasize that reinforcement sub-circuit 2 also enhances the slew rate to improve transient response. When the output load changes from light to heavy, Ppower's output current can't adjust quickly enough to respond to the load change. CL supplies the excess current, causing the Vout voltage to drop sharply, leading to an undershoot (similar to what happens when the drain of P6 experiences a single-particle strike). Reinforcement sub-circuit 2 adjusts Vg, rapidly reducing its slew rate. Similarly, when the output load changes from heavy to light, Ppower's output current doesn't have time to adjust, and the excess current is absorbed by CL. This causes the Vout voltage to increase sharply, leading to an overshoot (similar to what happens when the drain of N6 experiences a single-particle strike). Reinforcement sub-circuit 2 adjusts Vg, rapidly increasing its slew rate.

[0064] Therefore, for the high-transient SET-resistant, capacitor-free LDO circuit designed above, during stable operation, reinforcement sub-circuits 1 and 2 are inoperative, barely affecting the stability of the original circuit under heavy and light loads or the stable output of Vout. However, when encountering a load transient jump or when an internal node is bombarded by a single particle, the dynamic bias circuit, reinforcement sub-circuit 1, and reinforcement sub-circuit 2 will operate, improving transient response and SET resistance.

[0065] In addition, it should be noted that the component parameters of N7, N8, P7, and P8 (such as the width-to-length ratio, etc.) will affect the circuit's response speed to single-particle transients. Therefore, by matching the parameters of the above-mentioned MOS tubes, the circuit's response speed to radiation can meet the requirements; the component parameters of N15 (such as the width-to-length ratio, etc.) will affect the circuit's reinforcement effect against single-particle transients. Therefore, by adjusting the parameters of N15, the reinforcement effect of V2 can meet the requirements.

[0066] Example 2

[0067] This embodiment 2 discloses a SET-resistant, high-transient, no-external-capacitor LDO chip, which adopts the layout of the SET-resistant, high-transient, no-external-capacitor LDO circuit disclosed in embodiment 1. The chip packaging model makes it easier to promote and apply the above circuit.

[0068] Specifically, the SET-resistant high transient capacitor-free LDO chip has multiple pins, including a VDD pin, a GND pin, and a Vout pin. The VDD pin is used to connect to VDD; the GND pin is used to connect to GND; and the Vout pin is used to connect to Vout.

[0069] Of course, if the LDO sub-circuit example design without external capacitors given in Example 1 is adopted, then the pins of the SET-resistant high transient LDO chip without external capacitors need to be additionally provided with a Vref pin. The Vref pin is used to connect Vref.

[0070] Example 3

[0071] This embodiment 3 is intended to verify the performance of the SET-resistant high transient LDO circuit without external capacitors proposed in embodiment 1.

[0072] Specifically, yes Figure 1 A series of performance tests were conducted on the circuit (referred to as Circuit 1) and some projects were introduced Figure 2 The circuit (referred to as Circuit 2) is compared.

[0073] 1. Stability test:

[0074] Adjust the output load of circuit 1 and circuit 2 to heavy load and light load, and obtain the corresponding amplitude-frequency characteristic curve (i.e. Figure 3The upper half of the phase-frequency characteristic curve (i.e. Figure 3 the lower half of the ).

[0075] according to Figure 3 It can be seen that the phase margin of circuit 2 is 58.83° under heavy load, the phase margin under light load is 82.7°, the bandwidth under heavy load is 13.1586MHz, and the bandwidth under light load is 10.5719MHz, and the loop is in a stable state; the phase margin of circuit 1 is 59.2° under heavy load, the phase margin under light load is 88.77°, the bandwidth under heavy load is 10.6137MHz, and the bandwidth under light load is 7.745519MHz, and the loop is in a stable state.

[0076] This shows that although Circuit 1 has one additional dynamic bias subcircuit and two reinforcement subcircuits, it can still remain stable.

[0077] 2. Single particle bombardment test:

[0078] To cover a variety of typical radiation bombardment scenarios, bombardment tests were performed on all terminals in Circuit 2 (using a dual-exponential current source simulation test). Three terminals (the drain of P3, the drain of P6, and the drain of N6) where the pulse amplitude of the output signal under the influence of bombardment was significantly changed (the output voltage pulse amplitude was greater than 100mV) were selected as the sensitive terminals of the circuit.

[0079] A comparative test was conducted on Circuit 1 and Circuit 2 to measure the indicators of anti-radiation reinforcement effect: pulse amplitude and pulse width.

[0080] Specifically, when circuit 1 and circuit 2 are working normally, the P3-D (i.e., the drain of P3), P6-D (i.e., the drain of P6), and N6-D (i.e., the drain of N6) of the two circuits are subjected to radiation bombardment tests with the same bombardment intensity at 1μs. The corresponding Vout voltage waveforms are compared as follows: Figures 4 to 6 shown.

[0081] like Figure 4 As shown in the figure, when bombarding P3-D, circuit 1 reduces the voltage pulse width of Vout from 0.064μs to 0.032μs and the amplitude from 144mV to 71mV compared with circuit 2, which shows that circuit 1 has a reinforcement effect on P3-D.

[0082] like Figure 5 As shown in the figure, when bombarding P6-D, circuit 1 reduces the voltage pulse width of Vout from 0.119μs to 0.031μs and the amplitude from 195mV to 183mV compared with circuit 2, which shows that circuit 1 has a reinforcement effect on N6-D.

[0083] like Figure 6As shown in the figure, when bombarding N6-D, circuit 1 reduces the voltage pulse width of Vout from 0.073μs to 0.034μs and the amplitude from 484mV to 295mV compared with circuit 2, which shows that circuit 1 has a reinforcement effect on P6-D.

[0084] 3. Load transient jump test:

[0085] Test the output load transient performance of Circuit 1 and Circuit 2, observe the pulse changes of Vout, and measure the indicators of transient effect: pulse amplitude and pulse recovery time.

[0086] Specifically, when the load changes from light load (set to 1mA) to heavy load (set to 100mA) at 1μs, the rise time is 0.1μs; when the load changes from heavy load (set to 100mA) to light load (set to 1mA) at 3μs, the fall time is 0.1μs; the corresponding Vout voltage waveform is compared as follows: Figure 7 shown.

[0087] like Figure 7 As shown in the figure, compared to Circuit 2, at 1μs, the pulse amplitude of Circuit 1 is reduced from 373mV to 235mV, and the pulse recovery time is reduced from 540ns to 340ns (pulse amplitude is reduced by 27%, and recovery time is improved by nearly 50%). At 3μs, the pulse amplitude is reduced from 242mV to 100mV, and the pulse recovery time is reduced from 440ns to 190ns (pulse amplitude is reduced by 50.8%, and recovery time is improved by 66%). It can be seen that Circuit 2 has a significant improvement in transient performance.

[0088] 4. Adjustment rate test:

[0089] The regulation rate of circuit 1 is examined to verify the stability of the system. The results are as follows: Figures 8 and 9 The regulation rate includes load regulation rate and linear regulation rate.

[0090] Load regulation refers to the change in output voltage as the load current changes, while the input voltage remains constant. The smaller the load regulation, the better. Linear regulation refers to the change in output voltage as the input voltage changes, while the load remains constant. The smaller the linear regulation, the better.

[0091] like Figure 8 As shown in the figure, under the load range of 1-100mA, the load regulation rate of circuit 1 is 0.00566mV / mA, which is a good level. Figure 9 As shown in the figure, under the input voltage of 1~125mV, the linear regulation rate of circuit 1 is 3.129mV / V, which is a relatively excellent level.

[0092] 5. Output stability test:

[0093] Under the same power supply voltage and room temperature environment, 1000 Monte Carlo tests were performed on circuit 1 at different process angles and adaptation states, and the voltage change of Vout was examined. The test results are shown in the figure below. Figure 10 shown.

[0094] Depend on Figure 10 It can be seen that the average output voltage of circuit 1 is 1.0003V, the variance is 0.03165V, and the 2σ accuracy is 6.3%, indicating that the output voltage of circuit 1 has good stability at room temperature.

[0095] 6. Area test:

[0096] The final layout area of circuit 1 is 0.02218mm. 2 , only 0.0109mm longer than circuit 2 2 ; Indicates that the increase in area overhead of circuit 1 is acceptable.

[0097] 7. Power consumption test:

[0098] The quiescent current of circuit 1 and circuit 2 under light load (set to 1mA) is examined. The results are as follows Figure 11 As shown in Figure 1, the quiescent current of Circuit 1 is 24.31μA, and the quiescent current of Circuit 2 is 17.89μA. Although the power consumption of Circuit 1 is increased compared to Circuit 2, it is still within an acceptable range and is the price to pay for the increased functionality.

[0099] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A high transient SET-resistant LDO circuit without external capacitors, comprising: An LDO sub-circuit without external capacitors, comprising two sensitive nodes V2 and Vg, two bias control nodes V1 and Va, one op amp control node V5, one feedback node Vfb, and one output terminal Vout; further comprising: The dynamic bias subcircuit is connected to V5 and is used to ensure that Vout maintains a stable output when the load transient jumps; Reinforcement sub-circuit 1, connected to V2 and used to reinforce V2; as well as Reinforcement sub-circuit 2 is used to reinforce Vg and enhance the Vg slew rate to improve transient response; reinforcement sub-circuit 2 includes: 4 PMOS tubes P9~P12, 4 NMOS tubes N9~N12, and 1 capacitor Ct; the sources of P9~P12 are connected to the power supply VDD; the drain of P9 is connected to Vg, and the gate is connected to the drain of P12 and the drain of N12; the drain of P10 is connected to the gate of N9 and the drain of N10; the gate of P10 and the gate of P11 are connected to V1; the drain of P11 is connected to the gate of N11, the drain of N11, the gate of N10, the gate of P12, and the positive electrode of Ct; the negative electrode of Ct is connected to Vfb; the sources of N9~N12 are grounded GND; the gate of N12 is connected to Va.

2. The SET-resistant high transient LDO circuit without external capacitor according to claim 1, characterized in that: The dynamic bias subcircuit includes: a PMOS transistor P2; the drain of P2 is connected to V5, the gate is connected to Vg, and the source is connected to the power supply VDD.

3. The SET-resistant high transient LDO circuit without external capacitor according to claim 1, characterized in that: Reinforcement sub-circuit 1 includes: 3 NMOS transistors N7~N8, N15, and 2 PMOS transistors P7~P8; The source of N7, the source of N8, and the source of N15 are grounded GND; the gate of N7, the gate of P7, and the drain of N15 are connected to V2; the drain of N7 is connected to the gate of N8, the drain of P7, and the drain of P8; the drain of N8 is connected to the drain of P8 and the gate of N15; the sources of P7~P8 are connected to the power supply VDD.

4. The SET-resistant high transient LDO circuit without external capacitor according to claim 1, characterized in that: The LDO subcircuit without external capacitors includes: 7 PMOS transistors P1, P13, P3-P6, Ppower, 8 NMOS transistors N1-N6, N13-N14, 4 resistors Rt, Rf1, Rf2, Rload, 2 capacitors CL, Cc, and 1 current source Ibias; Among them, P1, P3~P6, N1~N6 form the op amp part and are connected to the reference voltage Vref; P13, N13, N14, and Ibias form the bias part; Ppower is the power transistor and forms Vout; Rf1 and Rf2 are the feedback part; Cc and Rt form the Miller compensation part; CL and Rload form the load part; The drain of N1, the gate of N1, the drain of N2, the gate of N3, the drain of P3, and the gate of N6 are connected to V2; the gate of Ppower, the drain of P6, and the drain of N6 are connected to Vg; the output end of Ibias, the gate of N13, the drain of N13, and the gate of N14 are connected to Va; the drain of P13, the source of P13, and the drain of N14 are connected to V1; the drain of P1, the drain of P3, and the source of P4 are connected to V5; the second end of Rf1, the first end of Rf2, and the gate of P3 are connected to the feedback node Vfb.

5. The SET-resistant high transient LDO circuit without external capacitor according to claim 4, characterized in that: In the op amp section, The source of P1, the source of P5, and the source of P6 are connected to the power supply VDD; the gate of P4 is connected to Vref; the drain of P4 is connected to the gate of N2, the drain of N3, the gate of N4, and the gate of N5; the gate of P5 is connected to the drain of P5, the drain of N5, and the gate of P6; the sources of N1 to N6 are grounded GND.

6. The SET-resistant high transient LDO circuit without external capacitor according to claim 5, characterized in that: In the bias section, The source of P13 and the input terminal of Ibias are connected to the power supply VDD; the sources of N13 to N14 are grounded GND.

7. The SET-resistant high transient LDO circuit without external capacitor according to claim 6, characterized in that: The source of Ppower is connected to the power supply VDD, and the drain is used as Vout.

8. The SET-resistant high transient LDO circuit without external capacitor according to claim 7, characterized in that: The first end of Rf1, the positive electrode of CL, and the first end of Rload are connected to Vout; the second end of Rf2, the negative electrode of CL, and the second end of Rload are grounded GND; the first end of Rt is connected to the first end of Rf1, and the second end is connected to the negative electrode of Cc; the positive electrode of Cc is connected to the drain of N4.

9. A high transient SET-resistant LDO chip without external capacitors, characterized in that: A layout of a SET-resistant, high-transient, and off-chip capacitor-free LDO circuit as claimed in any one of claims 1 to 8 is adopted.

10. The SET-resistant high transient LDO chip without external capacitor according to claim 9, characterized in that: The pins of the SET-resistant high transient LDO chip without external capacitors include: VDD pin, which is used to connect VDD; GND pin, which is used to connect to GND; as well as Vout pin, which is used to connect Vout.

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