On-chip clock controller, power consumption control method thereof and computer readable storage medium

Abstract

The invention relates to the technical field of communication, and discloses an on-chip clock controller and a power consumption control method thereof, and a computer readable storage medium, and the method comprises the steps: generating a differential delay control signal according to a scanning enable signal and a configuration signal of a test data register; generating a clock enable signal and a clock selection signal according to the scanning enable signal; determining a target clock from the clock sources through the clock selection signal; and determining an output sequence of the target clocks through the differential delay control signal, and controlling the target clocks to be sequentially output according to the output sequence through the clock enable signal. Through the mode, clock source switching and output are accurately controlled through the clock enable signal and the clock selection signal, the target clock is controlled to be output in sequence through the differential delay control signal, the register is prevented from capturing data at the same time, the instantaneous power consumption peak value is effectively reduced, and the power consumption is reduced. Therefore, the instantaneous power consumption of the chips of the plurality of clock sources during the scanning test is reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an on-chip clock controller, a power consumption control method thereof, and a computer-readable storage medium. Background Art

[0002] As the complexity of system-on-chip (SoC) designs continues to increase, the scale of integrated circuits is also expanding. This trend brings greater design challenges, especially in the testing and verification stages. Design for Testability (DFT) technology has become particularly important in this context. It aims to simplify the chip testing process, improve test coverage, and thus reduce time and cost to market.

[0003] Test power consumption becomes a key consideration when performing scan testing. As chip functionality increases, the power consumption required during testing can increase significantly, especially in high-frequency and complex designs. Excessive test power consumption can cause chip overheating or even damage, directly impacting the accuracy of test results.

[0004] During register shifts in scan testing, designers typically use AND or OR gates to prevent the scan flip-flop's value from propagating to the combinational logic. This approach primarily aims to reduce the power consumption caused by state flips during testing, thereby improving overall test efficiency and reducing power consumption. However, this safeguard introduces additional design complexity and significantly increases test logic overhead. This not only increases design costs but can also extend test time due to the large number of additional logic gates that need to be synthesized and verified. Therefore, reducing the instantaneous power consumption during scan testing on chips with multiple clock sources has become a pressing technical challenge. Summary of the Invention

[0005] The present application provides an on-chip clock controller and a power consumption control method thereof, and a computer-readable storage medium, so as to reduce instantaneous power consumption when a chip with multiple clock sources is scan-tested.

[0006] In a first aspect, the present application further provides an on-chip clock controller, the on-chip clock controller comprising:

[0007] Controllable delay module, clock control module, clock selection module and clock gating module:

[0008] One end of the controllable delay module is connected to the clock control module, and is used to receive a scan enable signal, determine a delay group according to a configuration signal of a test data register and the scan enable signal, and generate a differentiated delay control signal according to the delay group and the scan enable signal;

[0009] One end of the clock control module is connected to the controllable delay module, and the other end is connected to the clock selection module, and is used to generate a clock enable signal and a clock selection signal according to the differentiated delay control signal and the scan enable signal;

[0010] One end of the clock selection module is connected to the clock control module, and the other end is connected to the clock gating module, and is used to determine the target clock from at least one functional clock and / or at least one test clock according to the clock selection signal;

[0011] The clock gating module is connected to the clock selection module and is used to control the output of the target clock according to the clock enable signal.

[0012] Furthermore, the controllable delay module includes:

[0013] at least one of the delay groups, configured to apply different delay information to each of the scan enable signals;

[0014] The delay group selector is composed of a multiplexer and is used to determine the corresponding delay group according to the configuration signal of the test data register and the scan enable signal.

[0015] Furthermore, the delay group is formed by cascading the test data registers.

[0016] Furthermore, the configuration signal of the test data register is 2 bits wide, and a second selector is formed by cascading at least two first selectors, and each of the second selectors corresponds to each of the delay groups.

[0017] Furthermore, the clock gating module includes:

[0018] A first gating unit, configured to control enabling of the functional clock;

[0019] The second gating unit is used to control the enabling of the test clock.

[0020] Furthermore, the clock control module includes:

[0021] An input interface, configured to receive the scan enable signal delayed by the controllable delay module;

[0022] a logic generation unit, configured to generate the clock enable signal and the clock selection signal according to the scan enable signal delayed by the controllable delay module;

[0023] Wherein, the clock enable signal is used to control the enabled state or disabled state of the clock gating module;

[0024] The clock selection signal is used to control the clock selection module to determine the target clock from the functional clocks and / or the test clocks.

[0025] Furthermore, the clock selection module includes:

[0026] a multiplexer, wherein an input end of the multiplexer is connected to at least one of the functional clocks and / or at least one of the test clocks;

[0027] The selection logic unit receives the clock selection signal from the clock control module and controls the multiplexer to determine the target clock according to the state of the clock selection signal.

[0028] In a second aspect, the present application provides a method for controlling power consumption of an on-chip clock controller, the method comprising:

[0029] Generate differentiated delay control signals according to the scan enable signal and the configuration signal of the test data register;

[0030] generating a clock enable signal and a clock selection signal according to the scan enable signal;

[0031] Determine a target clock from each preset clock source using the clock selection signal;

[0032] The output sequence of the target clocks is determined by the differential delay control signal, and the target clocks are controlled to be output in sequence according to the output sequence by the clock enable signal.

[0033] Furthermore, a differentiated delay control signal is generated according to the scan enable signal and the configuration signal of the test data register, including:

[0034] parsing the configuration signal of the test data register to determine the field bit width of the configuration signal of the test data register;

[0035] Generate a corresponding delay parameter according to the field bit width;

[0036] A logical operation is performed on each of the scan enable signals according to the delay parameter to generate the differentiated delay control signal.

[0037] In a third aspect, the present application further provides a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to implement the above-mentioned on-chip clock controller power consumption control method.

[0038] The present application discloses an on-chip clock controller and its power consumption control method, and a computer-readable storage medium. The on-chip clock controller power consumption control method includes generating a differentiated delay control signal according to a scan enable signal and a configuration signal of a test data register; generating a clock enable signal and a clock selection signal according to the scan enable signal; determining a target clock from each preset clock source through the clock selection signal; determining the output order of the target clock through the differentiated delay control signal, and controlling the target clock to be output in sequence according to the output order through the clock enable signal. In the above manner, the present application accurately controls the switching and output of the clock source through the clock enable signal and the clock selection signal, controls the target clock to be output in sequence through the differentiated delay control signal, avoids the register from capturing data at the same time, effectively reduces the instantaneous power consumption peak, and thereby reduces the instantaneous power consumption when the chip with multiple clock sources is scan tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 This is a design architecture diagram of an on-chip clock controller provided by an embodiment of the present application;

[0041] Figure 2 is a schematic flow chart of a power consumption control method for an on-chip clock controller provided by the first embodiment of the present application;

[0042] Figure 3 is a schematic flow chart of a method for controlling power consumption of an on-chip clock controller provided in a second embodiment of the present application;

[0043] Figure 4 A schematic block diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0045] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0046] It should be understood that the terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0047] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0048] Embodiments of the present application provide an on-chip clock controller, a power consumption control method thereof, and a computer-readable storage medium. The on-chip clock controller power consumption control method can be applied to an on-chip clock controller, precisely controlling clock source switching and output through clock enable and clock select signals, and controlling target clocks to be output sequentially through differentiated delay control signals, thereby preventing registers from capturing data simultaneously and effectively reducing instantaneous power consumption peaks. This, in turn, reduces instantaneous power consumption during scan testing of chips with multiple clock sources.

[0049] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0050] See also Figure 1 , Figure 1 This is a design architecture diagram of an on-chip clock controller provided in an embodiment of the present application.

[0051] The on-chip clock controller includes a controllable delay module, a clock control module, a clock selection module, and a clock gating module:

[0052] One end of the controllable delay module is connected to the clock control module, and is used to receive a scan enable signal, determine a delay group according to a configuration signal of a test data register and the scan enable signal, and generate a differentiated delay control signal according to the delay group and the scan enable signal;

[0053] One end of the clock control module is connected to the controllable delay module, and the other end is connected to the clock selection module, and is used to generate a clock enable signal and a clock selection signal according to the differentiated delay control signal and the scan enable signal;

[0054] Specifically, the clock enable signal is used to control whether the clock signal is passed to the target module or register. When the enable signal is high (1), the clock signal is passed; when the enable signal is low (0), the clock signal is blocked.

[0055] By controlling the delivery of clock signals, clock enable signals can help reduce the chip's dynamic power consumption. When a module or register is not needed, its clock signal can be turned off, thereby reducing the dynamic power consumption of the module or register.

[0056] The clock enable signal can be used for synchronization control to ensure that multiple modules or registers receive the clock signal at the same time point.

[0057] One end of the clock selection module is connected to the clock control module, and the other end is connected to the clock gating module, and is used to determine the target clock from at least one functional clock and / or at least one test clock according to the clock selection signal;

[0058] The clock gating module is connected to the clock selection module and is used to control the output of the target clock according to the clock enable signal.

[0059] In a specific embodiment, the controllable delay module includes:

[0060] at least one of the delay groups, configured to apply different delay information to each of the scan enable signals;

[0061] The delay group selector is composed of a multiplexer and is used to determine the corresponding delay group according to the configuration signal of the test data register and the scan enable signal.

[0062] In a specific embodiment, the delay group is formed by cascading the test data registers.

[0063] In a specific embodiment, the configuration signal of the test data register is 2 bits wide, and a second selector is formed by cascading at least two first selectors, and each of the second selectors corresponds to each of the delay groups.

[0064] In a specific embodiment, the clock gating module includes:

[0065] A first gating unit, configured to control enabling of the functional clock;

[0066] The second gating unit is used to control the enabling of the test clock.

[0067] In a specific embodiment, the clock control module includes:

[0068] An input interface, configured to receive the scan enable signal delayed by the controllable delay module;

[0069] a logic generation unit, configured to generate the clock enable signal and the clock selection signal according to the scan enable signal delayed by the controllable delay module;

[0070] Wherein, the clock enable signal is used to control the enabled state or disabled state of the clock gating module;

[0071] The clock selection signal is used to control the clock selection module to determine the target clock from the functional clocks and / or the test clocks.

[0072] In a specific embodiment, the clock selection module includes:

[0073] a multiplexer, wherein an input end of the multiplexer is connected to at least one of the functional clocks and / or at least one of the test clocks;

[0074] The selection logic unit receives the clock selection signal from the clock control module and controls the multiplexer to determine the target clock according to the state of the clock selection signal.

[0075] Specifically, during the scan test process, the scan enable signal (scan_en) is pulled low, indicating that the scan test mode has been entered. When scan_en is low, the enable signal (enable) of the clock gating module (fast_clock_cgc) is activated, allowing the high-speed clock (fast_clock) to pass.

[0076] The clock control module (occ_control) generates clock enable signals (fast_clock_en and slow_clock_en) and a clock select signal (clock_mux_select) based on the scan_en signal. The clock select module selects the appropriate clock source (high-speed or slow) based on the clock_mux_select signal. The scan_en signal passes through delay groups in the controllable delay module, each with a different delay. The delay group selection is controlled by the test data register (tdr) signal. The delayed scan_en signal reaches the clock control module, which controls the sequential output of clock signals (clock_out1, clock_out2, clock_out3, and clock_out4) from each on-chip clock controller (OCC). The rising edges of these clock signals occur at different times, so that the chip registers capture data at different times, thereby reducing instantaneous power consumption.

[0077] like Figure 1The design architecture shown in the figure consists of four main components: a controllable delay module, a clock control module, a clock selection module, and a clock gating module. The input fast_clock is the high-speed capture clock. fast_clock1, fast_clock2, fast_clock3, and fast_clock4 are the three functional clocks of chip A. These functional clocks drive the fast clock input of the on-chip clock controller, typically a phase-locked loop (PLL). slow_clock is the test clock. scan_en is the scan enable signal, used for shifting and slow capture during scan testing. scan_en is the scan enable signal, used by the on-chip clock controller to determine whether to provide the circuit with a high-speed clock (functional clock) or a slow clock (test clock).

[0078] The clock control module, shown as occ_control in the diagram, influences the clock generation signals within the chip, ensuring that each module operates at the correct clock frequency. It outputs clock enable signals (slow_clock_en and fast_clock_en) and select signals (clock_mux_select) to the clock gating and clock enable modules based on design and test vector requirements.

[0079] The clock selection module is responsible for selecting between multiple clock sources to meet clock switching requirements during testing. The clock source comes from the clock gating module. The selection signal is generated by the clock control module (clock_mux_select) and selects the appropriate clock source and outputs it to the target module.

[0080] The clock gating module decides whether to enable the clock signal of a module based on the system status and control signal. Its fast_clock_cgc and slow_clock_cgc components are composed.

[0081] The controllable delay module consists of delay groups (delay group 1, delay group 2, delay group 3, and delay group 4) and a delay group selector, which selects the delay group used by the on-chip clock controller. Three two-to-one selectors (mux_1, mux_2, and mux_3) form a four-to-one selector, with the selector pin being the two-bit-wide TDR (test data register) configuration signal.

[0082] The four source clocks fast_clock1, fast_clock2, fast_clock3, and fast_clock4 contained in the chip have their frequencies decreasing in sequence. When performing testability design, it is necessary to insert an on-chip clock controller of the present invention into each clock, corresponding to on-chip clock controller 1, on-chip clock controller 2, on-chip clock controller 3, and on-chip clock controller 4 in sequence. During the scan test, when the scan enable signal scan_en is 0, the enable of the clock gating module fast_clock_cgc is 1, and the clock control module outputs a clock_mux_select signal with a value of 1 to the S end of the clock selection module. At this time, the output of the on-chip clock controller is a high-speed clock, and the registers in the chip will capture data on the rising edge of the high-speed clock.

[0083] After scan_en is pulled low, the tdr register will give different signals to on-chip clock controller 1, on-chip clock controller 2, clock controller 3 and on-chip clock controller 4:

[0084] The tdr signal in the on-chip clock controller 1 is 00, and the scan_en signal reaches the occ_control module through delay group 1;

[0085] The tdr signal in the on-chip clock controller 2 is 01, and the scan_en signal reaches the occ_control module through delay group 2;

[0086] The tdr signal in the on-chip clock controller 3 is 10, and the scan_en signal reaches the occ_control module through delay group 3;

[0087] The tdr signal in the on-chip clock controller 4 is 11, and the scan_en signal reaches the occ_control module through the delay group 4.

[0088] The delay value of a delay group is determined by the number of beat registers in the group. Therefore, the order in which the scan_en signal arrives at the on-chip clock control modules is, from earliest to latest, on-chip clock controller 1, on-chip clock controller 2, on-chip clock controller 3, and on-chip clock controller 4. The delay of the Scan_en signal affects the delay of the clock generated by the on-chip clock controller.

[0089] When scan_en is low, the high-speed clock (functional clock) is enabled and the register enters data capture mode. The delay parameters of different on-chip clock controllers are configured through TDR (such as tdr = 00 corresponds to delay group 1, tdr = 01 corresponds to delay group 2, etc.), so that the scan_en signal passes through different delay groups in turn to reach each control module, and the rising edges of clock_out1-4 output by each clock controller are triggered in turn, ensuring that registers with different clock sources capture data at different time points (such as Figure 4 For example, clock_out1 is triggered first and clock_out4 is triggered last, which disperses the instantaneous current and reduces the peak value of dynamic power consumption.

[0090] See also Figure 2 , Figure 2 This is a schematic flow chart of a power consumption control method for an on-chip clock controller provided in the first embodiment of this application. This power consumption control method can be applied to an on-chip clock controller. It precisely controls clock source switching and output through clock enable and clock select signals. It controls the sequential output of target clocks through differentiated delay control signals, preventing registers from capturing data simultaneously. This effectively reduces instantaneous power consumption peaks, thereby reducing instantaneous power consumption during scan testing of chips with multiple clock sources.

[0091] like Figure 2 As shown, the on-chip clock controller power consumption control method specifically includes steps S10 to S40.

[0092] Step S10: generating a differentiated delay control signal according to the scan enable signal and the configuration signal of the test data register;

[0093] Specifically, the scan enable signal instructs the chip to enter the scan test mode and is usually pulled low (low level) during the test process; the configuration signal of the test data register carries test configuration information, which is used to determine the delay settings of different on-chip clock controllers (OCCs).

[0094] The scan_en signal is logically combined with the tdr configuration signal to generate a differentiated delay control signal. The input signal is processed using a logic gate (such as an AND gate, an OR gate, etc.) to generate a signal for controlling the clock output sequence.

[0095] Different delays are set for different OCCs based on the value of the tdr signal. For example, different values of the tdr signal can correspond to different delay groups, each providing a different delay. The generated differentiated delay control signal is then used to control the order of clock outputs.

[0096] Step S20: generating a clock enable signal and a clock selection signal according to the scan enable signal;

[0097] Specifically, the scan enable signal is at a low level in the scan test mode, indicating entering the test mode.

[0098] Clock enable signal generation:

[0099] fast_clock_en: When scan_en is low, the fast_clock_en signal is generated to be high, enabling the high-speed clock; slow_clock_en: When scan_en is high, the slow_clock_en signal is generated to be high, enabling the slow clock.

[0100] Clock selection signal generation:

[0101] clock_mux_select: Generates the clock_mux_select signal based on the state of the scan_en signal. In scan test mode (scan_en is low), the clock_mux_select signal selects the high-speed clock; in normal operation mode (scan_en is high), it selects the slow clock.

[0102] Output fast_clock_en, slow_clock_en, and clock_mux_select signals: These signals will be passed to subsequent clock control modules.

[0103] Step S30: determining a target clock from each preset clock source using the clock selection signal;

[0104] Specifically, the clock_mux_select signal indicates which clock source is selected, such as fast_clock (high-speed clock) and slow_clock (slow clock).

[0105] Based on the value of the clock_mux_select signal, the target clock is selected from the preset clock sources. For example, if clock_mux_select is high, fast_clock is selected; if it is low, slow_clock is selected. The selected target clock signal is output to the subsequent clock control module.

[0106] Step S40: Determine the output sequence of the target clocks through the differentiated delay control signal, and control the target clocks to be output in sequence according to the output sequence through the clock enable signal.

[0107] Specifically, the differentiated delay control signal determines the clock output sequence of different OCCs.

[0108] The clock enable signal controls the clock output, and the target clock output sequence of each OCC is determined based on the differentiated delay control signal. For example, by selecting a delay group, the clock signals of different OCCs are ensured to be output in sequence.

[0109] The clock enable signal controls the clock gating module to determine whether to output the target clock and output the target clock signals in the specified output order. For example, by controlling the fast_clock_en and slow_clock_en signals, the high-speed clock and slow clock can be output in a predetermined order.

[0110] The control signal is passed to the corresponding clock gating module and clock selection module, and the clock signal output operation is performed according to the control signal to ensure that the clock signal is output to the target module according to the predetermined order and delay requirements.

[0111] The present embodiment discloses a method for controlling power consumption of an on-chip clock controller, the method comprising generating a differentiated delay control signal according to a scan enable signal and a configuration signal of a test data register; generating a clock enable signal and a clock selection signal according to the scan enable signal; determining a target clock from each preset clock source through the clock selection signal; determining the output sequence of the target clock through the differentiated delay control signal, and controlling the target clock to be output sequentially according to the output sequence through the clock enable signal. In the above manner, the present application accurately controls the switching and output of the clock source through the clock enable signal and the clock selection signal, controls the target clock to be output sequentially through the differentiated delay control signal, avoids the registers from capturing data at the same time, effectively reduces the instantaneous power consumption peak, and thereby reduces the instantaneous power consumption when performing scan testing on a chip with multiple clock sources.

[0112] See also Figure 3 , Figure 3 This is a schematic flow chart of a power consumption control method for an on-chip clock controller provided in the second embodiment of the present application. This power consumption control method for an on-chip clock controller can be applied to an on-chip clock controller. By parsing the configuration signal of the test data register, determining the field bit width and generating the corresponding delay parameter, it can perform precise logical operations on the scan enable signal to generate a differentiated delay control signal. The differentiated delay control signal ensures that the target clocks are output sequentially in a predetermined order, avoiding power consumption spikes caused by multiple registers capturing data simultaneously. This not only reduces the instantaneous power consumption of the chip during testing, but also improves the stability and reliability of the test.

[0113] like Figure 3 As shown, step S10 includes steps S101 to S103.

[0114] Step S101: parsing the configuration signal of the test data register to determine the field bit width of the configuration signal of the test data register;

[0115] Specifically, the system obtains a configuration signal from the test data register (TDR), which contains configuration information for controlling clock delays. The TDR configuration signal is parsed to identify different fields. Each field corresponds to different control information, such as delay group selection and clock source configuration.

[0116] For each identified field, determine its bit width. The bit width determines the range of values that the field can represent, which in turn affects the accuracy and configurability of the delay parameters. For example, a 2-bit field can represent four different delay settings.

[0117] Step S102: Generate a corresponding delay parameter according to the field width;

[0118] Specifically, a mapping relationship between the field value and the delay parameter is established based on the bit width of the field. For example, for a 2-bit wide field, its four possible values (00, 01, 10, 11) can be mapped to four different delay parameters respectively.

[0119] Based on the parsed field value and the mapping relationship, the corresponding delay parameter is calculated. The delay parameter can be a specific delay time or the number of delay units.

[0120] Step S103 : performing a logic operation on each of the scan enable signals according to the delay parameters to generate the differentiated delay control signal.

[0121] Specifically, a scan enable signal (scan_en) is received from the test logic, where the signal is used to indicate whether to enter the scan test mode.

[0122] The logic operation unit is configured according to the delay parameter. The logic operation unit may include logic circuits such as a shift register, a counter, an AND gate, and an OR gate, etc., for implementing delay control of the scan_en signal.

[0123] The scan_en signal is processed using the configured logic unit and delayed according to the delay parameters. For example, the signal delay can be implemented using a shift register. The delayed scan_en signal is combined with other control signals to generate the final differentiated delay control signal. This signal is used to control the output sequence of the clock signals.

[0124] The present embodiment discloses a method for controlling power consumption of an on-chip clock controller, the method comprising parsing the configuration signal of the test data register, determining the field width of the configuration signal of the test data register; generating a corresponding delay parameter according to the field width; performing a logical operation on each scan enable signal according to the delay parameter to generate the differentiated delay control signal; generating a clock enable signal and a clock selection signal according to the scan enable signal; determining a target clock from each preset clock source through the clock selection signal; determining the output order of the target clock through the differentiated delay control signal, and controlling the target clock to be output sequentially according to the output order through the clock enable signal. In the above manner, the present application parses the configuration signal of the test data register, determines the field width and generates the corresponding delay parameter, can perform an accurate logical operation on the scan enable signal, generate the differentiated delay control signal, the differentiated delay control signal ensures that the target clock is output sequentially in a predetermined order, avoids the power consumption spike caused by multiple registers capturing data at the same time, not only reduces the instantaneous power consumption of the chip during the test process, but also improves the stability and reliability of the test.

[0125] See also Figure 4 , Figure 4 1 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device may be a server.

[0126] See Figure 4 The computer device includes a processor, a memory, and a network interface connected through a system bus, wherein the memory may include a non-volatile storage medium and an internal memory.

[0127] The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, and when the program instructions are executed, the processor can execute any one of the on-chip clock controller power consumption control methods.

[0128] The processor is used to provide computing and control capabilities and support the operation of the entire computer equipment.

[0129] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor, the processor can execute any one of the power consumption control methods of the on-chip clock controller.

[0130] The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 4The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0131] It should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0132] In one embodiment, the processor is configured to execute a computer program stored in the memory to implement the following steps:

[0133] Generate differentiated delay control signals according to the scan enable signal and the configuration signal of the test data register;

[0134] generating a clock enable signal and a clock selection signal according to the scan enable signal;

[0135] Determine a target clock from each preset clock source using the clock selection signal;

[0136] The output sequence of the target clocks is determined by the differential delay control signal, and the target clocks are controlled to be output in sequence according to the output sequence by the clock enable signal.

[0137] In one embodiment, a differentiated delay control signal is generated based on a scan enable signal and a configuration signal of a test data register to achieve:

[0138] parsing the configuration signal of the test data register to determine the field bit width of the configuration signal of the test data register;

[0139] Generate a corresponding delay parameter according to the field bit width;

[0140] A logical operation is performed on each of the scan enable signals according to the delay parameter to generate the differentiated delay control signal.

[0141] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program, and the computer program includes program instructions. The processor executes the program instructions to implement any on-chip clock controller power consumption control method provided in the embodiment of the present application.

[0142] The computer-readable storage medium may be an internal storage unit of the computer device described in the aforementioned embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc., equipped on the computer device.

[0143] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An on-chip clock controller, characterized in that: The on-chip clock controller includes a controllable delay module, a clock control module, a clock selection module and a clock gating module: One end of the controllable delay module is connected to the clock control module, and is used to receive a scan enable signal, determine a delay group according to a configuration signal of a test data register and the scan enable signal, and generate a differentiated delay control signal according to the delay group and the scan enable signal; One end of the clock control module is connected to the controllable delay module, and the other end is connected to the clock selection module, and is used to generate a clock enable signal and a clock selection signal according to the differentiated delay control signal and the scan enable signal; One end of the clock selection module is connected to the clock control module, and the other end is connected to the clock gating module, and is used to determine the target clock from at least one functional clock and / or at least one test clock according to the clock selection signal; The clock gating module is connected to the clock selection module and is used to control the output of the target clock according to the clock enable signal.

2. The on-chip clock controller according to claim 1, wherein: The controllable delay module includes: at least one of the delay groups, configured to apply different delay information to each of the scan enable signals; The delay group selector is composed of a multiplexer and is used to determine the corresponding delay group according to the configuration signal of the test data register and the scan enable signal.

3. The on-chip clock controller according to claim 2, wherein: The delay group is composed of the test data registers connected in cascade.

4. The on-chip clock controller according to claim 3, wherein: The configuration signal of the test data register is 2 bits wide, and a second selector is formed by cascading at least two first selectors, and each of the second selectors corresponds to each of the delay groups.

5. The on-chip clock controller according to claim 1, wherein: The clock gating module includes: A first gating unit, configured to control enabling of the functional clock; The second gating unit is used to control the enabling of the test clock.

6. The on-chip clock controller according to claim 1, wherein: The clock control module includes: An input interface, configured to receive the scan enable signal delayed by the controllable delay module; a logic generation unit, configured to generate the clock enable signal and the clock selection signal according to the scan enable signal delayed by the controllable delay module; Wherein, the clock enable signal is used to control the enabled state or disabled state of the clock gating module; The clock selection signal is used to control the clock selection module to determine the target clock from the functional clocks and / or the test clocks.

7. The on-chip clock controller according to claim 1, wherein: The clock selection module includes: a multiplexer, wherein an input end of the multiplexer is connected to at least one of the functional clocks and / or at least one of the test clocks; The selection logic unit receives the clock selection signal from the clock control module and controls the multiplexer to determine the target clock according to the state of the clock selection signal.

8. A method for controlling power consumption of an on-chip clock controller, characterized in that: include: Generate differentiated delay control signals according to the scan enable signal and the configuration signal of the test data register; generating a clock enable signal and a clock selection signal according to the scan enable signal; Determine a target clock from each preset clock source using the clock selection signal; The output sequence of the target clocks is determined by the differential delay control signal, and the target clocks are controlled to be output in sequence according to the output sequence by the clock enable signal.

9. The method for controlling power consumption of an on-chip clock controller according to claim 8, wherein: The generating of the differentiated delay control signal according to the scan enable signal and the configuration signal of the test data register includes: parsing the configuration signal of the test data register to determine the field bit width of the configuration signal of the test data register; Generate a corresponding delay parameter according to the field bit width; A logical operation is performed on each of the scan enable signals according to the delay parameter to generate the differentiated delay control signal.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, enables the processor to implement the on-chip clock controller power consumption control method according to any one of claims 8 or 9.

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