An instruction processing method

Abstract

The application discloses an instruction processing method, which is suitable for a CPU in a pipeline mode, each pipeline comprises a plurality of pipeline stages, each pipeline stage has different processing functions, and the method comprises the following steps: performing instruction matching based on first instruction information representing an instruction and second instruction information representing a first pipeline stage, and determining whether the instruction needs bypass processing in the first pipeline stage; the first pipeline stage is a pipeline stage to be entered in a pipeline for processing the instruction; if the instruction needs bypass processing in the first pipeline stage, the first pipeline stage is stopped and corresponding bypass processing of the first pipeline stage is performed; after the bypass processing is completed, the second pipeline stage in the pipeline continues to process the instruction and the first pipeline stage is recovered. By using the method, the instruction processing of the pipeline stage can be realized.

Description

Technical Field

[0001] This application relates to the field of computer instruction processing technology, and in particular to an instruction processing method. Background Technology

[0002] With the continuous development of electronic technology, programmable logic devices (PLDs) and application-specific integrated circuits (ASICs) are increasingly widely used in electronic systems. PLDs have advantages such as high flexibility and reprogrammability, while ASICs excel in performance and power consumption. However, existing PLD and ASIC combination schemes have certain limitations. They can only rely on programs to interact using pre-designed high-level programming interfaces, and cannot achieve active cooperation at the hardware level, making it difficult to fully leverage the synergistic advantages of both.

[0003] In existing solutions, modifications, additions, and deletions of Central Processing Unit (CPU) behavior are performed through microcode. Microcode is essentially a program, not hardware logic. Modifying, adding, or deleting CPU behavior through microcode is essentially a program transformation, which cannot finely control the hardware logic. Furthermore, it depends on the CPU not making mistakes when executing the microcode. In other words, if there are loopholes in the CPU's logical implementation, the microcode may lose its ability to successfully modify, add, or delete CPU behavior. Summary of the Invention

[0004] This application provides an instruction processing method for implementing pipelined instruction processing.

[0005] In a first aspect, embodiments of this application provide an instruction processing method applicable to a pipelined CPU, wherein each pipeline includes multiple pipeline stages, each pipeline stage having different processing functions. The method includes: performing instruction matching based on first indication information representing an instruction and second indication information representing a first pipeline stage to determine whether the instruction needs to be bypassed at the first pipeline stage; the first pipeline stage being the pipeline stage to be entered in the pipeline processing the instruction; if the instruction needs to be bypassed at the first pipeline stage, then pausing the first pipeline stage and performing the bypass processing corresponding to the first pipeline stage; after the bypass processing is completed, continuing to process the instruction through a second pipeline stage in the pipeline and restoring the first pipeline stage.

[0006] Using the above method, the main components of the CPU can be implemented as ASICs, while the instruction bypass unit can be implemented as PLDs. This ensures high performance and low power consumption of the main components of the CPU, while also ensuring high flexibility of the hardware logic of the instruction bypass unit, allowing the hardware logic of bypass processing to be added, deleted, or modified arbitrarily, especially after the CPU leaves the factory.

[0007] Using the above method, even if the main components of the CPU are implemented as ASICs and their logic cannot be arbitrarily added, deleted, or modified, instructions can still be bypassed at the target pipeline level by instruction matching to the instruction bypass unit. This ensures that arbitrary additions, deletions, and modifications to the hardware logic are achieved for both instructions and pipeline levels. In other words, even if the pipeline (and its various stages) are implemented as ASICs and are fixed and cannot be modified, instruction matching can still bypass specific pipeline stages for specific instructions to the instruction bypass unit. Since the instruction bypass unit is implemented as a PLD, it has variable hardware logic, achieving the effect of "replacing" a specified pipeline stage, "deleting" an existing pipeline stage, or "inserting" a new pipeline stage, thus enabling fine-grained control of the hardware logic. Simultaneously, this method combines the efficiency of ASICs with the synergistic advantages of the variable logic of PLDs, achieving proactive cooperation at the hardware level.

[0008] Using the above method, the instruction matcher can be implemented as either a PLD or an ASIC. The instruction matcher can match instructions with the first pipeline stage. After matching at the first pipeline stage, the first pipeline stage is paused and bypassed. After bypassing, the instruction continues execution from the second pipeline stage. Thus, the combination of the instruction matcher and the instruction bypass unit enables cooperation between instructions at the pipeline levels. When the specific instruction matching method is complex, it can be implemented as a PLD to obtain greater customizability; when the performance of instruction matching is a primary concern, it can be implemented as an ASIC to accelerate the instruction matching process.

[0009] In one possible implementation, instruction matching is performed based on first indication information representing the instruction and second indication information representing the first pipeline level to determine whether the instruction needs to be bypassed at the first pipeline level. This includes: for any matching item, determining whether the first indication information representing the instruction matches the mask and target value in the matching item; if the instruction matches, determining whether the second indication information representing the first pipeline level is any pipeline level in the target pipeline level list in the matching item; if so, determining that the instruction needs to be bypassed at the first pipeline level; otherwise, determining that the instruction does not need to be bypassed at the first pipeline level.

[0010] By using the above method, and by setting the mask, target value, and target pipeline level list for each match, the instructions and pipeline levels that require bypass processing can be flexibly configured. This improves the flexibility and ease of instruction matching.

[0011] In one possible implementation, before determining whether the first indication information of the representation instruction matches the mask and target value in the matching item, the method further includes: querying the matching instruction cache using the first indication information to determine that the first indication information does not belong to the matching instruction cache; the matching instruction cache includes indication information of representation instructions that can successfully match the mask and target value in any matching item and a target pipeline level list of the corresponding matching item.

[0012] Using the above method, the matching instruction cache is used to cache the matching results. If the first indication information of the instruction belongs to the matching instruction cache, it can be directly determined whether the first pipeline level is any pipeline level in the pipeline level list of the matching item based on the information stored in the matching instruction cache, without needing to perform instruction matching again. If the first indication information of the instruction does not belong to the matching instruction cache, it cannot be determined whether the instruction has successfully matched the mask and target value in the matching item, so instruction matching is required. In this way, the matching instruction cache can speed up the determination of the instruction matching result.

[0013] In one possible implementation, before performing instruction matching based on the first instruction information representing the instruction and the second instruction information representing the first pipeline level, the method further includes: determining that the second instruction information belongs to the target pipeline level set, wherein the target pipeline level set is obtained by summarizing the target pipeline level list corresponding to each matching item.

[0014] Using the above method, if the second instruction information of the first pipeline stage belongs to the target pipeline stage set, then the first pipeline stage may need to perform bypass processing. If the second instruction information of the first pipeline stage does not belong to the target pipeline stage set, even if the first instruction information of the instruction successfully matches the mask and the target value, the first pipeline stage may not need to perform bypass processing. Thus, determining whether the first pipeline stage of an instruction needs to perform bypass processing can be accelerated based on the target pipeline stage set.

[0015] In one possible implementation, the method further includes: if the second instruction information does not belong to the target pipeline level set, then the instruction is pipelined according to the pipeline level of the first pipeline level.

[0016] In one possible implementation, pausing the first pipeline stage includes: inserting a vacuole into the first pipeline stage, the vacuole having the characteristic of propagating to subsequent pipeline stages and the vacuole not requiring instruction matching.

[0017] In one possible implementation, the second pipeline stage is the first pipeline stage, or the next pipeline stage in the pipeline after the first pipeline stage, or any pipeline stage in the pipeline after the first pipeline stage.

[0018] In one possible implementation, the method is executed by an instruction matcher located in any pipeline stage; the any pipeline stage is any pipeline stage other than the instruction fetch pipeline stage.

[0019] In one possible implementation, the method is executed by an instruction matcher located outside the pipeline.

[0020] In one possible implementation, if the instruction requires bypass processing at the first pipeline stage, then pausing the first pipeline stage includes: if the instruction requires bypass processing at both the first and third pipeline stages, then pausing the first pipeline stage and instructing the instruction bypass unit to perform bypass processing for the instruction at both the first and third pipeline stages; the third pipeline stage is N consecutive pipeline stages following the first pipeline stage in the pipeline; N is greater than or equal to 1.

[0021] Using the above method, for pipeline stages that need to be continuously bypassed in an instruction, the instruction bypass unit can complete the bypass processing of multiple pipeline stages at once, which can merge the logic of consecutive pipeline stages, eliminate intermediate results, and improve the processing efficiency of consecutive pipeline stages.

[0022] In one possible implementation, the list of target pipeline levels in any match includes one or more consecutive pipeline levels in the pipeline.

[0023] In one possible implementation, before continuing to process the instruction through the second pipeline stage, the method further includes: determining that a bubble inserted into the first pipeline stage has arrived at the second pipeline stage; otherwise, waiting for the bubble to arrive at the second pipeline stage.

[0024] In one possible implementation, the instruction is further processed through a second pipeline stage in the pipeline, including: if the second pipeline stage is the first pipeline stage or the third pipeline stage, then instruction matching is not required for the first instruction information and the instruction information corresponding to the second pipeline stage.

[0025] In one possible implementation, the instruction requiring bypass processing is used to acquire or record the current clock. The target pipeline stage list in the matching item includes a write-back pipeline stage or a pipeline stage that accesses the clock. The result of the bypass processing is input to a second pipeline stage in the pipeline, replacing the data input of the second pipeline stage. The result is clock information that is unrelated to the current clock or inaccurate clock information.

[0026] By using the above method, the instruction to acquire or record the current clock is set as an instruction that needs to be bypassed. By setting the bypass result of the instruction at the write-back pipeline level or the bypass result of the instruction at the access clock pipeline level to clock information that is unrelated to the current clock or inaccurate clock information, the side-channel attack problem can be mitigated.

[0027] In one possible implementation, the instruction requiring bypass processing has an error in the CPU's hardware implementation, which leads to an unexpected instruction result; the bypass processing result is empty, the target pipeline stage list in the matching item contains pipeline stages located at the head of the pipeline, and the second pipeline stage is a pipeline stage located at the tail of the pipeline; or the bypass processing result is an exception, and the target pipeline stage list in the matching item contains any pipeline stage.

[0028] Using the above method, the instruction that has an error in the CPU hardware implementation and causes an unexpected result is set as an instruction that needs to be bypassed. By setting the pipeline-level instruction bypass result of the instruction to null or triggering an exception, the illegal instruction can be corrected from being executed incorrectly.

[0029] Secondly, embodiments of this application provide a central processing unit (CPU), the CPU comprising: an instruction matcher for executing a method as described in any possible implementation of the first aspect; and an instruction bypass unit for bypassing the instruction based on an instruction matcher instruction, obtaining a bypass processing result, and feeding it back to the instruction matcher.

[0030] In one possible implementation, the instruction matcher includes a bypass decision unit, a matching unit, and a matching item storage unit; the matching item storage unit stores at least one matching item; the bypass decision unit is used to obtain first indication information representing an instruction and second indication information representing a first pipeline stage; the matching unit is used to perform instruction matching based on the first indication information and each matching item; the bypass decision unit is further used to pause the first pipeline stage and resume the first pipeline stage if the instruction needs to be bypassed at the first pipeline stage.

[0031] In one possible implementation, the instruction matcher further includes a matching instruction cache; the matching instruction cache includes indication information of instruction representation that can be successfully matched with the mask and target value in any matching item, and a target pipeline level list of the corresponding matching item; the bypass decision unit is further configured to query the matching instruction cache using the first indication information before performing instruction matching through the matching unit, and determine that the first indication information does not belong to the matching instruction cache.

[0032] In one possible implementation, the instruction matcher further includes a target pipeline level set, which is obtained by summarizing the target pipeline level lists corresponding to each matching item; the bypass decision unit is further configured to determine that the second indication information belongs to the target pipeline level set before instruction matching is performed by the matching unit.

[0033] In one possible implementation, the bypass decision unit is specifically configured to generate an instruction matching request based on first indication information representing the instruction and send it to the matching unit; and receive the instruction matching result from the matching unit; the matching unit is specifically configured to receive the instruction matching request, and after determining that there is a matching item matching the first indication information, send the target pipeline level list in the matching item to the bypass decision unit; the bypass decision unit is further configured to determine whether bypass processing is required based on the second indication information and the target pipeline level list.

[0034] Thirdly, embodiments of this application provide an instruction processing device, the instruction processing device comprising: a memory for storing computer programs or instructions; and a processor for calling the computer programs or instructions stored in the memory to execute the method as described in any possible implementation of the first aspect. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of pipelined instruction processing provided in an embodiment of this application;

[0037] Figure 2 This is a flowchart illustrating an instruction processing method provided in an embodiment of this application.

[0038] Figure 3A schematic diagram of a pipeline-level instruction processing method provided in an embodiment of this application;

[0039] Figure 4 A schematic diagram of another pipeline-level instruction processing method provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the structure of an instruction processing device 5000 provided in an embodiment of this application. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] ASICs are integrated circuits specifically designed to meet the needs of specific electronic systems. The circuit structure and functions of an ASIC are customized for a particular application. Once an ASIC is manufactured, its internal logic is fixed and cannot be changed. Currently, if a logic defect exists in an ASIC, it cannot be fundamentally repaired; only mitigation methods can be used to alleviate these defects. Mitigation solutions generally use microcode, which is essentially a program, not hardware logic. Microcode can manipulate the operation and internal state of the ASIC, but manipulating the ASIC's operation and internal state through microcode is essentially a program transformation and cannot finely control the hardware logic. Furthermore, it depends on the ASIC not making errors when executing the microcode. A CPU is essentially an ASIC. Therefore, it is necessary to propose a method that makes it possible to finely modify, add, and delete CPU behavior, and the normal operation of this method will not be disrupted by logic defects in the CPU.

[0043] Furthermore, existing PLD and ASIC integration solutions have certain limitations. They rely solely on pre-designed high-level programming interfaces for interaction, failing to achieve proactive collaboration at the hardware level and thus hindering the full realization of their synergistic advantages. Therefore, it is necessary to propose a method that enables PLD and ASIC to collaborate more deeply and at a more refined and fundamental level.

[0044] Based on this, embodiments of this application provide an instruction processing method for implementing pipeline-level instruction processing.

[0045] To facilitate understanding, some terms used in this application will be explained first.

[0046] Instruction is a shorthand term for machine code instruction, and it is the foundation of program execution. The core of a machine code instruction is its opcode. The decoder must first determine the instruction's opcode in order to determine the arrangement of operands and the meaning of each operand, and then further send the instruction to the subsequent pipeline stage for execution according to the behavior defined in the instruction set.

[0047] Pipelining is an essential part of modern computer processors. It refers to breaking down the computer instruction processing into multiple steps and executing them in parallel by multiple hardware processing units to accelerate instruction execution. Pipelining is a fixed hardware logic. Pipeline implementations vary, and different CPUs may have varying numbers of pipeline stages. The most classic pipeline design is a 5-stage pipeline. The 5-stage pipeline includes instruction fetch (IF), instruction decode (ID), execute (EX), memory access (MEM), and write back (WB). Specifically, IF fetches the instruction to be executed from memory; ID parses and interprets the fetched instruction; EX performs arithmetic, logical, and control transfer operations based on the decoded result, especially the operation type and operands; MEM handles memory-related operations, including reading data and storing results; and WB writes the execution result to the appropriate register for use by subsequent instructions. Figure 1 This is a schematic diagram of a pipelined instruction processing method provided in an embodiment of this application. Figure 1 It can be seen that, Figure 1 The diagram illustrates the execution of five instructions in a pipeline. Each instruction enters a different stage at different clock cycles. Each rectangle represents a stage of the pipeline for one instruction. It shows that under the same clock cycle, the subsequent stage of one instruction can be executed, as can the preceding stage of another instruction. This overlapping execution improves processor efficiency. This application does not limit the number of pipeline stages.

[0048] Figure 2 This is a flowchart illustrating an instruction processing method provided in an embodiment of this application. The method is applicable to a pipelined CPU, where each pipeline includes multiple pipeline stages, each with different processing functions. This flowchart can be executed by the CPU. Figure 2 As shown, the process includes the following steps:

[0049] Step 201: The CPU performs instruction matching based on the first instruction indication information and the second instruction indication information representing the first pipeline stage to determine whether the instruction needs to be bypassed at the first pipeline stage. The first pipeline stage is the pipeline stage to be entered in the pipeline that processes the instruction.

[0050] Specifically, the first indication information of an instruction can be the machine code of the instruction, its memory address, or its internal number. The instruction can be identified based on this first indication information. The second indication information of the first pipeline stage can be indication information representing the name of the first pipeline stage, which is the pipeline stage to be entered in the pipeline that processes the instruction. Instruction matching is performed based on the first indication information representing the instruction and the second indication information of the first pipeline stage to determine whether the instruction needs to be bypassed in the first pipeline.

[0051] There are several methods for instruction matching, including tree matching and graph matching. Optionally, instruction matching is performed based on the first indication information representing the instruction and the second indication information representing the first pipeline level to determine whether the instruction needs to be bypassed at the first pipeline level. This includes: for any matching item, determining whether the first indication information representing the instruction matches the mask and target value in the matching item; if the instruction matches, determining whether the second indication information representing the first pipeline level is any pipeline level in the target pipeline level list in the matching item; if so, determining that the instruction needs to be bypassed at the first pipeline level; otherwise, determining that the instruction does not need to be bypassed at the first pipeline level.

[0052] Specifically, instruction matching can be achieved using a target value and a mask. Each matching item includes a mask and a target value. The mask indicates the binary bits involved in the matching for each instruction; the target value is used to compare with the instruction to be matched. Each matching item also includes a target pipeline level list, where any pipeline level can be any one or more pipeline levels in the pipeline other than instruction fetch. Matching is performed on each matching item based on the first indication information representing the instruction. If the first indication information representing the instruction successfully matches the mask and target value in the matching item, it is further determined whether the target pipeline level list of the matching item includes the first pipeline level. If it does, it can be determined that the first pipeline level of the instruction needs to be bypassed; otherwise, the first pipeline level of the instruction does not need to be bypassed, and the first pipeline level is executed normally in the pipeline.

[0053] For example, the matching of an 8-bit instruction with a matching item is shown in Table 1.

[0054] Table 1

[0055]

[0056] In this table, 1 represents a binary bit that is 1, 0 represents a binary bit that is 0, and x represents any value for the binary bit. As shown in Table 1, if the binary representation of the instruction and the target value is the same in the bits where the mask is 1, then the instruction successfully matches the matching item. Furthermore, the matching item also includes a list of target pipeline stages. For example, if the pipeline stage in the target pipeline stage list of the matching item is a decoder stage, and the pipeline stage to be entered by the instruction is also a decoder stage, then the pipeline stage to be entered by the instruction needs to be bypassed; if the pipeline stage to be entered by the instruction is not a decoder stage, then the pipeline stage to be entered by the instruction executes normally.

[0057] Optionally, the instruction set can be a fixed-length instruction set or a variable-length instruction set, where the instruction length is not unique. For variable-length instruction sets, both the mask and the target value have the maximum length. Bits set to 0 in the mask allow non-existent bits to be matched, but bits set to 1 require the corresponding bit in the instruction to be present. Instructions shorter than the maximum length have two matching methods: matching with high-order bits aligned or matching with low-order bits aligned. If the instruction length in the variable-length instruction set could be 8 bits or 12 bits, then both the mask and the target value are 12 bits long. Assuming that instructions shorter than the maximum length are matched with high-order bits aligned, if at least four consecutive bits of the least significant bit of the mask are 0, then this match can match both 8-bit and 12-bit instructions; conversely, if any one of the four least significant bits of the mask is 1, then this match can only match 12-bit instructions.

[0058] Assuming that instructions shorter than the maximum length are matched by aligning the low bits, then if the highest bit of the mask has at least four consecutive 0 bits, the match can match both 8-bit and 12-bit instructions. Conversely, if any of the last four bits of the mask is 1, the match can only match 12-bit instructions.

[0059] Therefore, for variable-length instruction sets, the same match term can seem ambiguous because it can match instructions of two different lengths. However, this problem can be completely avoided by writing the match term appropriately.

[0060] For example, in some variable-length instruction sets, the instruction length is directly determined by the opcode. Therefore, as long as the matching term includes a match for the opcode, there is no ambiguity regarding the instruction length.

[0061] Therefore, to ensure that the matching terms do not cause ambiguity regarding instruction length for variable-length instruction sets, it is essential to ensure that the matching bits encompass the bits containing the opcode. If matching the first-level opcode is sufficient to determine the instruction length, then only the bits containing the first-level opcode should be included. Otherwise, if matching opcodes from level 1 to n is sufficient to determine the instruction length, then the bits containing opcodes from level 1 to n should be included.

[0062] Alternatively, some variable-length instruction sets may be too complex. In that case, we can add a new parameter to the match: the instruction length. This parameter specifies the expected instruction length for the match. If the instruction length is not equal to this parameter, the match is considered to have failed.

[0063] Optionally, embodiments of this application further include a matching instruction cache. The matching instruction cache includes indication information of representation instructions that can successfully match the mask and target value in any matching item, and a target pipeline level list for the corresponding matching item. The corresponding matching item represents a matching item successfully matched according to the matching instruction cache. Before determining whether the first indication information of the representation instruction matches the mask and target value in the matching item, the method further includes querying the matching instruction cache using the first indication information to determine if the first indication information does not belong to the matching instruction cache. This is because if the first indication information of the instruction belongs to the matching instruction cache, it is possible to directly determine whether the first pipeline level belongs to the pipeline level in the target pipeline level list of the matching item based on the information stored in the matching instruction cache, without needing to perform instruction matching again; if the first indication information of the instruction does not belong to the matching instruction cache, it cannot be determined whether the instruction successfully matches the matching item, therefore instruction matching is required. Thus, the matching instruction cache can speed up the determination of the instruction matching result.

[0064] Optionally, embodiments of this application further include a target pipeline level set, which is obtained by summarizing the target pipeline level lists corresponding to each matching item. In complex pipelines, there can be dozens of pipeline levels. The target pipeline level set is obtained by counting the target pipeline level lists corresponding to each matching item. Before performing instruction matching based on the first instruction indication information representing the instruction and the second instruction indication information representing the first pipeline level, it is further included to determine whether the second instruction indication information belongs to the target pipeline level set. This is because if the second instruction indication information of the first pipeline level belongs to the target pipeline level set, the first pipeline level may need to perform bypass processing. If the second instruction indication information of the first pipeline level does not belong to the target pipeline level set, even if the first instruction indication information of the instruction successfully matches the mask and target value of the matching item, the first pipeline level may not need to perform bypass processing. Thus, by using the target pipeline stage set, it's possible to quickly determine whether the first pipeline stage of an instruction needs bypass processing. For example, if a pipeline stage doesn't belong to the target pipeline stage set, then upon entering that stage, it's already known that bypass processing is unnecessary without needing to check the instruction matching results. Furthermore, if the first pipeline stage doesn't belong to the target pipeline stage set, then the instruction is pipelined according to the pipeline's requirements for the first pipeline stage.

[0065] Step 202: If the instruction needs to be bypassed at the first pipeline stage, then pause the first pipeline stage and perform the corresponding bypass processing at the first pipeline stage.

[0066] Furthermore, if it is determined that an instruction needs to be bypassed at the first pipeline stage, the first pipeline stage is paused, and the processing result of the previous pipeline stage is sent to the bypass processing unit. Optionally, pausing the first pipeline stage includes inserting a bubble into the pipeline. Bubbles have the characteristic of propagating to subsequent pipeline stages, and bubble matching is not required. Bubbles propagate to subsequent pipeline stages, ensuring that subsequent pipeline stages do not use meaningless output from the previous stage due to a pause in the preceding stage. If a bubble is inserted for other reasons, i.e., not by the instruction matcher, such as to avoid danger, this bubble will also cause a pipeline stage pause and propagate forward. The instruction matcher does not need to perform instruction matching or query the matching instruction cache for any bubble.

[0067] Step 203: After the CPU completes the bypass processing, it continues to process the instructions through the second pipeline stage and resumes the first pipeline stage.

[0068] Specifically, after processing the instruction via the bypass corresponding to the first pipeline stage, the instruction is processed again via the second pipeline stage, and the first pipeline stage is restored. The second pipeline stage is the target pipeline stage for resumption of execution. The second pipeline stage can be the first pipeline stage, the next pipeline stage following the first pipeline stage, or any pipeline stage following the first pipeline stage. Restoring the first pipeline stage allows other instructions to continue execution within the first pipeline stage.

[0069] Optionally, the above method is executed by an instruction matcher located in any pipeline stage of the CPU. Any pipeline stage is any pipeline stage other than the instruction fetch pipeline stage. That is, the instruction matcher can complete instruction matching on the premise that instruction fetching has been completed.

[0070] In one possible implementation, the instruction is further processed by a second pipeline stage in the pipeline. If the bypass processing corresponding to the first pipeline stage produces a bypass processing result, the bypass processing result is input to the second pipeline stage in the pipeline to replace the data input of the second pipeline stage.

[0071] For example, as shown in Table 2, there are 5 instructions, each of which will flow through 5 pipeline stages sequentially. After instruction 3 completes the fetch stage, since it is determined that instruction 3 needs to be bypassed in pipeline stage 1 (the first pipeline stage), pipeline stage 1 is paused and instruction 3 is bypassed starting from clock cycle 4. Therefore, instructions 4 to 5 cannot enter pipeline stage 1 for execution. The bypassing process takes 2 clock cycles. At clock cycle 6, after the bypassing process of instruction 3 in the first pipeline stage is completed, instruction 3 continues to be processed through pipeline stage 2 (the second pipeline stage) and pipeline stage 1 is restored (i.e., the pause is lifted). Since the second pipeline stage is not the first pipeline stage, pipeline stage 1 will process subsequent instructions at this time. Therefore, at clock cycle 6, instruction 4 enters pipeline stage 1 for execution; at the same time, since the second pipeline stage is pipeline stage 2, instruction 3 enters pipeline stage 2.

[0072] In this example, judging from the result, instruction 3 flows through the instruction fetch stage, the bypass processing corresponding to pipeline stage 1, pipeline stage 2, pipeline stage 3, and pipeline stage 4 in sequence, that is, pipeline stage 1 is replaced by bypass processing; the remaining instructions flow through all 5 pipeline stages in sequence.

[0073] The replacement of pipeline stage 1 with bypass processing depends on the specific logic implemented in the bypass processing. For example, the effect includes, but is not limited to, permutations and combinations of the following two types of sub-operations:

[0074] a) Replace the original pipeline stage 1 with an alternative implementation of pipeline stage 1 (which may fix the vulnerability); or, skip pipeline stage 1.

[0075] b) Insert a new pipeline stage before pipeline stage 1 (which may be an alternative implementation); and / or, insert a new pipeline stage after pipeline stage 1 (which may be an alternative implementation); or, do not insert a new pipeline stage.

[0076] The alternative implementation of pipeline stage 1 and the new pipeline stage are implemented in bypass processing.

[0077] Table 2

[0078]

[0079] Figure 3 This is a schematic diagram of a pipeline-level instruction processing method provided in an embodiment of this application. Figure 3 The instruction matcher in the pipeline can reside in any pipeline stage or operate independently of any pipeline stage. In both implementations, each pipeline stage can query the instruction matching results; the only constraint is that instruction matching can only occur after instruction fetching is complete. Figure 3 As can be seen, after the instruction fetch stage, before the execution of the first pipeline stage, it is checked whether the first pipeline stage needs to be bypassed. If the first pipeline stage is not in the target pipeline stage set, it is executed normally, meaning the first pipeline stage does not need to be bypassed, and in this case, there is no need to consider whether instruction matching is complete. If the first pipeline stage is in the target pipeline stage set, it is paused and waits for instruction matching. If the instruction matching is successful but the first pipeline stage is not in the target pipeline stage list of the matched item, it is also executed normally. If the instruction matching is successful and the first pipeline stage is in the target pipeline stage list of the matched item, the result of the previous pipeline stage is sent to the bypass. After the bypass processing is completed, the instruction is processed again through the second pipeline stage in the pipeline, and the first pipeline stage is restored.

[0080] Alternatively, the above method can also be executed by an instruction matcher located outside the pipeline in the CPU. Figure 4 This is a schematic diagram of another pipelined instruction processing method provided in an embodiment of this application. Figure 4 The instruction matcher in the pipeline is located outside the pipeline.

[0081] This application embodiment also provides a CPU, which includes an instruction matcher and an instruction bypass unit. The instruction matcher is used to execute the above-described instruction processing method, and the instruction bypass unit is used to bypass the instruction based on the instruction matcher's instruction, obtain the bypass processing result, and feed it back to the instruction matcher.

[0082] Optionally, the instruction matcher includes a bypass decision unit, a matching unit, and a matching item storage unit, wherein the matching item storage unit stores at least one matching item, the matching item storage unit provides matching items for the matching unit to use when performing matching, and the matching item storage unit can also generate or update the target pipeline-level total set.

[0083] Specifically, the bypass decision unit is used to acquire first indication information representing the instruction and second indication information representing the first pipeline stage; it is also used to pause and resume the first pipeline stage if the instruction needs to be bypassed at the first pipeline stage. The matching unit is used to perform instruction matching based on the first indication information and each matching item.

[0084] For example, the bypass decision unit will receive first indication information of the instruction to be processed by each pipeline stage and second indication information of the pipeline stage. Such indication information may be output from the pipeline stage to the bypass decision unit, or it may be input from other units in the CPU that maintain the pipeline state; this is not limited here. Figure 4 In the diagram, the lines pointing from each pipeline stage to the bypass decision unit are dashed, indicating that the instruction information does not necessarily have to be directly output by the pipeline stage. The matching unit receives the first instruction information from the bypass decision unit, and performs instruction matching based on the first instruction information and the matching items stored in the matching item storage unit. If the matching is successful, the result of the instruction matching also includes the target pipeline stage list of the corresponding matching item.

[0085] Optionally, the instruction matcher also includes a matching instruction cache, used to cache indication information of instructions that can successfully match the mask and target value in any matching item, as well as the target pipeline level list of the corresponding matching item. Before performing instruction matching on the first indication information of an instruction, the first indication information is used to query the matching instruction cache to determine if the first indication information does not belong to the matching instruction cache; if it does, the target pipeline level list can be determined directly based on the query result (i.e., the cached matching result). In this way, the bypass decision unit can quickly determine whether the instruction needs to be matched based on the matching instruction cache, and quickly obtain the cached matching result when querying for matching. Optionally, the number of cached results that the matching instruction cache can store is not less than the total number of pipeline stages.

[0086] Optionally, the instruction matcher also includes a target pipeline level set, which is a summary of the target pipeline level lists corresponding to each matching item. Before instruction matching is performed by the matching unit, it is determined that the second instruction information belongs to the target pipeline level set; if it does not, it can be quickly determined that the first pipeline level does not need to be bypassed and can continue to be processed by the first pipeline level in the pipeline. It should be noted that if matching items are added, deleted, or modified subsequently, the target pipeline level set may change.

[0087] Optionally, the bypass decision unit is further configured to generate an instruction matching request based on the first instruction indication information and send it to the matching unit. The matching unit receives the instruction matching request from the bypass decision unit, performs the matching, determines the matching items existing in the first instruction indication matching, and then sends the target pipeline level list from the matched items to the bypass decision unit. The bypass decision unit is also configured to determine whether bypass processing is required based on the second instruction indication information and the target pipeline level list. That is, the instruction matching request does not need to contain the second instruction indication information of the first pipeline level, but only needs to contain the first instruction indication information; the second instruction indication information is processed by the bypass decision unit after instruction matching, as described above.

[0088] Specifically, the bypass decision unit determines whether the first pipeline stage needs to be paused based on certain criteria, such as when instruction matching is not yet complete and the first pipeline stage belongs to the target pipeline stage set. In this case, the pause is to wait for the instruction matching to complete before making a final decision: whether to bypass the process or execute normally. At this point, the first pipeline stage should be paused at least until instruction matching is complete, meaning that cavitation is continuously inserted into the first pipeline stage during this period. Subsequently, based on the instruction matching result, it is decided whether to bypass the first pipeline stage. If so, the first pipeline stage continues to pause until bypass processing of the instruction is complete; otherwise, the first pipeline stage is allowed to continue execution. Alternatively, based on the instruction matching result of the output of the matched instruction buffer as described above, a quick decision may be made that the first pipeline stage needs to be paused; or based on the target pipeline stage set as described above, a quick decision may be made that the first pipeline stage does not need to be paused.

[0089] Understandably, if the first pipeline stage is the instruction fetch stage, then there is no need to pause the first pipeline stage, because if the instruction fetch stage pauses, then no instruction can enter the pipeline.

[0090] If at least one matching item matches an instruction, and the target pipeline stage list in the matching item contains the first pipeline stage, then the first pipeline stage also needs to be paused. This pause is to bypass the first pipeline stage and allow the instruction to enter the bypass. In this case, the first pipeline stage should remain paused until the instruction bypass unit completes processing the instruction. Pausing the first pipeline stage can be done by inserting a bubble into the first pipeline stage. Simultaneously or immediately after inserting the bubble, the instruction, the instruction's indication information for the first pipeline stage, and its input are sent to the instruction bypass unit. The input of the first pipeline stage is the output of the previous pipeline stage in the pipeline. Based on this information, the instruction bypass unit can execute the instruction according to the specified behavior of the first pipeline stage. After execution, the result of the instruction bypass is returned to the bypass decision unit.

[0091] After receiving the instruction bypass result, the bypass decision unit stops inserting cavitation into the first pipeline stage and can insert the instruction bypass result into the input of the second pipeline stage, which is generally the next pipeline stage after the first. At this point, the second pipeline stage will no longer receive the output of the preceding pipeline stage but will instead receive the instruction bypass result. In effect, the output of the preceding pipeline stage at this time is the output of the cavitation, meaning the cavitation is propagating to subsequent pipeline stages. By inserting the instruction bypass result into the second pipeline stage, it effectively prevents it from receiving cavitation, thus effectively terminating the propagation of cavitation after the instruction bypass result is generated, allowing the pipeline to efficiently resume normal execution.

[0092] Furthermore, if multiple consecutive pipeline stages need to be bypassed, for example, suppose there are three consecutive pipeline stages that need to be bypassed, denoted as A, B, and C. After pipeline stage A completes bypassing, its bypass result is sent to the bypass decision unit and then output to pipeline stage B. Since pipeline stage B also needs to be bypassed, its input, namely the bypass result of pipeline stage A, is sent to the instruction bypass unit by the bypass decision unit, and cavitation begins to be inserted into pipeline stage B at this time. After pipeline stage B completes bypassing, its bypass result is sent to the bypass decision unit and then output to pipeline stage C. Since pipeline stage C also needs to be bypassed, its input, namely the bypass result of pipeline stage B, is sent to the instruction bypass unit by the bypass decision unit, and cavitation begins to be inserted into pipeline stage C at this time. When pipeline stage C... After bypassing is completed, the bypass result is sent to the bypass decision unit and then output to the subsequent pipeline level to resume the normal execution of the pipeline.

[0093] The above process does not cause errors in the bypass execution results. However, since each consecutive pipeline stage needs to trigger instruction bypass separately, and intermediate results, i.e., the bypass results of pipeline stages A and B, are forced to be repeatedly transmitted, there is a problem of low efficiency. At the same time, the pipeline stages that are bypassed consecutively must be implemented separately in the instruction bypass unit, which must produce intermediate results. This is not conducive to the optimization of the logic implementation in the instruction bypass unit. If these pipeline stages that are bypassed consecutively are implemented together, the intermediate results can be eliminated, and more logic optimizations can be applied. Therefore, this application proposes a better implementation method.

[0094] Specifically, the target pipeline stage list in any matching item includes one or more consecutive pipeline stages. The first pipeline stage triggers a successful instruction match. Based on the matched instruction entries, the bypass decision unit can determine which pipeline stages need to be bypassed for this bypassed instruction. Further, it determines which pipeline stages among the subsequent consecutive pipeline stages immediately adjacent to the first pipeline stage need to be bypassed. These, along with the first pipeline stage, constitute the set of consecutive pipeline stages that need to be bypassed. The first pipeline stage can also be referred to as the first consecutive bypassed pipeline stage.

[0095] The bypass decision unit only needs to insert a vacuole into the first pipeline stage, without needing to insert vacuoles into other pipeline stages in the successive pipeline stages that need to be bypassed. This is because vacuoles propagate backward, and other pipeline stages may be processing other instructions, so inserting vacuoles into them would disrupt the processing results of those instructions. Since vacuoles propagate backward and do not participate in instruction matching or instruction bypassing, other pipeline stages in the successive pipeline stages that need to be bypassed will not trigger instruction matching due to this bypassed instruction.

[0096] It should be noted that during the instruction bypass process, cavitation bubbles need to be continuously inserted into the first pipeline stage.

[0097] After inserting a cavitation bubble into the first pipeline stage, or at the same time as inserting a cavitation bubble into the first pipeline stage, the bypass decision unit, while transmitting the instruction and the input of the first pipeline stage to the instruction bypass unit, also transmits a list of consecutive pipeline stages that need to be bypassed to the instruction bypass unit.

[0098] If an instruction requires bypass processing at the first pipeline stage, then the first pipeline stage is paused. This includes: if the instruction requires bypass processing at both the first and third pipeline stages, then the first pipeline stage is paused and the instruction bypass unit is instructed to perform bypass processing at both the first and third pipeline stages. The third pipeline stage is N consecutive pipeline stages following the first pipeline stage in the pipeline, where N is greater than or equal to 1.

[0099] At this point, the first and third pipeline stages together form the aforementioned list of consecutive pipeline stages that need to be bypassed.

[0100] In other words, the instruction bypass unit can complete the bypass processing of multiple pipeline stages at once according to this list, that is, execute the instruction according to the specified behavior of these consecutive pipeline stages, but it is not necessary to implement the logic of these consecutive pipeline stages separately. Instead, the logic of these pipeline stages can be combined and implemented.

[0101] When returning the instruction bypass result, the instruction bypass unit is also used to specify the second pipeline stage; that is, to specify the pipeline stage into which the instruction bypass result should be inserted. In one possible implementation, the second pipeline stage is specified as the next pipeline stage after the third pipeline stage; that is, the second pipeline stage is specified as the pipeline stage after the last pipeline stage in the list of consecutive pipeline stages that need to be bypassed.

[0102] Specifically, before returning the bypass processing result of the instruction to the second pipeline stage in the pipeline, it also includes: determining that the cavitation bubble inserted into the first pipeline stage has reached the second pipeline stage; otherwise, waiting for the cavitation bubble to reach the second pipeline stage.

[0103] For example, as shown in Table 3, there are 5 instructions, each of which will flow through 5 pipeline stages sequentially. After instruction 3 completes the fetch stage, since it is determined that instruction 3 needs to be bypassed in pipeline stage 1 (the first pipeline stage), pipeline stage 1 is paused and instruction 3 is bypassed starting from clock cycle 4. Therefore, instructions 4 to 5 cannot enter pipeline stage 1 for execution. The bypassing process takes 2 clock cycles. At clock cycle 6, after instruction 3 completes the bypassing process corresponding to the first pipeline stage, it continues to be processed through pipeline stage 4 (the second pipeline stage) and resumes (unpauses) pipeline stage 1. Since the second pipeline stage is not the first pipeline stage, pipeline stage 1 will process subsequent instructions at this time. Therefore, at clock cycle 6, instruction 4 enters pipeline stage 1 for execution. At the same time, since the second pipeline stage is pipeline stage 3, instruction 3 skips pipeline stages 2 and 3 and proceeds to pipeline stage 1. The first cavitation bubble is inserted in clock cycle 4 and will arrive at pipeline stages 2, 3, and 4 in clock cycles 5, 6, and 7, respectively. Although bypass processing is completed in clock cycle 6, instruction 2 will enter pipeline stage 4 and be processed first because the cavitation bubble has not yet arrived at pipeline stage 4. When the cavitation bubble arrives in clock cycle 7, pipeline stage 4 can process instruction 3 (at this time, it is not necessary to process the cavitation bubble anymore; we only need to determine its arrival, not process the cavitation bubble itself—as long as the cavitation bubble arrives, instruction 3 can be processed).

[0104] In this example, the result shows that instruction 3 flows through the instruction fetch stage, the bypass processing corresponding to pipeline stage 1, and pipeline stage 4 in sequence, that is, pipeline stages 1, 2, and 3 are replaced by bypass processing; the remaining instructions flow through all 5 pipeline stages in sequence.

[0105] The replacement of pipeline stages 1, 2, and 3 with bypass processing depends on the specific logic implemented in the bypass processing. For example, the effect includes, but is not limited to, permutations and combinations of the following four sub-operations:

[0106] c) Replace the original pipeline stage 1 with an alternative implementation of pipeline stage 1 (which may have fixed the vulnerability); or, skip pipeline stage 1.

[0107] d) Replace the original pipeline stage 2 with an alternative implementation of pipeline stage 2 (which may have fixed the vulnerability) or skip pipeline stage 2.

[0108] e) Replace the original pipeline stage 2 with an alternative implementation of pipeline stage 3 (which may have fixed the vulnerability) or skip pipeline stage 3.

[0109] f) Insert a new pipeline stage before pipeline stage 1 (which may be an alternative implementation); and / or, insert a new pipeline stage between pipeline stage 1 and an alternative implementation of pipeline stage 2 (which may both be alternative implementations); and / or, insert a new pipeline stage between pipeline stage 2 and an alternative implementation of pipeline stage 3 (which may both be alternative implementations); and / or, insert a new pipeline stage after pipeline stage 3 (which may be an alternative implementation); or, do not insert a new pipeline stage.

[0110] The alternative implementation of pipeline stage 1, 2, or 3, and the new pipeline stage, are implemented in bypass processing.

[0111] Table 3

[0112]

[0113] In one possible implementation, the bypass decision unit determines that the first cavitation bubble inserted into the first pipeline stage due to the bypass of this instruction has now arrived at or previously arrived at the second pipeline stage, and thus determines that the cavitation bubble inserted into the first pipeline stage has arrived at the second pipeline stage.

[0114] If it's determined that the cavitation bubble inserted into the first pipeline stage hasn't reached the second pipeline stage, wait for the first cavitation bubble inserted into the first pipeline stage due to instruction bypass to reach the second pipeline stage before proceeding to the next step (i.e., the next segment). If it's determined that the cavitation bubble previously inserted into the first pipeline stage has had sufficient time to propagate to the second pipeline stage, proceed directly to the next step. This is because if the first cavitation bubble inserted into the first pipeline stage due to instruction bypass hasn't reached the second pipeline stage, it means the bypass unit completed the bypass processing extremely quickly—so quickly that the second pipeline stage and even other subsequent pipeline stages that need to be bypassed might still be processing earlier instructions. If the instruction bypass result is inserted directly without waiting, it will disrupt the execution of these earlier instructions. Therefore, by judging the propagation of cavitation bubbles and waiting as needed, the integrity of the instruction flow and the correctness of program execution can be guaranteed. It should be noted that the waiting for the first cavitation bubble inserted into the first pipeline stage due to the bypass of this instruction to reach the second pipeline stage only affects the timing of the bypass result of the insertion instruction reaching the second pipeline stage, and does not affect the recovery of the first pipeline stage; in other words, the first pipeline stage can be recovered when the bypass processing is completed, regardless of whether the cavitation bubble inserted into the first pipeline stage reaches the second pipeline stage.

[0115] The bypass decision unit inserts the instruction bypass result into the second pipeline stage according to the instruction bypass unit's instruction. At this point, all consecutive pipeline stages that need to be bypassed can be considered as having already bypassed the instruction. For this instruction, the pipeline continues normal execution from the second pipeline stage.

[0116] The final result of this implementation is consistent with the final result of triggering instruction bypasses in each successive pipeline stage, thus improving efficiency and performance while ensuring correct execution.

[0117] To better explain the pipelined processing of multiple instructions, Table 4 is provided below. In Table 4, the second pipeline stage is the pipeline stage following the first pipeline stage.

[0118] Table 4

[0119]

[0120] For example, as shown in Table 4, there are 5 instructions, each of which will flow through 5 pipeline stages sequentially. After instruction 1 completes the fetch stage, since it is determined that instruction 1 needs to be bypassed in pipeline stage 1 (the first pipeline stage), pipeline stage 1 is paused and instruction 1 is bypassed starting from clock cycle 2. Therefore, instructions 2 through 5 cannot enter pipeline stage 1 for execution. The bypassing process takes 4 clock cycles. At clock cycle 6, after instruction 1 completes the bypassing process corresponding to the first pipeline stage, it continues to be processed through pipeline stage 3 (the second pipeline stage) and resumes (unpauses) pipeline stage 1. Since the second pipeline stage is not the first pipeline stage, pipeline stage 1 will process subsequent instructions at this time. Therefore, at clock cycle 6, instruction 2 enters pipeline stage 1 for execution. At the same time, since the second pipeline stage is pipeline stage 3, instruction 1 skips pipeline stage 2 and directly enters pipeline stage 3.

[0121] In this example, the result shows that instruction 1 flows through the instruction fetch stage, the bypass processing corresponding to pipeline stage 1, pipeline stage 3, and pipeline stage 4 in sequence, that is, pipeline stages 1 and 2 are replaced by bypass processing; the remaining instructions flow through all 5 pipeline stages in sequence.

[0122] The replacement of pipeline stages 1 and 2 with bypass processing depends on the specific logic implemented in the bypass processing. For example, the effect includes, but is not limited to, permutations and combinations of the following three types of sub-operations:

[0123] a) Replace the original pipeline stage 1 with an alternative implementation of pipeline stage 1 (which may fix the vulnerability); or, skip pipeline stage 1.

[0124] b) Replace the original pipeline stage 2 with an alternative implementation of pipeline stage 2 (which may have fixed the vulnerability) or skip pipeline stage 2.

[0125] c) Insert a new pipeline stage before pipeline stage 1 (which may be an alternative implementation); and / or, insert a new pipeline stage between pipeline stage 1 and an alternative implementation of pipeline stage 2 (which may both be alternative implementations); and / or, insert a new pipeline stage after pipeline stage 2 (which may be an alternative implementation); or, do not insert a new pipeline stage.

[0126] The alternative implementation of pipeline stage 1 or 2 and the new pipeline stage are implemented in bypass processing.

[0127] Optionally, the instruction bypass unit can also insert the instruction bypass result into the first pipeline stage that triggered the bypass, instead of its next pipeline stage or other subsequent pipeline stages; in other words, the second pipeline stage is allowed to be the first pipeline stage. That is, although an instruction is sent to the instruction bypass unit at a certain pipeline stage due to a matching item, the instruction bypass unit can still return the input of that pipeline stage unchanged or after some modification to that pipeline stage, so that the instruction can still be executed using the circuitry of that pipeline stage, instead of using the instruction bypass unit. Determining that the bubble inserted into the first pipeline stage has reached the second pipeline stage also includes: if the second pipeline stage is the first pipeline stage, then it can be determined that the bubble inserted into the first pipeline stage has reached the second pipeline stage. That is, if the second pipeline stage is the first pipeline stage, it can be unconditionally assumed that the bubble has reached the second pipeline stage.

[0128] For example, this might be because some matches are too complex to be implemented using only an instruction matcher. Therefore, the instruction bypass unit can also perform a secondary match on the bypassed instruction to determine whether the first pipeline stage in this instruction really needs to be bypassed. If not, then the input of the first pipeline stage is returned to the pipeline stage unchanged, so that the pipeline stage is not actually bypassed.

[0129] For example, this implementation may also correct a logical flaw in the implementation of the first pipeline stage by simply modifying its input (in other words, preprocessing its input); or, if a logical flaw exists in the implementation of the pipeline stage preceding the first pipeline stage, correcting the error may be achieved by simply modifying the output of that preceding pipeline stage (in other words, postprocessing its output). Since the output of the preceding pipeline stage is the input of the first pipeline stage, the two cases are behaviorally equivalent and can both be considered as preprocessing the input of the first pipeline stage. In this case, although the logical flaw can also be corrected by having the instruction bypass unit completely bypass the first pipeline stage or its preceding pipeline stage, completely bypassing this pipeline stage will result in a significant performance degradation because the execution speed of the instruction bypass unit may be slower than the original pipeline stage. Therefore, instructions can still flow through the original pipeline stages, but by having the instruction bypass unit modify their inputs or outputs, high performance can be guaranteed while fixing the logic defects of the pipeline stages. This is equivalent to partially bypassing these pipeline stages. At this time, when the instruction bypass result is output to the original pipeline stage, this pipeline stage temporarily skips one instruction match, allowing the first pipeline stage on the pipeline to directly process the modified pipeline stage input.

[0130] For example, suppose there are four pipeline stages: fetch, A, B, and C. If the implementation of B has a logical flaw, to correct the input of B, pipeline stage B is added to the list of pipeline stages requiring bypass in the matching terms (i.e., the target pipeline stage list). The instruction bypass unit, upon receiving the input of pipeline stage B, corrects it and outputs it as the instruction bypass result to pipeline stage B. To correct the output of B, the next pipeline stage after B, namely pipeline stage C, is added to the list of pipeline stages requiring bypass in the matching terms. The instruction bypass unit, upon receiving the input of pipeline stage C (which is actually the output of pipeline stage B), corrects it and outputs it as the instruction bypass result to pipeline stage C. In summary, to repair the input of pipeline stage X, pipeline stage X is treated as the first pipeline stage, and after the bypass result is generated, the instruction bypass result is inserted into pipeline stage X (i.e., pipeline stage X is treated as the second pipeline stage); to repair the output of pipeline stage X, the next pipeline stage X+1 in the pipeline is treated as the first pipeline stage, and after the bypass result is generated, the instruction bypass result is inserted into pipeline stage X+1 (i.e., pipeline stage X+1 is treated as the second pipeline stage).

[0131] Optionally, a pipeline stage can be inserted before or after a given pipeline stage. For example, suppose there are four pipeline stages: fetch, A, B, and C, and pipeline stage X is implemented in the instruction bypass unit. To insert pipeline stage X between B and C, pipeline stage C is added to the list of pipeline stages to be bypassed in the matching field. After receiving the input of pipeline stage C (which is actually the output of pipeline stage B), the instruction bypass unit uses this input to execute pipeline stage X and outputs the result of pipeline stage X as the instruction bypass result to pipeline stage C. In summary, if pipeline stage X is to be inserted between pipeline stage Y and pipeline stage Y+1, then pipeline stage Y+1 becomes the first pipeline stage, and after the bypass result is generated, the instruction bypass result is inserted into pipeline stage Y+1 (i.e., pipeline stage Y+1 becomes the second pipeline stage).

[0132] To better explain the pipelined processing of multiple instructions, Table 5 is provided below. In Table 5, the second pipeline stage is the same as the first pipeline stage.

[0133] Table 5

[0134]

[0135] For example, as shown in Table 5, there are 5 instructions, each of which will flow through 5 pipeline stages sequentially. After instruction 3 completes pipeline stage 1, since it is determined that instruction 3 needs to be bypassed in pipeline stage 2 (the first pipeline stage), pipeline stage 2 is paused and instruction 3 is bypassed starting from clock cycle 5. Therefore, instructions 4 to 5 cannot enter pipeline stage 2 for execution. The bypassing process takes 3 clock cycles. At clock cycle 8, after instruction 3 has completed the bypassing process corresponding to the first pipeline stage, it continues to process instruction 1 through pipeline stage 2 (the second pipeline stage). Since the second pipeline stage is still the first pipeline stage, pipeline stage 2 must process instruction 3 first in clock cycle 8 (at this time, it does not pause to enter the bypass process, but is directly processed by pipeline stage 2). Pipeline stage 2 will only continue to process subsequent instructions after processing instruction 3, so instruction 4 will not start processing until clock cycle 9.

[0136] In this example, judging from the result, instruction 3 flows through the following stages in sequence: instruction fetch stage, pipeline stage 1, bypass corresponding to pipeline stage 2, pipeline stage 2, pipeline stage 3, and pipeline stage 4, which is equivalent to inserting bypass processing between pipeline stages 1 and 2; the remaining instructions flow through all 5 pipeline stages in sequence.

[0137] The insertion of bypass processing between pipeline stages 1 and 2 depends on the specific logic implemented in the bypass processing. For further examples, the effects include, but are not limited to, the following: inserting a new pipeline stage, skipping bypass processing, and modifying the output of pipeline stage 1 before inputting it into pipeline stage 2. The new pipeline stage is implemented within the bypass processing; skipping bypass processing may be due to the logic in the bypass processing comprehensively considering various conditions and ultimately deciding that the instruction does not need to undergo actual bypass processing; modifying the output of pipeline stage 1 before inputting it into pipeline stage 2 is equivalent to the bypass processing input being the output of pipeline stage 1 (the pipeline stage preceding the first pipeline stage), with the bypass processing logic modifying its output to become the bypass processing result, which is then input into pipeline stage 2 (the second pipeline stage).

[0138] Optionally, after returning the bypass processing result of the bypassed instruction to the second pipeline stage in the pipeline, the process further includes: if the second pipeline stage is the first or third pipeline stage, then instruction matching is not required for the first instruction information and the instruction information corresponding to the second pipeline stage. That is, after the bypass decision unit transmits the list of consecutive pipeline stages to be bypassed to the instruction bypass unit, the instruction bypass unit only processes the preceding consecutive pipeline stages and sends the bypass processing result of the preceding consecutive pipeline stages to the second pipeline stage. If the second pipeline stage is the first or third pipeline stage, it means that the instruction bypass unit considers that the pipeline stages following the second pipeline stage and located in the list of consecutive pipeline stages to be bypassed do not need to be bypassed. At this time, the second pipeline stage and the pipeline stages following the second pipeline stage in the set of consecutive pipeline stages to be bypassed each temporarily skip instruction matching once for this instruction. In other words, for a series of pipeline stages that need to be bypassed, if the instruction will flow through these stages again due to the resumption of normal execution, instruction matching for that instruction is temporarily skipped once at these pipeline stages. It should be noted that this is only a temporary, one-time skip of instruction matching. When the same instruction flows to these pipeline stages later, matching should still be performed to allow it to enter bypass processing according to the matching result. If the bypass processing result again indicates that the second pipeline stage is the first or third pipeline stage, then the processing described in this paragraph should be repeated.

[0139] Using the above method, the instruction matcher can be made into a PLD or an ASIC, and the instruction bypass unit can be made into a PLD. The combination of the instruction matcher and the instruction bypass unit can realize a pipelined instruction processing method, which can realize operations such as modifying, adding or deleting CPU behavior.

[0140] Based on the above instruction processing method, this application also proposes a method for correcting logic defects in ASICs using instruction bypass.

[0141] For side-channel attacks, since side-channel attacks always require measuring the side effects of hardware, the following instruction sequence is often repeatedly executed during the measurement phase of a side-channel attack: Step 1: Obtain and record the current clock; Step 2: Execute instructions that may be affected by the aforementioned side effects; Step 3: Obtain and record the current clock.

[0142] Steps 1 and 3 can be used to determine the time required to execute step 2. After this sequence of instructions is executed repeatedly, attackers can use statistical analysis to determine the time required for step 2 execution under different conditions. The resulting statistical characteristics can be used to leak sensitive information from the side channel. Taking the cached side channel used by both Meltdown and Spectre as an example, the aforementioned side effects affect the access latency of each element in the array. Therefore, it is always necessary to measure the access latency of each element in the array (corresponding to step 2 above), resulting in the following cyclical execution pattern: obtain and record the current clock; access a certain array element; obtain and record the current clock.

[0143] Optionally, mask matching can be used as the instruction matching method. The mask of the matching item should select the bit containing the opcode of the instruction used to obtain the current clock, and the corresponding target value is the opcode of the instruction used to obtain the current clock. If there are multiple opcodes, all opcodes are included in the mask and target value. If the instruction used to obtain or record the current clock is an instruction that needs to be bypassed, the target pipeline stage list in the matching item includes either the write-back pipeline stage or the clock access pipeline stage. The result of the bypass processing is input to the second pipeline stage in the pipeline, replacing the input of the second pipeline stage. The result of the bypass processing is clock information unrelated to the current clock or inaccurate clock information. In one possible implementation, for this instruction, its write-back stage (i.e., selecting the write-back stage as the first pipeline stage), that is, the pipeline stage for writing to the register, is bypassed. The instruction bypass unit adds randomness to the value to be written to the register, or directly modifies it to a meaningless value. The instruction bypass unit can write the new value to the register itself, in which case the bypass result can be inserted into the next stage after the write-back stage (i.e., the next pipeline stage in the pipeline after the write-back stage is selected as the second pipeline stage); or, the instruction bypass unit simply inserts the new value as the instruction bypass result into the write-back stage (i.e., the write-back stage is selected as the second pipeline stage), and the write-back stage completes the final register write. In another possible implementation, for this instruction, the pipeline stage used for accessing the clock is bypassed (i.e., the pipeline stage used for accessing the clock is selected as the first pipeline stage), and the instruction bypass unit uses a meaningless value as the bypass result to insert into the next pipeline stage (i.e., the pipeline stage after the pipeline stage used for accessing the clock is selected as the second pipeline stage).

[0144] Based on the above instruction processing method, this application also proposes an instruction processing method to prevent certain instructions from being executed. Instructions requiring bypass processing are those with errors in the CPU's hardware implementation that lead to unexpected instruction results. To prevent these instructions from being executed, there are two methods: ignoring them or triggering an exception. If the implementation method is to ignore them, the instruction bypass unit directly outputs an empty result upon receiving such an instruction. Preferably, the pipeline stage to be bypassed can be designated as the pipeline stage near the pipeline start to improve performance. More preferably, the second pipeline stage can be designated as the pipeline stage near the pipeline end to improve performance. If the implementation method is to trigger an exception, the instruction bypass unit directly completes the bypass by triggering an exception upon receiving such an instruction, and there is no restriction on the bypassed pipeline stage. That is, if the implementation method is to ignore them, the target pipeline stage list in the matching item includes pipeline stages located at the pipeline head, and the second pipeline stage is the pipeline stage located at the pipeline tail. If the implementation causes an exception, the target pipeline level parameter list in the matching item contains any pipeline level.

[0145] Figure 5 This is a schematic diagram of the structure of an instruction processing device 5000 provided in an embodiment of this application. Figure 5 As shown, it includes at least one processor 501 and a memory 502 connected to at least one processor 501. In this embodiment, the specific connection medium between the processor 501 and the memory 502 is not limited. Figure 5 Taking the connection between processor 501 and memory 502 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0146] In this embodiment of the application, the memory 502 stores instructions that can be executed by at least one processor 501. By executing the instructions stored in the memory 502, the at least one processor 501 can implement the steps of the above-described instruction processing method.

[0147] The processor 501 is the control center of the computer device, capable of connecting various parts of the computer device via various interfaces and lines. It performs resource configuration by running or executing instructions stored in the memory 502 and accessing data stored in the memory 502. Optionally, the processor 501 may include one or more processing units. The processor 501 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the processor 501. In some embodiments, the processor 501 and the memory 502 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0148] Processor 501 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0149] Memory 502, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 502 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. Memory 502 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, memory 502 can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0150] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0151] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0152] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0153] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0154] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An instruction processing method, characterized in that, A method for a pipelined CPU, where each pipeline includes multiple pipeline stages, each with different processing capabilities, includes: The system performs instruction matching based on first indication information representing the instruction and a mask and target value in any matching item, and performs instruction matching based on second indication information representing the first pipeline level and any pipeline level in the target pipeline level list in any matching item, to determine whether the instruction needs to be bypassed at the first pipeline level; the first pipeline level is the pipeline level to be entered in the pipeline that processes the instruction; the first indication information is at least one of the machine code of the instruction, the address of the instruction in memory, and the internal encoding of the instruction; the second indication information is indication information of the name of the first pipeline level; the target value is a binary value compared with the instruction; If the instruction requires bypass processing at the first pipeline level, then the first pipeline level is paused and the corresponding bypass processing at the first pipeline level is performed. After the bypass processing is completed, the instruction is processed again through the second pipeline stage in the pipeline and the first pipeline stage is restored.

2. The method according to claim 1, characterized in that, Based on the first indication information representing the instruction, instruction matching is performed with the mask and target value in any matching item; and based on the second indication information representing the first pipeline level, instruction matching is performed with any pipeline level in the target pipeline level list in any matching item, determining whether the instruction needs to be bypassed at the first pipeline level, including: For any matching item, determine whether the first indication information representing the instruction matches the mask and target value in the matching item; if the instruction matches, determine whether the first pipeline level represented by the second indication information is any pipeline level in the target pipeline level list in the matching item; if so, determine that the instruction needs to be bypassed at the first pipeline level; otherwise, determine that the instruction does not need to be bypassed at the first pipeline level.

3. The method according to claim 2, characterized in that, Before performing instruction matching based on the first indication information representing the instruction with the mask and target value in any matching item, and before performing instruction matching based on the second indication information representing the first pipeline level with any pipeline level in the target pipeline level list in any matching item, the method further includes: The first indication information is used to query the matching instruction cache to determine that the first indication information does not belong to the matching instruction cache; the matching instruction cache includes indication information of the representation instruction that can successfully match the mask and target value in any matching item, as well as the target pipeline level list of the corresponding matching item.

4. The method according to claim 1, characterized in that, Before performing instruction matching based on the first indication information representing the instruction with the mask and target value in any matching item, and before performing instruction matching based on the second indication information representing the first pipeline level with any pipeline level in the target pipeline level list in any matching item, the method further includes: The first pipeline level represented by the second indication information is determined to belong to the target pipeline level set, which is obtained by summarizing the target pipeline level list corresponding to each matching item.

5. The method according to any one of claims 1 to 4, characterized in that, The second pipeline stage is the first pipeline stage, or the next pipeline stage in the pipeline after the first pipeline stage, or any pipeline stage in the pipeline after the first pipeline stage.

6. The method according to any one of claims 1 to 4, characterized in that, The method is executed by an instruction matcher located in any pipeline stage; any pipeline stage is any pipeline stage other than the instruction fetch pipeline stage.

7. The method according to any one of claims 1 to 4, characterized in that, If the instruction requires bypass processing at the first pipeline stage, then the first pipeline stage is paused, including: If the instruction requires bypass processing in both the first pipeline stage and the third pipeline stage, then the first pipeline stage is paused and the instruction bypass unit is instructed to perform bypass processing on the instruction in both the first pipeline stage and the third pipeline stage; the third pipeline stage is N consecutive pipeline stages located after the first pipeline stage in the pipeline; N is greater than or equal to 1.

8. The method according to claim 7, characterized in that, The instructions are further processed through a second pipeline stage in the pipeline, including: If the second pipeline level is the first pipeline level or the third pipeline level, then no instruction matching is required for the first instruction information and the instruction information corresponding to the second pipeline level.

9. The method according to claim 2, characterized in that, If an instruction requiring bypass processing is used to acquire or record the current clock, then the target pipeline stage list in the matching item includes a write-back pipeline stage or a pipeline stage that accesses the clock. The result of the bypass processing is input to the second pipeline stage in the pipeline, replacing the data input of the second pipeline stage. The result of the bypass processing is clock information that is unrelated to the current clock or inaccurate clock information.

10. The method according to claim 2, characterized in that, The instruction requiring bypass processing has an error in the CPU's hardware implementation, which leads to an unexpected instruction result; the bypass processing result is empty, the target pipeline stage list in the matching item contains the pipeline stage located at the head of the pipeline, and the second pipeline stage is the pipeline stage located at the tail of the pipeline; or the bypass processing result triggers an exception, and the target pipeline stage list in the matching item contains any pipeline stage.

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