A device management system and server

Abstract

The application discloses a device management system and a server, relates to the technical field of servers, and comprises the following steps: moving a topology identification storage component for storing a storage slot signal source identification to a server mainboard end, reducing the occupation of mainboard connector pins by the information transmission, and establishing and storing the corresponding relationship between the arbitration component address and the cabinet silk screen area by a management control component. The adapter card does not need to be pre-bound and configured, and can automatically identify the cabinet silk screen area by the relationship when being inserted into any communication interface of the mainboard, and generate slot silk screen information in combination with the pre-stored signal source identification. The problems of occupying a large number of pins for identifying and configuring the adapter card hardware address signal through the connector transmission and the lack of flexibility of the adapter card needing to be bound and fixedly configured are solved, the technical effects of reducing pin occupation, realizing the flexible insertion and automatic identification of the adapter card silk screen, reducing the hardware development cost and meeting the requirement of the server for reserving more bus interfaces for the connector are achieved.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a device management system and server. Background Technology

[0002] With the acceleration of digitalization, the expansion capabilities of servers, as the core of data processing, are crucial. Riser cards (adapter cards) are installed through the motherboard's MCIO (Multi-pair Cable I / O) interface. In related technologies, each MCIO interface needs to reserve at least 7 dedicated pins to transmit CPU (Central Processing Unit) and VPP (Virtual PCIe Port, Peripheral Component Interconnect Express) address signals and other signal sources to the downstream Riser card's IO Expander (Input / Output Expander) chip. This allows the BMC (Baseboard Management Controller) / BIOS (Basic Input / Output System) to access the Riser card via I2C (Inter-Integrated Circuit Bus) to identify the CPU and PCIe interfaces corresponding to each SLOT on the Riser card, so as to generate the corresponding slot silkscreen for device positioning. However, the new generation of servers requires the MCIO interface to integrate more bus types. The existing design of the address signal occupying 7 pins results in a shortage of pin resources for the connector, which is insufficient to meet the needs of the new generation of servers that require the MCIO connector to reserve more types of bus interfaces.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a device management system and server to at least solve the problems of occupying a large number of pins due to the need to transmit adapter card hardware address signals for configuration identification through connectors, and the lack of flexibility due to the need to bind adapter cards to fixed configurations.

[0005] This application provides a device management system, including at least one arbitration component mounted on a server motherboard, a motherboard communication interface connected to the arbitration component, a management and control component, and a topology identifier storage component. The motherboard communication interface is detachably connected to an adapter card. The topology identifier storage component is configured to store signal source identifier information corresponding to the motherboard communication interface. The management and control component is configured to store the correspondence between the address of at least one arbitration component and the silkscreen area of ​​the server chassis. When the adapter card is connected to the motherboard communication interface, the corresponding chassis silkscreen area of ​​the adapter card is determined through the correspondence, and the slot silkscreen information of the adapter card slot is generated based on the chassis silkscreen area and the signal source identifier information.

[0006] This application also provides a server including a server motherboard, at least one adapter card, and a device management system as described above.

[0007] This application addresses the issue of relocating the topology identifier storage component for the storage slot signal source to the server motherboard, reducing the pin occupancy of motherboard connectors for this information transmission. Simultaneously, the management and control component establishes and stores the correspondence between the arbitration component address and the chassis silkscreen area. The adapter card requires no pre-binding configuration; it can be inserted into any communication interface on the motherboard to automatically identify its chassis silkscreen area through this relationship, generating slot silkscreen information in conjunction with the pre-stored signal source identifier. This solves the problems of related technologies where transmitting adapter card hardware address signals for configuration identification via connectors occupies a large number of pins, and the fixed configuration of the adapter card lacks flexibility. It achieves the technical effects of significantly reducing pin occupancy, enabling flexible adapter card insertion and automatic silkscreen identification, reducing hardware development costs, and meeting the requirements of next-generation servers for more reserved bus interfaces on connectors. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of a first type of equipment management system provided in an embodiment of this application.

[0010] Figure 2 This is a schematic diagram of the screen printing on the rear window of a chassis, provided as an embodiment of this application.

[0011] Figure 3 This is a schematic diagram of the structure of a second type of equipment management system provided in an embodiment of this application.

[0012] Figure 4This is a schematic diagram of the structure of a third device management system provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] Please refer to Figure 1 This application provides a device management system including at least one arbitration component 11 mounted on a server motherboard, a motherboard communication interface 12, a management control component 13, and a topology identifier storage component 14 connected to the arbitration component 11. The motherboard communication interface 12 is detachably connected to an adapter card. The topology identifier storage component 14 is configured to store signal source identifier information corresponding to the motherboard communication interface 12. The management control component 13 is configured to store the correspondence between the address of at least one arbitration component 11 and the silkscreen area of ​​the server chassis. When the adapter card is connected to the motherboard communication interface 12, the corresponding chassis silkscreen area of ​​the adapter card is determined through the correspondence, and the slot silkscreen information of the adapter card slot is generated based on the chassis silkscreen area and the signal source identifier information.

[0017] In this embodiment, the device management system includes an arbitration component 11, a motherboard communication interface 12, a management control component 13, and a topology identifier storage component 14, all mounted on a server motherboard. The first end of the arbitration component 11 is connected to the management control component 13, and the second end of the arbitration component 11 is connected to both the motherboard communication interface 12 and the topology identifier storage component 14. Alternatively, the device management system may include multiple arbitration components 11, multiple motherboard communication interfaces 12, and multiple topology identifier storage components 14, where each component can be in a one-to-one correspondence with the other.

[0018] The topology identifier storage component 14 is set on the communication link of the motherboard connector (including but not limited to the motherboard communication interface 12 in this embodiment). If the motherboard connector communicates via the I2C link, a topology identifier storage component 14 is independently configured on the I2C link of each motherboard connector. The topology identifier storage component 14 is configured to store the signal source identifier information corresponding to the slot on the adapter card. The signal source identifier information includes CPU_ADDR and VPP_ADDR corresponding to the motherboard communication interface 12.

[0019] As an optional embodiment, the topology identifier storage component 14 stores the CPU_ADDR and VPP_ADDR of the corresponding motherboard communication interface 12 through pull-up and pull-down resistors. For example, for the first motherboard communication interface 12, the topology identifier storage component 14 stores CPU0_ADDR+VPP1_ADDR, and for the second motherboard communication interface 12, the topology identifier storage component 14 stores CPU1_ADDR+VPP2_ADDR.

[0020] For scenarios where the adapter card connects to a single motherboard communication interface 12, when the management and control component 13 accesses the topology identifier storage component 14 of a certain motherboard communication interface 12, the read CPU / VPP address is automatically inherited to all slots under that motherboard communication interface 12. For example, if the Riser card has 3 slots (SLOT0-2) connected to the first motherboard communication interface 12, all slots of the Riser card can share CPU0_ADDR+VPP1_ADDR. For scenarios where the adapter card connects to multiple motherboard communication interfaces 12, the topology identifier storage component 14 on the I2C link of each motherboard communication interface 12 stores the independent CPU_ADDR and VPP_ADDR of each motherboard communication interface 12. The management and control component 13 reads the CPU_ADDR and VPP_ADDR corresponding to each motherboard communication interface 12 and allocates them according to the physical connection of the slots.

[0021] It is understood that this embodiment eliminates 7 dedicated address signal pins and stores CPU_ADDR / VPP_ADDR in the motherboard-side topology identifier storage component 14 (such as IO Expander). The signal source identifier is transmitted via the I2C bus. The freed MCIO pin resources can be used to integrate new bus protocols, including but not limited to USB4 (Universal Serial Bus Generation 4) / CXL (Compute Express Link), to meet the expansion needs of next-generation servers. The adapter card does not require pre-binding to a fixed configuration. When inserted into a single motherboard communication interface 12, the slot automatically inherits the global address of that interface (e.g., the first motherboard communication interface 12 → all slots share CPU0_ADDR+VPP1_ADDR). When inserted into multiple motherboard communication interfaces 12, the management and control component 13 assigns independent addresses according to the physical connection, achieving plug-and-play silkscreen self-adaptation. This solves the silkscreen mismatch problem caused by adapter card position binding in traditional solutions, eliminates the MCU chip and decoding circuit, and reduces hardware costs.

[0022] The topology identifier storage component 14 can be implemented through an IO Expander chip, and the motherboard communication interface 12 can be selected from the MCIO interface. The selection can be made according to actual needs, and no specific limitation is made here.

[0023] In this embodiment, a pre-configured correspondence between the addresses of each arbitration component 11 on the server motherboard and the silkscreen area of ​​the chassis is stored in the storage medium of the management and control component 13. The management and control component 13 accesses the address of the arbitration component 11 and determines the corresponding chassis silkscreen area of ​​the adapter card connected to the server motherboard based on the address of the arbitration component 11. This correspondence can be between the address of the arbitration component 11 and the label of the chassis silkscreen area, or it can be a correspondence between the address of the arbitration component 11, the chassis silkscreen area, and the front and rear windows of the chassis. Figure 2 As shown, Figure 2This embodiment of the application provides a schematic diagram of the rear window silkscreen of a chassis. Exemplarily, the first chassis silkscreen area labeled LOC PIN0 includes PC0, PC1, and PC2, and the second chassis silkscreen area labeled LOC PIN1 includes PC3, PC4, and PC5. Taking an arbitration component 11 as an example, the management control component 13 accesses the address of the arbitration component 11 and, based on a preset correspondence, determines that the chassis silkscreen area labeled LOC PIN0 corresponds to that address. Therefore, the chassis silkscreen area corresponding to the adapter card includes PC0, PC1, and PC2. In this embodiment, the adapter card does not need to know which physical interface it is inserted into. The management control component 13 automatically derives its corresponding LOC_PIN (e.g., 0x70 → LOC0) from the address of the arbitration chip, and then maps the LOC_PIN to a fixed chassis silkscreen area, improving versatility.

[0024] In this embodiment, the adapter card includes at least one slot. The management and control component 13 can generate slot silkscreen information for each slot on the adapter card based on the CPU_ADDR / VPP_ADDR obtained from the topology identifier storage component 14 and the determined chassis silkscreen area. The information is CPU ID_PE PORT_Front and Rear Windows_Chassis Slot Silkscreen. CPU_ID is determined based on CPU_ADDR, PEPORT is determined based on VPP_ADDR, and the front and rear windows and chassis slot silkscreen are determined based on a preset relationship and the chassis silkscreen area. For example, the slot silkscreen information for a certain slot can be CPU0_PORT1_Rear Window_PC2, so as to locate the device later.

[0025] As an optional embodiment, the management control component 13 can be built from the BMC and CPU on the server motherboard.

[0026] As can be seen, in this embodiment, by moving the topology identifier storage component 14 for storing the slot signal source identifier to the server motherboard, the occupation of motherboard connector pins for this information transmission is reduced. Simultaneously, the management control component 13 establishes and stores the correspondence between the address of the arbitration component 11 and the chassis silkscreen area. The adapter card does not require pre-binding configuration; it can be inserted into any communication interface on the motherboard to automatically identify the chassis silkscreen area through this relationship, and generate slot silkscreen information by combining the pre-stored signal source identifier. This solves the problems in related technologies where a large number of pins are occupied due to the need to transmit adapter card hardware address signals for configuration identification through the connector, and the lack of flexibility due to the need for fixed configuration binding of the adapter card. It achieves the technical effects of significantly reducing pin occupation, enabling flexible insertion of the adapter card and automatic silkscreen identification, reducing hardware development costs, and meeting the technical requirements of next-generation servers for reserving more bus interfaces on the connector.

[0027] Based on the above embodiments, please refer to Figure 3The device management system also includes: an information recording component 21 located on the adapter card, configured to store the physical position offset information of the adapter card's slot; and a management control component 13 specifically configured to store the correspondence between the address of at least one arbitration component 11 and the silkscreen area of ​​the server chassis. When the adapter card is connected to the motherboard communication interface 12, the corresponding chassis silkscreen area of ​​the adapter card is determined through the correspondence, the chassis silkscreen information corresponding to the slot in the chassis silkscreen area is determined based on the physical position offset information, and the slot silkscreen information of the slot is generated based on the chassis silkscreen information corresponding to the slot and the signal source identification information.

[0028] In this embodiment, the adapter card is further provided with at least one information recording component 21. The information recording component 21 stores the physical position offset information (SLOT LOC offset information) of the slots of the adapter card. The physical position offset information of the slots is used to determine the positional relationship of each slot on the adapter card. For example, assuming that the adapter card includes three slots, namely the first slot, the second slot and the third slot, the physical position offset information can determine that the first slot, the second slot and the third slot are arranged in the order from bottom to top on the adapter card. The management and control component 13 can determine the binding relationship between each slot and each chassis silkscreen in the chassis silkscreen area according to the positional relationship of the first slot, the second slot and the third slot on the adapter card. Assuming that the chassis silkscreen area corresponding to the adapter card is LOC If PIN0 is used, then the first slot on the adapter card is bound to PC0, the second slot to PC1, and the third slot to PC2. Assuming the silkscreen area on the chassis corresponding to the adapter card is LOCPIN1, then the first slot on the adapter card is bound to PC3, the second slot to PC4, and the third slot to PC5. In this embodiment, the information recording component 21 can be built using an FRU (Field Replaceable Unit) chip.

[0029] It is understandable that automatically binding the chassis silkscreen area (PC0→PC1→PC2) based on physical position offset information (such as from bottom to top, first slot → second slot → third slot) improves positioning accuracy. Compared to related technologies that use position DIP switches and programmable chips in adapter cards, this method only requires an FRU chip to store static offset values, resulting in lower costs. It can store the binding relationship between each slot and the chassis silkscreen, thereby improving the efficiency and accuracy of subsequent generation of slot silkscreen information.

[0030] In one exemplary embodiment, there are multiple information recording components 21 and multiple motherboard communication interfaces 12, with multiple motherboard communication interfaces 12 corresponding to multiple information recording components 21; the information recording components 21 are also configured to store unique identification information of the adapter card; the management and control component 13 is also configured to determine that multiple motherboard communication interfaces 12 are connected to the same adapter card when the unique identification information stored in the information recording components 21 connected to multiple motherboard communication interfaces 12 is the same.

[0031] In this embodiment, the information recording component 21 is also configured with independent identification information of the adapter card it belongs to, such as the PN (Part Number) code of the adapter card. The management and control component 13 accesses the adapter card and reads the PN number in the FRU chip. When the management and control component 13 detects that the FRU chips under different I2C links all record the PN code of the same adapter card, it determines that the motherboard connectors corresponding to these I2C links are all connected to the same adapter card. Then, it binds the slot of the adapter card to the chassis silkscreen through the SLOT LOC offset information in the FRU. If the PN codes of any link are different, it is determined that there are multiple independent adapter cards. Compared with the related technology that requires additional pins to identify the subordinate relationship of multiple interfaces, this embodiment realizes logical association by reading the PN code, further saving the pin resources of the motherboard connector.

[0032] In one exemplary embodiment, reference is made to Figure 4 The device management system also includes: an on-premises information storage component 22 located on the adapter card, configured to store the on-premises signals of the devices in the adapter card slot; and a management control component 13 configured to access the on-premises information storage component 22 and determine the number of on-premises devices based on the on-premises signals.

[0033] In this embodiment, the adapter card is also provided with an in-situ information storage component 22. The in-situ information storage component 22 can also be built through an IO Expander. The device in-situ signal is written into the slot. The management and control component 13 reads the device in-situ signal in the IO Expander to confirm how many PCIe devices are in-situ under the current configuration, so that the management and control component 13 can perform subsequent management, including but not limited to dynamically activating valid slots and allocating resources.

[0034] In one exemplary embodiment, reference is made to Figure 4The device management system includes multiple information recording components 21 and multiple motherboard communication interfaces 12, with each motherboard communication interface 12 corresponding to a different information recording component 21. The system also includes a switching component 23, with its first end connected to a first motherboard communication interface and its second end connected to both an in-situ information storage component 22 and a first information recording component. At least one second information recording component is connected to at least one second motherboard communication interface. The second information recording component is any information recording component 21 other than the first information recording component, and the second motherboard communication interface is any motherboard communication interface 12 other than the first motherboard communication interface.

[0035] In this embodiment, the adapter card also includes a switching component 23. The first end of the switching component 23 is connected to the first motherboard communication interface on the server motherboard via a cable. The switching component 23 includes multiple second ends, namely S0, S1, S2, and S3. S0 is connected to the pull-up resistor, the first information recording component, the sensor, and the in-situ information storage component 22, respectively. S1 is connected to the pull-up resistor and the first slot, S2 is connected to the pull-up resistor and the second slot, and S3 is connected to the pull-up resistor and the third slot. The multiple second information recording components on the adapter card are connected one-to-one with the multiple second motherboard communication interfaces on the adapter card, improving the efficiency of the management and control component 13 in determining whether each MCIO interface is connected to the same adapter card.

[0036] Pull-up resistors ensure signal stability and correct level accuracy. Simultaneously, they allow for the rational allocation of slot resources based on actual equipment needs, enabling independent device connection to each slot without mutual interference. Switching component 23's S0 pin connects both the first information recording component and the presence information storage component 22, allowing for timely recording and storage of presence information. When a device is inserted into a slot, the presence information storage component 22 quickly responds and stores the device's presence status, while the first information recording component records this process, providing data support for subsequent equipment management and troubleshooting.

[0037] In one exemplary embodiment, the device management system further includes: a switching component configured to set the current control path of the management control component 13 according to the type of the downlink device connected to the motherboard communication interface 12, the control path including a first control path corresponding to host control and a second control path corresponding to virtual control. (Refer to...) Figure 4The switching components include: a controller 15 configured to generate control signals based on the type of downlink device connected to the motherboard communication interface 12; and a multiplexer 16, with a first end connected to the host control pin of the management control component 13, a second end connected to the virtual control pin of the management control component 13, and a third end connected to the arbitration component 11. The multiplexer 16 is configured to respond to the control signals by connecting the first end to the third end or connecting the second end to the third end.

[0038] In this embodiment, the management control component 13 includes a processor (CPU) and a management device (BMC). The CPU has a host control pin (HOST SMBUS I2C), which is connected to a first switching chip via a bus repeater (I2C Repeater). The CPU also has a virtual control pin (VPP I2C), which is connected to a second switching chip via a bus repeater. The S0 pin of the first switching chip is connected to the first terminal of a multiplexer 16, and the S0 pin of the second switching chip is connected to the second terminal of the multiplexer 16. The third terminal of the multiplexer 16 is connected to the second pin (M1) of the arbitration component 11. The host control pin (HOST SMBUS I2C) of the BMC is connected to the first pin (M0) of the arbitration component 11. The third pin (S) of the arbitration component 11 serves as the second terminal of the arbitration component 11 and is connected to the motherboard communication interface 12 and the topology identifier storage component 14, thus connecting the CPU VPP I2C, CPU HOST SMBUS I2C, and BMC. After I2C is integrated through logic chips, each MCIO connector can transmit all three types of I2C signals through one I2C link. This allows each MCIO connector to carry all control signals with only one set of pins (2 pins), reducing pin usage and freeing up space to integrate the new USB4 / CXL bus.

[0039] Specifically, the VPP I2C and CPU I2C first extend the I2C link to each MCIO through the I2C SWITCH chip, and then switch between the two I2C paths through the I2C MUX chip (multiplexer 16). The I2C MUX chip can expand one I2C bus into multiple independent bus segments, realizing the HOST switching function of the MCIO connector downlink board under different conditions. The I2C MUX chip is controlled by the CPLD for channel selection. The downlink board type is determined by the presence signal of the Riser card. When the downlink board is a Riser card, the HOST is switched to CPU HOST SMBUS I2C; when the downlink board is a backplane, the HOST is switched to VPP I2C. The two situations do not interfere with each other. Among them, the first switching chip and the second switching chip are both I2C SWITCH chips.

[0040] In an exemplary embodiment, the management control component 13 includes: a processor and a management device; the arbitration component 11 is configured to arbitrate a first signal output by the processor and a second signal output by the management device, and transmit a successful arbitration signal to a motherboard communication interface 12 connected to itself.

[0041] In this embodiment, considering that the management control component 13 includes a processor CPU and a management device BMC, the I2C signal of the I2C MUX chip (multiplexer 16) and the I2C signal of the BMC are logically judged by the I2C arbitration chip (arbitration component 11). The function of the I2C arbitration chip is to resolve the conflict problem of the I2C bus in the communication scenario between the CPU and the BMC, and ensure the normal operation of communication.

[0042] In one exemplary embodiment, the device management system further includes a display component configured to display slot silkscreen information corresponding to the device installed in the slot.

[0043] In this embodiment, the BMC in the management and control component 13 binds all the above information with the corresponding slots and displays the CPU ID_PE PORT_front and rear windows_chassis slot silkscreen of each PCIe device on the BMC WEB management interface.

[0044] In summary, the first aspect of this application is its ability to automatically identify silkscreen configurations and optimize commonly used server hardware circuits. The Riser card does not need to be bound to a fixed configuration; it can automatically recognize the silkscreen scheme under the current configuration regardless of which interface it is plugged into on the motherboard. The second aspect of this application reduces development costs. Compared to hardware links using MCU chips, the IO Expander chip of the Riser card in this application is moved to the motherboard, requiring only the addition of an FRU chip on the Riser card, resulting in lower costs. The third aspect of this application reduces maintenance costs. Since the entire system does not increase the number of main control chips, there is no need to maintain the main control chip's firmware, leading to stronger hardware circuit reliability. Furthermore, the number of connector types on the board is reduced, and all wiring requirements can be met using standard cables, making maintenance easier for hardware engineers.

[0045] Embodiments of this application also provide a server, including a server motherboard, at least one adapter card, and a device management system as described in any of the embodiments above.

[0046] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0047] The above provides a detailed description of the device management system and server provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A device management system, characterized by comprising: The device management system comprises at least one arbitration component arranged on a server mainboard, a mainboard communication interface connected with the arbitration component, a management control component, and a topology identification storage component, wherein the mainboard communication interface is detachably connected with a switching card; The topology identification storage component is arranged on a communication link of the mainboard communication interface on the server mainboard and is configured to store signal source identification information corresponding to the mainboard communication interface; The management control component is configured to store a corresponding relationship between an address of the at least one arbitration component and a server case silk screen area, to determine a case silk screen area corresponding to the switching card through the corresponding relationship when the switching card is connected with the mainboard communication interface, and to generate slot silk screen information of a slot of the switching card based on the case silk screen area and the signal source identification information; The device management system further comprises: An information recording component arranged on the switching card and configured to store physical position offset information of the slot of the switching card; The physical position offset information is used to determine a positional relationship of each slot on the switching card; The management control component is specifically configured to store a corresponding relationship between an address of the at least one arbitration component and a server case silk screen area, to determine a case silk screen area corresponding to the switching card through the corresponding relationship when the switching card is connected with the mainboard communication interface, to determine a binding relationship between each slot and corresponding case silk screen information in the case silk screen area based on the positional relationship, to determine case silk screen information corresponding to the slot by using the binding relationship, and to generate slot silk screen information of the slot based on the case silk screen information corresponding to the slot and the signal source identification information.

2. The device management system according to claim 1, characterized by The number of the information recording components is multiple, the number of the mainboard communication interfaces is multiple, and the multiple mainboard communication interfaces and the multiple information recording components correspond to each other; The information recording component is further configured to store unique identification information of the switching card; The management control component is further configured to determine that the multiple mainboard communication interfaces are connected with the same switching card when the unique identification information stored in the information recording components connected under the multiple mainboard communication interfaces is the same.

3. The device management system of claim 1, wherein The device management system further comprises: An in-place information storage component arranged on the switching card and configured to store device in-place signals of the slots of the switching card; The management control component is further configured to access the in-place information storage component and determine a number of in-place devices according to the device in-place signals.

4. The device management system according to claim 3, characterized by The number of the information recording components is multiple, the number of the mainboard communication interfaces is multiple, and the multiple mainboard communication interfaces and the multiple information recording components correspond to each other; The device management system further comprises: A switching component, wherein a first end of the switching component is connected with a first mainboard communication interface, and a second end of the switching component is connected with the in-place information storage component and a first information recording component respectively; At least one second information recording component is connected with at least one second mainboard communication interface correspondingly. The second information recording component is one of the information recording components other than the first information recording component, and the second mainboard communication interface is one of the mainboard communication interfaces other than the first mainboard communication interface.

5. The device management system of claim 1, wherein The device management system further comprises: The switching component is configured to set a current control path of the management control component according to a type of the downstream device connected to the mainboard communication interface, the control path comprising a first control path corresponding to a host control and a second control path corresponding to a virtual control.

6. The device management system of claim 5, wherein, The switching component comprises: A controller configured to generate a control signal according to the type of the downstream device connected to the mainboard communication interface; A multiplexer, a first end of which is connected to a host control pin of the management control component, a second end of which is connected to a virtual control pin of the management control component, and a third end of which is connected to the arbitration component, the multiplexer being configured to, in response to the control signal, connect the first end to the third end or connect the second end to the third end.

7. The device management system of claim 1, wherein The management control component comprises a processor and a management device. The arbitration component is configured to arbitrate a first signal output by the processor and a second signal output by the management device, and transmit the signal that wins the arbitration to the mainboard communication interface connected to the arbitration component.

8. The device management system according to any one of claims 1 to 7, characterized by, The device management system further comprises: A display component configured to display slot silk screen information corresponding to the device installed in the slot.

9. A server, characterized by The device management system comprises a server mainboard, at least one adapter card, and the device management system according to any one of claims 1-8.

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