Data processing method, device, equipment, storage medium and product

Abstract

The present application discloses a data processing method, apparatus, device, storage medium and product, which is applied to integrated circuit electronic design automation software, including: obtaining a digital circuit design file; parsing the digital circuit design file to generate a corresponding netlist data structure; in response to an object query request issued by a user, accessing the netlist data structure, and searching the netlist data structure for data items that match the target query object specified by the user; generating an object query result based on the data items that match the target query object specified by the user found in the netlist data structure. The present application uses the netlist data structure as the basis for data processing to perform object query, without the need for hierarchical recursive traversal and without the need to process branch relationships between multi-branch tree nodes, thereby significantly improving query efficiency.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit design technology, and in particular relates to a data processing method, device, equipment, storage medium and product. Background Art

[0002] Integrated circuit (IC) electronic design automation (EDA) software is an essential tool in the integrated circuit (IC) design process, widely used in every stage from system-level modeling, logic synthesis, layout and routing, to physical verification. Using EDA tools, designers can efficiently complete the design, simulation, verification, and implementation of digital circuits. Common IC EDA software currently on the market includes EnFortius, Protel, and OrCAD.

[0003] Digital chip design files are widely used in integrated circuit electronic design automation software and digital integrated circuit design. Verilog Hardware Description Language (Verilog HDL) is used in digital chip design files to describe the function, structure, and interconnection relationship of the circuit. The extension of digital chip design files is generally .v. They follow the Verilog syntax rules. Digital circuit design files record the structural composition, logical behavior, and interconnection relationship between the circuit modules in the form of Verilog code.

[0004] After reading a digital circuit design file, the integrated circuit electronic design automation software usually needs to parse the Verilog code in the digital circuit design file to convert it into a data structure that can be processed by a computer.

[0005] In the related prior art, integrated circuit electronic design automation software typically parses the aforementioned digital chip design files to generate a hierarchical tree to effectively manage and analyze structured information in the chip design, such as modules, ports, signals, and hierarchical relationships. After parsing the aforementioned digital circuit design files to generate the hierarchical tree structure, the integrated circuit electronic design automation software performs subsequent data processing and query operations based on the parsed hierarchical tree. For example, starting from the root node of the hierarchical tree, the software traverses the entire tree structure using a depth-first search (DFS) algorithm to locate specific circuit component objects.

[0006] However, since the relevant existing technologies need to rely on hierarchical multi-branch trees for data processing operations such as traversal queries, when it is necessary to query all modules corresponding to a target circuit device, it is usually necessary to perform tree traversal, such as depth-first traversal layer by layer starting from the root node. The entire query process requires accessing a large number of intermediate nodes to finally obtain the query results, which leads to problems such as long traversal paths, low query efficiency, and high consumption of computing resources.

[0007] Especially with the expansion of circuit scale, the complexity of circuit design and the number of nodes have increased dramatically. In the current large-scale integrated circuit (VLSI) design, the actual design file may contain up to millions of circuit devices, causing the search process to become more and more time-consuming, which directly affects the overall performance and running speed of integrated circuit electronic design automation software. It has now become one of the key bottlenecks restricting the performance of integrated circuit electronic design automation software.

[0008] Therefore, there is an urgent need for a more efficient query method to reduce unnecessary traversal operations, improve query efficiency and the running speed of EDA tools, so as to better meet the needs of large-scale integrated circuit design. Summary of the Invention

[0009] The embodiments of the present application provide a data processing method, apparatus, equipment, storage medium and product, which aim to solve the problem of low data processing query efficiency in the above-mentioned related technologies such as the integrated circuit electronic design automation software relying on hierarchical multi-branch trees for traversal queries, and provide a more efficient data processing solution.

[0010] In one aspect, an embodiment of the present application provides a data processing method, the method comprising:

[0011] Obtain digital circuit design files;

[0012] Parsing the digital circuit design file to generate a corresponding netlist data structure;

[0013] In response to an object query request issued by a user, accessing the netlist data structure and searching the netlist data structure for a data item that matches a target query object specified by the user;

[0014] An object query result is generated based on the data items found in the netlist data structure that match the target query object specified by the user.

[0015] On the other hand, an embodiment of the present application provides a data processing device, which may include:

[0016] An acquisition module, used for acquiring digital circuit design files;

[0017] A parsing module, configured to parse the digital circuit design file and generate a corresponding netlist data structure;

[0018] a search module, configured to access the netlist data structure in response to an object query request issued by a user, and search the netlist data structure for a data item that matches a target query object specified by the user;

[0019] A generating module is used to generate an object query result based on the data items found in the netlist data structure and matching the target query object specified by the user.

[0020] In another aspect, an embodiment of the present application provides a data processing device, comprising:

[0021] a processor and a memory storing computer program instructions;

[0022] When the processor executes the computer program instructions, the steps of the data processing method in the above aspects are implemented.

[0023] On the other hand, an embodiment of the present application provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the steps of the data processing method in the above aspect are implemented.

[0024] On the other hand, an embodiment of the present application provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the data processing method in the above aspect are implemented.

[0025] Compared with the object query method based on hierarchical multi-tree structure in the prior art, the present invention adopts netlist data structure as the query basis of integrated circuit electronic design automation software. Since the netlist data structure records the circuit hardware structure and its connection relationship in text format instead of adopting hierarchical multi-tree form, during the object query process, there is no need to rely on hierarchical traversal algorithms such as depth-first or breadth-first to access nodes step by level like traditional EDA tools. Instead, efficient search can be achieved directly through linear traversal of string matching of the text stored in the netlist data structure, eliminating the recursive traversal and branch judgment process, thereby significantly improving the query efficiency. Especially when dealing with large-scale circuit design, the efficiency improvement effect is particularly significant. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1It is a schematic diagram of a hierarchical multi-branch tree used in a related prior art data processing method;

[0028] Figure 2 This is a flow chart of a data processing method provided by one embodiment of the present application;

[0029] Figure 3 is a schematic diagram of a netlist data structure mapping container provided by one embodiment of the present application;

[0030] Figure 4 is a structural diagram of a data processing device provided by another embodiment of the present application;

[0031] Figure 5 It is a structural diagram of a data processing device provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0032] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0033] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0034] Verilog Hardware Description Language (Verilog HDL) is widely used in integrated circuit electronic design automation software and digital integrated circuit design to describe circuit functions, structures, and interconnections. Designers typically write digital chip design files in Verilog, typically with a .v file extension and following Verilog syntax. Digital circuit design files use Verilog code to record the circuit's structural composition, logical behavior, and interconnections between modules.

[0035] To improve design efficiency and maintainability, modern digital circuit design generally adopts a hierarchical design approach, dividing complex digital circuit designs into multiple modules with clear functions. A complete circuit system is constructed through the calling relationship between modules. Each module has clearly defined input and output ports for signal interaction with other modules. The top module, as the highest level of the entire system, is responsible for integrating the instances of all sub-modules and defining the primary input and output through its ports.

[0036] Accordingly, hierarchical names are used for description in hierarchical designs. A hierarchical name uniquely identifies an object (such as a signal, register, or unit) within a specific module instance. According to the IEEE Unified Power Format (IEEE 1801-2018, or UPF 3.0), a hierarchical name typically consists of multiple parts: the initial part is the scope of the module (Scope-relative HierarchicalName), followed by the names of the module instances at each level (Instance Name), and finally points to the specific object (ObjectName). For example, t2 / c2 indicates that a module instance named c2 is called within the scope of the top-level module t2.

[0037] In the related existing technology, integrated circuit electronic design automation software usually first parses the above-mentioned digital chip design file to generate a hierarchical multi-branch tree. After parsing the above-mentioned digital circuit design file to generate a hierarchical multi-branch tree structure, the integrated circuit electronic design automation software performs subsequent data processing and query operations based on the hierarchical multi-branch tree generated by the parsing. For example, starting from the root node of the hierarchical multi-branch tree, the entire tree structure is traversed through the depth-first search (DFS) algorithm to locate a specific circuit component object.

[0038] like Figure 1 As shown, the integrated circuit electronic design automation software uses a parser to parse the digital circuit design file to generate a hierarchical multi-branch tree, where each node corresponds to a digital circuit design object in the design, such as a module, instance, port, etc. The lines between the nodes in the hierarchical multi-branch tree represent the connection or derivation relationship between the objects. For example, in Figure 1 In the hierarchical multi-branch tree shown, TOP is the root node, representing the top-level module; A, B, and C are its next-level child nodes, respectively representing instances of the corresponding names in the top-level module; further, D and E are child nodes of the A node, while F and G appear as child nodes of the B node, H is the child node of the C node, I is the child node of the D node, and J is the child node of the E node, thus forming a complete hierarchical structure.

[0039] In the related prior art, after receiving the object query instruction (such as find_object I) input by the user, the integrated circuit electronic design automation software first determines the target query object identifier I to be queried from the object query instruction, and then needs to use the root node (such as TOP) of the hierarchical multi-branch tree as the starting point to perform a depth-first traversal to find all nodes containing the name I. Finally, after identifying the target node, it searches upward to the parent node to determine the location information of the object in the entire design hierarchy, and then traces back layer by layer to generate a complete hierarchical path name, such as A / D / I, and returns the generated complete hierarchical path name to the user as the query result.

[0040] However, since the integrated circuit electronic design automation software in the relevant existing technology needs to rely on hierarchical multi-branch trees for data processing operations such as traversal queries, for example, when it is necessary to query all modules corresponding to a target circuit device, it is usually necessary to start from the root node and use the depth-first traversal method to traverse downward layer by layer. The entire query process requires accessing a large number of intermediate nodes to finally obtain the query results, which leads to problems such as long traversal paths, low query efficiency, and high consumption of computing resources.

[0041] In order to solve the above problems existing in the related art, this embodiment provides a data processing method, device, equipment, storage medium and product. The data processing method provided by the embodiment of the present application is first introduced below.

[0042] Figure 2 The following is a flow chart of a data processing method provided by an embodiment of the present application. The data processing method of this embodiment is applied to integrated circuit electronic design automation software, and the method may include the following steps:

[0043] S110, obtaining a digital circuit design file;

[0044] S120, parsing the digital circuit design file to generate a corresponding netlist data structure;

[0045] S130 , in response to an object query request issued by a user, accessing the netlist data structure, and searching the netlist data structure for a data item that matches a target query object specified by the user;

[0046] S140 , generating an object query result based on the data items found in the netlist data structure and matching the target query object specified by the user.

[0047] In this embodiment, the integrated circuit electronic design automation software uses a netlist data structure as the data basis for traversal queries. Since the netlist data structure describes the circuit hardware structure and its connection relationships in the digital circuit design file in a non-multitree form, when performing object queries, the object query process does not rely on traditional multitree traversal methods (such as DFS / BFS), but is implemented by linear traversal of the text content stored in the netlist data structure through string matching. The method of the present invention does not require layer-by-layer recursive traversal or processing of node branch relationships, which significantly improves the efficiency of object queries. In particular, the efficiency improvement effect is particularly significant when processing large-scale circuit designs.

[0048] The specific implementation methods of the above steps are introduced below.

[0049] In S110, a digital circuit design file is obtained. The digital circuit design file contains a description of the circuit structure, connections, and circuit behavior. The digital circuit design file follows the syntax of a hardware description language and is described in Verilog code. The file extension of the digital circuit design file is .v. Specifically, the circuit structure and connections described in the digital circuit design file include modules, ports, nets, and instances. The circuit behavior described in the digital circuit design file includes sequential logic and combinational logic. Because the digital circuit design file is described in Verilog code, it is also referred to as a Verilog file.

[0050] As an example, the Verilog code used in a digital circuit design file to describe the structure, behavior, and connection relationship of a digital circuit is as follows:

[0051] module top(CLK, RST, D, Q);

[0052] input CLK, RST;

[0053] input [3:0] D;

[0054] output [3:0] Q;

[0055] reg [3:0] Q;

[0056] always @(posedge CLK or posedge RST)

[0057] begin

[0058] if(RST) Q <= 0; / / reset logic

[0059] else Q <= Q + D; / / accumulate logic

[0060] end

[0061] endmodule

[0062] The example digital circuit design file above describes a hierarchical digital circuit design using Verilog, including module definitions, signal declarations, and logic implementation. This example digital circuit design file defines a module called "top," which contains input ports CLK, RST, and D, and an output port Q. D is a 4-bit input, and Q is a 4-bit output. The internal signal Q is declared as a register type to store the accumulated result. Module "top" implements sequential logic using an "always" block, triggered by the rising edge of CLK or RST. The block contains an if-else conditional statement: If RST is high, Q is set to 0 to reset the module; otherwise, Q is added to D and updated to accumulate the result.

[0063] As a preferred embodiment, the circuit structure described in the digital circuit design file includes module definition, wire net definition or instance definition. Among them, module definition is used to organize circuit functions. Typical modules include top-level modules and submodules. The definition of each module uses the module keyword to declare the module name and its port list, and uses the endmodule keyword to mark the end of the module to clearly divide the functional boundaries and hierarchical structure of the module. The module definition also includes port declaration and internal signal declaration. Among them, the port includes input port, which uses input declaration, output port uses output declaration, and bidirectional port uses inout declaration. In addition, in some other embodiments, according to the needs of the design project, the circuit structure described in the digital circuit design file also includes wire net definition or instance definition. Among them, wire net definition is usually declared as net or wire to represent the signal connection between modules or within modules. Instance definition ensures the correct transmission of signals by describing port mapping and wire net connection.

[0064] As a preferred embodiment, the circuit behavior described in the digital circuit design file includes sequential logic and combinational logic. Specifically, sequential logic behavior is driven by a periodic clock signal, and its output result is determined by the current input signal and the state information stored in the circuit. Common descriptions of sequential logic behavior in digital circuit design files include triggers, registers, state machines, etc. The output of combinational logic behavior is based only on the current input, and a specific function is achieved through a combination of logic. Common descriptions of combinational logic behavior in digital circuit design files include, for example, logic gates, multiplexers, adders, etc. It should be noted that digital circuit design files include not only hardware descriptions such as circuit structure and connection relationships, but also logical descriptions such as circuit behavior.

[0065] As a preferred embodiment, the step of obtaining a digital circuit design file specifically includes: loading the digital circuit design file through a design file loading command in the integrated circuit electronic design automation software operating environment. The design file loading command includes but is not limited to a read_file or read_design command, and the design file loading command includes a parameter for specifying the path or file name of the digital circuit design file, which is used to guide the integrated circuit electronic design automation software to locate and load the corresponding digital circuit design file. For example, a user can use the command read_design top.v to load a Verilog file named top.v. The design file loading command read_design is a standardized operating interface provided by the integrated circuit electronic design automation software for receiving and loading digital circuit design files that describe circuit structure and behavior. The file format of the digital circuit design file includes but is not limited to Verilog, VHDL or SystemVerilog format.

[0066] It is understandable that in some other embodiments, after successfully loading the digital circuit design file, the following steps may also be included: the integrated circuit electronic design automation software performs syntax parsing and semantic analysis on the digital circuit design file to identify the circuit elements and their connection relationships defined in the digital circuit design file, which will not be repeated here.

[0067] In S120 , the digital circuit design file is parsed to generate a corresponding netlist data structure. Specifically, the steps include: using a Verific parser to parse the digital circuit design file to generate a netlist data structure.

[0068] Specifically, the Verific parser is a software tool developed by Verific Design Automation for parsing Hardware Description Language (HDL) and Unified Power Format (UPF). It supports data processing by Electronic Design Automation (EDA) tools. Integrated circuit electronic design automation software can use the Verific parser to parse corresponding digital circuit design files and generate the corresponding netlist data structure.

[0069] In this embodiment, the netlist data structure is parsed and generated by the Verific parser. The netlist data structure includes a description of the circuit hardware structure and the connection relationship between the circuit hardware structures in the digital circuit design file. The above-mentioned circuit hardware structure includes a library object Library, a cell object Cell, a netlist object Netlist, an instance object Instance, a line network object Net, and a port object Port. The connection relationship between the above-mentioned circuit hardware structures can be a connection relationship between one circuit hardware structure and another circuit hardware structure in the digital circuit design file.

[0070] As a preferred embodiment, the Verific parser is used to parse digital circuit design files to generate a netlist data structure. The specific steps include retaining the circuit hardware structure and the signal connection relationship descriptions between the circuit hardware structures, and removing the circuit behavior descriptions in the digital circuit design file. The circuit hardware structure and the signal connection relationship descriptions between the circuit hardware structures include descriptions of modules, ports, instances, and signal lines in the digital circuit design file, and the circuit behavior descriptions in the digital circuit design file include descriptions of always logic blocks and assign statements. The netlist data structure generated by parsing the digital circuit design file through the above steps has a lower level of abstraction than the digital circuit design file and is closer to the actual physical implementation.

[0071] The netlist data structure generated by the Verific parser parsing the digital circuit design file includes several netlist data structure objects, which can specifically include a global singleton object, at least one library object, at least one unit object, at least one netlist object and at least one circuit element object; the global singleton object contains a mapping relationship between the library object name and the library object, the library object contains a mapping relationship between the unit object name and the unit object, the unit object contains a mapping relationship between the netlist object name and the netlist object, and the netlist object contains a mapping relationship between the circuit element object name and the circuit element object.

[0072] As an example, the specific process of using the Verific parser to parse a digital circuit design file and generate a netlist data structure using the integrated circuit electronic design automation software in this embodiment is as follows: First, after loading the digital circuit design file, the integrated circuit electronic design automation software calls the Verific parser to parse the digital circuit design file. The Verific parser identifies the circuit hardware structure in the digital circuit design file through syntax analysis, such as modules, cells, ports, signal lines, and instance relationships. For each identified module or cell, it creates a cell object Verific::Cell and records information such as the module name and the library name in the cell object. Similarly, for each other identified netlist data structure object, the Verific parser creates a netlist object Verific::Netlist, a net object Verific::Net, an instance object Verific::Instance, and a port object Verific::Port, respectively, for each identified netlist, net, instance, and port. Finally, through the above steps, the digital circuit design file is parsed using the Verific parser to generate a netlist data structure that only contains the circuit hardware structure and its connection relationships in the original digital circuit design file, but does not contain the behavioral description in the original digital circuit design file.

[0073] As a preferred embodiment, the above S120 may include: configuring a netlist data structure mapping container, wherein the netlist data structure mapping container includes a global singleton object mapping container and multiple library object mapping containers, unit object mapping containers and netlist object mapping containers, the global singleton object mapping container includes a key-value pair for describing the mapping relationship from the library object name to the library object mapping container, the library object mapping container includes a key-value pair for describing the mapping relationship from the unit object name to the unit object mapping container; the unit object mapping container includes a key-value pair for describing the mapping relationship from the netlist object name to the netlist object mapping container; the netlist object mapping container includes a key-value pair for describing the mapping relationship from the circuit element object name to the circuit element object mapping container.

[0074] like Figure 3 As shown, in this embodiment, the netlist data structure generated by the Verific parser when parsing a digital circuit design file includes a unique global singleton object. This global singleton object is the top-level structure of the netlist data structure and contains a mapping relationship between library object names and library objects. Specifically, the netlist data structure mapping container includes a global singleton object mapping container corresponding to the global singleton object. The global singleton object mapping container includes several key-value pairs used to describe the mapping relationship between library object names and library object mapping containers, where the key of each key-value pair is the library object name and the value is a pointer address pointing to the library object container. The above-mentioned global singleton object mapping container is stored in the system memory of the integrated circuit electronic design automation software.

[0075] The above-mentioned netlist data structure includes a library object, which is owned by a global singleton object. The library object contains a mapping relationship between a unit name and a unit object. Specifically, the netlist data structure mapping container includes a library object mapping container corresponding to the library object. The library object mapping container includes a number of key-value pairs for describing the mapping relationship between the unit object name and the unit object mapping container, wherein the key of the key-value pair for describing the mapping relationship between the unit object name and the unit object mapping container is the unit object name, and the value is a pointer address pointing to the unit object mapping container. The above-mentioned library object mapping container is stored in the system memory of the integrated circuit electronic design automation software. This embodiment realizes unified management and rapid access to multiple unit objects contained in the library object by using the library object container and key-value pairs.

[0076] The netlist data structure also includes a unit object, which is owned by a library object. The unit object includes a mapping relationship between the netlist object name and the netlist object. Most preferably, the unit object has a corresponding relationship with the module defined in the digital circuit design file, that is, each module defined in the digital circuit design file has a corresponding unit object. Specifically, the netlist data structure mapping container includes a unit object mapping container corresponding to the unit object. The unit object mapping container includes a number of key-value pairs for describing the mapping relationship between the netlist object name and the netlist object mapping container, wherein the key of each key-value pair is the netlist object name and the value is a pointer address pointing to the netlist object mapping container. The unit object mapping container is stored in the system memory of the integrated circuit electronic design automation software. By using the unit object container and key-value pairs, unified management and fast access to multiple netlist objects contained in the unit object are achieved.

[0077] The above-mentioned netlist data structure also includes a netlist object, which is owned by a unit object. The netlist object contains a mapping relationship between circuit element object names and circuit element objects, wherein the circuit element objects include but are not limited to port objects, wire net objects, and instance objects. Specifically, the netlist data structure mapping container includes a netlist object mapping container corresponding to the netlist object, and the netlist object mapping container includes several key-value pairs for describing the mapping relationship between the circuit element object name and the circuit element object mapping container, wherein the key of each key-value pair is the circuit element object name, and the value is the pointer address pointing to the circuit element object mapping container. Specifically, the circuit element object mapping container includes an instance object mapping container, a wire mesh object mapping container and a port object mapping container. The circuit element object mapping container stores records of the circuit element object name, and the names of other circuit element objects to which the circuit element object belongs or is connected, or the pointer address of the circuit element object mapping container. For example, the instance object mapping container stores records of the instance object name and the pointer address of the netlist object mapping container to which the instance object belongs. For another example, the wire mesh object mapping container stores records of the wire mesh object name and the pointer address of the netlist object mapping container to which the wire mesh object belongs. The netlist object mapping container can be stored in the system memory of the integrated circuit electronic design automation software. Through the netlist object container and key-value pairs, unified management and fast access to multiple circuit component objects contained in the netlist object can be achieved.

[0078] It can be understood that the above-mentioned netlist object mapping container is one of the netlist data structure mapping containers. The netlist data structure mapping container in this embodiment, in addition to the above-mentioned netlist object mapping container, also includes a global singleton object mapping container, a library object mapping container and a circuit element object mapping container.

[0079] In this embodiment, a netlist data structure mapping container is configured in the integrated circuit electronic design automation software. Each netlist data structure mapping container contains a number of key-value pairs with strings as keys. The keys in the key-value pairs represent the names of other netlist data structure mapping containers associated with the netlist data structure mapping container, and the values ​​represent pointers to other netlist data structure mapping containers associated with the netlist data structure mapping container. The netlist data structure is hierarchically assembled into a globally unique global singleton object Verific::Libset. The global singleton object contains multiple library objects Verific::Library. Each library object stores a number of unit objects V Verific::Cell, the cell object contains several netlist objects Verific::Netlist, and the netlist object contains several circuit component objects, such as the instance object Verific::Instance, etc. Therefore, the integrated circuit electronic design automation software can use the global singleton object as the top-level query entry, traverse and access the corresponding netlist data structure mapping container level by level, and obtain the corresponding netlist data structure mapping container. It can also access the next level mapping container according to other related netlist data structure mapping containers contained in the netlist data structure mapping containers at each level, and then can retrieve the various objects contained in the netlist data structure level by level to achieve the search for the specified target object.

[0080] It should be noted that, in some other implementations, the netlist data structure generated by the Verific parser when parsing a digital circuit design file may also be in the form of other non-mapped containers. For example, the netlist data structure generated by the parsing may be output in the format of a file in a hardware description language format, where the hardware description language includes Verilog, VHDL, EDIF, or BLIF. Netlist data structures in the above formats are typically used in the physical implementation process after chip design, such as layout and routing, timing analysis, and manufacturing in the back-end design process of digital circuits. The following example code shows the output content of the Verilog format netlist data structure generated by the Verific parser based on the parsing of a digital circuit design file:

[0081] module newcell (in, out);

[0082] input in;

[0083] output out;

[0084] wire n1;

[0085] inv inv1 (in, n1);

[0086] buff buff2 (n1, out);

[0087] endmodule

[0088] In the above code example, the module newcell represents a functional unit derived from a digital circuit design file. It contains an input port in and an output port out, and defines an intermediate connection n1 inside the module. After the Verific parser parses the digital circuit design file, it can output the circuit hardware structure and its connection relationship parsed from the digital circuit design file in the form of the above Verilog file.

[0089] As an optional embodiment, the above S120 further includes: configuring a global query handle for the global singleton object, the global query handle being used to return a pointer to a global singleton object mapping container. The global singleton object is configured as a globally unique object in integrated circuit electronic design automation software for centralized resource or status management. The global singleton object is configured with a global query handle for obtaining the global singleton object. The global query handle can be configured as a static member function that returns a pointer to the global singleton object, such as Libset::Global(). The static member function returns a pointer to the global singleton object, such as Libset*, which points to the address of the global singleton object mapping container in memory.

[0090] After the global query handle returns the pointer to the global singleton object, the integrated circuit electronic design automation software uses the pointer to the global singleton object mapping container returned by the global query handle to access the internal data of the global singleton object mapping container. The internal data of the global singleton object mapping container includes the mapping relationship between the library object name and the library object. The above-mentioned mapping relationship between the library object name and the library object can be a key-value pair recorded in the global singleton object mapping container for describing the mapping relationship between the library object name and the library object mapping container.

[0091] This embodiment uses the above method to configure a global query handle for the global singleton object. The global query handle is used to return a pointer to the global singleton object mapping container, providing a unified access interface for the global singleton object. This allows integrated circuit electronic design automation software to access the global singleton object mapping container from any location and use it as a starting point for accessing the hierarchical storage structure, thereby obtaining the library object mapping relationship maintained internally and other mapping relationships stored in the netlist data structure, thereby achieving unified retrieval and calling of various objects in the entire netlist data structure, thereby facilitating subsequent data search and matching operations.

[0092] Exemplarily, the above-mentioned response to the object query request issued by the user, accessing the netlist data structure, and searching for data items that match the target query object specified by the user in the netlist data structure may include: accessing each key-value pair in the netlist data structure mapping container, and performing string matching on the key items of each key-value pair in the netlist data structure mapping container with the target query object specified by the user.

[0093] In this embodiment, the netlist data structure mapping container is accessed and all key items recording the netlist data structure object names are taken out one by one to perform string matching with the target name input by the user to determine whether a matching item that meets the query condition is included. Specifically, the user can input an object query command, such as -find_object i1, into the integrated circuit electronic design automation software, determine that the target query object specified by the user is i1 in the above object query command, and then access the netlist data structure mapping container and traverse and search the name string i1 of the above target query object. The above netlist data structure mapping container contains key-value pairs for describing the mapping relationship between the netlist data structure object name and the netlist data structure object mapping container. For example, if the accessed netlist data structure mapping container is a netlist object mapping container, then the netlist object mapping container includes several key-value pairs for describing the mapping relationship between the circuit element object name and the circuit element object mapping container, wherein the key of each key-value pair is the circuit element object name and the value is the pointer address pointing to the circuit element object mapping container. Finally, each key item in the netlist data structure mapping container is matched with the target query object specified by the user. If the match is successful, it indicates that there is a data item in the netlist data structure mapping container that matches the target query object specified by the user. In addition, in some embodiments, when a key item in the netlist data structure mapping container successfully matches a target query object string specified by the user, the name of the netlist data structure mapping container and the target query object string are recorded in a result container.

[0094] As an optional implementation, the accessing of each key-value pair in the netlist data structure mapping container and performing string matching between the key item of each key-value pair in the netlist data structure mapping container and the target query object specified by the user specifically includes the following steps:

[0095] Determine whether the name of the target query object specified by the user contains a wildcard character;

[0096] When the character string of the target query object name specified by the user does not contain a wildcard character, a hash search operation is performed in the corresponding netlist data structure mapping container using the character string of the target query object name as a key value;

[0097] When the string of the target query object name specified by the user contains a wildcard, the string of the target query object name is used as a matching condition, and string matching is performed one by one on each key item in the netlist data structure mapping container through a for loop statement.

[0098] In the steps of this embodiment, if the target query object specified by the user is a specific string that does not contain wildcards, a hash search operation is performed in the corresponding netlist data structure mapping container to quickly locate and obtain the data item that fully matches it. For example, assuming that the name of the target query object specified by the user is i1, and the name is stored in a netlist object mapping container in the netlist data structure mapping container, after receiving the query request, the system performs a hash search operation in the corresponding netlist object mapping container, wherein the netlist object mapping container may contain multiple key-value pairs, the key is the instance object name, such as i1, i2, i3, etc., and the value is the pointer to the corresponding instance object mapping container. Through the hash search operation, a key item that fully matches the name i1 of the target query object is found, and then the key-value pair can be recorded as an object query result, which contains the instance object name i1 and the pointer address corresponding to the instance object mapping container. The above object query result can be recorded in the result container and used for subsequent data processing or display.

[0099] In the case where the string of the name of the target query object specified by the user contains a wildcard, the string of the name of the target query object is used as a matching condition, and a for loop statement is used to perform string traversal matching on each key item in the netlist data structure mapping container one by one. Specifically, in the case where the string of the name of the target query object specified by the user contains a wildcard, the integrated circuit electronic design automation software can use the string of the name of the target query object as a matching condition, and a for loop statement is used to traverse each key item in the netlist object mapping container one by one to perform string traversal matching. During the traversal process, each key item is string-matched with the wildcard expression, and the key items that successfully match are found and the object query results are recorded. During the actual operation process, the above object search results can be saved in the result container for use in subsequent processes.

[0100] In the related prior art, object queries based on hierarchical multi-branch tree structures typically use depth-first or breadth-first traversals, with a traversal time complexity of O(n), where n is the total number of circuit nodes. However, the above-mentioned method of this embodiment can directly perform hash search operations based on the netlist data structure mapping container without involving traversal operations. With the help of the hash structure, the query time complexity is reduced to close to O(1), and the access efficiency is extremely high. In large-scale circuit design scenarios, this method can significantly improve the response speed and overall efficiency of object queries. In addition, this embodiment can also implement search matching when the target query object specified by the user contains wildcards. When the string of the name of the target query object specified by the user contains wildcards, each key item in the netlist data structure mapping container is traversed and matched in turn through a for loop statement, which has the beneficial effect of high query flexibility.

[0101] In some optional embodiments, at S130, in response to an object query request issued by a user, the netlist data structure is accessed, and before searching for data items matching the target query object specified by the user in the netlist data structure, the method may further include: in response to the object query request issued by the user, obtaining the type of the target query object in the object query request; when the type of the target query object is a circuit element object, searching for data items matching the target query object in the netlist data structure mapping container, wherein the circuit element object includes instance objects, port objects, and wire mesh objects.

[0102] As an example, the target query object specified by the user in an object query request is a data item named i1. In response to this request, the name of the target query object i1 is first determined, and the type of the target query object is obtained. A determination is made as to whether the type of the target query object i1 is a circuit component object. If the object type of the target query object i1 is such a circuit component object, for example, if the object type of the target query object i1 is an instance, the netlist data structure mapping container is accessed and a data item matching the target query object is searched within the netlist data structure mapping container. For example, a netlist object mapping container containing key-value pairs describing data related to the circuit component object mapping container may be accessed, wherein the netlist object mapping container includes a key-value pair with the instance object name as the key value. Accordingly, if the type of the target query object i1 is not an instance, port, or net, for example, a non-circuit component object such as a library object or metadata, the request processing flow is terminated directly and an error message is returned, prompting the user that the current object type does not support the query operation, thereby avoiding ineffective resource consumption and subsequent processing.

[0103] In some optional implementations, before accessing the netlist data structure in response to the object query request issued by the user at S130 and searching the netlist data structure for data items matching the target query object specified by the user, the method may further include:

[0104] Receiving a traversal search range specified by a user in an object query request, wherein the traversal search range is used to limit traversal to only within a netlist data structure mapping container corresponding to a specified object type;

[0105] When the user specifies a traversal search range, only the netlist data structure mapping container corresponding to the specified object type is traversed to search for data items that match the target query object.

[0106] The above-mentioned netlist data structure includes multiple netlist data structure mapping containers, such as: global singleton object mapping container, netlist object mapping container, library object mapping container and circuit element object mapping container, etc. Each netlist data structure mapping container contains a specific type of object and stores the object name and its pointer reference in the form of key-value pairs.

[0107] In this embodiment, the user can specify the traversal search range in the object query request. For example, the user can specify the traversal search range as a specific object type through the -object_type parameter, and subsequently only traverse the netlist data structure mapping container corresponding to the type. For example, the user specifies the traversal search range as only traversing the netlist object mapping container through -object_type netlist in the object query request. In the subsequent traversal search process, only string matching is performed on each key item in the netlist object mapping container and the target query object specified by the user, and the access and search matching of netlist data structure mapping containers of other non-target types are skipped, for example, the access and search matching of the library object mapping container are skipped.

[0108] In step S140 , an object query result is generated based on the data items found in the netlist data structure that match the target query object.

[0109] In this embodiment, after accessing the netlist data structure and finding data items matching the target query object specified by the user, an object query result is generated based on the data items matching the target query object found in the netlist data structure.

[0110] As a preferred embodiment, the above-mentioned step of generating an object query result based on the data items matching the target query object found in the netlist data structure includes: generating the object query result by sequentially splicing the name of the upper-level object to which the target query object belongs, the hierarchical separator, and the name of the target query object, wherein the name of the upper-level object to which the target query object belongs is the name of the netlist data structure mapping container that stores the key-value pairs containing the name of the target query object.

[0111] Before generating object query results, this embodiment processes data items found in the netlist data structure that match the target query object specified by the user according to the hierarchical name format specified by the IEEE, and further generates and provides a hierarchical path name corresponding to the target query object. The hierarchical path name is used to indicate the ownership relationship and hierarchical position of the target query object in the netlist data structure, making it easier for users to quickly identify the source of the object and its scope.

[0112] Specifically, the object query result generated by this embodiment is composed of the name of the upper-level object to which the target query object belongs, the hierarchical separator, and the name of the target query object, which are spliced ​​together in sequence. The name of the upper-level object to which the target query object belongs is the name of the netlist data structure mapping container that stores the key-value pairs containing the name of the target query object. For example, the name of the target query object specified by the user in the object query request is c2. When the system performs object search, it retrieves a matching item of the key-value pair named c2 from the key-value pair of the instance object mapping container and the instance object name recorded in a certain netlist object mapping container. Since the name of the netlist data structure mapping container that stores the key-value pairs containing the name c2 of the above-mentioned target query object is t1 netlist object mapping container, based on this, the netlist data structure mapping container t1 that stores the key-value pairs containing the name of the above-mentioned target query object can be determined as the upper-level object name of the target query object c2, and combined with the separator / and the target object name c2, the complete hierarchical path name t1 / c2 is obtained by splicing in the order of the name of the upper-level object to which the target query object belongs, the preset hierarchical separator and the name of the target query object.

[0113] In addition, it can be understood that before generating the object query result, the integrated circuit electronic design automation software can create and use a result container to record the data items that match the user-specified target query object found in the netlist data structure and the name of the corresponding netlist object mapping container, and after completing the traversal of all netlist data structure mapping containers, obtain the above data items and the record of the corresponding netlist object mapping container name from the result container to generate the object query result.

[0114] This embodiment uses the above-mentioned method to generate object query results by utilizing the reference relationship between the netlist data structure mapping container and the key-value pairs contained therein, in accordance with the hierarchical name specification of the integrated circuit design specification. For example, if the type of the target query object provided by the user is an instance object, this embodiment finds a match for the target query object in the netlist object mapping container to which the instance object belongs, and then generates an object query result based on the above-mentioned instance object name and the name of the netlist object mapping container that stores the key-value pairs containing the instance object name, such as netlist object name / instance object name. The object query result thus generated not only meets the requirements of the integrated circuit design specification, but also its name format also complies with the hierarchical path naming specification.

[0115] As a preferred implementation, the above S140 may include:

[0116] After finding a first target netlist object mapping container containing the target query object in the netlist data structure, accessing a similar name container corresponding to the target netlist object mapping container, the similar name container pre-stored with names of similar netlist object mapping containers belonging to the same unit object as the target netlist object, and generating a first query result based on the name of the target netlist object mapping container, the names of the similar netlist object mapping containers, and the name of the target query object;

[0117] Traversing other netlist object mapping containers except the target netlist object mapping container, searching for matching items of the target query object in the other netlist object mapping containers, and generating a second query result;

[0118] The object query result is generated based on the first query result and the second query result.

[0119] In this embodiment, first, the first target netlist object mapping container containing the target query object is found in the netlist data structure through the above steps S110-S130. Specifically, the first target netlist object mapping container containing the target query object can be found in the netlist data structure by traversing the key-value pairs in the netlist data structure mapping container and performing string matching between each key item and the target query object specified by the user. For example, if the target query object specified in the object query request issued by the user is named i2, after the first data item containing the target query object i2 is found in the netlist object mapping container named t1, the netlist object mapping container named t1 is determined as the target netlist object mapping container.

[0120] After finding the first target netlist object mapping container containing the target query object in the netlist data structure, accessing the same name container corresponding to the target netlist object mapping container, wherein the same name container pre-stores the names of similar netlist object mapping containers belonging to the same unit object as the target netlist object mapping container, and generating a first query result based on the name of the target netlist object mapping container, the names of the similar netlist object mapping containers, and the name of the target query object. Specifically, after finding the first target netlist object mapping container t1 containing the target query object in the netlist data structure, traversing other netlist object mapping containers in the netlist data structure is stopped, and the same name container is accessed instead, wherein the same name container pre-stores the names of similar netlist object mapping containers belonging to the same unit object as the target netlist object. By accessing the same name container, the name of the similar netlist object mapping container corresponding to the target netlist object mapping container t1 can be found and determined. For example, after determining the target netlist object mapping container t1, the same-name container can be accessed and the name of the same-name netlist object mapping container corresponding to the target netlist object mapping container t1, such as t2 and t3, can be queried therefrom. Based on the name of the target netlist object mapping container, the name of the same-name netlist object mapping container, and the name of the target query object, a first query result is generated. The first query result includes: query results t1 / i2 generated based on the name t1 of the target netlist object mapping container and the name i2 of the target query object, and query results t1 / i2 generated based on the name t2 of the same-name netlist object mapping container. The query result t2 / i2 is generated based on the name i2 of the target query object, and the query result t3 / i2 is generated based on the name t3 of the same type of netlist object mapping container and the name i2 of the target query object. It can be understood that after the above-mentioned first query result is generated, the above-mentioned first query results (such as t1 / i2, t2 / i2, t3 / i2, etc.) can be uniformly collected and stored in the result container, and after the traversal of other netlist object mapping containers is completed, the above-mentioned first query result and other query results generated subsequently, such as the second query result, are summarized as the final object query result and output to the user.

[0121] After generating the above-mentioned first query result, this embodiment continues to traverse other netlist object mapping containers except the target netlist object mapping container and similar netlist object mapping containers, traverses and searches for data items that match the target query object specified by the user in other netlist object mapping containers, generates a second query result, and finally generates an object query result based on the first query result and the second query result. For example, after finding the first target netlist object mapping container t1 containing the target query object, and finding the same type of netlist object mapping container corresponding to the target netlist object mapping container t1 through the same type name container to generate the above-mentioned first query results t1 / i2, t2 / i2, and t3 / i2, the other netlist object mapping containers stored in the netlist data structure are traversed to find matches with the target query object. The above-mentioned other netlist object mapping containers are netlist object mapping containers other than the target netlist object mapping container and the same type netlist object mapping containers in all netlist object mapping containers. During the traversal process, the traversal of the target netlist object mapping container and the same type netlist object mapping containers is skipped, and only the other netlist object mapping containers other than the target netlist object mapping container are traversed. For example, the above-mentioned other netlist object mapping containers may include netlist object mapping containers e1 and e2 that belong to different unit objects from the target netlist object mapping container t1 and are not stored in the same type name container corresponding to the target netlist object mapping container t1. The second query results generated based on the above-mentioned other netlist object mapping containers may be e1 / i2 and e2 / i2. Finally, based on the first query result and the second query result, the final object query result is determined to be generated. The final object query result includes the above-mentioned first query result and second query result. For example, the final object query result includes t1 / i2, t2 / i2, t3 / i2, e1 / i2, and e2 / i2.

[0122] Through the above method, this embodiment records the names of the multiple netlist objects generated by instantiating the same unit object in a similar name container in advance, aiming at the case where multiple netlist objects are generated by instantiating the same unit object. Then, when performing an object query, the name information of the similar netlist objects recorded in the similar name container is directly used to quickly assemble and generate the query results, thereby avoiding the need to traverse and compare the key-value pairs in all netlist object mapping containers one by one, thereby greatly reducing invalid operations and significantly improving query efficiency.

[0123] Figure 4 The hardware structure diagram of the data processing device provided in the embodiment of the present application is shown. Figure 4 In the embodiment, the data processing device may include:

[0124] An acquisition module 401 is used to acquire a digital circuit design file;

[0125] Parsing module 402, used to parse the digital circuit design file and generate a corresponding netlist data structure;

[0126] A search module 403 is configured to access the netlist data structure in response to an object query request issued by a user, and search the netlist data structure for a data item that matches a target query object specified by the user;

[0127] The generating module 404 is configured to generate an object query result based on the data items found in the netlist data structure and matching the target query object specified by the user.

[0128] Figure 5 The following is a schematic diagram of the hardware structure of a data processing device provided in an embodiment of the present application. The data processing device includes a processor 501 and a memory 502 storing computer program instructions. Specifically, the processor 501 may include a central processing unit (CPU) or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiment of the present application.

[0129] Memory 502 may include a large-capacity memory for data or instructions. By way of example and not limitation, memory 502 may include a hard disk drive (HDD), a floppy disk drive, flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 502 may include removable or non-removable (or fixed) media. Where appropriate, memory 502 may be internal or external to the data processing device. In certain embodiments, memory 502 is a non-volatile solid-state memory.

[0130] The memory 502 may include read-only memory (ROM), flash memory devices, random access memory (RAM), magnetic disk storage media devices, optical storage media devices, electrical, optical, or other physical / tangible memory storage devices. Thus, typically, the memory 502 includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software, which may include computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods according to the above aspects of the present disclosure.

[0131] The processor 501 implements any one of the data processing methods in the above embodiments by reading and executing computer program instructions stored in the memory 502 .

[0132] In one example, the data processing device may further include a communication interface 503 and a bus 510. Figure 5 As shown, the processor 501, the memory 502, and the communication interface 503 are connected via a bus 510 and communicate with each other.

[0133] The communication interface 503 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0134] Bus 510 includes hardware, software, or both that couples components of a data processing device to one another. By way of example, and not limitation, a bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industrial Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industrial Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 510 may include one or more buses. Although the embodiments of the present application describe and illustrate specific buses, the present application contemplates any suitable bus or interconnect.

[0135] The data processing device may be based on the data processing method, thereby realizing a combination of the above-mentioned data processing method and apparatus.

[0136] In addition, in conjunction with the data processing methods in the above embodiments, embodiments of the present application may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any one of the data processing methods in the above embodiments is implemented.

[0137] In addition, an embodiment of the present application further provides a computer program product, including a computer program, which, when executed by a processor, can implement the steps and corresponding contents of the aforementioned data processing method embodiment.

[0138] The above are only specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data processing method, applied to integrated circuit electronic design automation software, characterized in that: include: Obtain digital circuit design files; Parsing the digital circuit design file to generate a corresponding netlist data structure includes: configuring a netlist data structure mapping container, wherein the netlist data structure mapping container includes a global singleton object mapping container and multiple library object mapping containers, unit object mapping containers, and netlist object mapping containers, the global singleton object mapping container includes a key-value pair for describing a mapping relationship between a library object name and a library object mapping container, the library object mapping container includes a key-value pair for describing a mapping relationship between a unit object name and a unit object mapping container; the unit object mapping container includes a key-value pair for describing a mapping relationship between a netlist object name and a netlist object mapping container; and the netlist object mapping container includes a key-value pair for describing a mapping relationship between a circuit element object name and a circuit element object mapping container; In response to an object query request issued by a user, accessing the netlist data structure and searching the netlist data structure for a data item that matches a target query object specified by the user; An object query result is generated based on the data items found in the netlist data structure that match the target query object specified by the user.

2. The data processing method according to claim 1, wherein: The parsing of the digital circuit design file to generate a corresponding netlist data structure includes: parsing the digital circuit design file using a Verific parser to generate the netlist data structure.

3. The data processing method according to claim 1, wherein: The parsing of the digital circuit design file to generate a corresponding netlist data structure includes: configuring a global query handle to the global singleton object, wherein the global query handle is used to return a pointer to the global singleton object mapping container.

4. The data processing method according to claim 1, wherein: The method responds to an object query request issued by a user, accesses the netlist data structure, and searches for data items that match the target query object specified by the user in the netlist data structure, including: accessing each key-value pair in the netlist data structure mapping container, and performing string matching on the key items of each key-value pair in the netlist data structure mapping container with the target query object specified by the user.

5. The data processing method according to claim 1, wherein: The step of accessing the netlist data structure in response to an object query request issued by a user and searching the netlist data structure for a data item that matches a target query object specified by the user comprises: In response to an object query request issued by a user, obtaining the type of a target query object in the object query request; In the case that the type of the target query object is a circuit element object, a data item matching the target query object is searched in the netlist data structure mapping container, wherein the circuit element object includes an instance object, a port object, and a wire net object.

6. The data processing method according to claim 1, wherein: The step of accessing the netlist data structure in response to an object query request issued by a user and searching the netlist data structure for a data item that matches a target query object specified by the user comprises: receiving a traversal search range specified by a user in the object query request, wherein the traversal search range is used to limit traversal to only the netlist data structure mapping container corresponding to the specified object type; In the case where the user specifies a traversal search range, only the netlist data structure mapping container corresponding to the specified object type is traversed to search for data items that match the target query object.

7. The data processing method according to claim 1, wherein: Based on the data items found in the netlist data structure that match the target query object specified by the user, an object query result is generated, including: generating the object query result by sequentially splicing and combining the name of the upper-level object to which the target query object belongs, the hierarchical separator, and the name of the target query object, wherein the name of the upper-level object to which the target query object belongs is the name of the netlist data structure mapping container that stores key-value pairs of items matching the target query object.

8. The data processing method according to claim 1, wherein: Generating an object query result based on the data items found in the netlist data structure that match the target query object specified by the user, including: After finding a first target netlist object mapping container containing the target query object in the netlist data structure mapping container, accessing a similar name container corresponding to the target netlist object mapping container, the similar name container recording names of similar netlist objects belonging to the same unit object as the target netlist object, and generating a first query result based on the name of the target netlist object mapping container, the names of the similar netlist objects recorded in the corresponding similar name container, and the name of the target query object; Traversing other netlist object mapping containers except the target netlist object mapping container, searching for matching items of the target query object in the other netlist object mapping containers, and generating a second query result; Based on the first query result and the second query result, it is determined to generate the object query result.

9. A data processing device, characterized in that: include: An acquisition module, used for acquiring digital circuit design files; a parsing module, configured to parse the digital circuit design file and generate a corresponding netlist data structure, comprising: configuring a netlist data structure mapping container, wherein the netlist data structure mapping container comprises a global singleton object mapping container and a plurality of library object mapping containers, a unit object mapping container, and a netlist object mapping container; the global singleton object mapping container comprises a key-value pair for describing a mapping relationship between a library object name and a library object mapping container; the library object mapping container comprises a key-value pair for describing a mapping relationship between a unit object name and a unit object mapping container; the unit object mapping container comprises a key-value pair for describing a mapping relationship between a netlist object name and a netlist object mapping container; and the netlist object mapping container comprises a key-value pair for describing a mapping relationship between a circuit element object name and a circuit element object mapping container; a search module, configured to access the netlist data structure in response to an object query request issued by a user, and search the netlist data structure for a data item that matches a target query object specified by the user; A generating module is used to generate an object query result based on the data items found in the netlist data structure and matching the target query object specified by the user.

10. A data processing device, characterized in that: include: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the steps of the data processing method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the steps of the data processing method according to any one of claims 1 to 8.

12. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor, the steps of the data processing method according to any one of claims 1 to 8 are implemented.

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