Experimental platform and method for applying multi-modal large model digital circuit and medium

Abstract

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuit experimental teaching, and more specifically, to an experimental platform, method and medium for applying a multi-modal large-scale digital circuit. Background Art

[0002] In the field of digital circuit experimental teaching, the technical bottlenecks of traditional experimental platforms and methods are becoming increasingly prominent. In the existing technical system, the implementation of experimental tasks is highly dependent on manual labor. This model not only requires users to master multiple skills, but also requires rich engineering practice experience. Deeper technical limitations are reflected in the lack of capabilities in natural language processing and intelligent generation. Traditional platforms have difficulty automatically parsing natural language tasks into structured functional requirements, interface constraints, and timing parameters, and are even unable to generate context-aware prompts based on electronic component knowledge bases to guide code generation. When faced with circuit designs involving multiple clock domains and complex combinational logic, manual operations are prone to problems such as signal naming conflicts and timing path violations.

[0003] Furthermore, existing electronic component knowledge bases generally utilize a static storage architecture and lack a dynamic update mechanism based on experimental data. This makes it difficult to quickly incorporate the latest component models into the knowledge base when new logic units or advanced process libraries are released. Furthermore, excellent circuit designs verified through historical experiments cannot be automatically incorporated into the knowledge base as new nodes, leading to a serious phenomenon of "knowledge islands."

[0004] Therefore, based on the above background, the present invention proposes a digital circuit experimental platform, method and medium using a multi-modal large model. Summary of the Invention

[0005] In view of the shortcomings of the existing technology, the purpose of the present invention is to provide a multi-modal large-model digital circuit experimental platform, method and medium.

[0006] To achieve the above object, the present invention provides the following technical solutions: Apply a multimodal large-model digital circuit experimental platform, including an experimental task semantic parsing module, a circuit prompt word construction module, a Verilog HDL code generation module, a code verification module, a circuit schematic generation module, and an electronic component knowledge base + RAG enhancement and update module; Experimental task semantic parsing module: converts the experimental task requirements described in natural language into structured representation of the experimental task; Circuit prompt word construction module: connects to the electronic component knowledge base, retrieves circuit functional blocks according to the experimental task, generates candidate circuit prompt words using the circuit prompt word construction function, and calculates the circuit prompt word diversity index; Verilog HDL code generation module: uses circuit prompts to guide multi-modal large models to generate Verilog HDL code; Code verification module: performs interface constraints, syntax checking and functional verification on the generated Verilog HDL code; Circuit schematic generation module: used to perform logic synthesis on the verified code and generate a circuit schematic; Electronic component knowledge base + RAG enhanced update module: used to update the electronic component knowledge base.

[0007] Step 1: Experimental task semantic analysis: Convert the input natural language description of the functional requirements into a structured representation of the experimental task Task={F,I,T}; where F represents the function type (such as adder, trigger, etc.), I represents the interface constraints (such as input and output bit width, signal naming, etc.), and T represents the key timing requirements (such as rising edge trigger, hold time, etc.); Step 2: Circuit prompt word construction: retrieve the optimal circuit function block from the electronic component knowledge base, and use the circuit prompt word construction function to combine the defined error prompt information and the experimental task described in step 1 to construct the circuit prompt word; Step 3: Verilog code generation and verification: Using the circuit prompts described in step 2, through the multi-modal large model Generate Verilog HDL code V; and perform interface constraints, syntax checking, and function verification on the Verilog HDL code V generated by the MLLMs.

[0008] Step 4. Circuit schematic generation: Use the Yosys tool to perform logic synthesis on the Verilog HDL code V described in step 3 to generate a JSON format circuit netlist. Where, Represents a circuit netlist generation function; performs logic synthesis detection on the code V using the conflict detection mechanism and backtracking generation strategy; and converts the circuit netlist N into an SVG format circuit schematic using the Netlistsvg tool. Where, Indicates the function of generating schematic diagram; Step 5. Circuit schematic timing verification: Use the MLLMs model to perform timing verification on the circuit schematic G obtained in step 4 to meet the timing constraint set in the experimental task. , each timing constraint Indicates that the signal is from the node arrive Maximum propagation delay If the verification fails, update the circuit prompt word And regenerate Verilog HDL code and continue to iterate until timing consistency is met; Step 6. Update the electronic component knowledge base: Select candidate circuit functional blocks According to the experimental task Task of step 1 and the candidate circuit function block Structural semantic similarity, retrieval weight Calculate the candidate circuit functional blocks Search score of , the calculation formula is as follows: ; in, Represents experimental tasks and circuit function blocks Structural semantic similarity, Represents the adjustment coefficient, which is set based on experience or through search optimization; For the candidate circuit functional blocks , according to the search score Sort in descending order and record the circuit function block with the highest search score as the optimal circuit function block B * , the formula is as follows: ; in, Indicates the value of the independent variable corresponding to the maximum value of the function; Then the optimal circuit functional block Output to the circuit prompt word construction module; extract the digital circuit structure information after verification by the circuit schematic generation module ,in Representation code Functional semantic labels, Write into the electronic component knowledge base as a new circuit function block ;Introduce penalty score adjustment mechanism to update the optimal circuit function block Index weight ; The present invention also provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the program implements the above-mentioned digital circuit experimental method using a multimodal large model. The method is specifically used in a digital circuit experimental teaching platform to implement a closed-loop process from task semantic analysis, code generation, logic verification, generation of circuit schematics to knowledge enhancement.

[0009] Furthermore, in step 2, the specific steps for constructing the circuit prompt word are as follows: S0, define circuit prompt words to build function set , No. Wheel error message , represents the number of circuit prompt word construction functions in the set; S1. Retrieve the first Optimal circuit functional blocks ; S2. Use the structured representation of the experimental task Task and the optimal circuit functional block described in step 1 And the error message , No. Wheel construction function Generate candidate circuit hint words ; S3. Calculate the candidate circuit prompt words Diversity indicators , The larger the value, the more diverse the circuit prompt words. The calculation formula is as follows: ; in, Respectively represent Wheel construction function Generated circuit prompt words, Indicates the first The turn circuit prompts the similarity between words; S4. Set diversity indicator threshold ,like , then the candidate circuit prompt word As the first Circuit prompt words ; S5. If , calculate the diversity score of each construction function in the circuit prompt word construction function set, and the calculation formula is as follows: ; in, represents the consistency weight factor, represents cosine similarity; S6. Score each construction function according to diversity Sort descending, select The highest construction function Regenerate , the calculation formula is: .

[0010] Furthermore, the interface constraints, syntax checking, and function verification in step 3 are as follows: The constraints are as follows: ; in, represents the interface constraints in the experimental task, Indicates that the code V semantically satisfies the interface constraints , 、 Respectively represent Verilog HDL syntax checking and functional verification functions; If the above constraints do not hold, the backtracking mechanism is executed: ; Where, Indicates the Iterate multi-modal large model to generate Verilog HDL code, Indicates the In the iteration, the optimal circuit functional block is retrieved by RAG.

[0011] Furthermore, the conflict detection mechanism and retroactive generation strategy set in step 4 are as follows: For the signal in the Verilog HDL code V , if there is a conflict set , no processing is done; Otherwise, use the conflict set Construct circuit prompt words to guide MLLMs to repair the target, the expression is: ; After multiple iterations until , ; Where, Indicates the first A signal, Indicates that there is a conflicting set of signals. Indicates the set of all signals defined in the code, Indicates the Iteration circuit prompt word, Represents a union operation.

[0012] Furthermore, the timing verification of the circuit schematic in step 5 is as follows: Model the circuit schematic diagram G and record it as a directed graph , where the node set Represents a logic unit (such as a NAND gate, a D flip-flop, etc.), an edge set Indicates the signal connection direction; Define the attribute vector of each logic unit node as: ; in, Represents an embedded operation function that can convert node attributes into continuous vectors, where Type(v) represents the type of logic unit represented by node v, Delay(v) represents the static propagation delay of the logic unit represented by node v, and ClockDomain(v) represents the clock domain to which node v belongs. Construct a global diagram representation of the circuit schematic: ; in, Representing a graph neural network; Capture timing path dependencies and perform timing verification. The formula is as follows: ; Among them, 1 indicates successful verification, and 0 indicates failed verification; Representation diagram mid-edge node src i to dst i The shortest path propagation delay is calculated as follows: ; in, Represents the node src i to dst i The set of all paths, δ uv It represents the propagation delay of the signal from node u to v.

[0013] Furthermore, a penalty score adjustment mechanism is introduced in step 6, as follows: If the optimal circuit functional block Generate candidate circuit hint words Diversity indicators Greater than or equal to The search weight remain unchanged; Otherwise, update the optimal circuit function block Corresponding search weight , the formula is: ; in: Indicates the current index weight, is the penalty item, Indicates the basic penalty range, represents the attenuation coefficient, Indicates circuit function block B * The cumulative number of verification failures, Represents the weighting coefficient.

[0014] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention converts natural language experimental tasks into structured representations, guiding the multimodal large model to generate Verilog HDL code based on circuit prompts. This achieves intelligent conversion from natural language to circuit code, reduces the tedious process of manual code writing, lowers the technical threshold for experimental operation, enables students to easily carry out digital circuit experiments, and thus improves the intelligent level of experimental teaching. 2. Through circuit function block retrieval score calculation, optimal circuit function block selection, index weight update, and penalty score adjustment, the verified digital circuit structured information is continuously added to the knowledge base, realizing the cyclic evolution and adaptive enhancement of knowledge, providing more comprehensive and accurate knowledge support for subsequent experimental teaching. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a module block diagram of the multi-modal large-model digital circuit experimental platform used in the present invention; Figure 2 The figure is a flow chart of the multi-modal large-model digital circuit experimental method applied in the present invention. DETAILED DESCRIPTION

[0016] Example 1, refer to Figure 1 The multi-modal large-model digital circuit experimental platform of this embodiment includes: Experimental task semantic parsing module: This module extracts the structured semantic information from the input natural language description of the experimental task requirements through parsing and converts it into a structured representation of the experimental task. Circuit prompt word construction module: This module connects to the electronic component knowledge base, retrieves circuit functional blocks according to the task, generates candidate circuit prompt words using the circuit prompt word construction function, and calculates the circuit prompt word diversity index to determine whether the generated circuit prompt words meet the requirements. Verilog HDL code generation module: uses circuit prompts to guide multi-modal large models to generate Verilog HDL code; Code verification module: performs interface constraints, syntax checking and functional verification on the generated Verilog HDL code; Circuit schematic generation module: includes Yosys and Netlistsvg tools, which are used to perform logic synthesis on the verified code, generate a JSON format circuit netlist, and convert it into an SVG format circuit schematic. Electronic component knowledge base + RAG enhancement and update module: used to update the electronic component knowledge base to support the cyclic evolution and adaptive enhancement of knowledge.

[0017] Reference Figure 2 The multi-modal large-model digital circuit experimental method of this embodiment specifically includes the following steps: Step 1: Semantic analysis of experimental tasks.

[0018] Convert the input natural language description of functional requirements into a structured representation of the experimental task: Task={F,I,T}; Where F represents the function type (such as adder, flip-flop, etc.), I represents the interface constraints (such as input and output bit width, signal naming, etc.), and T represents the key timing requirements (such as rising edge trigger, hold time, etc.); Step 2: Construct circuit prompt words.

[0019] S0, define circuit prompt words to build function set , No. Wheel error message , represents the number of circuit prompt word construction functions in the set; S1. Retrieve the first Optimal circuit functional blocks ; S2. Use the structured representation of the experimental task Task and the optimal circuit functional block described in step 1 And the error message , No. Wheel construction function Generate candidate circuit hint words ; S3. Calculate the candidate circuit prompt words Diversity indicators , The larger the value, the more diverse the circuit prompt words. The calculation formula is as follows: ; in, Respectively represent Wheel construction function Generated circuit prompt words, Indicates the first The turn circuit prompts the similarity between words; S4. Set diversity indicator threshold In this embodiment Take the value 0.68; if , then the candidate circuit prompt word As the first Circuit prompt words ; S5. If , calculate the diversity score of each construction function in the circuit prompt word construction function set, and the calculation formula is as follows: ; in, represents the consistency weight factor, represents cosine similarity; S6. Score each construction function according to diversity Sort descending, select The highest construction function Regenerate , the calculation formula is: ; Step 3: Verilog code generation and verification.

[0020] Use the circuit prompts described in step 2 , through a multimodal large model Generate VerilogHDL code V, where MLLMs Indicates the Verilog HDL code generation function for a multi-modal large model; Perform interface constraints, syntax checking, and functional verification on the Verilog HDL code V generated by MLLMs. The constraints are as follows: ; in, represents the interface constraints in the experimental task, Indicates that the code V semantically satisfies the interface constraints , 、 Respectively represent Verilog HDL syntax checking and functional verification functions; If the above constraints do not hold, the backtracking mechanism is executed: ; Where, Indicates the Iterate multi-modal large model to generate Verilog HDL code, Indicates the In the iteration, the optimal circuit functional block is retrieved by RAG; Step 4: Generate circuit schematic.

[0021] Use the Yosys tool to perform logic synthesis on the Verilog HDL code V described in step 3 to generate a JSON format circuit netlist N: ; Where, Represents the function of generating circuit netlist; When performing logic synthesis on code V, a conflict detection mechanism and a backtracking generation strategy are set, specifically including the following process: For the signal in the Verilog HDL code V , if there is a conflict set , no processing is done; Otherwise, use the conflict set Construct circuit prompt words to guide MLLMs to repair the target, the expression is: ; After multiple iterations until , ; Where, Indicates the first A signal, Indicates that there is a conflicting set of signals. Indicates the set of all signals defined in the code, Indicates the Iteration circuit prompt word, Represents a union operation; Use the Netlistsvg tool to convert the circuit netlist N into an SVG format circuit schematic G: ; Where, Indicates the function of generating schematic diagram; Step 5: Circuit schematic timing verification.

[0022] Use the MLLMs model to perform timing verification on the circuit schematic G obtained in step 4 to meet the timing constraint set in the experimental task. , each timing constraint Indicates that the signal is from the node arrive Maximum propagation delay If the verification fails, update the circuit prompt word Regenerate the Verilog HDL code and continue to iterate until timing consistency is met. The specific verification process is as follows: Model the circuit schematic diagram G and record it as a directed graph , where the node set Represents a logic unit (such as a NAND gate, a D flip-flop, etc.), an edge set Indicates the signal connection direction; Define the attribute vector of each logic unit node as: ; in, Represents an embedded operation function that can convert node attributes into continuous vectors. Type(v) represents the type of logic unit represented by node v. Delay(v) represents the static propagation delay of the logic unit represented by node v. ClockDomain(v) represents the clock domain to which node v belongs. Construct a global diagram representation of the circuit schematic: ; in, Representing a graph neural network; Capture a global view of the circuit schematic The timing path dependency relationship in the experimental task is verified to meet the timing constraint set in the experimental task. , the specific formula is as follows: ; Among them, 1 indicates successful verification, and 0 indicates failed verification; Represents the global diagram of the circuit schematic mid-edge node src i to dst i The shortest path propagation delay is calculated as follows: ; in, Represents the node src i to dst i The set of all paths, δ uv represents the propagation delay of the signal from node u to v; Step 6: Update the electronic component knowledge base.

[0023] From the Electronic Components Knowledge Base Select candidate circuit functional blocks According to the experimental task Task of step 1 and the candidate circuit function block Structural semantic similarity, retrieval weight Calculate the candidate circuit functional blocks Search score of , the calculation formula is as follows: ; in, Represents experimental tasks and circuit function blocks Structural semantic similarity, Represents the adjustment coefficient, which is set based on experience or through search optimization. In this embodiment The value is 1.0, The value is 0.5; For the candidate circuit functional blocks , according to the search score Sort in descending order and record the circuit function block with the highest search score as the optimal circuit function block B * , the formula is as follows: ; in, Indicates the value of the independent variable corresponding to the maximum value of the function; Then the optimal circuit functional block Output to the circuit prompt word construction module; extract the digital circuit structure information after verification by the circuit schematic generation module ,in Representation code Functional semantic labels, Write into the electronic component knowledge base as a new circuit function block ; Update the optimal circuit function block Index weight , and introduce a penalty score adjustment mechanism, as follows: If the optimal circuit functional block Generate candidate circuit hint words Diversity indicators Greater than or equal to The search weight remain unchanged; Otherwise, update the optimal circuit function block Corresponding search weight , the formula is: ; in: Indicates the current index weight, is the penalty item, Indicates the basic penalty range, represents the attenuation coefficient, Indicates circuit function block B * The cumulative number of verification failures, represents the weighting coefficient; in this embodiment, η is 0.02, λ is 0.3, and γ is 1.0.

[0024] This embodiment also provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, it implements the above-mentioned digital circuit experimental method using a multimodal large model. It is specifically used in a digital circuit experimental teaching platform to implement a closed-loop process from task semantic analysis, code generation, logic verification, generation of circuit schematics to knowledge enhancement.

[0025] Through the detailed introduction of the above embodiments, the present invention uses a multimodal large model digital circuit experimental method, which converts experimental tasks in natural language into structured representations and guides the multimodal large model to generate Verilog HDL code according to circuit prompt words, thereby realizing intelligent conversion from natural language to circuit code, reducing the tedious process of manual code writing, lowering the technical threshold of experimental operation, and enabling students to easily carry out digital circuit experiments, thereby improving the intelligence level of experimental teaching; through the continuous enrichment and updating of the electronic component knowledge base, the cyclic evolution and adaptive enhancement of knowledge are realized, providing more comprehensive and accurate knowledge support for subsequent experimental teaching.

[0026] The above formulas are all dimensionless and numerically calculated, and the preset parameters in the formulas are set by technicians in this field according to actual conditions.

[0027] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via wired or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0028] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0029] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0030] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0031] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0032] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0033] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. Apply multi-modal large-model digital circuit experimental platform, characterized by: include: The experimental task semantic parsing module extracts the structured semantic information from the input natural language description of the experimental task requirements through parsing and converts it into a structured representation of the experimental task; The circuit prompt word construction module is connected to the electronic component knowledge base, retrieves circuit function blocks according to the experimental task, and generates candidate circuit prompt words using the circuit prompt word construction function; Verilog HDL code generation module, which uses circuit prompts to guide multi-modal large models to generate Verilog HDL code; Code verification module, which performs interface constraints, syntax checking and functional verification on the generated Verilog HDL code; The circuit schematic generation module is used to perform logic synthesis on the verified code, generate a circuit netlist and convert it into a circuit schematic; Electronic component knowledge base + RAG enhanced update module is used to update the electronic component knowledge base.

2. Apply a multi-modal large-model digital circuit experimental method, characterized in that: The steps include: Step 1: Experimental task semantic analysis: convert the input natural language description of functional requirements into a structured representation of the experimental task; Step 2: Circuit prompt word construction: retrieve the optimal circuit function block from the electronic component knowledge base, and use the circuit prompt word construction function to construct the circuit prompt word; Step 3: Verilog code generation and verification: Using the circuit prompts described in step 2, generate Verilog HDL code through the multi-modal large model and perform interface constraints, syntax checking, and functional verification; Step 4: Generating a circuit schematic: Using the Yosys tool to perform logic synthesis on the Verilog HDL code described in step 3 to generate a circuit netlist; using the Netlistsvg tool to convert the circuit netlist into a circuit schematic; Step 5: Timing verification of the circuit schematic: Use the MLLMs model to perform timing verification on the circuit schematic obtained in step 4. If the verification fails, update the circuit prompt word and regenerate the Verilog HDL code, and continue to iterate until timing consistency is met. Step 6: Updating the electronic component knowledge base: selecting candidate circuit function blocks from the electronic component knowledge base; calculating the search score of the candidate circuit function blocks; The circuit function block with the highest retrieval score is output to the circuit prompt word construction module; the digital circuit structured information verified by the circuit schematic generation module is written into the electronic component knowledge base as a new circuit function block; and the introduced penalty score adjustment mechanism is used to update the optimal circuit function block index weight.

3. The method for applying a multi-modal large-scale digital circuit experiment according to claim 2, characterized in that: In step 2, the circuit prompt words are constructed. The specific steps include: S0, define circuit prompt words to build function set , No. Wheel error message , represents the number of circuit prompt word construction functions in the set; S1. Retrieve the first Optimal circuit functional blocks ; S2. Use the structured representation of the experimental task Task and the optimal circuit functional block described in step 1 And the error message , No. Wheel construction function Generate candidate circuit hint words ; S3. Calculate the diversity index of the candidate circuit prompt words ; S4. Set diversity indicator threshold ,like , then the candidate circuit prompt word As the first Circuit prompt words ; S5. If , calculate the diversity score of each construction function in the circuit prompt word construction function set; S6. Select the construction function with the highest diversity score to regenerate the circuit prompt word.

4. The method for applying a multi-modal large-scale digital circuit experiment according to claim 2, characterized in that: The interface constraints, syntax checking, and function verification in step 3 are as follows: Determine whether the constraints are met ,in, represents the interface constraints in the experimental task, Indicates that the code V semantically satisfies the interface constraints , 、 They represent Verilog HDL syntax checking and functional verification functions respectively; if the above constraints are not met, the backtracking mechanism is executed.

5. The method for applying a multi-modal large-scale digital circuit experiment according to claim 2, characterized in that: In step 4, logic synthesis, the specific process is as follows: Set up the conflict detection mechanism and backtracking generation strategy, and check the signal in the Verilog HDL code described in step 3. , if there is a conflict set , no processing is done; otherwise, the conflict set is used Construct circuit prompt words to guide MLLMs to repair the target, the expression is: ； After multiple iterations until , Where, Indicates the first A signal, Indicates that there is a conflicting set of signals, Indicates the set of all signals defined in the code, Indicates the Iteration circuit prompt word, Represents a union operation.

6. The method for applying a multi-modal large-scale digital circuit experiment according to claim 2, characterized in that: The timing verification of the circuit schematic in step 5 is as follows: Model the circuit schematic described in step 4 and record it as a directed graph ; Define each logic unit node attribute vector as ;use Constructing a global graph h of circuit schematics through graph neural networks (GNNs) G ; Using the formula , capture timing path dependencies and perform timing verification, Among them, 1 indicates successful verification, and 0 indicates failed verification; Representation diagram mid-edge node src i to dst i Shortest path propagation delay.

7. The method for applying a multi-modal large-scale digital circuit experiment according to claim 2, characterized in that: In step 6, a penalty score adjustment mechanism is introduced, as follows: If the optimal circuit function block generates the diversity index of candidate circuit prompt words Greater than or equal to , the retrieval weight remains unchanged; Otherwise, a penalty term, a decay coefficient and the cumulative number of failures are introduced to update the corresponding retrieval weight of the optimal circuit functional block.

8. Apply multi-modal large-scale digital circuit experimental medium, characterized by: Provided is a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the program implements the multimodal large-model digital circuit experiment method described in any one of claims 2 to 7. The program is specifically used in a digital circuit experiment teaching platform to implement a closed-loop process from task semantic analysis, code generation, logic verification, schematic diagram generation to knowledge enhancement.

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