Memory device and refresh method thereof

Abstract

The invention provides a memory device and a refresh method thereof. The memory device may include: a refresh controller configured to generate a first control signal and a second control signal based on an active command and a row address corresponding to the active command; an attacker row determiner configured to determine the row address as an attacker row address based on the first control signal; and a victim row determiner configured to determine a victim row address based on the attacker row address, and determine whether to output the victim row address as a refresh address based on the second control signal. The memory device may be configured to perform a refresh on a row corresponding to the refresh address.

Description

Technical Field

[0001] The present invention relates to a memory device and a refreshing method thereof. Background Art

[0002] Volatile memory devices such as dynamic random access memory (DRAM) can store data by storing charge in the capacitor of a memory cell, and can read data by determining the charge stored in the capacitor. The charge stored in the capacitor leaks over time, so the memory device must periodically perform a refresh operation.

[0003] The memory controller can randomly access the address of the memory device and may frequently access a specific address. As the density of memory cells in the memory device increases, the charge of the memory cells in adjacent rows may be affected by the voltage distribution in a certain row. In particular, when a row is accessed intensively like an attack, the data stored in the memory cells of another row adjacent to the row may change due to the voltage of the activation state of the row. This phenomenon is called row hammering. Therefore, it is useful to effectively improve the refresh operation of the memory device. Summary of the Invention

[0004] The present disclosure attempts to provide a memory device and a refresh method for handling attacks.

[0005] In an embodiment of the present disclosure, a memory device may include: a refresh controller configured to generate a first control signal and a second control signal based on an activate command and a row address corresponding to the activate command; an aggressor row determiner configured to determine the row address as an aggressor row address based on the first control signal; and a victim row determiner configured to determine a victim row address based on the aggressor row address and determine whether to output the victim row address as a refresh address based on the second control signal. The memory device is configured to refresh a row corresponding to the refresh address.

[0006] In an embodiment of the present disclosure, a memory device may include: a memory cell array including a plurality of memory cells; and a refresh control circuit configured to determine an aggressor row address based on an activation signal and a row address corresponding to the activation signal, determine a victim row address based on the aggressor row address, and determine a difference between a row corresponding to the aggressor row address and a row corresponding to a previous aggressor row address. The memory device is configured such that, when an absolute value of the difference is a reference value, the refresh control circuit skips refreshing a previously refreshed row corresponding to the victim row address or refreshes another row.

[0007] In an embodiment of the present disclosure, a refresh method for a memory device may include: receiving an activation signal and a row address corresponding to the activation signal; determining a first aggressor row based on the activation signal and the row address; determining whether a first victim row adjacent to the first aggressor row is a duplicate of a previously refreshed row; determining a second aggressor row different from the first aggressor row when the first victim row is a duplicate of a previously refreshed row, and determining a second victim row adjacent to the second aggressor row as to be refreshed; and determining the first victim row as to be refreshed when the first victim row is not a duplicate of a previously refreshed row. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of a storage system according to an embodiment is shown.

[0009] Figure 2 A block diagram of a memory device according to an embodiment is shown.

[0010] Figure 3 A block diagram of a refresh control circuit according to an embodiment is shown.

[0011] Figure 4 A block diagram of an attacker row determiner according to an embodiment is shown.

[0012] Figure 5 A block diagram of a linear feedback shift register according to an embodiment is shown.

[0013] Figure 6 A block diagram of a victim row determiner according to an embodiment is shown.

[0014] Figure 7 A timing diagram illustrating a refresh operation of a memory device according to an embodiment is shown.

[0015] Figure 8 and Figure 9 A portion of a memory cell array of a memory device is shown.

[0016] Figure 10 A block diagram of a refresh control circuit according to an embodiment is shown.

[0017] Figure 11 A block diagram of an attacker row determiner according to an embodiment is shown.

[0018] Figure 12 A block diagram of a victim row determiner according to an embodiment is shown.

[0019] Figure 13 A timing diagram illustrating a refresh operation of a memory device according to an embodiment is shown.

[0020] Figure 14 A flow chart of a refresh method according to an embodiment is shown.

[0021] Figure 15 A block diagram of a computing system according to an embodiment is shown.

[0022] Figure 16 A memory module according to an embodiment is shown.

[0023] Figure 17 A semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0024] In the following detailed description, only certain embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.

[0025] Therefore, the drawings and description should be regarded as illustrative rather than restrictive in nature, and the same reference numerals represent the same elements throughout the specification. Unless otherwise explicitly stated, the order of operations or steps is not limited to the order presented in the claims or drawings. The order of operations or steps may be changed, multiple operations or steps may be combined, some operations or steps may be divided, and some operations or steps may not be performed.

[0026] As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Although the terms first, second, etc. may be used herein to describe various elements, components, steps and / or operations, these terms are only used to distinguish one element, component, step or operation from another element, component, step or operation.

[0027] Figure 1 A block diagram of a storage system according to an embodiment is shown.

[0028] refer to Figure 1 , a memory system 100 according to an embodiment may include a memory device 110 and a memory controller 120. In some embodiments, the memory device 110 and the memory controller 120 may be connected through a memory interface and may transmit and receive signals through the memory interface.

[0029] The memory device 110 may include a memory cell array 111 and a refresh control circuit 112. The memory cell array 111 may include a plurality of memory cells defined by a plurality of rows and a plurality of columns. In the present disclosure, the rows may be defined by word lines, and the columns may be defined by bit lines. The refresh control circuit 112 may detect an aggressor row (or attack row) from the plurality of rows, may determine the row address of a victim row (victim row) to be refreshed (hereinafter referred to as the victim row address) based on the row address of the aggressor row (hereinafter referred to as the attack row address), and may output the victim row address. In some embodiments, the aggressor row may be a row hammer aggressor row, and the victim row may be a row that is a target of row hammer protection. In some embodiments, the refresh control circuit 112 may select the aggressor row address, and may output the refresh address based on the victim row address at the refresh time.

[0030] The refresh control circuit 112 can determine a refresh address so that the victim row address is not repeatedly refreshed. For example, the refresh control circuit 112 can determine an aggressor row address and can determine the difference or difference value between the currently determined aggressor row address and the previous aggressor row address. Here, the difference between the two row addresses can represent the difference between the two rows corresponding to the two row addresses. The difference between the two rows can indicate how far apart the first row of the two rows is from the second row of the two rows. For example, if the first row is located a positive number of rows above the second row, the difference has a positive value, and if the first row is located a negative number of rows below the second row, the difference has a negative value. For example, when the difference between the first row and the second row is ±2, the third row is located between the first row and the second row. The refresh control circuit 112 can replace the victim row address with another row address based on the difference between the aggressor row address (i.e., the currently determined aggressor row address and the previous aggressor row address), or can skip refreshing the row corresponding to the victim row address. Here, replacing the victim row address with another row address can mean replacing the row corresponding to the victim row address with a row corresponding to another row address to be refreshed. For example, the refresh control circuit 112 may replace memory cells connected to a row corresponding to a victim row address (e.g., a victim row) with memory cells connected to a row corresponding to another row address, or may skip refreshing memory cells connected to a row corresponding to the victim row address. Thus, the memory device 110 may increase defense performance and reduce power consumption.

[0031] The memory controller 120 may provide signals to the memory device 110 to control the memory operation of the memory device 110. The signals may include commands CMD and addresses ADDR. In some embodiments, the memory controller 120 may also provide a clock signal to the memory device 110, and provide commands CMD and addresses ADDR to the memory device 110 in synchronization with the clock signal to control the operation of the memory device 110.

[0032] In some embodiments, the memory controller 120 may provide a command CMD and an address ADDR to the memory device 110 to access the memory cell array 111 and control memory operations such as read or write. Data may be transferred from the memory cell array 111 to the memory controller 120 according to a read operation, and data may be transferred from the memory controller 120 to the memory cell array 111 according to a write operation.

[0033] The command CMD may include an activation command, a read / write command, a refresh command, and a precharge command. The activation command may switch the target row of the memory cell array 111 to an activation state to write data to the memory cell array 111 or read data from the memory cell array 111. The memory cells of the target row may be activated (e.g., driven) in response to the activation command. The read / write command may perform a read operation or a write operation on the target memory cells of the row switched to the activation state. The refresh command may perform a refresh operation on the memory cell array 111. In some embodiments, the refresh control circuit 112 may output a normal refresh command or a target row refresh (TRR, target row refresh) command in response to the refresh command. The TRR command may indicate an operation for refreshing the victim row. The normal refresh command may indicate a normal refresh operation, for example, an operation for sequentially refreshing the rows of the memory cell array 111.

[0034] In some embodiments, the memory controller 120 may access the memory device 110 according to a request from a host outside the memory system 100. The memory controller 120 may communicate with the host by using various protocols.

[0035] The memory device 110 may be a semiconductor-based storage device. In some embodiments, the memory device 110 may include a dynamic random access memory (DRAM). For example, the memory device 110 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, or a Rambus dynamic random access memory (RDRAM).

[0036] In some embodiments, the memory device 110 may include another volatile or non-volatile memory device that uses a refresh operation.

[0037] Figure 2 A block diagram of a memory device according to an embodiment is shown.

[0038] refer to Figure 2 According to an embodiment, a memory device 200 may include a memory cell array 210, a sense amplifier 211, a command decoder (or control logic circuit) 220, an address buffer 230, a row decoder 250, a column decoder 260, an input / output (I / O) gating circuit 270, a data I / O buffer 280, and a refresh control circuit 290.

[0039] The memory cell array 210 may include a plurality of memory cells MC. In some embodiments, the memory cell array 210 may include a plurality of memory banks 210a to 210h. Figure 2 Eight memory banks (BANK0 to BANK7) 210a to 210h are shown, and the number of memory banks is not limited thereto. Each memory bank 210a to 210h may include a plurality of rows, a plurality of columns, and a plurality of memory cells MC arranged at respective intersections of the plurality of rows and the plurality of columns. In some embodiments, the plurality of rows may be defined by a plurality of word lines WL, and the plurality of columns may be defined by a plurality of bit lines BL.

[0040] The command decoder 220 may generate a control signal so that the memory device 200 may perform a read operation, a write operation, or a refresh operation. The command decoder 220 may generate a control signal so that the memory device 200 may perform a read operation, a write operation, or a refresh operation. Figure 1 The command decoder 220 decodes the command CMD received by the memory controller 120 to generate an internal command signal ICS. The internal command signal ICS may include an activation signal, a precharge signal, a refresh signal, a program signal, an erase signal, and a read signal. The activation signal may correspond to an activation command of the memory controller 120. In some embodiments, the activation command of the memory controller 120 may also be directly provided to the refresh control circuit 290. The refresh signal may include a normal refresh command, a TRR command, etc. According to an embodiment, the command decoder 220 may also output a control signal to other components of the memory device 200 (e.g., a row decoder 250, etc.).

[0041] The address buffer 230 may receive an address ADDR provided from the memory controller 120. The address ADDR may include a row address RA indicating a row of the memory cell array 210 and a column address CA indicating a column of the memory cell array 210. The row address RA may be provided to the row decoder 250, and the column address CA may be provided to the column decoder 260. The row address RA may be provided to the refresh control circuit 290 through the command decoder 220, or may be directly provided to the refresh control circuit 290. In some embodiments, the row address RA may be provided to the row decoder 250 through a row address multiplexer (RA MUX) 251. In some embodiments, the address ADDR may further include a bank address BA indicating a memory bank.

[0042] In some embodiments, the memory device 200 may further include a row address multiplexer 251. The row address multiplexer 251 may receive a row address RA from the address buffer 230 and may receive a row address REF_RA to be refreshed from the refresh control circuit 290. The row address multiplexer 251 may selectively output the row address RA received from the address buffer 230 and the row address REF_RA received from the refresh control circuit 290 to the row decoder 250. In some embodiments, the row address multiplexer 251 may output the row address REF_RA to be refreshed in response to an internal command signal ICS (e.g., a refresh signal) from the command decoder 220.

[0043] Figure 2 The command decoder 220 and the address buffer 230 are shown to be separate components, but are not limited thereto. The command decoder 220 and the address buffer 230 may also be implemented as inseparable components.

[0044] The row decoder 250 may select a row to be activated from among the plurality of rows of the memory cell array 210 based on the row address RA or REF_RA. To this end, the row decoder 250 may apply a driving voltage to a word line corresponding to the row to be activated. In some embodiments, a plurality of respectively corresponding row decoders 250a to 250h may be provided to the plurality of memory banks 210a to 210h.

[0045] The column decoder 260 can select a column to be activated from among the multiple columns of the memory cell array 210 based on the column address. To this end, the column decoder 260 can activate the sense amplifier 211 corresponding to the column address CA through the I / O gating circuit 270. In some embodiments, a plurality of respectively corresponding column decoders 260a to 260h can be provided to the multiple memory banks 210a to 210h. In some embodiments, the I / O gating circuit 270 can gate input / output data and can include a data latch for storing data read from the memory cell array 210 and a write driver for writing data to the memory cell array 210. The data read from the memory cell array 210 can be sensed by the sense amplifier 211 and can be stored in the I / O gating circuit 270 (e.g., a data latch). In some embodiments, a plurality of respectively corresponding sense amplifiers 211a to 211h can be provided to the multiple memory banks 210a to 210h.

[0046] In some embodiments, the memory device 200 may further include bank control logic 240 for generating a bank control signal in response to a bank address BA. In response to the bank control signal, a row decoder 250 corresponding to the bank address BA among a plurality of row decoders 250a to 250h may be activated, and a column decoder 260 corresponding to the bank address BA among a plurality of column decoders 260a to 260h may be activated. The activated row decoder may apply a driving voltage to a word line corresponding to the row to be activated.

[0047] In some embodiments, data read from the memory cell array 210 (e.g., data stored in the data latches) may be provided to the memory controller 120 through the data I / O buffer 280. Data to be written to the memory cell array 210 may be provided from the memory controller 120 to the data I / O buffer 280, and the data provided to the data I / O buffer 280 may be provided to the I / O gating circuit 270.

[0048] The memory controller 120 may periodically transmit a refresh-related command CMD to the memory device 110. The refresh control circuit 290 may schedule the refresh based on the command CMD. The process of the refresh control circuit 290 scheduling the refresh may be understood as a process for determining a ratio of normal refresh to TRR and periodically generating a normal refresh command and a TRR command based on the determined ratio.

[0049] The refresh control circuit 290 may transmit a row address REF_RA to be refreshed to the row decoder 250 in response to a refresh signal among the internal command signals ICS. In some embodiments, the row address REF_RA may indicate a row address for normal refresh or a victim row address for target row refresh.

[0050] The refresh control circuit 290 may output the victim row address in response to a TRR command among the internal command signals ICS. In some embodiments, the TRR command may be a row hammering refresh command.

[0051] The refresh control circuit 290 can determine the refresh address so that the victim row address is not repeatedly refreshed. For example, the refresh control circuit 290 can determine the aggressor row address in response to an activation command or activation signal of the memory controller among the internal command signals ICS. The refresh control circuit 290 can determine the difference between the currently determined aggressor row address and the previous aggressor row address. The refresh control circuit 290 can replace the victim row address with another row address based on the difference between the aggressor row address (i.e., the currently determined aggressor row address and the previous aggressor row address), or can skip refreshing the victim row address. Therefore, the memory device 200 can increase defense performance and reduce power consumption.

[0052] In some embodiments, the refresh control circuit 290 may output a row address that is a target of a normal refresh in response to a normal refresh command in the internal command signal ICS. The refresh control circuit 290 may calculate a row address for performing a normal refresh operation and may output the row address in response to the normal refresh command. The refresh control circuit 290 may sequentially increase / decrease the row address each time a normal refresh operation is performed.

[0053] In some embodiments, the refresh control circuit 290 may output a row address for normal refresh as the row address REF_RA in response to a normal refresh command, and may output a victim row address as the row address REF_RA in response to a TRR command. In some embodiments, the refresh control circuit 290 may randomly generate a TRR command or a normal refresh command in response to a refresh signal. In some embodiments, the refresh control circuit 290 may generate a TRR command or a normal refresh command based on a predetermined refresh ratio in response to a refresh signal.

[0054] Figure 3 A block diagram of a refresh control circuit 300 according to an embodiment is shown.

[0055] refer to Figure 3 , the refresh control circuit 300 according to the embodiment may generate a refresh address RA_FREF to be used for target row refresh. The refresh control circuit 300 may include a refresh controller 310, an aggressor row determiner 320, and a victim row determiner 330. In an embodiment, Figure 3 The refresh control circuit 300 may correspond to Figure 2 In an embodiment, the refresh control circuit 290 may include Figure 3For example, the refresh control circuit 290 can be controlled by using Figure 3 The refresh address RA_FREF is used to output the row address REF_RA.

[0056] The refresh controller 310 may receive an active signal ACT, a row address RA corresponding to the active signal ACT, and a refresh command REF_CMD. The refresh controller 310 may generate internal signals ISG1 and ISG2 based on the active signal ACT, the row address RA, and the refresh command REF_CMD.

[0057] The internal signal ISG1 may include a refreshed signal, a row selection signal, an activation signal ACT, a row address RA, and a target row refresh signal (eg, Figure 7 The internal signal ISG2 may include a victim row switching signal, a row selection signal, a difference signal, and a row spacing signal. Figures 4 to 9 The internal signal ISG1 and the internal signal ISG2 are described. The refresh controller 310 may transmit the internal signal ISG1 to the aggressor row determiner 320 and may transmit the internal signal ISG2 to the victim row determiner 330. According to an embodiment, the internal signal ISG1 and the internal signal ISG2 may further include at least one common signal.

[0058] The attacker row determiner 320 may determine the attacker row address ARA based on the internal signal ISG1. In one embodiment, the attacker row determiner 320 may generate a random number based on the internal signal ISG1 and may determine whether to determine the row address RA as the attacker row address ARA based on the random number. In another embodiment, the attacker row determiner 320 may count the number of activations of the row address RA based on the activation signal ACT and the row address RA. For example, the attacker row determiner 320 may count the number of activations of the row address RA in a target row refresh segment (i.e., the segment from one target row refresh time to the next target row refresh time). The attacker row determiner 320 may determine the attacker row address ARA based on the number of activations. For example, the attacker row determiner 320 may determine the row address RA with the largest number of activations as the attacker row address ARA. The method by which the attacker row determiner 320 determines the attacker row address ARA is not particularly limited and may be implemented in many ways. The attacker row determiner 320 may transmit the attacker row address ARA to the victim row determiner 330.

[0059] The victim row determiner 330 may determine a plurality of victim row addresses based on the aggressor row address ARA. The victim row determiner 330 may determine one of the plurality of victim row addresses as a refresh address RA_FREF based on the internal signal ISG2. The memory device may perform refresh based on the refresh address RA_FREF.

[0060] The victim row determiner 330 can determine the refresh address RA_FREF so that the previously refreshed victim row address is not repeatedly refreshed. In this context, a refreshed row address can indicate that the memory cells connected to the row corresponding to the row address are refreshed. For example, the victim row determiner 330 can determine whether the difference between the previous aggressor row address ARA and the current aggressor row address ARA is 2. If the difference is 2, the victim row determiner 330 can replace the victim row address with another row address based on the previous aggressor row address and refresh the other row address. Therefore, the defense performance of the memory device including the refresh control circuit 300 can be improved.

[0061] Will refer to it later Figures 4 to 9 A configuration in which the aggressor row determiner 320 and the victim row determiner 330 determine the aggressor row address ARA and the refresh address RA_FREF is described.

[0062] Figure 4 A block diagram of an attacker row determiner 400 according to an embodiment is shown.

[0063] refer to Figure 4 , the attacker row determiner 400 according to an embodiment may be based on an internal signal (e.g., Figure 3 The attacker row addresses ARA1 and ARA2 are determined by ISG1 of the memory controller. The internal signals may include a refresh signal FREF_DONE, a row selection signal NEW_CAPTURE, an activation signal ACT, and a row address RA. In some embodiments, the activation signal ACT and the row address RA may also be directly received from the memory controller (e.g., Figure 1 120) received.

[0064] The attacker row determiner 400 may include an attacker row selector 410, AND gates 420 and 440, transistors 425 and 435, and registers (REGA1 and REGA2) 430 and 450. In some embodiments, the registers 430 and 450 may also be implemented to be arranged outside the attacker row determiner 400. In an embodiment, Figure 4 The attacker row determiner 400 may correspond to Figure 3 The attacker row determiner 320.

[0065] The aggressor row selector 410 may receive an activation signal ACT and a row address RA. Upon receiving the activation signal ACT, the aggressor row selector 410 may determine the aggressor row addresses ARA1 and ARA2 based on the row address RA.

[0066] The attacker row selector 410 may generate a random number upon receiving the activation signal ACT. For example, the attacker row selector 410 may include a random number generator. According to an embodiment, the random number generator may be a true random number generator (TRNG) or a pseudo random number generator (PRNG). That is, the random number may be a true random number or a pseudo random number. In an embodiment, when the random number generator is a PRNG, the random number generator may be implemented using a linear feedback shift register (LFSR). In an embodiment, the random number generator may generate a random number that is a real number in the range of 0 to 1. In an embodiment, the random number generator may generate a random number that is an integer in the range of 0 to a maximum value. In an embodiment, when the random number generator is an n-bit LFSR, the maximum value may be 2 n -1 (here, n is an integer greater than 1).

[0067] The attacker row selector 410 may determine the attacker row addresses ARA1 and ARA2 based on the generated random number. For example, the attacker row selector 410 may generate a first condition signal COND1 of a first level (e.g., a logic high level) when the random number value is within a first range. Hereinafter, the first level may be referred to as a logic high level. The attacker row selector 410 may generate a second condition signal COND2 of a first level when the random number value is within a second range. In some embodiments, when the random number value is not within the first range or the second range, the attacker row selector 410 may not generate a signal. In this case, the row address RA may not be determined as either of the attacker row addresses ARA1 and ARA2.

[0068] The attacker row selector 410 may output a first condition signal COND1 and a second condition signal COND2 at different times. For example, the attacker row selector 410 may output a first condition signal COND1 of a first level at a first time. In this example, when the refreshed signal FREF_DONE is at a first level, the attacker row selector 410 may transmit the row address RA as the attacker row address ARA1. When the attacker row address ARA1 is output, the level of the refreshed signal FREF_DONE may change. For example, the refreshed signal FREF_DONE may change from a first level to a second level (e.g., a logic low level). Hereinafter, the second level may be referred to as a logic low level. When the target row refresh is performed, the refreshed signal FREF_DONE may change from the second level to the first level.

[0069] The aggressor row selector 410 may output a second condition signal COND2 at a first level at a second time. In this example, the aggressor row selector 410 may transmit the row address RA as the aggressor row address ARA2 when the row select signal NEW_CAPTURE is at a first level. When a refresh is performed on a victim row based on the aggressor row address ARA2, the level of the row select signal NEW_CAPTURE may change. For example, the row select signal NEW_CAPTURE may change from a first level to a second level. When a refresh is performed on another victim row the next time, the level of the row select signal NEW_CAPTURE may change from the second level to the first level.

[0070] The AND gate 420 may receive the refreshed signal FREF_DONE and the first condition signal COND1 , perform an AND operation on the refreshed signal FREF_DONE and the first condition signal COND1 , and transmit the operation result to the transistor 425 .

[0071] AND gate 420 may output a first-level operation result when refresh signal FREF_DONE and first condition signal COND1 are at a first level or a second-level operation result when at least one of refresh signal FREF_DONE and first condition signal COND1 is at a second level.

[0072] The AND gate 440 may receive the row selection signal NEW_CAPTURE and the second condition signal COND2 , perform an AND operation on the row selection signal NEW_CAPTURE and the second condition signal COND2 , and transmit the operation result to the transistor 435 .

[0073] AND gate 440 may output a first-level operation result when row selection signal NEW_CAPTURE and second condition signal COND2 are at a first level. AND gate 440 may output a second-level operation result when at least one of row selection signal NEW_CAPTURE and second condition signal COND2 is at a second level.

[0074] According to an embodiment, transistors 425 and 435 may be implemented as metal oxide silicon (or semiconductor) field effect transistors (MOSFETs). According to an embodiment, each of transistors 425 and 435 may be implemented as a p-channel or n-channel transistor.

[0075] Transistor 425 may receive an operation result from AND gate 420 through its gate and may operate based on the operation result of AND gate 420. Transistor 435 may receive an operation result from AND gate 440 through its gate and may operate based on the operation result of AND gate 440. For example, when receiving an operation result of a first level, transistors 425 and 435 may be turned on and may transmit the row address RA of aggressor row selector 410 as aggressor row addresses ARA1 and ARA2 to registers 430 and 450. The row address RA may include multiple bits. Registers 430 and 450 may receive and store aggressor row addresses ARA1 and ARA2.

[0076] The transistors 425 and 435 may receive the second-level operation result and may be turned off. For example, when receiving the row address RA, the transistors 425 and 435 may not transmit the row address RA to the registers 430 and 450 based on the second-level operation result.

[0077] In some embodiments, the registers 430 and 450 may output the attacker row addresses ARA1 and ARA2 in response to a target row refresh signal of a first level.

[0078] Figure 5 A block diagram of a linear feedback shift register (LFSR) 500 is shown according to an embodiment.

[0079] refer to Figure 5 According to an embodiment, the linear feedback shift register 500 may include a register circuit 510 and a logic operation circuit 520. The linear feedback shift register 500 may be understood as a random bit generator or a random number generator. For example, the attacker row selector 410 may include the linear feedback shift register 500.

[0080] The linear feedback shift register 500 can determine the feedback bit based on a characteristic polynomial with coefficients of 0 or 1. The register circuit 510 and the logic operation circuit 520 of the linear feedback shift register 500 can be designed based on the characteristic polynomial. For example, when the characteristic polynomial is x 10 +x 7 +x 2 +1, the register circuit 510 may include the first to tenth registers, and the logic operation circuit 520 may include the first logic circuit and the second logic circuit. Figure 5 In the example, N may be 10 and M may be 2. The first to tenth registers and the first logic circuit and the second logic circuit may be connected to satisfy the characteristic polynomial. The outputs of the seventh register and the tenth register among the first to tenth registers may be transmitted to the second logic circuit, and the output of the second logic circuit and the output of the second register may be transmitted to the first logic circuit. The output of the first logic circuit may be transmitted to the first register.

[0081] The register circuit 510 can output feedback bits bT1 ..., bT2, and bN based on the input bits. The register circuit 510 can output the feedback bits bT1 ..., bT2, and bN to the feedback path of the linear feedback shift register 500. The logic operation circuit 520 can perform a logic operation based on the feedback bits bT1 ..., bT2, and bN and can generate operation bits bO1 ..., bO2, and bX. The operation bit bX generated by the logic operation circuit 520 is the input bit and can be input to the register circuit 510. The linear feedback shift register 500 can generate a pseudo-random number sequence by performing a shift operation based on the bits input to the input terminal.

[0082] The register circuit 510 may include first to Nth registers REG1 to REGN (N is an integer greater than 1). The first to Nth registers REG1 to REGN may store first to Nth bits b1 to bN, respectively. The bit values of the first to Nth bits b1 to bN may change according to a shift operation.

[0083] The logic operation circuit 520 may receive the feedback bits bT1 ..., bT2, and bN from the register circuit 510 and may perform a logic operation based on the feedback bits bT1 ..., bT2, and bN. The logic operation circuit 520 may include a first logic circuit XOR1 to an Mth logic circuit XORM (M is an integer greater than 1). The first logic circuit XOR1 to the Mth logic circuit XORM may perform an exclusive OR (XOR) operation.

[0084] The output terminal of the M-th logic circuit XORM may be connected to the (M-1)-th logic circuit, and the first logic circuit XOR1 may be connected to the output terminal of the second logic circuit. For example, the first logic circuit XOR1 among the first logic circuit XOR1 to the M-th logic circuit XORM may perform an operation last, and the operation result of the first logic circuit XOR1 may be input to the first register REG1 of the register circuit 510.

[0085] The first logic circuit XOR1 to the Mth logic circuit XORM can be connected along a feedback path and can transmit the operation result to the logic circuit at the previous end. For example, the Mth logic circuit XORM can be connected to the output of the Nth register REGN. The Mth logic circuit XORM can be further connected to the output of one of the first register to the (N-1)th register. The output of the (N-1)th register can be connected to the Nth register REGN.

[0086] The Mth logic circuit XORM can receive the feedback bit bN from the Nth register REGN and can receive the feedback bit bT2 from one of the first register to the (N-1)th register. The Mth logic circuit XORM can perform a logical operation on the feedback bit bN and the feedback bit bT2 and can generate an operation bit bO2. The first logic circuit XOR1 can receive the operation bit bO1 from the logic circuit at the back end and can receive the feedback bit bT1 from one of the first register to the (N-1)th register. The operation bit bO1 can be generated by a logical operation based on the operation bit bO2. The first logic circuit XOR1 can generate an operation bit bX by performing a logical operation on the operation bit bO1 and the feedback bit bT1. The first logic circuit XOR1 can transmit the operation bit bX to the first register REG1.

[0087] The first register REG1 may store the operation bit bX input through the feedback path as the first bit b1. The bit input through the feedback path may be shifted through the first register REG1 to the Nth register REGN based on a control signal.

[0088] The linear feedback shift register 500 can output a first value VAL1 through the register circuit 510. The first value VAL1 is a random number. The linear feedback shift register 500 can output the first value VAL1 upon receiving the activation signal ACT. The first value VAL1 can be a random binary code having a predetermined number of bits. For example, the linear feedback shift register 500 can output a random binary code having N bits based on the first bit b1 to the Nth bit bN stored in the first register REG1 to the Nth register REGN.

[0089] Figure 6 A block diagram of a victim row determiner 600 according to an embodiment is shown.

[0090] refer to Figure 6 The victim row determiner 600 according to an embodiment may generate a victim row address VRA based on the aggressor row address ARA, and may generate a refresh address RA_FREF based on the victim row address VRA. The aggressor row address ARA may include a first register (eg, Figure 4 430) of the attacker row address ARA1 and the second register (e.g., Figure 4 The attacker row address ARA2 of 450 may include the victim row address VRA1_1, VRA1_2, VRA2_1, and VRA2_2.

[0091] The victim row determiner 600 may include a victim row generator 610, a first multiplexer 620, a victim row selector 630, and a second multiplexer 640. In an embodiment, Figure 6 The victim row determiner 600 may correspond to Figure 3 Victim row determiner 330 .

[0092] The victim row generator 610 may generate a victim row address VRA based on the aggressor row address ARA. For example, the victim row generator 610 may generate the victim row address VRA. The victim row (or victim word line) corresponding to the victim row address VRA is set near the aggressor row (or attack row) corresponding to the aggressor row address ARA. The physical position difference between the victim row and the aggressor row may be 1. In some embodiments, the victim row generator 610 may generate a victim row address VRA from Figure 3 The refresh controller 310 receives the control signal and may also generate a victim row address VRA having a physical position difference between the victim row and the aggressor row equal to or greater than 2 based on the control signal.

[0093] The victim row generator 610 may be based on Figure 4 The victim row generator 610 can generate victim row addresses VRA1_1 and VRA1_2 based on the attacker row address ARA1. Figure 4 In some embodiments, the victim row generator 610 may also be implemented using two generators for receiving the aggressor row addresses ARA1 and ARA2 and for generating the victim row addresses VRA1_1, VRA1_2, VRA2_1, and VRA2_2, respectively.

[0094] The first multiplexer 620 may receive the victim row addresses VRA1_1 and VRA1_2 from the victim row generator 610 and may receive the victim row switching signal VICTIM_SELECT from the refresh controller 310. The first multiplexer 620 may transmit one of the victim row addresses VRA1_1 and VRA1_2 to the second multiplexer 640 based on the victim row switching signal VICTIM_SELECT.

[0095] The refresh controller 310 may change the level of the victim row switching signal VICTIM_SELECT when a row corresponding to one of the victim row addresses VRA1_1 and VRA1_2 is refreshed. For example, the first multiplexer 620 may transmit the victim row address VRA1_2 to the second multiplexer 640 based on the victim row switching signal VICTIM_SELECT at the second level. When the row corresponding to the victim row address VRA1_2, which is the refresh address RA_FREF, is refreshed, the refresh controller 310 may output the victim row switching signal VICTIM_SELECT at the first level. The first multiplexer 620 may transmit the victim row address VRA1_1 to the second multiplexer 640 based on the victim row switching signal VICTIM_SELECT at the first level. When the row corresponding to the victim row address VRA1_1, which is the refresh address RA_FREF, is refreshed, the refresh controller 310 may output the victim row switching signal VICTIM_SELECT at the second level.

[0096] The victim row selector 630 may receive the victim row addresses VRA2_1 and VRA2_2 from the victim row generator 610 , and may receive the row selection signal NEW_CAPTURE and the difference signals DIST_P2 and DIST_M2 from the refresh controller 310 .

[0097] The victim row selector 630 may transmit one of the victim row addresses VRA2_1 and VRA2_2 to the second multiplexer 640 based on the row select signal NEW_CAPTURE and the difference signals DIST_P2 and DIST_M2. For example, the victim row selector 630 may transmit the victim row address VRA2_1 to the second multiplexer 640 based on the row select signal NEW_CAPTURE at a first level and the difference signal DIST_P2 at a first level. The victim row selector 630 may transmit the victim row address VRA2_2 to the second multiplexer 640 based on the row select signal NEW_CAPTURE at a first level and the difference signal DIST_M2 at a first level.

[0098] The refresh controller 310 may change the level of the row select signal NEW_CAPTURE when a row corresponding to one of the victim row addresses VRA2_1 and VRA2_2 (e.g., VRA2_2) is refreshed. For example, the refresh controller 310 may change the row select signal NEW_CAPTURE of a first level to a second level when a row corresponding to the victim row address VRA2_2 is refreshed. The refresh controller 310 may change the row select signal NEW_CAPTURE of a second level to a first level when a row corresponding to the other of the victim row addresses VRA2_1 and VRA2_2 (e.g., VRA2_1) is refreshed.

[0099] The refresh controller 310 can calculate the difference between the row corresponding to the previous aggressor row address ARA1 and the row corresponding to the current aggressor row address ARA1. For example, the refresh controller 310 can include a subtractor. When the row corresponding to the current aggressor row address ARA1 is greater than the row corresponding to the previous aggressor row address ARA1 by a value of 2, the subtractor can output a difference signal DIST_P2 of a first level. In this case, the row corresponding to the current aggressor row address ARA1 is positioned above the row corresponding to the previous aggressor row address ARA1 and spaced apart by 2. For example, a row is positioned below the row corresponding to the current aggressor row address ARA1 and above the row corresponding to the previous aggressor row address ARA1. When the row corresponding to the current aggressor row address ARA1 is less than the row corresponding to the previous aggressor row address ARA1 by a value of 2, the subtractor can output a difference signal DIST_M2 of a first level. In this case, the row corresponding to the current aggressor row address ARA1 is positioned below the row corresponding to the previous aggressor row address ARA1 and spaced apart by 2. For example, one row is set above the row corresponding to the current attacker row address ARA1 and below the row corresponding to the previous attacker row address ARA1.

[0100] The refresh controller 310 may change the difference signal DIST_P2 or DIST_M2 of the first level to the second level when the target row refresh signal FREF_EN changes from the first level to the second level.

[0101] The victim row selector 630 may generate a replaced switch signal REPS based on the difference signals DIST_P2 and DIST_M2. The victim row selector 630 may include an OR gate. The OR gate may perform an OR operation on the difference signals DIST_P2 and DIST_M2. For example, when one of the difference signals DIST_P2 and DIST_M2 is at a high level (e.g., a first level), the OR gate may output a high level, and when the difference signals DIST_P2 and DIST_M2 are at a low level (e.g., a second level), the OR gate may output a low level.

[0102] Victim row selector 630 may delay and output a replacement switching signal REPS when difference signal DIST_M2 is at a high level. For example, victim row selector 630 may generate replacement switching signal REPS so that victim row address VRA2_2 is output as refresh address RA_FREF after victim row address VRA1_2 is output as refresh address RA_FREF. When difference signal DIST_P2 is at a high level, victim row selector 630 may generate replacement switching signal REPS so that victim row address VRA1_1 is output as refresh address RA_FREF after victim row address VRA2_1 is output as refresh address RA_FREF. Victim row selector 630 may transmit replacement switching signal REPS to second multiplexer 640.

[0103] The second multiplexer 640 may output the refresh address RA_FREF based on the replacement switching signal REPS. For example, the second multiplexer 640 may receive the replacement switching signal REPS of the second level and may output the address from the first multiplexer 620 as the refresh address RA_FREF. The second multiplexer 640 may receive the replacement switching signal REPS of the first level and may output the address from the victim row selector 630 as the refresh address RA_FREF.

[0104] Figure 7 shows a timing diagram illustrating a refresh operation of a memory device according to an embodiment, and Figure 8 and Figure 9 A portion of a memory cell array of a memory device is shown.

[0105] refer to Figure 7 , the memory device according to the embodiment may receive a command (eg, an active command ACT, a refresh command, etc.) from the memory controller.

[0106] The memory device may generate internal signals based on the command of the memory controller. The internal signals may include a target row refresh signal FREF_EN, row spacing signals CURR_RE and PREV_RE, a first condition signal COND1, a refreshed signal FREF_DONE, difference signals DIST_P2 and DIST_M2, a register signal REG_EMPTY, a row selection signal NEW_CAPTURE, a second condition signal COND2, a difference signal SUB_AGGR, Figure 6 The victim row switching signal VICTIM_SELECT, etc. The register signal REG_EMPTY may indicate that the first register (eg, Figure 4 The difference signal SUB_AGGR may indicate the difference between the row corresponding to the aggressor row address ARA1 and the row address corresponding to the received activation command ACT. For example, the difference signal SUB_AGGR may indicate the difference between the row corresponding to the aggressor row address ARA1 and the row corresponding to the row address corresponding to the received activation command ACT.

[0107] The memory device may determine aggressor row addresses ARA1 and ARA2 based on a command from a memory controller and an internal signal. The memory device may determine a victim row address based on the aggressor row addresses ARA1 and ARA2 and may output one of the victim row addresses as a refresh address RA_FREF. The memory device may perform a target row refresh operation using the refresh address RA_FREF.

[0108] The memory device may generate row spacing signals CURR_RE and PREV_RE. The row spacing signals CURR_RE and PREV_RE may indicate that a row that is a predetermined distance away from the determined aggressor row address ARA1 or ARA2 is determined as a victim row.

[0109] The row spacing signal CURR_RE may indicate how far the row corresponding to the victim row address currently to be refreshed is from the row corresponding to the aggressor row address ARA1 or ARA2. The row spacing signal PREV_RE may indicate how far the row corresponding to the victim row address previously refreshed is from the row corresponding to the previously determined aggressor row address. The victim row generator (e.g., Figure 6 610) can determine the victim row address based on the row spacing signal CURR_RE.

[0110] For example, when the row spacing signal CURR_RE indicates "RH", the victim row generator may indicate ±1 row relative to the aggressor row address ARA1 or ARA2. When the row spacing signal CURR_RE indicates "ERH", the victim row generator may indicate ±2 rows relative to the aggressor row address ARA1 or ARA2. However, this is not limiting, and the memory device may indicate ±p (p is an integer greater than 2) rows relative to the aggressor row address ARA1 or ARA2.

[0111] refer to Figure 8 The memory cell array 291 includes three word lines WLt-1, WLt and WLt+1 extending along the row direction (or first direction) D1 and arranged sequentially close to each other in the column direction (or second direction) D2; three bit lines BLg-1, BLg and BLg+1 extending along the column direction D2 and arranged sequentially close to each other in the row direction D1; and memory cells MC respectively combined therewith.

[0112] In this example, word line WLt among word lines WLt-1, WLt, and WLt+1 may correspond to a frequently accessed aggressor row address ARA. Here, the term frequently accessed means that the number of times a word line is activated is large or the activation frequency is large. For example, the number of times a particular word line (e.g., WLt) is activated during a predetermined time period is equal to or greater than a reference value. Word line WLt may be referred to as a hammer word line. When word line WLt is accessed to be activated and precharged, that is, when the voltage of word line WLt increases and decreases, the voltages of adjacent word lines WLt-1 and WLt+1 may rise and fall due to a coupling phenomenon generated between adjacent word lines WLt-1 and WLt+1, and the cell charge stored in the memory cells MC connected to the adjacent word lines WLt-1 and WLt+1 may be affected. When word line WLt is frequently accessed, the cell charge in the memory cells MC connected to victim word lines WLt-1 and WLt+1 may be lost and the stored data may be damaged.

[0113] By using the line spacing signals CURR_RE and PREV_RE indicating "RH", Figure 7 The memory device may provide addresses VRA1 and VRA2 of word lines WLt-1 and WLt+1 that are physically located near the word line WLt corresponding to the aggressor row address ARA. That is, the memory device may prevent data corruption of memory cells caused by frequent access by performing a refresh operation on the adjacent word lines WLt-1 and WLt+1 based on the victim row address.

[0114] refer to Figure 9Memory cell array 292 includes five word lines (WLt-2, WLt-1, WLt, WLt+1, and WLt+2) extending along row direction D1 and sequentially arranged adjacent to one another in column direction D2; three bit lines (BLg-1, BLg, and BLg+1) extending along column direction D2 and sequentially arranged adjacent to one another in row direction D1; and memory cells MC associated with each bit line. In this example, word line WLt among word lines WLt-2, WLt-1, WLt, WLt+1, and WLt+2 may correspond to a frequently accessed attacker row address ARA.

[0115] By using the line spacing signals CURR_RE and PREV_RE indicating "RH", Figure 7 The memory device can provide addresses VRA2 and VRA3 of word lines WLt-1 and WLt+1 that are physically located near the word line WLt corresponding to the aggressor row address ARA. By using the row spacing signals CURR_RE and PREV_RE indicating "ERH", the memory device can provide addresses VRA1 and VRA4 of word lines WLt-2 and WLt+2 that are physically located near the word line WLt corresponding to the aggressor row address ARA. For example, the memory device can prevent data corruption of memory cells caused by frequent access by performing a refresh operation on adjacent word lines WLt-1, WLt+1, WLt-2, and WLt+2 based on the victim row address.

[0116] refer to Figure 7 , the memory device may transition the level of the target row refresh signal FREF_EN from low to high at time ta1. For example, the memory device may generate the target row refresh signal FREF_EN in response to a refresh command of a memory controller.

[0117] A first register of the memory device (eg, Figure 4 430) may store "A" as the aggressor row address ARA1 at time ta1. When the first register stores the aggressor row address ARA1, the register signal REG_EMPTY may be at a low level. The first register may output the aggressor row address ARA1 as "A" in response to the target row refresh signal FREF_EN being at a high level, and may transition the level of the register signal REG_EMPTY to high at time ta2.

[0118] Victim row determiner (e.g., Figure 6 600) of the victim row generator (e.g., Figure 6610) can receive the aggressor row address ARA1 and the row spacing signal CURR_RE. The victim row generator can confirm that the row spacing signal CURR_RE is "RH" and can determine "A-1" and "A+1" as the victim row addresses.

[0119] The victim row determiner may output “A-1” and “A+1” as the refresh address RA_FREF. The victim row determiner may sequentially output “A-1” and “A+1” based on the victim row switching signal. Figure 7 It is shown that the victim row determiner outputs “A−1” and “A+1”, but the embodiment is not limited thereto, and the victim row determiner may also be implemented to output “A+1” and “A−1”.

[0120] The memory device may change the level of the target row refresh signal FREF_EN from high to low at time ta3. The memory device may store the row spacing signal CURR_RE used during the first refresh of the time section ta1 to ta3 as the row spacing signal PREV_RE. For example, during the first refresh, the row spacing signal CURR_RE may be "RH," and the memory device may change the row spacing signal PREV_RE to "RH" at time ta3. The memory device may determine the row spacing signal CURR_RE to be used during the next refresh. For example, the memory device may maintain the row spacing signal CURR_RE at "RH" at time ta3.

[0121] The memory device may complete the first refresh and may receive an active command ACT.

[0122] The memory device may receive an active command ACT and a row address X corresponding to the active command ACT at time tb1. The attacker row selector (eg, Figure 4 410) can generate a second condition signal COND2 at a high level based on the activation command ACT and the row address X at time tb1. When the second condition signal COND2 and the row selection signal NEW_CAPTURE are at a high level, the refresh controller 310 can generate a difference signal SUB_AGGR. The difference signal SUB_AGGR can indicate the difference between the attacker row address ARA1 and the row address corresponding to the received activation command ACT. For example, the subtractor of the refresh controller 310 can receive the attacker row address ARA1 of "A" and the row address of "X", and can output the difference AX of the two addresses as the difference signal SUB_AGGR. For example, the difference AX of the two row addresses can represent the difference between the row corresponding to the attacker row address ARA1 of "A" and the row corresponding to the row address of "X".

[0123] The aggressor row selector may determine whether the difference signal SUB_AGGR is greater than a reference value (a number equal to or greater than 2). The reference value may be determined based on the current row spacing signal and the previous row spacing signal. In an embodiment, the aggressor row selector may determine whether the difference signal SUB_AGGR is greater than 2. The aggressor row selector may determine the row address as the aggressor row address ARA2 when the difference signal SUB_AGGR is greater than 2. The aggressor row selector may store the aggressor row address ARA2 in a second register (e.g., Figure 4 450).

[0124] The memory device may receive an activation command ACT and a row address A-2 corresponding to the activation command ACT at time tb2. The aggressor row selector may generate a first condition signal COND1 at a high level based on the activation command ACT and the row address A-2 at time tb2. The aggressor row selector may maintain the condition signals COND1 and COND2 at a high level for a unit time. In other words, the aggressor row selector may transition the condition signals COND1 and COND2 to a low level after the unit time has elapsed. When the first condition signal COND1 and the refresh signal FREF_DONE are high, the aggressor row selector may determine the row address A-2 as the aggressor row address ARA1. The aggressor row selector may store the aggressor row address ARA1 in the first register.

[0125] The memory device may transition the refresh signal FREF_DONE to a low level when the aggressor row address ARA1 of “A-2” is stored in the first register. The memory device may transition the register signal REG_EMPTY to a low level when the aggressor row address ARA1 of “A-2” is stored in the first register.

[0126] The memory device can calculate the difference between the current aggressor row address ARA1 and the previous aggressor row address ARA1. For example, the memory device can calculate the difference between "A-2" and "A." For example, the memory device can calculate the difference between two rows corresponding to row addresses "A-2" and "A." The row corresponding to the current aggressor row address ARA1 of "A-2" is two smaller than the row corresponding to the previous aggressor row address ARA1 of "A," so the memory device can generate a high-level difference signal DIST_M2.

[0127] The memory device may receive an active command ACT and a row address Y corresponding to the active command ACT at time tb3 .

[0128] The aggressor row selector can generate a second condition signal COND2 at a high level at time tb3 based on the active command ACT and the row address Y. When the second condition signal COND2 and the row select signal NEW_CAPTURE are at a high level, the aggressor row selector can generate a difference signal SUB_AGGR. For example, the subtractor can output the difference AY between the aggressor row address ARA1 of "A" and the row address of "Y" as the difference signal SUB_AGGR. For example, the difference AY can represent the difference between the row corresponding to the aggressor row address ARA1 of "A" and the row corresponding to the row address of "Y."

[0129] The aggressor row selector may determine that the difference signal SUB_AGGR is greater than 2 and may determine the row address as the aggressor row address ARA2. The aggressor row selector may change the aggressor row address ARA2 of the second register to "Y".

[0130] The memory device may transition the level of the target row refresh signal FREF_EN from low to high at time tb4. The memory device may transition the refreshed signal FREF_DONE to a high level in response to the target row refresh signal FREF_EN being at a high level.

[0131] The first register may output the aggressor row address ARA1 of 'A-2' in response to the target row refresh signal FREF_EN being at a high level, and may transition the level of the register signal REG_EMPTY to high.

[0132] The memory device may operate the victim row determiner when the inter-row signals CURR_RE and PREV_RE are “RH.” For example, when at least one of the inter-row signals CURR_RE and PREV_RE is “ERH,” the victim row determiner may not be operated.

[0133] The victim row generator of the victim row determiner may receive the aggressor row address ARA1 of “A-2” and the row spacing signal CURR_RE of “RH”. The victim row generator may determine “A-3” and “A-1” as the victim row addresses. “A-3” and “A-1” generated by the victim row generator may be input to a first multiplexer (e.g., Figure 6 620). The first multiplexer may transmit "A-3" to the second multiplexer (eg, Figure 6 640). The second multiplexer may output "A-3" as the refresh address RA_FREF based on the replaced switching signal of the low level.

[0134] The victim row generator may receive the aggressor row address ARA2 of “Y” and the row spacing signal CURR_RE of “RH”. The victim row generator may determine “Y-1” and “Y+1” as the victim row addresses. “Y-1” and “Y+1” generated by the victim row generator may be input to a victim row selector (e.g., Figure 6 630). The victim row selector may transmit "Y-1" to the second multiplexer based on the row selection signal NEW_CAPTURE being at a high level. When "A-3" is output as the refresh address RA_FREF and the replaced switching signal becomes a high level, the second multiplexer may output "Y-1" as the refresh address RA_FREF.

[0135] The victim row address of “Y−1” may be output as the refresh address RA_FREF, and the memory device may transition the level of the row select signal NEW_CAPTURE from high to low at time tb5 .

[0136] The memory device may transition the level of the target row refresh signal FREF_EN from high to low at time tb6. The memory device may transition the level of the difference signal DIST_M2 from high to low in response to the transition of the target row refresh signal FREF_EN.

[0137] The memory device may store the inter-row signal CURR_RE used during the second refresh of time period tb4 to tb6 as the inter-row signal PREV_RE. For example, during the second refresh, the inter-row signal CURR_RE may be "RH," and the memory device may maintain the inter-row signal PREV_RE at "RH" at time tb6. The memory device may determine that the inter-row signal CURR_RE to be used during the next refresh is "RH." The memory device may complete the second refresh and may receive an activate command ACT.

[0138] The memory device may receive an active command ACT and a row address B corresponding to the active command ACT at time tc1. The aggressor row selector of the memory device may generate a first condition signal COND1 at a high level based on the active command ACT and the row address B at time tc1. When the first condition signal COND1 and the refresh signal FREF_DONE are high, the aggressor row selector may determine the row address B as the aggressor row address ARA1. The aggressor row selector may store the aggressor row address ARA1 in a first register.

[0139] When the aggressor row address ARA1 of “B” is stored in the first register, the memory device may transition the refresh signal FREF_DONE to a low level. When the aggressor row address ARA1 of “B” is stored in the first register, the memory device may transition the register signal REG_EMPTY to a low level.

[0140] The memory device may calculate the difference between the current aggressor row address ARA1, which is "B," and the previous aggressor row address ARA1, which is "A-2." For example, the memory device may calculate the difference between "B" and "A-2." For example, the memory device may calculate the difference between the rows corresponding to row addresses "B" and "A-2." Because the difference between "B" and "A-2" is not 2, the memory device may maintain difference signals DIST_P2 and DIST_M2 at a low level.

[0141] The memory device may receive an activation command ACT and a row address corresponding to the activation command ACT at time tc2. The aggressor row selector may generate a high-level second condition signal COND2 based on the activation command ACT and the row address at time tc2. When the second condition signal COND2 is high and the row select signal NEW_CAPTURE is low, the aggressor row selector may not generate the difference signal SUB_AGGR. Because the difference signal SUB_AGGR is not generated, the aggressor row selector may not change the aggressor row address ARA2, and the second register may maintain the stored "Y".

[0142] The memory device may transition the level of the target row refresh signal FREF_EN from low to high at time tc3. The memory device may transition the refreshed signal FREF_DONE to a high level in response to the target row refresh signal FREF_EN being at a high level.

[0143] The first register may output the attacker row address ARA1 of 'B' in response to the target row refresh signal FREF_EN being at a high level, and may transition the level of the register signal REG_EMPTY to high.

[0144] The memory device may operate the victim row determiner when the inter-row signals CURR_RE and PREV_RE are “RH.” For example, when at least one of the inter-row signals CURR_RE and PREV_RE is “ERH,” the victim row determiner may not be operated.

[0145] The victim row generator of the victim row determiner can receive the attacker row address ARA1 of "B" and the row spacing signal CURR_RE of "RH". The victim row generator can determine "B-1" and "B+1" as the victim row addresses. "B-1" and "B+1" generated by the victim row generator can be input to the first multiplexer of the victim row determiner. The first multiplexer can transmit "B-1" to the second multiplexer based on the victim row switching signal at a low level. The second multiplexer can output "B-1" as the refresh address RA_FREF based on the replacement switching signal at a low level. When the victim row switching signal becomes a high level, the first multiplexer can transmit "B+1" to the second multiplexer. The second multiplexer can output "B+1" as the refresh address RA_FREF based on the replacement switching signal at a low level. Therefore, "B-1" and "B+1" as the victim row addresses can be refreshed sequentially.

[0146] The memory device may transition the level of the target row refresh signal FREF_EN from high to low at time tc4. The memory device may store the row spacing signal CURR_RE used during the third refresh in time section tc3 to tc4 as the row spacing signal PREV_RE. For example, during the third refresh, the row spacing signal CURR_RE may be "RH," and the memory device may maintain the row spacing signal PREV_RE at "RH" at time tc4. The memory device may determine that the row spacing signal CURR_RE to be used during the next refresh is "RH." The memory device may complete the third refresh and may receive an activate command ACT.

[0147] The memory device may receive an active command ACT and a row address B+2 corresponding to the active command ACT at time td1. An aggressor row selector of the memory device may generate a first condition signal COND1 at a high level based on the active command ACT and the row address B+2 at time td1. When the first condition signal COND1 and the refresh signal FREF_DONE are at high levels, the aggressor row selector may determine the row address B+2 as the aggressor row address ARA1. The aggressor row selector may store the aggressor row address ARA1 in a first register.

[0148] When the aggressor row address ARA1 of "B+2" is stored in the first register, the memory device may transition the refresh signal FREF_DONE to a low level. When the aggressor row address ARA1 of "B+2" is stored in the first register, the memory device may transition the register signal REG_EMPTY to a low level.

[0149] The memory device can calculate the difference between the current aggressor row address ARA1, which is "B+2," and the previous aggressor row address ARA1, which is "B." For example, the memory device can calculate the difference between "B+2" and "B." For example, the memory device can calculate the difference between the rows corresponding to row addresses "B+2" and "B." The current aggressor row address ARA1 is greater than the previous aggressor row address ARA1 by 2, so the memory device can generate a high-level difference signal DIST_P2. For example, the row corresponding to the current aggressor row address ARA1, which is "B+2," is greater than the row corresponding to the previous aggressor row address ARA1 by 2, so the memory device can generate a high-level difference signal DIST_P2.

[0150] The memory device may receive an activation command ACT and a row address corresponding to the activation command ACT at time td2. The aggressor row selector may generate a high second condition signal COND2 based on the activation command ACT and the row address at time td2. Since the second condition signal COND2 is high and the row select signal NEW_CAPTURE is low, the aggressor row selector may not generate the difference signal SUB_AGGR. Since the difference signal SUB_AGGR is not generated, the aggressor row selector may not change the aggressor row address ARA2, and the second register may maintain the stored "Y".

[0151] The memory device may transition the target row refresh signal FREF_EN from low to high at time td3. The memory device may transition the refreshed signal FREF_DONE to high in response to the target row refresh signal FREF_EN being high. The first register may output the aggressor row address ARA1 of "B+2" in response to the high target row refresh signal FREF_EN and may transition the register signal REG_EMPTY to high.

[0152] The memory device may operate the victim row determiner when the inter-row signals CURR_RE and PREV_RE are “RH.” That is, when at least one of the inter-row signals CURR_RE and PREV_RE is “ERH,” the victim row determiner may not be operated.

[0153] The victim row selector may transmit "Y+1" from "Y-1" and "Y+1" input during the fourth refresh of time sections td3 to td5 to the second multiplexer based on the low-level row select signal NEW_CAPTURE. The second multiplexer may output "Y+1" as the refresh address RA_FREF in response to the high-level replacement switching signal. The victim row address of "Y+1" may be output as the refresh address RA_FREF, and the memory device may transition the level of the row select signal NEW_CAPTURE from low to high at time td4.

[0154] The victim row generator of the victim row determiner may receive the aggressor row address ARA1 of "B+2" and the row spacing signal CURR_RE of "RH". The victim row generator may determine "B+1" and "B+3" as the victim row addresses. "B+1" and "B+3" generated by the victim row generator may be input to the first multiplexer of the victim row determiner. The first multiplexer may transmit "B+3" to the second multiplexer based on the high-level victim row switching signal. The second multiplexer may output "B+3" as the refresh address RA_FREF based on the low-level replacement switching signal.

[0155] The memory device may transition the level of the target row refresh signal FREF_EN from high to low at time td5. The memory device may transition the level of the difference signal DIST_P2 in response to the transition of the target row refresh signal FREF_EN.

[0156] The memory device may store the inter-row signal CURR_RE used during the fourth refresh in the time period td3 to td5 as the inter-row signal PREV_RE. For example, during the fourth refresh, the inter-row signal CURR_RE may be "RH," and the memory device may maintain the inter-row signal PREV_RE at "RH" at time td5. The memory device may determine that the inter-row signal CURR_RE to be used during the next refresh is "RH." The memory device may complete the fourth refresh and may receive an active command ACT.

[0157] Therefore, the memory device can increase defense performance by preventing the victim row address from being repeatedly refreshed.

[0158] Figure 10 A block diagram of a refresh control circuit 700 according to an embodiment is shown.

[0159] refer to Figure 10The refresh control circuit 700 according to an embodiment may generate a refresh address RA_FREF to be used for target row refresh. The refresh control circuit 700 may include a refresh controller 710 , an aggressor row determiner 720 , and a victim row determiner 730 .

[0160] The refresh controller 710 may receive an active signal ACT, a row address RA corresponding to the active signal ACT, and a refresh command REF_CMD. The refresh controller 710 may generate internal signals ISF1 and ISF2 based on the active signal ACT, the row address RA, and the refresh command REF_CMD.

[0161] The internal signal ISF1 may include a refreshed signal, an activation signal ACT, a row address RA, and a target row refresh signal. The internal signal ISF2 may include a victim row switch signal, a difference signal, and a row spacing signal. The refresh controller 710 may transmit the internal signal ISF1 to the aggressor row determiner 720, and may transmit the internal signal ISF2 to the victim row determiner 730. Figures 11 to 13 Internal signal ISF1 and internal signal ISF2 are described. According to an embodiment, internal signal ISF1 and internal signal ISF2 may further include at least one common signal.

[0162] The attacker row determiner 720 may determine the attacker row address ARA based on the internal signal ISF1. In an embodiment, the attacker row determiner 720 may generate a random number based on the internal signal ISF1 and may determine whether to determine the row address RA as the attacker row address ARA based on the random number. In another embodiment, the attacker row determiner 720 may count the number of activations of the row address RA based on the activation signal ACT and the row address RA. For example, the attacker row determiner 720 may count the number of activations of the row address RA in the target row refresh segment. The attacker row determiner 720 may determine the attacker row address ARA based on the number of activations. For example, the attacker row determiner 720 may determine the row address RA with the largest number of activations as the attacker row address ARA. The method by which the attacker row determiner 720 determines the attacker row address ARA is not specifically limited and may be implemented in various ways. The attacker row determiner 720 may transmit the attacker row address ARA to the victim row determiner 730.

[0163] The victim row determiner 730 may determine a plurality of victim row addresses based on the aggressor row address ARA. The victim row determiner 730 may determine one of the plurality of victim row addresses as a refresh address RA_FREF based on the internal signal ISF2. The memory device may perform refresh based on the refresh address RA_FREF.

[0164] The victim row determiner 730 can determine the refresh address RA_FREF so that the refreshed victim row address does not need to be repeatedly refreshed. For example, the victim row determiner 730 can determine whether the difference between the previous aggressor row address ARA and the current aggressor row address ARA is 2. When the difference between the previous aggressor row address ARA and the current aggressor row address ARA is 2, the victim row determiner 730 can skip refreshing the refreshed victim row address based on the previous aggressor row address. Therefore, the power consumption of the memory device including the refresh control circuit 700 can be reduced.

[0165] Will refer to it later Figures 11 to 13 A configuration in which the aggressor row determiner 720 and the victim row determiner 730 determine the aggressor row address ARA and the refresh address RA_FREF is described.

[0166] Figure 11 A block diagram of an attacker row determiner 800 is shown according to an embodiment.

[0167] refer to Figure 11 , the attacker row determiner 800 according to an embodiment may be based on an internal signal (e.g., Figure 10 The attacker row address ARA is determined by ISF1. The internal signal may include a refresh signal FREF_DONE, an activation signal ACT, a row address RA, etc. In some embodiments, the activation signal ACT and the row address RA may also be directly received from the memory controller (e.g., Figure 1 120) received.

[0168] The aggressor row determiner 800 may include an aggressor row selector 810, an AND gate 820, a transistor 825, and a register (REG) 830. In some embodiments, the register 830 may also be arranged outside the aggressor row determiner 800.

[0169] The aggressor row selector 810 may receive an active signal ACT and a row address RA. The aggressor row selector 810 may determine an aggressor row address ARA based on the row address RA when receiving the active signal ACT.

[0170] The attacker row selector 810 may generate a random number upon receiving the activation signal ACT. For example, the attacker row selector 810 may include a random number generator. Figure 4 and Figure 5 The description will apply to the random number generator. No duplicate description will be provided.

[0171] The attacker row selector 810 may determine the attacker row address ARA based on the generated random number. For example, the attacker row selector 810 may generate a condition signal COND of a first level when the random number value is within a first range. The attacker row selector 810 may generate a condition signal COND of a second level when the random number value is not within the first range.

[0172] When the refresh signal FREF_DONE is at the first level, the aggressor row selector 810 may transmit the row address RA as the aggressor row address ARA. When the aggressor row address ARA is output, the level of the refresh signal FREF_DONE may change. For example, the refresh signal FREF_DONE may change from the first level to the second level. When the target row is refreshed, the refresh signal FREF_DONE may change from the second level to the first level.

[0173] The AND gate 820 may receive the refreshed signal FREF_DONE and the condition signal COND, perform an AND operation on the refreshed signal FREF_DONE and the condition signal COND, and transmit the operation result to the transistor 825.

[0174] AND gate 820 may output a first-level operation result when refresh signal FREF_DONE and condition signal COND are at a first level, or may output a second-level operation result when at least one of refresh signal FREF_DONE and condition signal COND is at a second level.

[0175] The transistor 825 may be implemented as a MOSFET. Depending on the embodiment, the transistor 825 may be implemented as a P-channel or N-channel transistor.

[0176] Transistor 825 can receive the operation result from AND gate 820 through its gate and can operate based on the operation result. For example, transistor 825 can be turned on when receiving the operation result of the first level and can transmit the row address RA of aggressor row selector 810 as aggressor row address ARA to register 830. Row address RA can include multiple bits. Register 830 can receive and store aggressor row address ARA.

[0177] The transistor 825 may be turned off when receiving the operation result of the second level. For example, when receiving the row address RA, the transistor 825 may not transmit the row address RA to the register 830 based on the operation result of the second level.

[0178] Figure 12 A block diagram of a victim row determiner 900 according to an embodiment is shown.

[0179] refer to Figure 12 , the victim row determiner 900 according to an embodiment may generate victim row addresses VRA1 and VRA2 based on the aggressor row address ARA, and may generate a refresh address RA_FREF based on the victim row addresses VRA1 and VRA2.

[0180] The victim row determiner 900 may include a victim row generator 910 , a first multiplexer 920 , a pass determiner 930 , and a second multiplexer 940 .

[0181] The victim row generator 910 may generate victim row addresses VRA1 and VRA2 based on the aggressor row address ARA. For example, the victim row generator 910 may generate victim row addresses VRA1 and VRA2 corresponding to a victim row (or victim word line) that is located adjacent to the aggressor row (or attack row) corresponding to the aggressor row address ARA and whose physical position difference is 1. In some embodiments, the victim row generator 910 may generate victim row addresses VRA1 and VRA2 corresponding to the aggressor row address ARA. Figure 10 The refresh controller 710 receives the control signal and may also generate victim row addresses VRA1 and VRA2 having a physical position difference of 2 based on the control signal.

[0182] The first multiplexer 920 may receive the victim row addresses VRA1 and VRA2 from the victim row generator 910 and may receive the victim row switching signal VICTIM_SELECT from the refresh controller 710. The first multiplexer 920 may transmit one of the victim row addresses VRA1 and VRA2 to the second multiplexer 940 based on the victim row switching signal VICTIM_SELECT.

[0183] The refresh controller 710 may change the level of the victim row switching signal VICTIM_SELECT when a row corresponding to one of the victim row addresses VRA1 and VRA2 is refreshed. For example, the first multiplexer 920 may transmit the victim row address VRA2 to the second multiplexer 940 based on the victim row switching signal VICTIM_SELECT at the second level. The refresh controller 710 may output the victim row switching signal VICTIM_SELECT at the first level when a row corresponding to the victim row address VRA2, which is the refresh address RA_FREF, is refreshed. The first multiplexer 920 may transmit the victim row address VRA1 to the second multiplexer 940 based on the victim row switching signal VICTIM_SELECT at the first level. The refresh controller 710 may output the victim row switching signal VICTIM_SELECT at the second level when a row corresponding to the victim row address VRA1, which is the refresh address RA_FREF, is refreshed.

[0184] The pass determiner 930 may receive the difference signals DIST_P2 and DIST_M2 from the refresh controller 710. The pass determiner 930 may transmit a blank signal to the second multiplexer 940 based on the difference signals DIST_P2 and DIST_M2. In some embodiments, the blank signal may indicate a signal of a second level.

[0185] The refresh controller 710 can calculate the difference between the previous aggressor row address ARA and the current aggressor row address ARA. For example, the refresh controller 710 can include a subtractor. When the current aggressor row address ARA is greater than the previous aggressor row address ARA by 2, the subtractor can output a difference signal DIST_P2 of a first level. When the current aggressor row address ARA is less than the previous aggressor row address ARA by 2, the subtractor can output a difference signal DIST_M2 of a first level.

[0186] The refresh controller 710 may change the difference signal DIST_P2 or DIST_M2 from the first level to the second level when the target row refresh signal changes from the second level to the first level.

[0187] The pass determiner 930 may generate a replacement switching signal REPS based on the difference signals DIST_P2 and DIST_M2. The pass determiner 930 may include an OR gate. The OR gate may perform an OR operation on the difference signals DIST_P2 and DIST_M2. For example, when at least one of the difference signals DIST_P2 and DIST_M2 is at a high level (e.g., a first level), the OR gate may output a high level, and when the difference signals DIST_P2 and DIST_M2 are at a low level (e.g., a second level), the OR gate may output a low level.

[0188] The determiner 930 may delay the replacement switching signal REPS and output the resulting signal when the difference signal DIST_M2 is at a high level. For example, the determiner 930 may generate the replacement switching signal REPS so that when the victim row address VRA2 is output as the refresh address RA_FREF, the blank signal may be output as the refresh address RA_FREF. When the difference signal DIST_P2 is at a high level, the determiner 930 may generate the replacement switching signal REPS so that when the blank signal is output as the refresh address RA_FREF, the victim row address VRA1 may be output as the refresh address RA_FREF. The determiner 930 may transmit the replacement switching signal REPS to the second multiplexer 940.

[0189] The second multiplexer 940 may output a refresh address RA_FREF based on the replacement switching signal REPS. For example, the second multiplexer 940 may receive the replacement switching signal REPS at a second level and may output the address of the first multiplexer 920 as the refresh address RA_FREF. The second multiplexer 940 may receive the replacement switching signal REPS at a first level and may output the blank signal passed through the determiner 930 as the refresh address RA_FREF. When the blank signal is output as the refresh address RA_FREF, refresh may not be performed. In other words, the memory device may skip refresh based on the blank signal.

[0190] Figure 13 A timing diagram illustrating a refresh operation of a memory device according to an embodiment is shown.

[0191] refer to Figure 13 , the memory device according to the embodiment may receive a command (eg, an active command ACT, a refresh command, etc.) from the memory controller.

[0192] The memory device can generate internal signals based on the command of the memory controller. The internal signals may include a target row refresh signal FREF_EN, row spacing signals CURR_RE and PREV_RE, a condition signal COND, a refreshed signal FREF_DONE, difference signals DIST_P2 and DIST_M2, a register signal REG_EMPTY, Figure 12 The victim row switching signal VICTIM_SELECT etc.

[0193] The memory device may determine an aggressor row address ARA based on a command from a memory controller and an internal signal. The memory device may determine a victim row address based on the aggressor row address ARA and may output one of the victim row addresses as a refresh address RA_FREF. The memory device may perform a target row refresh operation using the refresh address RA_FREF.

[0194] The memory device may generate row spacing signals CURR_RE and PREV_RE. The row spacing signals CURR_RE and PREV_RE may indicate that a row having a predetermined spacing from a row corresponding to the determined aggressor row address ARA is determined as a victim row.

[0195] The row spacing signal CURR_RE may indicate how far the row corresponding to the victim row address currently to be refreshed is spaced relative to the row corresponding to the aggressor row address ARA. The row spacing signal PREV_RE may indicate how far the row corresponding to the victim row address previously refreshed is spaced relative to the row corresponding to the previously determined aggressor row address. The victim row generator (e.g., Figure 12910) can determine the victim row address based on the row spacing signal CURR_RE.

[0196] For example, when the row spacing signal CURR_RE indicates "RH", it may indicate ±1 row relative to the aggressor row address ARA. When the row spacing signal CURR_RE indicates "ERH", it may indicate ±2 rows relative to the aggressor row address ARA. However, embodiments are not limited thereto, and the memory device may indicate ±p (p is an integer greater than 2) rows relative to the aggressor row address ARA.

[0197] The memory device may transition the level of the target row refresh signal FREF_EN from low to high at time ta11. For example, the memory device may generate the target row refresh signal FREF_EN in response to a refresh command of a memory controller.

[0198] Registers of memory devices (e.g. Figure 11 830) may store "A" as the aggressor row address ARA at time ta11. When the register stores the aggressor row address ARA, the register signal REG_EMPTY may be at a low level. The register may output the aggressor row address ARA as "A" in response to the target row refresh signal FREF_EN being at a high level, and may transition the level of the register signal REG_EMPTY to high at time ta12.

[0199] Victim row determiner (e.g., Figure 12 900) of the victim row generator (e.g., Figure 12 910) can receive the aggressor row address ARA and the row spacing signal CURR_RE. The victim row generator can confirm that the row spacing signal CURR_RE is "RH" and can determine "A-1" and "A+1" as the victim row address.

[0200] The victim row determiner may output "A-1" and "A+1" as the refresh address RA_FREF. The victim row determiner may sequentially output "A-1" and "A+1" based on the victim row switching signal. Figure 13 The victim row determiner is shown to output “A−1” and “A+1”, but the embodiment is not limited thereto, and the victim row determiner may also be implemented to output “A+1” and “A−1”.

[0201] The memory device may change the level of the target row refresh signal FREF_EN from high to low at time ta13. The memory device may store the row spacing signal CURR_RE used during the first refresh of the time section ta11 to ta13 as the row spacing signal PREV_RE. For example, the row spacing signal CURR_RE may be "RH" during the first refresh, and the memory device may change the row spacing signal PREV_RE to "RH" at time ta13. The memory device may determine the row spacing signal CURR_RE to be used during the next refresh. For example, the memory device may maintain the row spacing signal CURR_RE at "RH" at time ta13.

[0202] The memory device may complete the first refresh and may receive an active command ACT.

[0203] The memory device may receive an activation command ACT and a row address A-2 corresponding to the activation command ACT at time tb11. The attacker row selector may generate a high-level condition signal COND based on the activation command ACT and the row address A-2 at time tb11. The attacker row selector may maintain the condition signal COND at a high level for a unit time. In other words, the attacker row selector may transition the condition signal COND to a low level after the unit time has elapsed. When the condition signal COND and the refresh signal FREF_DONE are at a high level, the attacker row selector may determine the row address A-2 as the attacker row address ARA. The attacker row selector may store the attacker row address ARA in a register.

[0204] The memory device may transition the refresh signal FREF_DONE to a low level when the aggressor row address ARA of “A-2” is stored in the register. The memory device may transition the register signal REG_EMPTY to a low level when the aggressor row address ARA of “A-2” is stored in the register.

[0205] The memory device can calculate the difference between the row corresponding to the current aggressor row address ARA and the row corresponding to the previous aggressor row address ARA. For example, the memory device can calculate the difference between the row corresponding to the current aggressor row address "A-2" and the row corresponding to the previous aggressor row address "A". The row corresponding to the current aggressor row address ARA is less than the row corresponding to the previous aggressor row address ARA by 2, so the memory device can generate a high-level difference signal DIST_M2.

[0206] The memory device may transition the level of the target row refresh signal FREF_EN from low to high at time tb12. The memory device may transition the refreshed signal FREF_DONE to a high level in response to the target row refresh signal FREF_EN being at a high level.

[0207] The register may output the aggressor row address ARA of “A-2” in response to the target row refresh signal FREF_EN being at a high level, and may transition the level of the register signal REG_EMPTY to high.

[0208] The memory device may operate the victim row determiner when the inter-row signals CURR_RE and PREV_RE are “RH.” For example, when at least one of the inter-row signals CURR_RE and PREV_RE is “ERH,” the victim row determiner may not be operated.

[0209] The victim row generator of the victim row determiner may receive the aggressor row address ARA of “A-2” and the row spacing signal CURR_RE of “RH”. The victim row generator may determine “A-3” and “A-1” as the victim row addresses. “A-3” and “A-1” generated by the victim row generator may be input to a first multiplexer (e.g., Figure 12 920). The first multiplexer may transmit "A-3" to the second multiplexer (eg, Figure 12 940). The second multiplexer may output "A-3" as the refresh address RA_FREF based on the replaced switching signal at a low level.

[0210] The pass determiner may generate an alternative switching signal based on the difference signals DIST_P2 and DIST_M2. For example, when one of the difference signals DIST_P2 and DIST_M2 is at a first level, the pass determiner may generate an alternative switching signal at a first level. The pass determiner may delay the alternative switching signal and output the resulting signal when the difference signal DIST_M2 is at a high level.

[0211] The determiner may transmit a blank signal to the second multiplexer. When "A-3" is output as the refresh address RA_FREF and the replaced switching signal becomes high, the second multiplexer may output the blank signal as the refresh address RA_FREF. The memory device may skip refreshing in response to the blank signal. For example, the blank signal may have a second level.

[0212] The memory device may transition the level of the target row refresh signal FREF_EN from high to low at time tb13. The memory device may transition the level of the difference signal DIST_M2 from high to low in response to the transition of the target row refresh signal FREF_EN.

[0213] The memory device may store the row spacing signal CURR_RE used during the second refresh in the time period tb12 to tb13 as the row spacing signal PREV_RE. For example, the row spacing signal CURR_RE may be "RH" during the second refresh, and the memory device may maintain the row spacing signal PREV_RE at "RH" at time tb13. The memory device may determine that the row spacing signal CURR_RE to be used during the next refresh is "RH." The memory device may complete the second refresh and may receive the activate command ACT.

[0214] The memory device may receive an active command ACT and a row address B corresponding to the active command ACT at time tc11. The aggressor row selector of the memory device may generate a high-level condition signal COND based on the active command ACT and the row address B at time tc11. When the condition signal COND and the refresh signal FREF_DONE are high, the aggressor row selector may determine the row address B as the aggressor row address ARA. The aggressor row selector may store the aggressor row address ARA in a register.

[0215] The memory device may transition the refresh signal FREF_DONE to a low level when the aggressor row address ARA of “B” is stored in the register. The memory device may transition the register signal REG_EMPTY to a low level when the aggressor row address ARA of “B” is stored in the register.

[0216] The memory device may calculate the difference between the current aggressor row address ARA, which is "B," and the previous aggressor row address ARA, which is "A-2." For example, the memory device may calculate the difference between "B" and "A-2." For example, the memory device may calculate the difference between the row corresponding to the current aggressor row address "B" and the row corresponding to the previous aggressor row address "A-2." Because the difference between "B" and "A-2" is not 2, the memory device may maintain the difference signals DIST_P2 and DIST_M2 at a low level.

[0217] The memory device may transition the level of the target row refresh signal FREF_EN from low to high at time tc12. The memory device may transition the refreshed signal FREF_DONE to a high level in response to the target row refresh signal FREF_EN being at a high level.

[0218] The register may output the aggressor row address ARA of “B” in response to the target row refresh signal FREF_EN being at a high level, and may transition the level of the register signal REG_EMPTY to high.

[0219] The memory device may operate the victim row determiner when the inter-row signals CURR_RE and PREV_RE are “RH.” That is, when at least one of the inter-row signals CURR_RE and PREV_RE is “ERH,” the victim row determiner may not be operated.

[0220] The victim row generator of the victim row determiner can receive the attacker row address ARA of "B" and the row spacing signal CURR_RE of "RH". The victim row generator can determine "B-1" and "B+1" as the victim row addresses. "B-1" and "B+1" generated by the victim row generator can be input to the first multiplexer of the victim row determiner. The first multiplexer can transmit "B-1" to the second multiplexer based on the victim row switching signal at a low level. The second multiplexer can output "B-1" as the refresh address RA_FREF based on the replacement switching signal at a low level. When the victim row switching signal becomes a high level, the second multiplexer can transmit "B+1" to the second multiplexer. The second multiplexer can output "B+1" as the refresh address RA_FREF based on the replacement switching signal at a low level. Therefore, "B-1" and "B+1" as the victim row addresses can be refreshed sequentially.

[0221] The memory device may transition the target row refresh signal FREF_EN from high to low at time tc13. The memory device may store the row spacing signal CURR_RE used during the third refresh in time section tc12 to tc13 as the row spacing signal PREV_RE. For example, the row spacing signal CURR_RE may be "RH" during the third refresh, and the memory device may maintain the row spacing signal PREV_RE at "RH" at time tc13. The memory device may determine that the row spacing signal CURR_RE to be used during the next refresh is "RH." The memory device may complete the third refresh and may receive the activate command ACT.

[0222] The memory device may receive an active command ACT and a row address B+2 corresponding to the active command ACT at time td11. The aggressor row selector of the memory device may generate a high-level condition signal COND based on the active command ACT and the row address B+2 at time td11. When the condition signal COND and the refresh signal FREF_DONE are high, the aggressor row selector may determine the row address B+2 as the aggressor row address ARA. The aggressor row selector may store the aggressor row address ARA in a register.

[0223] The memory device may transition the refresh signal FREF_DONE to a low level when the aggressor row address ARA of "B+2" is stored in the register. The memory device may transition the register signal REG_EMPTY to a low level when the aggressor row address ARA of "B+2" is stored in the register.

[0224] The memory device may calculate the difference between the current aggressor row address ARA, which is "B+2," and the previous aggressor row address ARA, which is "B." For example, the memory device may calculate the difference between "B+2" and "B." For example, the memory device may calculate the difference between the row corresponding to row address "B+2" and the row corresponding to row address "B." The current aggressor row address ARA is greater than the previous aggressor row address ARA by 2, so the memory device may generate a high-level difference signal DIST_P2. For example, the row corresponding to the current aggressor row address ARA, which is "B+2," is greater than the row corresponding to the previous aggressor row address ARA, which is "B," by 2, so the memory device may generate a high-level difference signal DIST_P2.

[0225] The memory device may transition the target row refresh signal FREF_EN from low to high at time td12. The memory device may transition the refreshed signal FREF_DONE to high in response to the target row refresh signal FREF_EN being high. The register may output the aggressor row address ARA of "B+2" in response to the target row refresh signal FREF_EN being high, and may transition the register signal REG_EMPTY to high.

[0226] The memory device may operate the victim row determiner when the inter-row signals CURR_RE and PREV_RE are “RH.” For example, when at least one of the inter-row signals CURR_RE and PREV_RE is “ERH,” the victim row determiner may not be operated.

[0227] The pass determiner may transmit a blank signal to the second multiplexer, and the second multiplexer may output the blank signal to the refresh address RA_FREF in response to the replaced switching signal being at a high level. The memory device may skip refreshing in response to the blank signal.

[0228] The victim row generator of the victim row determiner may receive the aggressor row address ARA of "B+2" and the row spacing signal CURR_RE of "RH". The victim row generator may determine "B+1" and "B+3" as the victim row addresses. "B+1" and "B+3" generated by the victim row generator may be input to the first multiplexer of the victim row determiner. The first multiplexer may transmit "B+3" to the second multiplexer based on the victim row switching signal at a high level. The second multiplexer may output "B+3" as the refresh address RA_FREF based on the replacement switching signal at a low level.

[0229] The memory device may transition the level of the target row refresh signal FREF_EN from high to low at time td13. The memory device may transition the level of the difference signal DIST_P2 in response to the transition of the target row refresh signal FREF_EN.

[0230] The memory device may store the row spacing signal CURR_RE used during the fourth refresh in the time section td12 to td13 as the row spacing signal PREV_RE. For example, the row spacing signal CURR_RE may be "RH" during the fourth refresh, and the memory device may maintain the row spacing signal PREV_RE at "RH" at time td13. The memory device may determine that the row spacing signal CURR_RE to be used during the next refresh is "RH." The memory device may complete the fourth refresh and may receive the active command ACT.

[0231] Therefore, the memory device can reduce power consumption by skipping the refresh of the victim row address.

[0232] Figure 14 A flow chart of a refresh method according to an embodiment is shown.

[0233] refer to Figure 14 , the refresh method according to the embodiment may be performed by a memory device.

[0234] The memory device may receive an activation signal and a row address corresponding to the activation signal (S1810). For example, the memory device may receive the activation signal and the row address from a memory controller.

[0235] The memory device may determine a first attacker row (S1820). The memory device may determine the first attacker row based on an activation signal. For example, the memory device may generate a random number upon receiving the activation signal. The memory device may determine the row address as the first attacker row based on the random number or may not determine the row address as the first attacker row. The memory device may also determine the row address as the second attacker row based on the random number. For example, when the random number is in a first range, the memory device may determine the row address as the first attacker row, and when the random number is in a second range, the memory device may determine the row address as the second attacker row. In some embodiments, the first attacker row address and the second attacker row address may be stored in different registers. However, embodiments are not limited thereto, and the memory device may determine the attacker row in many ways. For example, the memory device may count the number of activations of the row address, and may also determine the attacker row based on the number of activations of the row address.

[0236] The memory device may determine whether the victim row is repeated (S1830). The memory device may determine at least one victim row based on the first aggressor row. The memory device may determine a row spaced a predetermined distance apart from the first aggressor row as a victim row based on the row spacing signal.

[0237] The memory device may determine that the victim row is repeated when the first aggressor row address and the previous aggressor row address have a difference determined based on the current row spacing signal and the previous row spacing signal.

[0238] In an embodiment, when the current row spacing signal and the previous row spacing signal are first spacing signals indicating a difference of 1, the memory device may determine whether the difference between the first aggressor row address and the previous aggressor row address is 2.

[0239] In an embodiment, when one of the current row spacing signal and the previous row spacing signal is a first spacing signal and the other is a second spacing signal indicating a difference of 2, the memory device may determine whether the difference between the first aggressor row address and the previous aggressor row address is 3.

[0240] In an embodiment, when the current row spacing signal and the previous row spacing signal are the second spacing signal, the memory device may determine whether the difference between the first aggressor row address and the previous aggressor row address is 4.

[0241] Therefore, the memory device may determine that the victim row is duplicated when a first aggressor row address has a predetermined difference from a previous aggressor row address.

[0242] The memory device may determine a second aggressor row when the victim row is repeated (S1840).The memory device may read the second aggressor row stored by another register.

[0243] The memory device may replace the duplicate victim row based on the second aggressor row (S1850). For example, the memory device may determine a row spaced a predetermined distance apart from the second aggressor row as the replacement victim row based on the current row spacing signal. The memory device may output the replacement victim row address as a refresh address, and the replacement victim row may be refreshed.

[0244] However, embodiments are not limited thereto, and the memory device may also skip refreshing of repeated victim rows.

[0245] The memory device may determine a victim row based on the first aggressor row when the victim row is not repeated (S1860). The memory device may determine a row spaced a predetermined distance apart from the first aggressor row as a victim row based on the current row spacing signal. The memory device may output the victim row address as a refresh address, and the victim row may be refreshed.

[0246] Figure 15 A block diagram of a computing system 1900 is shown, according to an embodiment.

[0247] refer to Figure 15 , the computing system 1900 according to the embodiment may include a processor 1910, a memory 1920, a memory controller 1930, a storage device 1940, a communication interface 1950, and a bus 1960. The computing system 1900 may further include general components.

[0248] The processor 1910 may control general operations of corresponding components of the computing system 1900. The processor 1910 may be implemented with at least one of various processing units, such as a central processing unit (CPU), an application processor (AP), or a graphics processing unit (GPU).

[0249] The memory 1920 may store various data and commands. The memory controller 1930 may control the transmission of data or commands to / from the memory 1920. The memory 1920 and / or the memory controller 1930 may perform reference Figures 1 to 14 The refresh operation described above is described. That is, the memory 1920 may perform a target row refresh in response to a command from the memory controller 1930. For example, the memory 1920 may determine an aggressor row address upon receiving an activate command. The memory 1920 may determine a difference between the determined aggressor row address and a previous aggressor row address. The memory 1920 may change the victim row address based on the difference in the aggressor row address or may skip refreshing the victim row address.

[0250] In an embodiment, when the difference between the attacker row addresses is 2, and the victim row address indicates ±1 row relative to the attacker row address at the previous refresh and the current refresh, the memory 1920 may replace one of the current victim row addresses with another address, or may skip the refresh of one of the current victim row addresses.

[0251] In an embodiment, when the difference between the attacker row addresses is 3, the victim row address indicates ±1 row relative to the attacker row address at one of the previous refresh and the current refresh, and the victim row address indicates ±2 rows relative to the attacker row address at the other of the previous refresh and the current refresh, the memory 1920 may replace one of the current victim row addresses with another address, or may skip the refresh of one of the current victim row addresses.

[0252] In an embodiment, when the difference between the aggressor row addresses is 4 and the victim row address indicates ±2 rows relative to the aggressor row address at the time of the previous refresh and the current refresh, the memory 1920 may replace one of the current victim row addresses with another address, or may skip refreshing one of the current victim row addresses. However, the embodiment is not limited thereto, and the memory 1920 may replace the current victim row address with another address, or may skip refreshing, when the difference between the aggressor row addresses is 5 or greater.

[0253] In some embodiments, the memory controller 1930 may be provided as a separate chip from the processor 1910. In some embodiments, the memory controller 1930 may be provided as an internal component of the processor 1910.

[0254] Storage device 1940 can store programs and data non-temporarily. In some embodiments, storage device 1940 can be implemented as non-volatile memory. Communication interface 1950 can support wired or wireless network communication for computing system 1100. Communication interface 1950 can also support various communication methods other than network communication. Bus 1960 can provide communication functions between components of computing system 1900. Bus 1960 can include at least one type of bus according to the communication protocol between the components.

[0255] Figure 16 A memory module 2000 according to an embodiment is shown.

[0256] refer to Figure 16According to an embodiment, the memory module 2000 may include a plurality of memory chips (DRAMs) each including a memory cell array, a buffer chip (RCD) for routing a memory controller and transmitting / receiving signals or for managing memory operations of the memory chips, and a power management chip (PMIC). The RCD may control the memory chips (DRAMs) and the power management chip (PMIC) according to the control of the memory controller. For example, the RCD may receive command signals, control signals, and a clock signal (CLK) from the memory controller.

[0257] The memory chip (DRAM) can be connected to a corresponding one of the data buffers (DB) through respectively corresponding data transmission lines, and can transmit / receive data signals and data strobe signals. The memory chip (DRAM) can be connected to the data buffer (DB) through respectively corresponding data transmission lines, and can transmit / receive parity data and data strobe signals.

[0258] The memory module 2000 may include an electrically erasable programmable read-only memory (EEPROM). The EEPROM may include initial information or device information of the memory module 2000. For example, the EEPROM may include information or device information of the memory module 2000, such as module form, module structure, storage capacity, module type, or execution conditions. When a memory system including the memory module 2000 is started, the memory controller may read the device information from the EEPROM and may identify the memory module based on the device information.

[0259] The memory module 2000 may include a plurality of memory ranks. In an embodiment, each memory rank may include eight memory bank groups. Each memory bank group may include four memory banks.

[0260] The memory module 2000 can perform reference Figures 1 to 14 The refresh operation described above. That is, the memory module 2000 may perform a target row refresh in response to a command from the memory controller. For example, the memory module 2000 may determine an aggressor row address upon receiving an activate command. The memory module 2000 may determine a difference between the determined aggressor row address and a previous aggressor row address. The memory module 2000 may change the victim row address based on the difference between the aggressor row addresses or may skip refreshing the victim row address.

[0261] In an embodiment, when the difference between the attacker row addresses is 2, and the victim row address indicates ±1 row relative to the attacker row address at the previous refresh and the current refresh, the memory module 2000 may replace one of the current victim row addresses with another address, or may skip the refresh of one of the current victim row addresses.

[0262] In an embodiment, when the difference between the attacker row addresses is 3, the victim row address indicates ±1 row relative to the attacker row address at one of the previous refresh and the current refresh, and the victim row address indicates ±2 rows relative to the attacker row address at the other of the previous refresh and the current refresh, the memory module 2000 may replace one of the current victim row addresses with another address, or may skip the refresh of one of the current victim row addresses.

[0263] In an embodiment, when the difference between the aggressor row addresses is 4, and the victim row address indicates ±2 rows relative to the aggressor row address at the time of the previous refresh and the current refresh, the memory module 2000 may replace one of the current victim row addresses with another address, or may skip refreshing one of the current victim row addresses. However, the embodiment is not limited thereto, and the memory module 2000 may replace the current victim row address with another address, or may skip refreshing, when the difference between the aggressor row addresses is 5 or greater.

[0264] Figure 17 A semiconductor package 3000 according to an embodiment is shown.

[0265] refer to Figure 17 According to an embodiment, a semiconductor package 3000 may be a memory module including at least one stacked semiconductor chip 3300 and a system on chip (SoC) 3400 mounted on a package substrate 3100, such as a printed circuit board (PCB). In some embodiments, an interposer 3200 may be optionally further provided on the package substrate 3100. The stacked semiconductor chip 3300 may be formed by a chip on chip (CoC).

[0266] The stacked semiconductor chip 3300 may include at least one memory chip 3320 stacked on a buffer chip 3310, such as a logic chip. The buffer chip 3310 and the at least one memory chip 3320 may be connected via through-silicon vias (TSVs). The buffer chip 3310 may perform training operations on the memory chip 3320. For example, the stacked semiconductor chip 3300 may be a high-bandwidth memory (HBM) with a capacity of 500 GB / sec to 1 TB / sec or higher.

[0267] At least one memory chip 3320 can execute reference Figures 1 to 14The refresh operation described above. That is, the at least one memory chip 3320 may perform a target row refresh in response to a command from the memory controller. For example, the at least one memory chip 3320 may determine an aggressor row address upon receiving an activate command. The at least one memory chip 3320 may determine a difference between the determined aggressor row address and a previous aggressor row address. The at least one memory chip 3320 may change the victim row address based on the difference between the aggressor row addresses or may skip refreshing the victim row address.

[0268] In an embodiment, when the difference between the attacker row addresses is 2, and the victim row address indicates ±1 row relative to the attacker row address at the time of the previous refresh and the current refresh, at least one memory chip 3320 may replace one of the current victim row addresses with another address, or may skip the refresh of one of the current victim row addresses.

[0269] In an embodiment, when the difference between the attacker row addresses is 3, the victim row address indicates ±1 row relative to the attacker row address at one of the previous refresh and the current refresh, and the victim row address indicates ±2 rows relative to the attacker row address at the other of the previous refresh and the current refresh, at least one memory chip 3320 may replace one of the current victim row addresses with another address, or may skip the refresh of one of the current victim row addresses.

[0270] In an embodiment, when the difference between the aggressor row addresses is 4, and the victim row addresses at the time of the previous refresh and the current refresh indicate ±2 rows relative to the aggressor row address, the at least one memory chip 3320 may replace one of the current victim row addresses with another address, or may skip refreshing one of the current victim row addresses. However, embodiments are not limited thereto, and the at least one memory chip 3320 may replace the current victim row address with another address, or may skip refreshing, when the difference between the aggressor row addresses is 5 or greater.

[0271] In some embodiments, reference Figures 1 to 17 Each component described or a combination of two or more components may be implemented using a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or the like.

[0272] Although the present disclosure has been described in conjunction with what are presently considered to be practical embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A memory device, comprising: a refresh controller configured to generate a first control signal and a second control signal based on an active command and a row address corresponding to the active command; an aggressor row determiner configured to determine the row address as an aggressor row address based on the first control signal; as well as a victim row determiner configured to determine a victim row address based on the aggressor row address and determine whether to output the victim row address as a refresh address based on the second control signal, The memory device is configured to refresh a row corresponding to the refresh address.

2. The memory device according to claim 1, wherein: The refresh controller is further configured to determine a difference between a row corresponding to the aggressor row address and a row corresponding to a previous aggressor row address, and generate a second control signal including the difference, and The victim row determiner is further configured to determine whether to output the victim row address based on the difference value.

3. The memory device according to claim 1, wherein The victim row determiner is further configured to replace the victim row address with another address or not output the victim row address based on the second control signal.

4. The memory device according to claim 3, wherein: The victim row determiner comprises: a victim row generator configured to generate a first victim row address and a second victim row address based on the first aggressor row address, and to generate a third victim row address and a fourth victim row address based on the second aggressor row address; a victim row selector configured to generate a replacement switching signal based on a difference signal from among the second control signals and a row selection signal and output one of the third victim row address and the fourth victim row address; a first multiplexer configured to output one of the first victim row address and the second victim row address based on a victim row switching signal from among the second control signals; and a second multiplexer configured to output one of the first to fourth victim row addresses from the victim row selector and the first multiplexer as the refresh address based on the replaced switching signal.

5. The memory device according to claim 4, wherein The memory device is further configured such that the victim row selector: When the row selection signal is at the second level, the third victim row address is output, and When the row selection signal is at a first level higher than the second level, the fourth victim row address is output. The memory device according to claim 4 , wherein: The memory device is further configured such that the victim row selector generates the replaced switching signal when the difference signal is at a first level.

7. The memory device according to claim 6, wherein: The memory device is further configured such that the victim row selector delays the replacement switching signal when the difference signal indicates that the row corresponding to the aggressor row address is smaller than a row corresponding to a previous aggressor row address by a predetermined difference.

8. The memory device according to claim 4, wherein The memory device is further configured such that, when one of the first victim row address and the second victim row address is output as the refresh address, the refresh controller transitions a level of the victim row switching signal.

9. The memory device according to claim 4, wherein: The victim row generator is further configured to generate the victim row address according to the aggressor row address based on a row spacing signal indicating a difference between an aggressor row corresponding to the aggressor row address and a victim row corresponding to the victim row address.

10. The memory device according to claim 9, wherein The memory device is further configured such that, when a difference between the aggressor row and a row corresponding to a previous aggressor row address is the same as a difference determined based on a current row spacing signal and a previous row spacing signal, the victim row determiner replaces the victim row address with another address or does not output the victim row address. The memory device according to claim 10 , wherein: The memory device is configured such that the victim row determiner: When the current row spacing signal and the previous row spacing signal are first spacing signals indicating that the difference is 1, determining whether the difference between the aggressor row and the row corresponding to the previous aggressor row address is 2, When one of the current row spacing signal and the previous row spacing signal is the first spacing signal and the other of the current row spacing signal and the previous row spacing signal is the second spacing signal indicating that the difference is 2, determining whether the difference between the aggressor row and the row corresponding to the previous aggressor row address is 3, and When the current row spacing signal and the previous row spacing signal are the second spacing signal, it is determined whether a difference between the aggressor row and a row corresponding to the previous aggressor row address is 4.

12. The memory device according to claim 1, wherein The attacker row determiner includes: an aggressor row selector configured to determine the row address as a first aggressor row address or a second aggressor row address based on the activate command; a first register configured to store the first aggressor row address and output the first aggressor row address in response to a target row refresh signal of a first level; and A second register is configured to store the second aggressor row address and output the second aggressor row address in response to the target row refresh signal of the first level.

13. The memory device according to claim 12, wherein: The attacker row selector is also configured to: generating a random number based on the activation command, and A condition signal for classifying the row address is generated based on the random number.

14. The memory device according to claim 13, wherein: The attacker row selector is further configured to: generating a first condition signal for classifying the row address as the first attacker row address when the random number is in a first range, and When the random number is in a second range, a second condition signal for classifying the row address as the second attacker row address is generated.

15. The memory device according to claim 14, wherein The attacker row determiner further includes: a first AND gate configured to perform an AND operation on the first condition signal and a refreshed signal, and output a first operation signal; a first transistor configured to be turned on when the first operation signal is at a first level and to transmit the first attacker row address to the first register; a second AND gate configured to perform an AND operation on the second condition signal and a row selection signal and output a second operation signal; and a second transistor configured to be turned on when the second operation signal is at a first level and to transmit the second attacker row address to the second register.

16. The memory device according to claim 1, wherein The attacker row determiner includes: an aggressor row selector configured to generate a condition signal for determining the row address as the aggressor row address based on the activate command; an AND gate configured to perform an AND operation on the condition signal and the refreshed signal and output an operation signal; a transistor configured to receive the operation signal through a gate, be turned on when the operation signal is at a first level, and transmit the attacker row address; and A register is configured to store the aggressor row address and output the aggressor row address in response to a target row refresh signal being at a first level.

17. The memory device according to claim 16, wherein: The victim row determiner comprises: a victim row generator configured to generate a first victim row address and a second victim row address based on the aggressor row address; a first multiplexer configured to output one of the first victim row address and the second victim row address based on a victim row switching signal from among the second control signals; a pass determiner configured to generate an alternate switching signal and a blanking signal based on a difference signal from the second control signal; and a second multiplexer configured to output an output from the first multiplexer or the pass determiner as the refresh address based on the replaced switching signal.

18. A memory device, comprising: a memory cell array, the memory cell array comprising a plurality of memory cells; as well as A refresh control circuit, wherein the refresh control circuit is configured to: determining an attacker row address based on an activation signal and a row address corresponding to the activation signal, determining a victim row address based on the aggressor row address, and determining a difference between a row corresponding to the aggressor row address and a row corresponding to a previous aggressor row address, The memory device is configured such that: when the absolute value of the difference is a reference value, the refresh control circuit skips refreshing a previously refreshed row corresponding to the victim row address or refreshes another row.

19. The memory device according to claim 18, wherein: The reference value is determined based on a spacing signal indicating a difference between a row corresponding to the aggressor row address and a row corresponding to the victim row address adjacent to the row corresponding to the aggressor row address.

20. A refresh method for a memory device, the method comprising: receiving an activation signal and a row address corresponding to the activation signal; determining a first aggressor row based on the activation signal and the row address; determining whether a first victim row adjacent to the first aggressor row is a duplicate of a previously refreshed row; determining a second aggressor row different from the first aggressor row when the first victim row overlaps with a previously refreshed row, and determining a second victim row adjacent to the second aggressor row as to be refreshed; as well as The first victim row is determined to be to be refreshed when the first victim row does not overlap with a previously refreshed row.

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